Communication interface module and use method thereof

Abstract

The invention discloses a communication interface module and a use method thereof. The communication interface module comprises an input circuit + 48V, a logic processing circuit, a command receiving circuit and an input / output circuit + 5V, the input circuit + 48V is used for collecting state data to be transmitted; the logic processing circuit serializes the data and performs longitudinal parity check, and sends the data to an upper computer after the check is passed; and the command receiving circuit receives and verifies the command from the upper computer, sends the command to the output circuit after the verification is passed, and generates an error report and sends the error report to the output circuit when the verification is not passed. And the input / output circuit + 5V transmits the command to an electronic device and sends an error report back to the upper computer when receiving the error report. Data serialization, longitudinal parity check, command check and error report mechanisms are realized in a hardware circuit, so that the dependence on software is effectively reduced, and the reliability of a communication system in a radiation environment is improved.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and particularly to a communication interface module and its usage method. Background Art

[0002] In modern electronic devices, microprocessors and their peripheral devices (such as UART, memory, programmable logic devices (PAL, GAL, PLD, FPGA, etc.)) have become important components for implementing complex functions and enhancing system flexibility.

[0003] Current communication technologies usually rely on microprocessors to achieve communication, and this technology requires software programming to control and process data. However, the presence of ionizing radiation may have an adverse impact on these microprocessors and their peripheral devices (such as UART interfaces, memory, programmable logic devices such as PAL, GAL, PLD, FPGA, etc.), resulting in system failures or instability. Therefore, communication systems that rely on software programming have poor reliability in radiation environments. Summary of the Invention

[0004] This application provides a communication interface module and its usage method, aiming to improve the reliability of communication systems in radiation environments.

[0005] To achieve the above objective, this application provides the following technical solutions:

[0006] A communication interface module, comprising: an input circuit +48V, a logic processing circuit, a command receiving circuit, and an input / output circuit +5V;

[0007] The input circuit +48V is used to collect status data to be transmitted;

[0008] The logic processing circuit is used to serialize the status data to be transmitted; the logic processing circuit is further used to perform longitudinal parity check on the serialized status data to be transmitted. When the serialized status data to be transmitted passes the check, the serialized status data to be transmitted is sent to the host computer;

[0009] The command receiving circuit is used to, when receiving a command fed back by the host computer based on the serialized status data to be transmitted, check the command; when the command passes the check, send the command to the output circuit; when the command fails to pass the check, generate a target error report byte based on the command and send the target error report byte to the output circuit;

[0010] The input / output circuit is +5V and is used to send the command to the electronic device after receiving the command; it is also used to send the target error report byte to the host computer after receiving the target error report byte.

[0011] Optionally, the logic processing circuit includes: a clock unit, a shift register, and a line driver;

[0012] The clock unit is used to set the time base transmitted to the host computer and send the time base to the shift register and the line driver;

[0013] The shift register is used to serialize the to-be-transmitted status data according to the time base when receiving the time base, perform vertical parity check on the serialized to-be-transmitted status data, and transmit the serialized to-be-transmitted status data that passes the check to the line driver;

[0014] The line driver is used to send the serialized to-be-transmitted status data to the host computer according to the time base after receiving the serialized to-be-transmitted status data and the time base.

[0015] Optionally,

[0016] The shift register is further used to obtain and invert the to-be-transmitted status data according to the valid level of the to-be-transmitted status data, and store the processed to-be-transmitted status data after obtaining the processed to-be-transmitted status data.

[0017] Optionally, the shift register for performing vertical parity check on the serialized to-be-transmitted status data specifically is used to:

[0018] Calculate the number of 1s in the serialized to-be-transmitted status data to obtain the total number;

[0019] Judge whether the total number conforms to the parity check rule;

[0020] If the total number conforms to the parity check rule, it is determined that the serialized to-be-transmitted status data passes the check;

[0021] If the total number does not conform to the parity check rule, it is determined that the serialized to-be-transmitted status data fails the check.

[0022] Optionally, the command receiving circuit includes: a byte receiving unit, a byte control unit, a dialogue management unit, a transmission feedback unit, and an output control unit;

[0023] The byte receiving unit is configured to, after receiving the command fed back by the host computer based on the serialized to-be-transmitted status data, perform format verification on the command, and send the command that passes the format verification to the byte control unit;

[0024] The byte control unit is configured to, after receiving the command, perform address verification on the command; if the command fails the address verification, send the command that fails the address verification to the dialogue management unit; if the command passes the address verification, send the command that passes the address verification to the output control unit;

[0025] The dialogue management unit is configured to, when receiving the command that fails the address verification, generate an error report byte based on the command that fails the address verification, and send the error report byte to the emission feedback unit.

[0026] The emission feedback unit is configured to, when receiving the error report byte, add a start bit, a parity bit, and a stop bit to the error report byte to obtain a target error report byte, and send the target error report byte to the host computer through the output circuit;

[0027] The output control unit is configured to, when receiving the command that passes the address verification, send the command that passes the address verification to the output circuit.

[0028] Optionally,

[0029] The emission feedback unit is further configured to, when receiving the confirmation signal fed back by the host computer based on the target error report byte, send the confirmation signal to the dialogue management unit;

[0030] The dialogue management unit is further configured to, when receiving the confirmation signal, send the confirmation signal to the output control unit.

[0031] Optionally,

[0032] The byte receiving unit is further configured to generate a valid pulse when the command passes the format verification; and is further configured to generate a data reception pulse when the command fails the format verification.

[0033] Optionally,

[0034] The output control unit is further configured to obtain the address in the command, and send the command to the hardware link according to the address.

[0035] Optionally,

[0036] The output control unit is further configured to send the address, the enable bit, and the disable bit in the command to the electronic device.

[0037] A method for using a communication interface module, which is applied to the communication interface module described above, includes:

[0038] Collecting the status data to be transmitted through the input circuit +48V;

[0039] Serializing the status data to be transmitted through the logic processing circuit;

[0040] Performing vertical parity check on the serialized status data to be transmitted through the logic processing circuit;

[0041] When the serialized status data to be transmitted passes the check, sending the serialized status data to the host computer through the logic processing circuit;

[0042] When receiving the command fed back by the host computer based on the serialized status data to be transmitted, checking the command through the command receiving circuit;

[0043] When the command passes the check, sending the command to the input / output circuit +5V through the command receiving circuit;

[0044] When the command fails to pass the check, generating a target error report byte based on the command through the command receiving circuit, and sending the target error report byte to the input / output circuit +5V;

[0045] When receiving the command, sending the command to the electronic device through the input / output circuit +5V;

[0046] When receiving the target error report byte, sending the target error report byte to the host computer through the input / output circuit +5V.

[0047] The technical solution provided by this application, the communication interface module includes: an input circuit +48V, a logic processing circuit, a command receiving circuit, and an input / output circuit +5V; the input circuit +48V is used to collect the status data to be transmitted; the logic processing circuit serializes the data and performs vertical parity check, and sends the data to the host computer after passing the check; the command receiving circuit receives and checks the command from the host computer, and sends the command to the output circuit after passing the check, and generates an error report and sends it to the output circuit when it fails to pass the check. The input / output circuit +5V transmits the command to the electronic device and sends the error report back to the host computer when receiving it. By implementing data serialization, vertical parity check, command check, and error report mechanism in the hardware circuit, the dependence on software is effectively reduced, thereby improving the reliability of the communication system in the radiation environment. Description of the Drawings

[0048] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0049] Figure 1 It is a schematic diagram of the architecture of a communication interface module provided by an embodiment of the present application;

[0050] Figure 2 It is a schematic diagram of a +48V input circuit provided by an embodiment of the present application;

[0051] Figure 3 It is a schematic diagram of a time base provided by an embodiment of the present application;

[0052] Figure 4 It is a schematic diagram of a transmission logic state architecture provided by an embodiment of the present application;

[0053] Figure 5 It is a schematic diagram of a command receiving circuit provided by an embodiment of the present application;

[0054] Figure 6 It is a schematic diagram of a +5V input circuit provided by an embodiment of the present application;

[0055] Figure 7 It is a schematic diagram of a +5V output circuit provided by an embodiment of the present application;

[0056] Figure 8 It is a flowchart of a method for using a communication interface module provided by an embodiment of the present application.

[0057] Reference numerals:

[0058] 11 - Input circuit; 12 - Logic processing circuit; 13 - Command receiving circuit; 14 - Output circuit; 51 - Byte receiving unit; 52 - Byte control unit; 53 - Dialogue management unit; 54 - Transmit feedback unit; 55 - Output control unit. Detailed implementation manners

[0059] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0060] In this application, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element qualified by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising the element.

[0061] As Figure 1 shown, it is a schematic diagram of the architecture of a communication interface module provided by an embodiment of this application. The communication interface module includes: an input circuit +48V11, a logic processing circuit 12, a command receiving circuit 13, and an input / output circuit +5V14.

[0062] The input circuit +48V11 is used to collect the status data to be transmitted.

[0063] Among them, the input circuit +48V11 includes, but is not limited to, a +48V input circuit.

[0064] The +48V input circuit needs to meet several specific requirements, which are respectively: optocoupler isolation, attenuating the voltage to a value compatible with 74HCT logic, having a sufficient RC filter, EMC and low-frequency circuits, and "low-pass" filtering with a cut-off frequency of about 100 Hz (minimum 80 Hz). The reason for choosing "low-pass" filtering is that this frequency is still low compared to the usual radio frequencies, and the impact on the response time of the processed signal can be ignored. Specifically, see Figure 2 for a schematic diagram of a +48V input circuit shown.

[0065] It should be noted that generally, the status data to be transmitted is collected through the +48V input circuit.

[0066] Specifically, for the specific manifestation form of the status data to be transmitted, reference can be made to the content shown in Table 1.

[0067] Table 1

[0068]

[0069]

[0070]

[0071]

[0072]

[0073]

[0074]

[0075]

[0076]

[0077] For serializing the status data to be transmitted; the logic processing circuit 12 is further configured to perform vertical parity check on the serialized status data to be transmitted, and when the serialized status data to be transmitted passes the check, send the serialized status data to be transmitted to the host computer.

[0078] Optionally, the host computer includes but is not limited to: a measurement and control cabinet.

[0079] Further, the logic processing circuit 12 includes: a clock unit, a shift register, and a line driver.

[0080] The clock unit is configured to set the time base transmitted to the host computer and send the time base to the shift register and the line driver.

[0081] Wherein, the time base refers to the time reference used to synchronize each operation during signal transmission or data processing.

[0082] Optionally, the time base required to transmit the status data to be transmitted to the host computer is: a 38400Hz clock from a crystal oscillator (usually 4.9152MHz). The period of this clock corresponds to 26μs for each encoded bit of the state "all 1s or all 0s"; a 9600Hz clock, derived from the previous clock, which is used to shift the input acquisition register before encoding; a 1200Hz clock "transmission", these pulses correspond to the start of a 32-bit encoded transmission and correspond to one byte of useful data; a 1200Hz "parity" clock, offset by 26μs compared to the previous clock, which allows preparation of the vertical parity check to be used at the end of the frame; a 50Hz clock "byte 22", this pulse allows specific processing of the frame number; a 50Hz clock "byte 23", this pulse corresponds to the final processing of the vertical parity check; a 50Hz clock "byte 0", this pulse corresponds to the start of the frame and thus corresponds to the synchronization bit, which is also used to increment the frame counter. Specifically, see Figure 3 , a schematic diagram of a time base shown.

[0083] The shift register is configured to, when receiving the time base, serialize the status data to be transmitted according to the time base, perform vertical parity check on the serialized status data to be transmitted, and transmit the serialized status data to be transmitted that passes the check to the line driver.

[0084] It is understandable that the data in the to-be-transmitted state is serialized by a 176-bit shift register, which corresponds to 110 states (useful data, including 8 auxiliary inputs for future use) and 66 unused bits. The transmission is executed at the beginning of the frame using the clock "50Hz byte 0", and the offset is executed at a frequency of 9600Hz.

[0085] Specifically, the to-be-transmitted state data is transmitted bit by bit through the shift register. The shift register packs the data into groups of 8 bits (corresponding to 32-bit encoding), and receives and stores the data according to a certain clock frequency (1200Hz transmission frequency). Each transmission is in units of a complete data frame, which includes the following: 8-bit "Start": Marks the starting position of the data frame. 8-bit "Synchronization" (7 bits are fixed, and 1 bit is related to the start signal of "50Hz byte 0": The synchronization part helps the receiving end correctly identify the starting position of the data frame). 8-bit "Stop": Marks the end part of the data frame, organized in the transmission order, and the offset frequency is 38400Hz.

[0086] Among them, the useful data to be sent (such as ETOR status, frame number, or longitudinal parity check) will be transmitted in groups of 8-bit data. Each data frame may include the following: ETOR status, indicating the status information of a certain device or system; frame number (byte 22), used to identify the number of the current frame to ensure that the receiving end can identify the order of the data frames; longitudinal parity check (byte 23), used to ensure that the data has not been corrupted during transmission. The longitudinal parity check is generated by performing an "exclusive OR" operation on all data bytes and is switched under the control of the "50Hz byte 22" and "50Hz byte 23" clocks.

[0087] Optionally, the shift register for performing longitudinal parity check on the serialized to-be-transmitted state data is specifically used for: calculating the number of 1s in the serialized to-be-transmitted state data to obtain the total number; determining whether the total number conforms to the parity check rule; if the total number conforms to the parity check rule, determining that the serialized to-be-transmitted state data passes the check; if the total number does not conform to the parity check rule, determining that the serialized to-be-transmitted state data fails the check.

[0088] It should be noted that the longitudinal parity check corresponds to the "exclusive OR" of the useful bytes. It can be developed using 8 D flip-flops associated with 8 "exclusive OR" gates and the "1200Hz parity check" clock.

[0089] Specifically, for the above-described content, reference can be made to Figure 4 a schematic diagram of a transmission logic state architecture shown.

[0090] The shift register is also used to obtain and, according to the valid level of the status data to be transmitted, invert the status data to be transmitted. After obtaining the processed status data to be transmitted, the processed status data to be transmitted is stored.

[0091] It should be noted that when there is special status data to be transmitted, it is inverted according to the valid level of the shift register or the level in the frame before being transmitted to the shift register. Specifically, see Table 1. When the status data to be transmitted is +48V leakage input, it needs to be isolated through an optocoupler.

[0092] It should be emphasized that the output of the shift register is implemented by 8-bit data bytes, and these bytes correspond to the content of the useful data and are used to generate and transmit data frames.

[0093] The line driver is used to, when receiving the serialized status data to be transmitted and the time base, send the serialized status data to be transmitted to the host computer according to the time base.

[0094] Specifically, the process of the clock unit, shift register, and line driver processing the status data to be transmitted is as follows: Serialize and verify the status data to be transmitted according to the time base set by the clock unit, transmit the serialized status data to be transmitted that passes the verification to the line driver, and the line driver sends the serialized status data to be transmitted to the host computer according to the time base.

[0095] It should be noted that the line driver also forms an RS422 interface. The line driver plays a bridging role between the 74HCT logic chip on the card and the twisted pair communication pair of external devices, enabling data to be transmitted between devices. The RS422 line receiver must be associated with a +5V resistor bridge, which is responsible for setting the electric potential when the line is interrupted, and the load of the line is close to 110Ω. It must then be a low-pass filter with a cut-off frequency of 30kHz, which is compatible with the data rate.

[0096] The command receiving circuit 13 is used to, when receiving the command fed back by the host computer based on the serialized status data to be transmitted, verify the command; when the command verification passes, send the command to the input / output circuit +5V14; when the command verification fails, generate a target error report byte based on the command and send the target error report byte to the input / output circuit +5V14.

[0097] Optionally, the specific manifestation form of the command is shown in Table 2.

[0098] Table 2

[0099]

[0100]

[0101] Further, see Figure 5 The command receiving circuit 13 includes: a byte receiving unit 51, a byte control unit 52, a dialogue management unit 53, a transmission feedback unit 54 and an output control unit 55.

[0102] The byte receiving unit 51 is used to perform format verification on the command after receiving the command fed back by the host computer based on the serialized state data to be transmitted, and send the command that passes the format verification to the byte control unit 52.

[0103] It is understood that when receiving a command, the byte receiving unit 51 receives the start bit, stop bit, and parity bit of the byte in the command. Each byte of received data contains these specific control bits. When receiving a data byte, it processes the 8 bits of the data byte and synchronously controls the signal pulse of the received byte and the validity information of the byte.

[0104] To process these bytes, the shift register serializes the received data, which means that the bytes are received bit by bit in sequence, including the control bits. The shift register is responsible for transferring the 12 received bits (including data bits and control bits) in sequence and must ensure that these operations are synchronized with the start time of the received message.

[0105] In addition, when receiving commands, in addition to using the oscillator, it is also necessary to use the frequency divider and cycle counter associated with the "receive in progress" trigger to ensure that the receiving process is synchronized with the clock in order to correctly process the reception of data.

[0106] When the receive command is received, the correctness of the data format must be verified by the combinational logic. In particular, the start bit, stop bit, and parity bit must be checked to ensure they conform to the protocol. If the format is correct, the logic block generates a pulse signal to indicate that valid format data has been received.

[0107] The byte receiving unit 51 is further used to generate a valid pulse when the command passes the format check; and is also used to generate a data receiving pulse when the command fails the format check.

[0108] The byte control unit 52 is used to perform address verification on the command after receiving the command; if the command fails the address verification, the command that fails the address verification is sent to the dialogue management unit 53; if the command passes the address verification, the command that passes the address verification is sent to the output control unit 55.

[0109] Among them, the specific process of address verification of the command is: verify whether the address in the command is within the valid range; if the address in the command is within the valid range, it is determined that the command has passed the verification; if the address in the command is not within the valid range, it is determined that the command has failed the verification.

[0110] Specifically, when a request (preparation) to activate or deactivate the output is received, the address (7 - bit) must be between 0 (inclusive) and 95 (inclusive). Therefore, the received byte is between 0 and 95 or between 128 and 223. In the order of execution, the received byte must be equal to 255.

[0111] In addition, when a request (preparation) to activate or disable the output is received, after the execution is confirmed, the received 8 - bit byte is stored for development.

[0112] The dialogue management unit 53 is used to generate an error report byte based on the command that fails the address check when a command that fails the address check is received, and send the error report byte to the transmission feedback unit 54.

[0113] The dialogue management unit 53 is also used to send the confirmation signal to the output control unit 55 when a confirmation signal is received.

[0114] Among them, when the dialogue management unit 53 is powered on or a dialogue box error occurs, the dialogue management unit 53 enters a default state, waiting to receive a request for "activating or deactivating the output". After receiving the request, the system enters the "waiting for confirmation of execution" stage. This means that the request has been received, but a confirmation message (such as a confirmation byte) is needed to ensure that the request can be executed. If the received request has no error, the system will send an "echo byte" as confirmation. If an error occurs when the request is received, the system will send an "error report byte" to report the problem.

[0115] In addition, at the end of each stage, the dialogue management unit 53 generates a signal indicating that it is waiting to receive the execution confirmation. This is to ensure that the system is in a waiting state until the execution confirmation byte arrives. If no error occurs and the execution confirmation byte is received, an execution pulse will be sent to the I / O card, instructing the I / O card to start performing the corresponding operation.

[0116] The transmission feedback unit 54 is used to add a start bit, a parity bit, and a stop bit to the error report byte when the error report byte is received, obtain the target error report byte, and send the target error report byte to the host computer through the input / output circuit +5V14.

[0117] Among them, the transmission feedback unit 54 includes: implementing a shift register, scoring the broadcast using an appropriate time base, calculating the parity bit, adding the start bit, parity bit, and stop bit to the byte to be sent, and directing the generated signal to the line driver.

[0118] In addition, the generation of the message requires the use of a shift register, which is responsible for serializing the 12 bits (including the control bit) to be sent. It also needs to synchronize the time base with the start of the message transmission. The proposed arrangement includes, in addition to the oscillator, a frequency divider and a cycle counter associated with "being transmitted".

[0119] The emission feedback unit 54 is also used to send the confirmation signal to the dialogue management unit 53 when receiving the confirmation signal fed back by the host computer based on the target error report byte.

[0120] The output control unit 55 is used to send the command that has passed the address check to the input / output circuit +5V14 when receiving the command that has passed the address check.

[0121] The output control unit 55 is also used to obtain the address in the command and send the command to the hardware link according to the address.

[0122] The output control unit 55 is also used to send the address, enable bit, and disable bit in the command to the electronic device.

[0123] Among them, the electronic device includes but is not limited to: a drive module, a selector interface module.

[0124] It can be understood that during the processing of the output control unit 55, the address conversion involves mapping between 48 and 95 (on a 7-bit address) and 0 and 47 (on a 6-bit address). Specifically, the least significant bit remains unchanged during the address conversion to ensure data consistency. The calculated address and the enable / disable bit will be transmitted to the drive module and the selector interface module through execution pulses. The transmission of these pulses is based on the determination of the relevant address range and is sent to the hardware link (such as link A or link B) respectively.

[0125] To achieve this conversion, the circuit uses a 3-bit adder (or a 4-bit adder that ignores the least significant bit), and its carry signal is used to determine whether the current address belongs to a specific range, and selects the corresponding link A or link B according to the different address ranges. This design ensures the accuracy of the address conversion and can flexibly switch the address link as needed.

[0126] Specifically, the address conversion can be seen in Table 3.

[0127] Table 3

[0128]

[0129] The input / output circuit +5V14 is used to send the command to the electronic device when receiving the command; it is also used to send the target error report byte to the host computer when receiving the target error report byte.

[0130] The +5V input circuit also needs to be able to withstand an accidentally applied +48V voltage and limit it to approximately 2mA by controlling the current to ensure that the circuit will not be damaged in abnormal situations, thus providing safety protection. Specifically, refer to Figure 6 the schematic diagram of a +5V input circuit shown.

[0131] Refer to Figure 7 , the schematic diagram of a +5V output circuit shown. The +5V output circuit must have an output impedance compatible with the +5V input circuit to ensure the normal operation of the system and avoid problems such as signal loss or reflection. Secondly, considering possible accidental situations, the circuit design needs to be able to withstand an input voltage of up to +48V. This design ensures that the circuit can still work properly even in the case of accidental voltage. Finally, to protect the circuit safety, if an abnormal voltage situation occurs, the current should be limited to within approximately 2mA to prevent the circuit from overloading or being damaged, ensuring the stability and safety of the system.

[0132] It should be noted that to ensure the reliability and functionality of the communication interface module, each important function in the communication interface module must be equipped with test points, and if possible, the front panel should have status indicator LEDs. In addition, to improve the convenience of configuration, jumpers should be avoided. To prevent insertion errors or accidental short circuits (such as short circuits at 0V or +48V), sufficient protection must be provided for the input and output of the electronic board. It is worth noting that active circuits (such as transistors and optocouplers) should be arranged on the main board that can be inserted from the front of the rack and supplemented by "mezzanine" cards if necessary, while resistors, capacitors, inductors, diodes and other components are allowed to be used on the back of the rack. The size of the communication interface module must meet the standards, specifically 233.4 mm in height, 220 mm in diameter and length, and the front panel size should meet the IEC 60297-3 and DIN 41494 standards (261.9 mm x 19.9 mm). Finally, the device needs to be treated with varnish and equipped with two labeled handles for easy installation and operation.

[0133] In summary, this solution effectively reduces the dependence on software by implementing data serialization, longitudinal parity check, command checksum and error reporting mechanisms in the hardware circuit, thereby improving the reliability of the communication system in a radiation environment. Through hardware-level checksum and error detection, errors caused by radiation interference can be captured in a timely manner and error feedback can be provided to ensure the integrity of data and commands, avoid abnormal operation of the system, and enhance the stability and fault tolerance of the system in a harsh environment.

[0134] Corresponding to the communication interface module provided in the present application above, refer to Figure 8 , provided by an embodiment of the present application, including the following steps:

[0135] S801: Collect the status data to be transmitted through the input circuit with +48V.

[0136] S802: Serialize the status data to be transmitted through the logic processing circuit.

[0137] Optionally, the shift register in the logic processing circuit can be used to serialize the status to be transmitted, and the serialized status data to be transmitted is obtained.

[0138] S803: Perform vertical parity check on the serialized status data to be transmitted through the logic processing circuit.

[0139] It can be understood that performing a vertical parity check on the serialized status data to be transmitted is to check whether the 1s in the serialized status data to be transmitted satisfy the parity check rule; if the 1s in the serialized status data to be transmitted satisfy the parity check rule, it is determined that the serialized status data to be transmitted passes the check; if the 1s in the serialized status data to be transmitted do not satisfy the parity check rule, it is determined that the serialized status data to be transmitted fails the check.

[0140] S804: When the serialized status data to be transmitted passes the check, send the serialized status data to be transmitted to the host computer through the logic processing circuit.

[0141] Optionally, the host computer includes but is not limited to: the measurement and control cabinet.

[0142] S805: When receiving the command feedback by the host computer based on the serialized status data to be transmitted, check the command through the command receiving circuit.

[0143] It should be noted that checking the command through the command receiving circuit is to perform format check and address check on the command.

[0144] S806: When the command passes the check, send the command to the input / output circuit with +5V through the command receiving circuit.

[0145] S807: When the command fails the check, generate a target error report byte based on the command through the command receiving circuit, and send the target error report byte to the input / output circuit with +5V.

[0146] S808: When receiving the command, send the command to the electronic device through the input / output circuit with +5V.

[0147] Optionally, the electronic device includes but is not limited to: the drive module, the selector interface module.

[0148] S809: After receiving the target error report byte, send the target error report byte to the host computer through the input / output circuit +5V.

[0149] In summary, this solution effectively reduces the dependence on software by implementing data serialization, longitudinal parity check, command check, and error reporting mechanisms in the hardware circuit, thereby improving the reliability of the communication system in a radiation environment. Through hardware-level checksum and error detection, errors caused by radiation interference can be captured in a timely manner, and error feedback can be provided to ensure the integrity of data and commands, avoid abnormal system operation, and enhance the stability and fault tolerance of the system in a harsh environment.

[0150] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0151] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of the examples have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0152] The above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A communication interface module, characterized in that, Including: Input circuit +48V, logic processing circuit, command receiving circuit, and input / output circuit +5V; The input circuit +48V is used to collect the status data to be transmitted; The logic processing circuit is used to serialize the status data to be transmitted; the logic processing circuit is also used to perform vertical parity check on the serialized status data to be transmitted. When the serialized status data to be transmitted passes the check, the serialized status data to be transmitted is sent to the host computer; The command receiving circuit is used to check the command when receiving the command fed back by the host computer based on the serialized status data to be transmitted; When the command passes the check, the command is sent to the output circuit; When the command fails to pass the check, a target error report byte is generated based on the command and the target error report byte is sent to the output circuit; The input / output circuit +5V is used to send the command to the electronic device when receiving the command; It is also used to send the target error report byte to the host computer when receiving the target error report byte.

2. The communication interface module according to claim 1, characterized in that The logic processing circuit includes: a clock unit, a shift register, and a line driver; The clock unit is used to set the time base transmitted to the host computer and send the time base to the shift register and the line driver; The shift register is used to serialize the status data to be transmitted according to the time base when receiving the time base, perform vertical parity check on the serialized status data to be transmitted, and transmit the serialized status data to be transmitted that passes the check to the line driver; The line driver is used to send the serialized status data to be transmitted to the host computer according to the time base after receiving the serialized status data to be transmitted and the time base.

3. The communication interface module according to claim 2, wherein The shift register is further used to obtain and invert the status data to be transmitted according to the valid level of the status data to be transmitted, and store the processed status data to be transmitted after obtaining the processed status data to be transmitted.

4. The communication interface module according to claim 2, wherein The shift register for performing vertical parity check on the serialized status data to be transmitted specifically is used for: Calculating the number of 1s in the serialized status data to be transmitted to obtain the total number; Judging whether the total number conforms to the parity check rule; If the total number conforms to the parity check rule, it is determined that the serialized status data to be transmitted passes the check; If the total number does not conform to the parity check rule, it is determined that the serialized status data to be transmitted fails to pass the check.

5. The communication interface module according to claim 1, wherein The command receiving circuit includes: a byte receiving unit, a byte control unit, a dialogue management unit, a transmission feedback unit, and an output control unit; The byte receiving unit is used to check the format of the command when receiving the command fed back by the host computer based on the serialized status data to be transmitted, and send the command that passes the format check to the byte control unit; The byte control unit is configured to perform address verification on the command when the command is received; if the command fails the address verification, the command that fails the address verification is sent to the dialogue management unit; if the command passes the address verification, the command that passes the address verification is sent to the output control unit; The dialogue management unit is configured to generate an error report byte based on the command that fails the address verification and send the error report byte to the transmission feedback unit when the command that fails the address verification is received; The transmission feedback unit is configured to add a start bit, a parity bit, and a stop bit to the error report byte to obtain a target error report byte and send the target error report byte to the host computer through the output circuit when the error report byte is received; The output control unit is configured to send the command that passes the address verification to the output circuit when the command that passes the address verification is received; 6. The communication interface module according to claim 5, wherein The transmission feedback unit is further configured to send the acknowledgment signal to the dialogue management unit when the acknowledgment signal based on the target error report byte is received from the host computer; The dialogue management unit is further configured to send the acknowledgment signal to the output control unit when the acknowledgment signal is received; 7. The communication interface module according to claim 5, wherein The byte receiving unit is further configured to generate a valid pulse when the command passes the format verification; and is further configured to generate a data reception pulse when the command fails the format verification.

8. The communication interface module according to claim 1, wherein The output control unit is further configured to obtain the address in the command and send the command to the hardware link according to the address.

9. The communication interface module according to claim 8, wherein The output control unit is further configured to send the address, the enable bit, and the disable bit in the command to the electronic device.

10. A method for using a communication interface module, characterized in that, Applied to the communication interface module according to any one of claims 1-9 above, including: Collecting the status data to be transmitted through the input circuit +48V; Serializing the status data to be transmitted through the logic processing circuit; Performing longitudinal parity check on the serialized status data to be transmitted through the logic processing circuit; When the serialized status data to be transmitted passes the check, sending the serialized status data to be transmitted to the host computer through the logic processing circuit; When the command feedback from the host computer based on the serialized status data to be transmitted is received, verifying the command through the command receiving circuit; When the command passes the verification, sending the command to the input / output circuit +5V through the command receiving circuit; When the command fails the verification, generating a target error report byte based on the command through the command receiving circuit and sending the target error report byte to the input / output circuit +5V; After receiving the command, send the command to the electronic device through the input / output circuit +5V; After receiving the target error report byte, send the target error report byte to the host computer through the input / output circuit +5V.

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