Management board, universal substrate and monitoring method

Abstract

The present application provides a management board, a universal substrate, and a monitoring method, which can be applied to the field of server technology. The management board includes: a processing unit for selecting a target firmware from a plurality of firmwares based on the type of universal substrate, and configuring a logic unit through the target firmware to adapt the management board to the target type of universal substrate; a bus interface unit for electrically connecting the management board to an accelerated computing module disposed on the universal substrate; and a logic unit electrically connected to the bus interface unit for processing data from the accelerated computing module to monitor the accelerated computing module.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a management board, a universal substrate, and a monitoring method. Background Art

[0002] In the fields of artificial intelligence and high-performance computing, the Universal Baseboard (UBB), the core carrier of open accelerator infrastructure, requires the coordinated management of multiple Open Compute Project Accelerator Modules (OAM) via the headboard motherboard. However, in related technologies, the headboard motherboard and the UBB are designed independently, resulting in problems such as poor hardware reusability, insufficient protocol compatibility, weak real-time monitoring capabilities, and inefficient resource utilization for the management board used on the UBB. Summary of the Invention

[0003] In view of the above problems, the present application provides a management board, a universal substrate and a monitoring method.

[0004] According to the first aspect of the present application, a management board is provided, comprising: a processing unit for selecting a target firmware from a plurality of firmwares based on the type of a universal substrate, and configuring a logic unit through the target firmware so that the management board adapts to the universal substrate of the target type; a bus interface unit for realizing an electrical connection between the management board and an accelerated computing module arranged on the universal substrate; and the logic unit, electrically connected to the bus interface unit, for processing data from the accelerated computing module to realize monitoring of the accelerated computing module.

[0005] According to an embodiment of the present application, the above-mentioned management board also includes: a first memory for storing logic unit firmware; a second memory for storing data from the above-mentioned accelerated computing module and monitoring results of the above-mentioned accelerated computing module; a debugging interface for connecting the above-mentioned processing unit with the above-mentioned logic unit; and reconfigurable hardware, including a preset number of logic units.

[0006] According to an embodiment of the present application, the above-mentioned management board also includes: a power management unit, connected to the above-mentioned logic unit, for supplying power to the above-mentioned accelerated computing module; a clock generator, connected to the above-mentioned logic unit, for providing a clock signal to the above-mentioned accelerated computing module.

[0007] According to an embodiment of the present application, the above-mentioned bus interface unit includes: a data bus, used to electrically connect the serializer / deserializer on the above-mentioned management board with the serializer / deserializer on the above-mentioned accelerated computing module to realize data interaction between the above-mentioned management board and the above-mentioned accelerated computing module; the above-mentioned serializer / deserializer is used for conversion between serial data and parallel data.

[0008] According to an embodiment of the present application, the above-mentioned management board also includes: a monitoring unit, which is used to collect eye diagram parameters from the above-mentioned accelerated computing module and trigger a fault response when the above-mentioned eye diagram parameters do not meet preset conditions; and parse the data transmission protocol between the above-mentioned management board and the above-mentioned accelerated computing module to monitor protocol layer faults.

[0009] According to an embodiment of the present application, the management board further includes: a diagnostic engine for locating a fault position of the accelerated computing module and performing recovery processing on the faulty accelerated computing module.

[0010] According to an embodiment of the present application, the management board further includes a layered dynamic software system, which includes a hardware layer, a management layer, and an application interface layer.

[0011] According to an embodiment of the present application, the above-mentioned hardware layer is used to provide a unified interface for the above-mentioned management board so that the above-mentioned management board can be adapted to the hardware of various types of universal substrates; device enumeration and hot-plug detection are implemented for the above-mentioned accelerated computing module to obtain detection results; and an accelerated computing module list is generated based on the above-mentioned detection results, wherein the above-mentioned accelerated computing module list includes at least one of the connection status, hot-plug status, load and data transmission rate of the above-mentioned accelerated computing module.

[0012] According to an embodiment of the present application, the above-mentioned management layer also includes: a power and clock management module, which is used to adjust the current output of the above-mentioned power management unit according to the load of the above-mentioned accelerated computing module in the above-mentioned accelerated computing module list; and adjust the frequency of the clock signal output by the above-mentioned clock generator according to the data transmission rate in the above-mentioned accelerated computing module list.

[0013] According to an embodiment of the present application, the above-mentioned management layer also includes: a protocol parsing module, which is used to control the above-mentioned monitoring unit to parse the data transmission protocol according to a preset priority; and control the above-mentioned logic unit to process the data from the above-mentioned accelerated computing module to generate a monitoring result for the above-mentioned accelerated computing module.

[0014] According to an embodiment of the present application, the management board further includes a fault detection module for: controlling the diagnosis engine to perform fault detection on the accelerated computing module based on a preset fault knowledge base; and performing a fault response when a fault is detected.

[0015] According to an embodiment of the present application, the above-mentioned application interface layer includes: an onboard interactive interface for displaying the status of the above-mentioned accelerated computing module in real time; a remote management interface for obtaining the status of the above-mentioned management board and issuing configuration instructions for the above-mentioned management board.

[0016] A second aspect of the present application provides a universal substrate, which is integrated with the management board.

[0017] According to an embodiment of the present application, the universal substrate includes an accelerated computing module disposed on a side of the universal substrate close to the bus interface unit of the management board.

[0018] The third aspect of the present application provides a monitoring method, which uses the above-mentioned management board and is characterized in that the above-mentioned method includes: in response to detecting that the universal substrate is powered on, using the processing unit to select target firmware from multiple firmware based on the type of the universal substrate, and configuring the logic unit through the above-mentioned target firmware to make the above-mentioned management board adapt to the above-mentioned universal substrate of the target type; using the bus interface unit to realize the electrical connection between the above-mentioned management board and the accelerated computing module arranged on the above-mentioned universal substrate; using the above-mentioned logic unit to process the data from the above-mentioned accelerated computing module to realize the monitoring of the above-mentioned accelerated computing module.

[0019] According to the management board, universal substrate and monitoring method of the present application, the processing unit is adapted to the logic unit, that is, the processing unit and the logic unit work together, and the processing unit can select the target firmware according to the type of universal substrate into which the management board is integrated, and configure the logic unit with the target firmware, so that the management board can adapt to the universal substrate into which it is integrated. Thus, based on the different types of universal substrates integrated, the processing unit can adapt to different types of universal substrates by configuring the logic unit with different firmware. On this basis, the management board of the present application can support more than 80% of universal substrate types without the need to redesign the hardware, shorten the R&D cycle by 70%, reduce the hardware development cost by 50%, and adapt to the rapid iteration of the accelerated computing module. In addition, the hardware acceleration engine of the logic unit realizes real-time analysis of 200Gbps-level data, meeting the real-time monitoring requirements of the high-speed bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram of a management board according to an embodiment of the present application is shown;

[0022] Figure 2 A schematic diagram of a storage and configuration unit on a management board according to an embodiment of the present application is shown;

[0023] Figure 3 A schematic diagram of a power supply and clock subsystem on a management board according to an embodiment of the present application is shown;

[0024] Figure 4A schematic diagram showing the connection between the power supply, the clock subsystem, and the logic unit according to an embodiment of the present application is shown;

[0025] Figure 5 A schematic diagram of a hierarchical dynamic software system on a management board according to an embodiment of the present application is shown;

[0026] Figure 6 A schematic diagram of an application interface layer on a management board according to an embodiment of the present application is shown;

[0027] Figure 7 A schematic diagram of a management board according to another embodiment of the present application is shown;

[0028] Figure 8 A flow chart of a monitoring method according to an embodiment of the present application is shown;

[0029] Figure 9 A flowchart of a management board application according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0031] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0033] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0034] In the process of implementing this application, it was found that for the management board used on the UBB board, the solutions in the relevant technology include the following: an independent head management board, a distributed control architecture and an external management unit.

[0035] For the independent head management board, a dedicated hardware design is used, which is connected to the UBB board through a low-speed bus. However, it only supports power monitoring of specific OAM modules and is not compatible with the CXL protocol (Compute Express Link Protocol) module.

[0036] For a distributed control architecture, power management, clock generation, and protocol analysis are distributed to multiple chips and interconnected through PCB (Printed Circuit Board) routing. For example, the power management chip, clock generator, and ASIC (Application-Specific Integrated Circuit) analysis chip are deployed independently. However, this will cause the data exchange delay between chips to exceed 10μs, and fault diagnosis requires cross-module coordination.

[0037] For external management units, an external management controller is connected through an RJ45 (Registered Jack 45) or USB (Universal Serial Bus) interface. However, this relies on network transmission for remote monitoring, such as traditional server management solutions, resulting in poor real-time performance (error reporting delay exceeds 50μs) and inability to directly access the underlying signals of the high-speed bus.

[0038] Therefore, in the related technologies, the management board used on the UBB board has the following problems: hardware customization requires independent design of management boards for different models of UBB boards, which results in a long R&D cycle (single design cycle exceeds 6 months) and high cost (hardware repeated development cost increases by 40%), and is unable to adapt to the rapid iteration of market demand, resulting in high reuse costs; the software parsing engine is rigid and only supports fixed bus protocols. When new protocols are added, the hardware logic needs to be redeveloped and designed or the firmware needs to be upgraded. For example, supporting CXL3.0 requires an additional investment of 2000+ man-hours, and the cycle is as long as 9 months, which lags behind in technology iteration, resulting in single protocol support and insufficient protocol compatibility; high-speed bus data parsing relies on software to be gradually updated. Packet processing results in long delays, making it impossible to meet the microsecond-level synchronization requirements between OAM modules and to capture complete signals in real time. This reduces system throughput by more than 15%, reduces fault location efficiency, and leads to weak real-time monitoring capabilities. The independent head is separated from the UBB board, and hardware resources such as power filtering and clock buffering cannot be shared, resulting in an increase of more than 25% in system power consumption. In addition, the redundant board layout occupies more than 30% of the board area in high-density computing scenarios, resulting in inefficient resource utilization. Independent components increase board complexity, the power conversion efficiency is only 85%, and the clock synchronization error exceeds 100ps, affecting the stability of high-speed data transmission and resulting in insufficient integration.

[0039] To this end, an embodiment of the present application provides a management board to solve the problems of poor hardware reusability, insufficient protocol compatibility, weak real-time monitoring capabilities, and inefficient resource utilization existing in the management board in related technologies.

[0040] Figure 1 A schematic diagram of a management board according to an embodiment of the present application is shown.

[0041] like Figure 1 As shown, the management board 110 is arranged on the universal substrate 100 , the universal substrate 100 is provided with an OAM (accelerated computing module), and the management board 110 is provided with a processing unit 111 , a logic unit 112 and a bus interface unit 113 .

[0042] In one embodiment, the universal substrate 100 may have eight accelerated computing modules, such as Figure 1 The accelerated computing module 1, accelerated computing module 2, ..., accelerated computing module 8 shown in FIG.

[0043] In one embodiment, the processing unit 111 may be an AST2600 (AST2600 Baseboard Management Controller) processing unit.

[0044] Specifically, the processing unit 111 is connected to the logic unit 112 and can be used to select a target firmware from multiple firmware based on the type of the universal substrate 100, and configure the logic unit 112 through the target firmware to make the management board 110 adapt to the universal substrate 100 of the target type.

[0045] According to an embodiment of the present application, when the management board is integrated into a universal substrate, a target firmware corresponding to the universal substrate can be selected based on the type of the universal substrate to be integrated into. The target firmware configures the logic unit so that the management board adapts to the universal substrate to which it is integrated.

[0046] The target firmware may be used to represent firmware related to the logic unit and to configure the logic unit.

[0047] Since different types of universal baseboards have different requirements, the management board must adapt to the universal baseboard and meet the requirements of the universal baseboard. Therefore, the target firmware can be selected according to the type of universal baseboard into which the management board is integrated.

[0048] In one embodiment, the processing unit 111 may be responsible for system resource scheduling, remote communication, and user interaction logic, and support dynamic loading of accelerated computing module drivers to achieve software flexibility.

[0049] According to an embodiment of the present application, the bus interface unit 113 can be used to realize the electrical connection between the management board 110 and the accelerated computing module arranged on the universal substrate 100 to ensure the stability of data transmission between the management board and the accelerated computing module.

[0050] In one embodiment, the logic unit 112 may be a Field-Programmable Gate Array (FPGA).

[0051] Specifically, the logic unit 112 can be electrically connected to the bus interface unit 113 to process data from the accelerated computing module to monitor the accelerated computing module.

[0052] In one embodiment, the logic unit 112 can implement a high-speed protocol pre-processing engine with a single-channel data processing rate greater than or equal to 200 Gbps, and support parallel processing of data from 8-way accelerated computing modules to achieve hardware accelerated parsing.

[0053] Based on the above content, the management board 110 adopts a collaborative design of the processing unit 111 and the logic unit 112 to form a hybrid architecture of "software control + hardware acceleration". This hybrid architecture is also a heterogeneous processing architecture, which combines software flexibility with hardware acceleration and supports dynamic protocol loading and high-speed data parallel processing.

[0054] According to an embodiment of the present application, the processing unit is adapted to the logic unit, that is, the processing unit and the logic unit work together, and the processing unit can select the target firmware according to the type of universal substrate into which the management board is integrated, and configure the logic unit with the target firmware, so that the management board can adapt to the universal substrate into which it is integrated. Thus, based on the different types of universal substrates integrated, the processing unit can adapt to different types of universal substrates by configuring the logic unit with different firmware. On this basis, the management board of the present application can support more than 80% of universal substrate types without the need to redesign the hardware, shorten the R&D cycle by 70%, reduce the hardware development cost by 50%, and adapt to the rapid iteration of the accelerated computing module. In addition, the hardware acceleration engine of the logic unit realizes real-time analysis of 200Gbps-level data, meeting the real-time monitoring requirements of the high-speed bus.

[0055] Figure 2 A schematic diagram of a storage and configuration unit on a management board according to an embodiment of the present application is shown.

[0056] like Figure 2 As shown, a storage and configuration unit 200 is further arranged on the management board. The storage and configuration unit 200 may include a first memory 210 , a second memory 220 , a debugging interface 230 and reconfigurable hardware 240 .

[0057] In one embodiment, the first memory 210 may be Flash Memory.

[0058] Specifically, the first memory 210 can be used to store logic unit firmware.

[0059] The logic unit firmware may represent firmware related to the logic unit.

[0060] According to an embodiment of the present application, since the logic unit firmware is stored in the first memory 210, the processing unit 111 can select the target firmware corresponding to the type of the universal substrate 100 from the logic unit firmware stored in the first memory 210, so that the management board 110 is adapted to the universal substrate 100.

[0061] According to an embodiment of the present application, the first memory 210 can also be used to store management board firmware, protocol parsing rule library, accelerated computing module firmware library, etc., supporting remote online upgrades, shortening firmware update time and facilitating technology iteration and maintenance.

[0062] In one embodiment, the second memory 220 may be 4GB LPDDR4 (Low-Power Double Data Rate 4).

[0063] Specifically, the second memory 220 can be used to store data from the accelerated computing module and monitoring results of the accelerated computing module.

[0064] According to an embodiment of the present application, the second memory 220 can serve as a high-speed data buffer to store real-time data collected from the accelerated computing module and monitoring results of the accelerated computing module. As a result, the second memory 220 can support dual-channel reading and writing, meeting the needs of high-speed data caching.

[0065] In one embodiment, the debug interface 230 may be a JTAG (Joint Test Action Group) debug interface.

[0066] Specifically, the debugging interface 230 can connect the processing unit 111 and the logic unit 112 , that is, the processing unit 111 and the logic unit 112 can be connected through the debugging interface 230 .

[0067] According to an embodiment of the present application, the debugging interface 230 supports the processing unit 111 to perform online debugging of the hardware logic and configuration loading of the logic unit 112. By cooperating with the onboard dip switch, the working mode of the management board can be manually switched to facilitate debugging and configuration.

[0068] In one embodiment, the reconfigurable hardware 240 refers to a logic unit.

[0069] Specifically, the reconfigurable hardware 240 includes a preset number of logic units.

[0070] The preset number can be set as needed.

[0071] For example, the preset number of logic units may be logic units accounting for 20% of all logic units, that is, 20% of the logic units are reserved.

[0072] Specifically, the reconfigurable hardware 240 supports dynamic loading of new protocol parsing IP (Intellectual Property) cores through software instructions, that is, configuring logic units through target firmware, so that there is no need for hardware revisions, and the hardware reuse rate is increased to more than 80%.

[0073] Thus, the processing unit 111 may configure a preset number of logic units reserved by the target firmware.

[0074] According to the embodiments of the present application, online upgrades are supported through the first memory, and the firmware update time is short; high-speed data cache requirements are met through the second memory; online debugging and logic unit configuration loading are supported through the debugging interface; and through reconfigurable hardware, there is no need for hardware revisions, and the hardware reuse rate is increased to more than 80%.

[0075] Figure 3 A schematic diagram of a power supply and clock subsystem on a management board according to an embodiment of the present application is shown.

[0076] like Figure 3 As shown, a power supply and clock subsystem 300 is also arranged on the management board. The power supply and clock subsystem 300 includes a power management unit 310 and a clock generator 320 .

[0077] According to an embodiment of the present application, the power management unit 310 can be connected to the logic unit 112 to provide power to the accelerated computing module.

[0078] Specifically, the power management unit 310 supports 54V / 48V main power input and 12V auxiliary power supply. The power management unit 310 can power 8 independent accelerated computing modules through a multi-phase power controller, and can dynamically adjust the power of each accelerated computing module. It can also provide overcurrent protection for each accelerated computing module and respond in a timely manner.

[0079] In one embodiment, the power and clock subsystem 300 may further include an integrated power status sensor for real-time monitoring of the voltage, current, and temperature of the power supply on the management board 110 to achieve intelligent distribution and protection of the power supply.

[0080] According to an embodiment of the present application, the clock generator 320 may also be connected to the logic unit 112 to provide a clock signal to the accelerated computing module.

[0081] Specifically, clock generator 320 uses a high-precision differential crystal oscillator combined with a clock recovery circuit to generate a reference clock. A low-jitter clock buffer is used to reduce jitter in the reference clock and distribute the reduced-jitter clock signal to each accelerated computing module, ensuring low clock phase error between the modules. Furthermore, clock generator 320 supports dynamic clock frequency switching to ensure high-speed data acquisition synchronization for each accelerated computing module.

[0082] Figure 4 A schematic diagram of the connection between the power supply, the clock subsystem and the logic unit according to an embodiment of the present application is shown.

[0083] like Figure 4 As shown, the power management unit 310 and the clock generator 320 in the power and clock subsystem 300 disposed on the management board are both connected to the logic unit 112 .

[0084] Specifically, the power management unit 310 can be connected to the logic unit 112 via a low-impedance power line, and the clock generator 310 can be connected to the logic unit 112 via a low-impedance clock line. Therefore, using low-impedance power lines and clock lines to connect can reduce noise interference.

[0085] According to the embodiments of the present application, the power management unit supports dynamic power regulation and timely overcurrent protection response; the clock generator supports dynamic clock frequency switching to ensure high-speed data acquisition synchronization.

[0086] According to an embodiment of the present application, the bus interface unit includes: a data bus, used to electrically connect the serializer / deserializer on the management board with the serializer / deserializer on the accelerated computing module to realize data interaction between the management board and the accelerated computing module; a serializer / deserializer, used to convert serial data into parallel data.

[0087] According to an embodiment of the present application, the bus interface unit 113 disposed on the management board 110 may include a data bus and a serializer / deserializer.

[0088] Since serial transmission can significantly improve transmission efficiency and reduce the number of physical cables in high-speed data transmission, the communication between the management board and the accelerated computing module is carried out through the data bus and is transmitted in a serial data format.

[0089] Specifically, the management board 110 may be provided with a first serializer and a first deserializer, and the accelerated computing module may be provided with a second serializer and a second deserializer.

[0090] In one embodiment, the data bus can be used to connect the first serializer on the management board 110 with the second deserializer on the accelerated computing module, and can also be used to connect the first deserializer on the management board 110 with the second serializer on the accelerated computing module.

[0091] Specifically, during data transmission from the management board 110 to the accelerated computing module, the first serializer on the management board 110 can be used to convert the parallel data from the management board into serial data and send it to the data bus, which then transmits the serial data to the accelerated computing module. The second deserializer on the accelerated computing module can convert the received serial data into parallel data for processing by the accelerated computing module. The data conversion process during data transmission from the accelerated computing module to the management board 110 is similar and will not be further described here.

[0092] In one embodiment, the serializer / deserializer may be a Serializer / Deserializer; the data bus may be a high-speed data bus for high-speed data interaction between the management board and the accelerated computing module, thereby realizing rapid transmission of fault logs and configuration parameters.

[0093] In another embodiment, the bus interface unit may also include a low-speed control bus, which can be multiple I2C (Inter-Integrated Circuit) buses supporting communication rates of 100kHz-400kHz. The low-speed control bus can connect the management board to the sensors on the universal substrate and the configuration registers on the accelerated computing module. This allows for simultaneous access to multiple devices, increasing the frequency of data acquisition and enabling real-time interaction of low-speed data.

[0094] According to an embodiment of the present application, when an 8-way accelerated computing module is arranged on the universal substrate 100, a high-speed data path is arranged on the management board 110, and the high-speed data path can integrate 8 sets of SerDes (Serializer / Deserializer) hard cores.

[0095] Specifically, the high-speed data path supports high-speed interfaces and dynamically configures PHY layer (physical layer) parameters to adapt to the signal characteristics of different accelerated computing modules. Impedance matching of the high-speed data path is controlled at 50Ω±5% to ensure stable high-speed signal transmission.

[0096] According to an embodiment of the present application, data is transmitted between the management board and the accelerated computing module through a serializer / deserializer and a data bus, which can achieve rapid data transmission while ensuring the stability of high-speed signal transmission.

[0097] According to an embodiment of the present application, the management board also includes: a monitoring unit for collecting eye diagram parameters from the accelerated computing module and triggering a fault response when the eye diagram parameters do not meet preset conditions; and parsing the data transmission protocol between the management board and the accelerated computing module to monitor protocol layer faults.

[0098] According to an embodiment of the present application, a monitoring unit is further provided on the management board 110 , and the monitoring unit can be used to perform signal integrity monitoring and protocol layer error detection.

[0099] Specifically, for signal integrity monitoring, the monitoring unit can collect eye diagram parameters from the accelerated computing module in real time, that is, it can collect SerDes signal eye diagram parameters in real time.

[0100] In one embodiment, the signal transmitted on the SerDes is analyzed in real time to obtain eye diagram parameters to evaluate the quality and transmission performance of the transmitted signal.

[0101] The preset condition may indicate that the acquired eye diagram parameters do not exceed a preset range, and the preset range is set according to needs.

[0102] According to an embodiment of the present application, when the collected eye diagram parameters exceed a preset range, the collected eye diagram parameters do not meet a preset condition, and a fault response may be triggered.

[0103] Specifically, the monitoring unit supports parallel monitoring of 8-way accelerated computing modules and provides real-time feedback on the quality of transmitted data.

[0104] According to an embodiment of the present application, for protocol layer error detection, the monitoring unit can parse the data transmission protocol between the management board and the accelerated computing module, and monitor the protocol layer fault based on the parsed errors.

[0105] In one embodiment, the data transmission protocol may include PCI-ETLP packets (PCI Express Transaction Layer Packet), CXL instructions (Compute Express Link), and Gen-Z messages (Generation Z).

[0106] According to the embodiments of the present application, the data transmission protocol is parsed, mainly analyzing the request / response delay of the CXL protocol, the ECRC (End-to-End Cyclic Redundancy Check) error of PCI-E, and the sequence error. The error type is counted through hardware counters, and the statistical results are updated every second to achieve real-time detection of protocol layer faults.

[0107] According to an embodiment of the present application, the monitoring unit supports real-time monitoring of the accelerated computing module, real-time feedback of signal quality, and real-time monitoring of protocol layer faults.

[0108] According to an embodiment of the present application, the management board further includes: a diagnosis engine for locating a fault position of the accelerated computing module and performing recovery processing on the faulty accelerated computing module.

[0109] According to an embodiment of the present application, a diagnosis engine is also provided on the management board 110. The diagnosis engine can be used to locate the fault location of the accelerated computing module and to execute a self-healing mechanism.

[0110] Specifically, the diagnosis engine can track bus state transitions based on a finite state machine and, combined with a Bayesian network algorithm, locate the fault hierarchy and quickly locate the fault location of the fault point in the accelerated computing module.

[0111] The finite state machine tracking bus state transition refers to managing and controlling different states of the bus in the system by means of a finite state machine, and tracking the transition process of the bus state.

[0112] Specifically, the diagnosis engine can also execute a self-healing mechanism to recover the faulty acceleration computing module when it detects that there is a communication anomaly in the acceleration computing module.

[0113] In one embodiment, the self-healing mechanism may include automatically restarting the power supply corresponding to the accelerated computing module, resetting the link, etc.

[0114] According to an embodiment of the present application, the diagnostic engine also supports the isolation of faulty accelerated computing modules and system downtime, thereby improving system reliability.

[0115] According to the embodiments of this application, through the hardware circuit co-grounding design and intelligent self-healing mechanism, anti-interference capabilities are improved, making it suitable for harsh industrial environments. At the same time, the fault location algorithm based on finite state machines and Bayesian networks can achieve microsecond-level abnormal response and system recovery, improving system reliability.

[0116] Figure 5 A schematic diagram of a hierarchical dynamic software system on a management board according to an embodiment of the present application is shown.

[0117] like Figure 5 As shown, a layered dynamic software system 500 is also deployed on the management board. The layered dynamic software system 500 may include a hardware layer 510 , a management layer 520 and an application interface layer 530 .

[0118] Based on the above content, the processing unit 111, bus interface unit 113, logic unit 112, storage and configuration unit 200, power supply and clock subsystem 300, data bus, serializer / deserializer, monitoring unit and diagnostic engine arranged on the management board 110 belong to the hardware architecture on the management board 110.

[0119] According to the embodiments of the present application, the architecture of "heterogeneous hardware fusion + layered software collaboration" is adopted, and hardware reuse and protocol adaptation of the head and the universal substrate can be achieved through standardized interfaces.

[0120] According to an embodiment of the present application, the hardware layer is used to provide a unified interface for the management board to enable the management board to adapt to the hardware of various types of universal substrates; implement device enumeration and hot-plug detection for the accelerated computing module to obtain detection results; generate an accelerated computing module list based on the detection results, wherein the accelerated computing module list includes at least one of the connection status, hot-plug status, load and data transmission rate of the accelerated computing module.

[0121] According to an embodiment of the present application, the hardware layer 510 is responsible for encapsulating hardware interface drivers, specifically including a power management unit driver, a clock generator driver, and a SerDes PHY (Serializer / Deserializer Physical Layer) control interface.

[0122] Specifically, the hardware layer 510 also provides a unified API (Application Programming Interface) for the management board 110 to call.

[0123] Therefore, the management board can be compatible with the hardware of various types of universal baseboards, shielding the hardware differences between different types of universal baseboards and achieving hardware independence.

[0124] In addition, the hardware layer 510 is also used to implement device enumeration and hot plug detection for the accelerated computing module, and obtain the detection results, thereby generating an accelerated computing module list based on the detection results.

[0125] Device enumeration refers to identifying and listing all currently connected hardware devices, that is, listing all currently connected accelerated computing modules.

[0126] Specifically, the hardware layer 510 detects whether a new accelerated computing module has been connected to obtain the connection status of the accelerated computing module. When an accelerated computing module is inserted or removed, the hardware layer 510 senses the change in hot-plug status and triggers an interrupt or event. Hot-plug detection ensures that the accelerated computing module can be automatically identified when inserted and that related resources are promptly cleaned up when removed. The detection results may include the detected connection status of the accelerated computing module and the hot-plug status of the accelerated computing module.

[0127] Thus, a list of accelerated computing modules can be generated based on the detection results.

[0128] After the hardware layer identifies a new accelerated computing module and generates a list of accelerated computing modules, it automatically loads the protocol parsing plug-in associated with the new module, enabling plug-and-play. Furthermore, the list of accelerated computing modules is updated whenever a new module is added or the status of an existing module changes.

[0129] According to the embodiments of this application, the hardware layer, through a unified interface, can shield hardware differences between different universal baseboards, achieving hardware independence and automatically loading corresponding protocol parsing plug-ins, supporting plug-and-play. Furthermore, the hardware layer can automatically adapt to new devices when hardware changes occur and generate or update the accelerated computing module list without intervention, greatly improving system usability and user experience.

[0130] According to an embodiment of the present application, the management layer also includes: a power and clock management module, which is used to adjust the current output of the power management unit according to the load of the accelerated computing module in the accelerated computing module list; and adjust the frequency of the clock signal output by the clock generator according to the data transmission rate in the accelerated computing module list.

[0131] According to an embodiment of the present application, the management layer 520 in the layered dynamic software system 500 further includes a power and clock management module, which can be used to implement dynamic power allocation and clock frequency adaptation.

[0132] According to an embodiment of the present application, for dynamic power allocation, the power and clock management module can be used to adjust the current output of the power management unit 310 according to the load of the accelerated computing module in the accelerated computing module list, thereby realizing dynamic power allocation.

[0133] Specifically, the power and clock management module can adjust the output current of the power management unit through hardware PWM (Pulse Width Modulation) according to the load of the accelerated computing module.

[0134] For example, the power management unit supports a 54V main power supply, and the power and clock management module can adjust the output current of the 54V main power supply through hardware PWM.

[0135] According to an embodiment of the present application, the power supply and clock management module supports energy-saving mode and full-load mode, and can be used to integrate thermal power consumption limiting protection, prevent overheating and frequency reduction, and improve energy efficiency.

[0136] According to an embodiment of the present application, for clock frequency adaptation, the power and clock management module can adjust the frequency of the clock signal output by the clock generator 320 according to the data transmission rate.

[0137] In one embodiment, the power and clock management module can achieve glitch-free switching through a hardware phase-locked loop to ensure optimal utilization of clock resources.

[0138] According to the embodiments of the present application, the power supply and clock management module can dynamically adjust power and adapt clock frequency, so that the system energy efficiency ratio is improved, the full load power consumption is reduced, the idle state power consumption is reduced, and the heat dissipation and energy saving requirements of high-density data centers are adapted.

[0139] According to an embodiment of the present application, the management layer also includes: a protocol parsing module, which is used to control the monitoring unit to parse the data transmission protocol according to a preset priority; and a control logic unit to process data from the accelerated computing module to generate monitoring results for the accelerated computing module.

[0140] According to an embodiment of the present application, the management layer 520 may further include a protocol parsing module, which may be configured to parse the data transmission protocols in sequence according to priority.

[0141] Specifically, when the data transmission protocol includes PCI-E LP packets, CXL instructions, and Gen-Z messages, the priority order can be CXL memory access, PCI-E configuration access, and normal data transmission. Therefore, parsing CXL memory access, PCI-E configuration access, and normal data transmission in sequence can improve parsing efficiency.

[0142] In one embodiment, the protocol parsing module may schedule parsing tasks through a software queue and parse the data transmission protocols in sequence according to priority.

[0143] According to an embodiment of the present application, the protocol parsing module is also used to control the logic unit 112 to process data from the accelerated computing module to generate monitoring results for the accelerated computing module.

[0144] Specifically, the monitoring results may include the real-time throughput curve of the accelerated computing module, the error rate histogram, the bus utilization report, etc.

[0145] In one embodiment, the monitoring results of the accelerated computing module can be stored in the second memory 220 and uploaded to the remote management platform through the IPMI (Intelligent Platform Management Interface) interface to facilitate real-time monitoring and data analysis.

[0146] According to the embodiments of this application, through the protocol parsing module, the hardware acceleration engine can achieve real-time parsing of 200Gbps-level data with low parsing latency and fast error detection response time, meeting the real-time monitoring requirements of high-speed buses and reducing fault location time from minutes to seconds. Furthermore, it can implement layered parsing from the physical layer to the transaction layer, supporting hybrid processing and priority scheduling of protocols such as CXL and PCI-E, thereby improving parsing efficiency.

[0147] According to an embodiment of the present application, the management layer also includes: a fault detection module, which is used to control the diagnosis engine to perform fault detection on the accelerated computing module based on a preset fault knowledge base; and to perform a fault response when a fault is detected.

[0148] According to an embodiment of the present application, the management layer 520 may further include a fault detection module, which may be used for fault detection and fault response.

[0149] In one embodiment, a preset fault knowledge base may be pre-established, which may include more than 200 bus error codes. The fault detection module determines the fault of the accelerated computing module from the preset fault knowledge base to a certain extent.

[0150] According to an embodiment of the present application, the fault detection module can control the diagnosis engine to perform fault detection on the accelerated computing module based on a preset fault knowledge base.

[0151] Specifically, based on the preset fault knowledge base, the fault detection module supports rule-based rapid diagnosis and machine learning-based anomaly prediction to improve fault handling efficiency.

[0152] According to an embodiment of the present application, when the fault detection module detects that the accelerated computing module has a fault, a fault response can be performed.

[0153] In one embodiment, the fault detection module supports three levels of fault response. Specifically, the three levels of fault response may include warning, degradation, and shutdown.

[0154] Among them, the fault response strategy can be customized through the remote management interface to meet the needs of different scenarios.

[0155] According to the embodiments of the present application, the fault detection module performs fault detection on the accelerated computing module based on a preset fault knowledge base, thereby improving fault handling efficiency and supporting different fault response strategies to meet the needs of different scenarios.

[0156] Figure 6 A schematic diagram of the application interface layer on the management board according to an embodiment of the present application is shown.

[0157] like Figure 6 As shown, the application interface layer 530 may include an onboard interactive interface 610 and a remote management interface 620 .

[0158] In one embodiment, the onboard interactive interface 610 can be used to display the status of the accelerated computing module in real time.

[0159] Specifically, the onboard interactive interface 610 may display the status of the accelerated computing module in real time through an OLED (Organic Light Emitting Diode) display screen.

[0160] The status of the accelerated computing module may include the connection status and monitoring results of the accelerated computing module.

[0161] According to an embodiment of the present application, the onboard interactive interface 610 also supports key input configuration parameters, which shortens the interactive response time and facilitates local operation and monitoring.

[0162] In one embodiment, the remote management interface 620 may be used to obtain the status of the management board and issue configuration instructions for the management board.

[0163] Specifically, the remote management interface 620 supports IPMI 2.0 (Intelligent Platform Management Interface 2.0) and SNMPv3 (Simple Network Management Protocol version 3), enabling remote access to the management board's status, issuing configuration commands, and upgrading firmware. Furthermore, the remote management interface 620 is compatible with mainstream data center management platforms, supporting batch device monitoring and configuration, and enabling remote operation and maintenance.

[0164] According to the embodiments of the present application, the onboard interactive interface can facilitate local operation and monitoring; the remote management interface can support batch device monitoring and configuration, and realize remote operation and maintenance.

[0165] Figure 7 A schematic diagram of a management board according to another embodiment of the present application is shown.

[0166] like Figure 7 As shown, the management board can be specifically divided into a layered dynamic software system 500 and a hardware architecture 700 .

[0167] According to an embodiment of the present application, the hardware architecture 700 may include a monitoring and diagnosis module 710 , a storage and configuration unit 200 , a power and clock subsystem 300 , a bus interface unit 113 and a control module 720 .

[0168] The monitoring and diagnosis module 710 may include a monitoring unit and a diagnosis engine; the control module 720 may include a processing unit 111 , a logic unit 112 and a bus interface unit 113 .

[0169] According to the embodiments of the present application, Figure 7 The layouts of various layers, various units, etc. in the management board 110 shown in FIG are all illustrative embodiments.

[0170] The present application also provides a universal substrate, which is integrated with the above-mentioned management board.

[0171] exist Figure 1 In the embodiment, the management board 110 is integrated onto the universal substrate 100 .

[0172] According to the embodiments of the present application, the management board is deeply integrated with the universal substrate, the volume is smaller than that of the traditional solution, the board area occupied is reduced, and high integration and reliability are achieved.

[0173] According to an embodiment of the present application, the universal base plate includes an accelerated computing module disposed on a side of the universal base plate close to the bus interface unit of the management board.

[0174] exist Figure 1 In the embodiment, the accelerated computing module arranged on the universal substrate 100 is close to the bus interface unit 113 on the management board 110 .

[0175] According to an embodiment of the present application, the bus interface unit on the management board is close to the accelerated computing module on the universal substrate to reduce the length of the signal wiring.

[0176] by Figure 1 Taking the layout of the universal substrate shown as an example, the SerDes interface (bus interface unit 113) can be directly soldered next to the acceleration computing module of the universal substrate 100. The SerDes interface can also be connected to the logic unit 112 through a 20mil differential trace, and the impedance matching of the differential trace is controlled at 50Ω±5%. The power pins are connected with thick copper wires to ensure the stability of large current transmission.

[0177] Based on the above content, it can be seen that the management board provided in this application can achieve the following goals: deep hardware reuse, through programmable logic FPGA and standardized interfaces, compatible with multiple generations of UBB boards and OAM modules, supporting plug-and-play, and reducing R&D costs by more than 50%; multi-protocol adaptation: hardware acceleration and software collaboration, real-time analysis of protocols such as CXL3.0, PCI-E5.0, analysis delay less than or equal to 50ns, error detection response time less than 1μs; intelligent resource collaboration: dynamic allocation of power and clock resources, support for adaptive adjustment of OAM module power consumption, energy efficiency improved by 20%, and idle power consumption less than 150mW; high integration and low latency: deep integration with the UBB board, 40% smaller in size, hardware resource sharing, and improved system reliability and density.

[0178] Figure 8 A flow chart of a monitoring method according to an embodiment of the present application is shown.

[0179] like Figure 8 As shown, the monitoring method 800 includes operations S810 to S830.

[0180] According to an embodiment of the present application, the monitoring method 800 can be implemented using the above-mentioned management board.

[0181] In operation S810 , in response to detecting that the universal baseboard is powered on, a processing unit is used to select a target firmware from a plurality of firmwares based on the type of the universal baseboard, and a logic unit is configured using the target firmware to adapt the management board to the universal baseboard of the target type.

[0182] In operation S820, the bus interface unit is used to realize electrical connection between the management board and the accelerated computing module disposed on the universal substrate.

[0183] In operation S830, the data from the accelerated computing module is processed using the logic unit to monitor the accelerated computing module.

[0184] According to an embodiment of the present application, the processing unit is adapted to the logic unit, that is, the processing unit and the logic unit work together, and the processing unit can select the target firmware according to the type of universal substrate into which the management board is integrated, and configure the logic unit with the target firmware, so that the management board can adapt to the universal substrate into which it is integrated. Thus, based on the different types of universal substrates integrated, the processing unit can adapt to different types of universal substrates by configuring the logic unit with different firmware. On this basis, the management board of the present application can support more than 80% of universal substrate types without the need to redesign the hardware, shorten the R&D cycle by 70%, reduce the hardware development cost by 50%, and adapt to the rapid iteration of the accelerated computing module. In addition, the hardware acceleration engine of the logic unit realizes real-time analysis of 200Gbps-level data, meeting the real-time monitoring requirements of the high-speed bus.

[0185] Figure 9 A flowchart of a management board application according to an embodiment of the present application is shown.

[0186] like Figure 9 As shown, this embodiment includes operations S910 to S922.

[0187] In operation S910 , in response to detecting that the universal substrate is powered on, target firmware is loaded using a processing unit to configure a logic unit.

[0188] In operation S911 , the clock generator outputs a clock signal to synchronize the accelerated computing module with the management board clock.

[0189] According to an embodiment of the present application, after operations S910 and S911 are performed, system initialization is completed.

[0190] In operation S912, the collected data of the accelerated computing module is pre-processed.

[0191] According to an embodiment of the present application, preprocessing of data may include oversampling through an ADC (Analog-to-Digital Converter) and hardware equalization processing to restore the original data stream, and calibrate the signal DC offset and cable attenuation to improve signal quality.

[0192] In operation S913 , the monitoring unit parses the data transmission protocol and monitors protocol layer failures.

[0193] According to an embodiment of the present application, the parsing engine identifies CXL instructions or PCI-ETLP packets, extracts key information, and monitors the engine statistics error rate in real time.

[0194] In operation S914 , it is determined whether the error rate exceeds a threshold.

[0195] According to an embodiment of the present application, when the error rate exceeds the threshold, operation S915 is performed; when the error rate does not exceed the threshold, operation S917 is performed.

[0196] In operation S915 , the hardware is interrupted.

[0197] In operation S916 , the processing unit records the exception and reports it.

[0198] In operation S917 , the protocol parsing module controls the logic unit to process the data from the accelerated computing module to generate a monitoring result for the accelerated computing module.

[0199] In operation S918 , the monitoring result is uploaded to the remote management platform.

[0200] In operation S919 , it is determined whether a user operates a trigger.

[0201] According to an embodiment of the present application, if the user operation is triggered, operation S920 is performed; if the user operation is not triggered, operation S921 is performed.

[0202] In operation S920 , the configuration parameters are executed or the self-healing mechanism is triggered.

[0203] According to the embodiments of the present application, users can configure parameters through interfaces or trigger self-healing mechanisms to achieve rapid fault handling.

[0204] In operation S921, the current state is maintained.

[0205] In operation S922, end.

[0206] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0207] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A management board, characterized in that: The management board includes: a processing unit configured to select a target firmware from a plurality of firmwares based on a type of a universal substrate, and configure a logic unit using the target firmware to adapt the management board to the universal substrate of the target type; wherein the target firmware corresponds to the type of the universal substrate into which the management board is integrated; A bus interface unit, configured to realize electrical connection between the management board and the accelerated computing module disposed on the universal substrate; The logic unit is electrically connected to the bus interface unit and is used to process data from the accelerated computing module to monitor the accelerated computing module; The management board further includes a clock generator for providing a clock signal to the accelerated computing module. The clock generator uses a differential crystal oscillator in combination with a clock recovery circuit to generate a reference clock, and uses a clock buffer to reduce jitter in the reference clock and distribute the jitter-reduced clock signal to each accelerated computing module to reduce clock phase errors between the accelerated computing modules. The clock generator also supports dynamically adjusting the frequency of the clock signal based on the data transmission rate of the accelerated computing module.

2. The management board according to claim 1, characterized in that: The management board also includes: A first memory, configured to store logic unit firmware; a second memory, configured to store data from the accelerated computing module and monitoring results of the accelerated computing module; a debugging interface, connecting the processing unit with the logic unit; Reconfigurable hardware includes a preset number of logic units.

3. The management board according to claim 1, characterized in that: The management board also includes: A power management unit is connected to the logic unit and is used to supply power to the accelerated computing module.

4. The management board according to claim 1, characterized in that: The bus interface unit comprises: a data bus, configured to electrically connect the serializer / deserializer on the management board to the serializer / deserializer on the accelerated computing module, so as to implement data exchange between the management board and the accelerated computing module; The serializer / deserializer is used for converting serial data into parallel data.

5. The management board according to claim 3, characterized in that: The management board also includes: Monitoring unit for collecting eye diagram parameters from the accelerated computing module, and triggering a fault response when the eye diagram parameters do not meet preset conditions; The data transmission protocol between the management board and the accelerated computing module is parsed to monitor protocol layer failures.

6. The management board according to claim 5, characterized in that: The management board also includes: The diagnosis engine is used to locate the fault position of the accelerated computing module and perform recovery processing on the faulty accelerated computing module.

7. The management board according to claim 6, characterized in that: The management board further comprises a layered dynamic software system, which comprises a hardware layer, a management layer and an application interface layer.

8. The management board according to claim 7, characterized in that: The hardware layer is used to Providing a unified interface for the management board to enable the management board to adapt to the hardware of various types of universal baseboards; Implementing device enumeration and hot-plug detection for the accelerated computing module to obtain detection results; An accelerated computing module list is generated based on the detection result, wherein the accelerated computing module list includes at least one of a connection status, a hot plug status, a load, and a data transmission rate of the accelerated computing module.

9. The management board according to claim 8, characterized in that: The management layer also includes: Power and clock management module for adjusting the current output of the power management unit according to the load of the accelerated computing module in the accelerated computing module list; The frequency of the clock signal output by the clock generator is adjusted according to the data transmission rate in the accelerated computing module list.

10. The management board according to claim 9, characterized in that: The management layer also includes: Protocol parsing module for Controlling the monitoring unit to parse the data transmission protocol according to a preset priority; The logic unit is controlled to process the data from the accelerated computing module to generate a monitoring result for the accelerated computing module.

11. The management board according to claim 9, characterized in that: The management layer also includes a fault detection module for: Based on a preset fault knowledge base, controlling the diagnosis engine to perform fault detection on the accelerated computing module; Perform a fault response in the event of a detected fault.

12. The management board according to claim 7, characterized in that: The application interface layer includes: An onboard interactive interface for displaying the status of the accelerated computing module in real time; The remote management interface is used to obtain the status of the management board and issue configuration instructions for the management board.

13. A universal substrate, characterized in that: The universal substrate is integrated with the management board according to any one of claims 1 to 12.

14. The universal substrate according to claim 13, wherein: The universal substrate includes an accelerated computing module arranged on one side of the universal substrate close to the bus interface unit of the management board.

15. A monitoring method, using the management board according to any one of claims 1 to 12, characterized in that: The method comprises: In response to detecting that the universal substrate is powered on, using the processing unit, selecting a target firmware from a plurality of firmwares based on the type of the universal substrate, and configuring the logic unit with the target firmware to adapt the management board to the universal substrate of the target type; Using a bus interface unit, an electrical connection is achieved between the management board and the accelerated computing module disposed on the universal substrate; The logic unit is used to process data from the accelerated computing module to monitor the accelerated computing module.

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