A method and system for implementing DSMC communication interface between RK3576 ARM and FPGA

Abstract

This invention relates to a method and system for implementing a DSMC communication interface between an RK3576 ARM and an FPGA. The system initiates DMA transfer and specifies the data read location on the ARM side, while the FPGA initializes the input port and bidirectional data bus. The ARM side sends the read address, and the FPGA performs clock conversion, chip select signal processing, and clock counting. It detects the read operation flag and switches the bus to output mode. The DRAM module reads data and returns it to the FPGA side, and the ARM side receives the data via DMA. The FPGA side dynamically identifies the transmitted data length and ensures clock synchronization to complete the data transmission. This invention solves the problems of high DSMC bus protocol overhead and low transmission bandwidth. By optimizing clock management and data transmission processes, it significantly improves bus bandwidth utilization, reduces transmission latency, and enhances system flexibility and data transmission efficiency, making it suitable for high-speed data transmission scenarios.

Description

Technical Field

[0001] This invention relates to the technical field of implementing high-speed parallel transmission between DSMC bus and FPGA, specifically a method and system for implementing DSMC communication interface between RK3576ARM and FPGA. Background Technology

[0002] For the common ARM bus, data is usually sampled at the rising edge or falling edge of the clock within a unit sampling clock cycle.

[0003] Unlike other buses, the DSMC bus can achieve dual-edge sampling within a unit sampling clock cycle. In this case, at the same bus frequency, the communication rate will be twice as high as that of a single-edge sampling bus.

[0004] For example, the SPI bus samples on a single edge, while DSMC samples on both the rising and falling edges of the clock.

[0005] However, the DSMC bus has significant protocol overhead. Within eight clock cycles, only two cycles contain valid data bits, with the remainder being protocol overhead, resulting in low data transmission bandwidth. This bandwidth falls far short of the bus's theoretical value. Furthermore, due to the complexity of the protocol overhead and timing synchronization mechanisms, the DSMC bus suffers from high data transmission latency, making it unsuitable for applications with high real-time requirements.

[0006] Furthermore, the DSMC bus requires precise timing synchronization during data transmission. The complex clock management mechanisms in existing technologies increase the complexity of hardware design and may lead to delays and instability in data transmission. Summary of the Invention

[0007] The purpose of this invention is to provide a method and system for implementing the DSMC communication interface between RK3576ARM and FPGA, so as to solve the technical problems mentioned in the background art.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a method for implementing a DSMC communication interface between an RK3576 ARM and an FPGA, comprising the following steps:

[0009] The ARM side sends the address and corresponding multiple data through DMA burst transfer characteristics;

[0010] The DSMC bus control module responds to the transmission request by pulling the DSMC chip select signal low to start the transmission, generating a DSMC differential clock signal, and re-encoding the data transferred by DMA before sending it to the FPGA input / output port module in burst mode through the ARM input / output port module.

[0011] The FPGA-side direction control signal generation module detects read or write operation flags and generates direction control signals to indicate the bus direction.

[0012] The dynamic bus direction switching module sets the bidirectional data buses DSMC_DQ and DSMC_DQ1 to input or output mode according to the direction control signal;

[0013] In input mode, the sampled data is transmitted to the internal signal after passing through the data double-edge decoding module; in output mode, the prepared data is transmitted to the input / output port after passing through the data double-edge encoding module.

[0014] Preferably, the method further includes the following steps:

[0015] The FPGA-side data clock conversion module converts the DSMC differential clock into a single-ended clock, which serves as the internal master clock for data encoding and signal processing.

[0016] The chip select signal inverting module at the PGA end inverts the DSMC chip select signal to generate the cs_n signal, which clearly identifies the data transmission status;

[0017] The clock counter module on the FPGA side starts counting, records the valid clock cycles, and strictly controls the data reception timing.

[0018] Preferably, the method further includes the following steps:

[0019] The ARM side receives the returned data via DMA to complete the data reading operation; the FPGA side's data length identification module monitors the DMA transfer completion status and dynamically identifies the length of the transmitted data to adapt to data transmission requirements of different lengths.

[0020] Preferably, step 3 includes the following sub-steps:

[0021] Sub-step 31: The ARM side sends the address and corresponding data through the DMA burst length feature;

[0022] Sub-step 32: Detect the completion status of DMA transfer. When the transfer is completed, trigger an interrupt and enter the DMA transfer completion interrupt service function.

[0023] Sub-step 33: After the DMA transfer is completed, the ARM side pulls the DSMC chip select signal high to end the current communication;

[0024] Sub-step 34: After the DMA transfer is completed, the ARM side sends an event signal to the / dev / input / eventX node to notify the upper-layer application of the ARM that the transfer is complete;

[0025] Sub-step 35: The data length identification module on the FPGA side dynamically identifies the length of the data being transmitted by changing the DSMC chip select signal;

[0026] Sub-step 36: The data length identification module continuously monitors the status of the DSMC chip select signal DSMC_CS;

[0027] Sub-step 37: The data length identification module updates the data length value according to the status of the clock counting module.

[0028] Preferably, the timing calibration module on the FPGA side fine-tunes the clock signal to ensure clock synchronization; when the bidirectional data bus is in input mode, the timing calibration module synchronously adjusts the sampling timing of the data line, and compensates for the difference in transmission delay between the clock and the data by moving the data sampling point forward or backward, so as to ensure that the data is sampled at the correct clock edge.

[0029] The present invention also provides a system based on the DSMC communication interface between RK3576 ARM and FPGA, the system comprising: an ARM terminal and an FPGA terminal; the ARM terminal comprising: a user logic module, a DMA burst transfer module, a DSMC bus control module, and an ARM input / output port module;

[0030] The FPGA terminal includes: an FPGA top-level module, a timing calibration module, a data double-edge decoding module, a data decoding module, a DRAM module, a data double-edge encoding module, a dynamic bus direction switching module, a data length identification module, a chip select signal inversion module, a data clock conversion module, a clock counter module, and an FPGA input / output port module.

[0031] Compared with the prior art, the beneficial effects of the present invention are:

[0032] This invention combines DMA and DSMC to send data to the ARM input / output port module in burst mode. On the FPGA side, the DSMC bus control module dynamically adjusts the bus direction (read / write) and switches the operating mode of the bidirectional data lines (DSMC_DQ / DSMC_DQ1), and ensures accurate data transmission through clock synchronization and signal sampling. Simultaneously, the DRAM module directly processes read / write requests from the FPGA side, reducing protocol latency. This significantly improves bus bandwidth utilization (close to theoretical values), reduces transmission latency, and enhances system flexibility and data transmission efficiency. Attached Figure Description

[0033] Figure 1 : A flowchart of a method for implementing a DSMC communication interface between an RK3576 ARM and an FPGA, provided by the present invention;

[0034] Figure 2The present invention provides a structural block diagram of a system based on the DSMC communication interface between RK3576ARM and FPGA. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Please see Figure 1-2 The present invention provides a technical solution: a system based on the DSMC communication interface between RK3576 ARM and FPGA, the system comprising: an ARM end and an FPGA end; the ARM end comprising: a user logic module, used to access the / dev / ttySX node via ioctl, request data transmission and send DMA transfer commands;

[0037] The DMA burst transfer module is used to receive commands from the / dev / dma_memcpy node, obtain data from DDRRAM, and start the DMA control DSMC bus control module to transfer data in burst mode.

[0038] The DSMC bus control module is used to respond to transmission requests, control the DSMC chip select signal to be pulled low to start transmission, generate the DSMC differential clock signal, re-encode the data transferred by DMA, and send it to the FPGA input / output port module through the ARM input / output port module.

[0039] ARM Input / Output Port Module: Used to communicate with the FPGA Input / Output Port Module;

[0040] The FPGA terminal includes:

[0041] The top-level module of the FPGA is used to control the operation of the entire FPGA.

[0042] The timing calibration module is used to convert the DSMC differential clock into a single-ended clock as the internal master clock.

[0043] The data double-edge encoding module is used to encode the data on both sides.

[0044] The data decoding module is used to decode the received data;

[0045] The data double-edge decoding module is used to perform double-edge decoding on the data.

[0046] DRAM modules are used for storing and accessing data;

[0047] The dynamic bus direction switching module is used to switch the working modes of the bidirectional data bus DSMC_DQ and DSMC_DQ1 according to the direction control signal.

[0048] The data length recognition module is used to dynamically identify the length of the transmitted data;

[0049] The chip select signal inverting module is used to invert the DSMC chip select signal to generate the cs_n signal;

[0050] The data clock conversion module is used to convert the DSMC differential clock signal into a single-ended clock signal used internally by the FPGA.

[0051] The clock counter module is used to record the effective clock cycle and control the timing of data reception.

[0052] FPGA input / output port module, used to communicate with ARM input / output port module.

[0053] Based on the above system, the present invention also provides a method for implementing the DSMC communication interface between RK3576ARM and FPGA, the method comprising the following steps:

[0054] Step 11: The upper-layer application on the ARM side accesses the / dev / dma_memcpy node via ioctl, requests data transfer, and sends a DMA transfer command.

[0055] Step 12: On the ARM side, the DMA burst transfer module receives commands from the / dev / dma_memcpy node, parses the command content, retrieves data from the DDR RAM, and starts the DMA control DSMC bus control module to transfer data in burst mode.

[0056] Step 13: The ARM-side DSMC bus control module responds to the transmission request by pulling the DSMC chip select signal low to indicate the start of transmission; it controls the DSMC differential clock to generate a 100MHz clock signal; it re-encodes the DMA transmission data according to the user logic and sends the data to the ARM input / output port module in burst mode, and then sends it to the FPGA input / output port module through the ARM input / output port module, such as sending data address addr_0 and data_0 ~ data_1024.

[0057] Step 14: The direction control signal generation module detects the read or write operation flag and generates a direction control signal to indicate the bus direction as "receive data" or "send data".

[0058] Step 15: The dynamic bus direction switching module sets the bidirectional data buses DSMC_DQ and DSMC_DQ1 to input or output mode according to the direction control signal.

[0059] Step 16: When in input mode, the dynamic bus direction switching module transmits the sampled data_0 to the internal signal after passing through the data double-edge decoding module.

[0060] Step 17: When in output mode, the dynamic bus direction switching module transmits the prepared data to the input / output port after passing through the data double-edge encoding module.

[0061] Step 18: The DRAM module receives the read address and read enable signal from the FPGA and reads data from the specified address in the DRAM and returns it to the FPGA to realize the data reading operation;

[0062] This solution combines DMA and DSMC to send data to the ARM input / output port module in burst mode. On the FPGA side, the DSMC bus control module dynamically adjusts the bus direction (read / write) and switches the operating mode of the bidirectional data lines (DSMC_DQ / DSMC_DQ1), while clock synchronization and signal sampling ensure accurate data transmission. Simultaneously, the DRAM module directly handles read / write requests from the FPGA side, reducing protocol latency. This significantly improves bus bandwidth utilization (close to theoretical values), reduces transmission latency, and enhances system flexibility and data transmission efficiency.

[0063] To address timing misalignment and data reliability issues caused by incompatibility between DSMC differential clock and chip select signals in communication between FPGA and external devices (such as ARM), this method also includes the following steps:

[0064] Step 19: The FPGA-side data clock conversion module converts the DSMC differential clock into a single-ended clock as the internal master clock, which is used by the data encoding module and for assigning values ​​to internal signals.

[0065] Step 20: The FPGA chip select signal inverting module inverts the DSMC chip select signal to generate the cs_n signal, indicating that data transmission is currently in progress.

[0066] Step 21: The clock counter module starts counting, records the number of valid clock cycles, and controls the timing of data reception.

[0067] Through the above steps: First, the FPGA-side data clock conversion module converts the DSMC differential clock into a single-ended clock as the internal master clock, ensuring strict synchronization between data encoding and signal processing. Second, the chip select signal inversion module inverts the DSMC chip select signal to generate cs_n, clearly identifying the data transmission status. Finally, the clock counter module accurately records the effective clock cycle, strictly controlling the data reception timing. After optimization, the system achieves efficient synchronous communication between the FPGA and external devices, significantly improving data reception reliability, timing stability, and overall performance, making it suitable for high-speed data transmission scenarios.

[0068] To address the lack of flexibility and variable-length data adaptation issues caused by the fixed data length limitation in traditional DMA transfers, this method also includes the following steps:

[0069] Step 31: The ARM side uses the DMA burst length feature to send an address addr_0 and multiple data (assuming that only one data data_0 is being sent at present).

[0070] Step 32: Detect the completion status of DMA transfer. When the transfer is completed, trigger an interrupt and enter the DMA transfer completion interrupt service function.

[0071] Step 33: After the DMA transfer is completed, the ARM side pulls the DSMC chip select signal high to end the communication.

[0072] Step 34: When the DMA transfer is complete, the ARM side sends an event signal to the / dev / input / eventX node to notify the upper-layer application of the ARM that the transfer is complete.

[0073] Step 35: The data length identification module on the FPGA side dynamically identifies the length of the data being transmitted (currently 1 data point) by changing the DSMC chip select signal.

[0074] Step 36: The data length identification module continuously monitors the status of the DSMC chip select signal DSMC_CS.

[0075] Step 37: The data length recognition module updates the data length value according to the status of the clock counting module.

[0076] Through the above steps, a dynamic identification mechanism is implemented using the data length identification module on the FPGA side: the ARM side uses the DMA burst transfer characteristic to send data (e.g., multiple data points per address, in the current example, one data point, data_0). After the transmission is completed, an interrupt is triggered and the DSMC chip select signal (DSMC_CS) is pulled high to end the communication. At the same time, the upper-layer application is notified through the / dev / input / eventX node. The data length identification module on the FPGA side continuously monitors the changes in the DSMC_CS signal and dynamically calculates the length of the data transmitted in this transmission (identified as one data point in the current example) in conjunction with the status of the clock counter module. Therefore, the system can adapt to arbitrary variable-length transmission requirements without pre-setting a fixed data length, simplifying protocol design and reducing hardware complexity. At the same time, accurate identification avoids data truncation or overflow issues, significantly improving communication reliability, flexibility, and system scalability, making it suitable for diverse data interaction needs in high-performance embedded scenarios.

[0077] To address the issue of inconsistent DSMC bus clock and data signal transmission delays caused by PCB trace differences, this method also includes the following steps:

[0078] Step 41: The timing calibration module on the FPGA side ensures clock synchronization and fine-tuning to ensure that data is sent to the ARM side within the correct clock cycle, thus ensuring the real-time performance and accuracy of data transmission.

[0079] Step 42: When the bidirectional data bus (DSMC_DQ and DSMC_DQ1) is an input, connect to the timing calibration module and advance and delay by a specified number of clock cycles (25ps per cycle) to achieve synchronization and alignment between the data and the clock, ensuring that the data is sent and received at the correct clock edge.

[0080] The timing calibration module on the FPGA side ensures data transmission synchronization through a dynamic adjustment mechanism: when the bidirectional data bus is in input mode, the module fine-tunes the clock signal in 25ps steps and synchronously adjusts the sampling timing of the data lines (DSMC_DQ / DSMC_DQ1). By advancing or delaying the data sampling points, it compensates for the transmission delay difference between the clock and data, ensuring that data is sent to the ARM side within a precise clock cycle or sampled at the correct clock edge. Therefore, the system effectively eliminates the clock-data skew problem caused by inconsistent PCB traces, significantly improving the accuracy and reliability of high-speed data transmission. It also enhances adaptability to complex PCB layouts and multi-rate transmission scenarios, ensuring the stability of data transmission in burst modes and providing reliable data interaction guarantees for high-performance embedded systems.

[0081] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for implementing a DSMC communication interface between an RK3576 ARM and an FPGA, characterized in that, Includes the following steps: The ARM side sends the address and corresponding multiple data through DMA burst transfer characteristics; The DSMC bus control module responds to the transmission request by pulling the DSMC chip select signal low to start the transmission, generating a DSMC differential clock signal, and re-encoding the data transferred by DMA before sending it to the FPGA input / output port module in burst mode through the ARM input / output port module. The FPGA-side direction control signal generation module detects read or write operation flags and generates direction control signals to indicate the bus direction. The dynamic bus direction switching module sets the bidirectional data buses DSMC_DQ and DSMC_DQ1 to input or output mode according to the direction control signal; In input mode, the sampled data is transmitted to the internal signal after passing through the data double-edge decoding module; in output mode, the prepared data is transmitted to the input / output port after passing through the data double-edge encoding module. The method further includes the following steps: The FPGA-side data clock conversion module converts the DSMC differential clock into a single-ended clock, which serves as the internal master clock for data encoding and signal processing. The chip select signal inverting module on the FPGA side inverts the DSMC chip select signal to generate the cs_n signal, which indicates the data transmission status; The clock counter module on the FPGA side records the effective clock cycle and controls the data reception timing; The method further includes the following steps: The ARM side receives the returned data via DMA to complete the data read operation; the FPGA side's data length identification module monitors the DMA transfer completion status and dynamically identifies the transmitted data length to adapt to data transmission requirements of different lengths; it includes the following sub-steps: Sub-step 31: The ARM side sends the address and corresponding data through the DMA burst length feature; Sub-step 32: Detect the completion status of DMA transfer. When the transfer is completed, trigger an interrupt and enter the DMA transfer completion interrupt service function. Sub-step 33: After the DMA transfer is completed, the ARM side pulls the DSMC chip select signal high to end the current communication; Sub-step 34: After the DMA transfer is completed, the ARM side sends an event signal to the / dev / input / eventX node to notify the upper-layer application of the ARM that the transfer is complete; Sub-step 35: The data length identification module on the FPGA side dynamically identifies the length of the data being transmitted by changing the DSMC chip select signal; Sub-step 36: The data length identification module continuously monitors the status of the DSMC chip select signal DSMC_CS; Sub-step 37: The data length identification module updates the data length value according to the status of the clock counting module.

2. The implementation method based on the DSMC communication interface between RK3576ARM and FPGA according to claim 1, characterized in that, The method further includes the following steps: The timing calibration module on the FPGA side fine-tunes the data signal to ensure that the clock and data signals are synchronized; When the bidirectional data bus is in input mode, the timing calibration module synchronously adjusts the sampling timing of the data lines. By moving the data sampling points forward or backward, it compensates for the difference in transmission delay between the clock and the data, ensuring that the data is sampled at the correct clock edge.

3. A system based on the DSMC communication interface between RK3576ARM and FPGA, characterized in that, The method for implementing the DSMC communication interface between RK3576 ARM and FPGA as described in claim 1 or 2 includes: an ARM terminal and an FPGA terminal; the ARM terminal includes: a user logic module, a DMA burst transfer module, a DSMC bus control module, and an ARM input / output port module; The FPGA terminal includes: an FPGA top-level module, a timing calibration module, a data double-edge encoding module, a data decoding module, a data double-edge decoding module, a DRAM module, a dynamic bus direction switching module, a data length identification module, a chip select signal inversion module, a data clock conversion module, a clock counter module, and an FPGA input / output port module.

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