Radar radiation source identification method and system based on FPGA

Abstract

The invention discloses an FPGA-based radar radiation source identification method and system. The method comprises the following steps: constructing a radar radiation source signal data set; performing time-frequency analysis on radar signals in the radar radiation source signal data set to obtain a two-dimensional time-frequency graph; inputting the two-dimensional time-frequency graph into a preset radar radiation source identification network for pre-training to obtain a pre-training model; performing parameter quantization processing and parameter fusion processing on the pre-training model by adopting a preset optimization strategy to obtain a radar radiation source identification model; and deploying and operating the radar radiation source identification model through a preset FPGA platform, and then receiving a radar radiation source signal in real time through the FPGA platform and identifying the radar radiation source signal to obtain an identification result. According to the invention, efficient and accurate radar radiation source signal identification is realized.

Description

Technical Field

[0001] The present invention relates to the field of radar emitter signal recognition, and in particular, to a radar emitter recognition method and system based on FPGA. Background Art

[0002] Electronic reconnaissance is an important part of electronic countermeasures, and radar emitter recognition is one of the most important links in electronic reconnaissance, which plays an important supporting role in threat warning, interference decision-making, etc.

[0003] Early radar emitter recognition methods mainly relied on template matching or expert systems, and the systems were relatively simple. With the increasing complexity of the electromagnetic environment, traditional radar emitter methods gradually could not meet the needs. At this time, with the development of machine learning, various artificial intelligence methods were also introduced into this field, mainly including three aspects: feature selection, feature extraction, and classifier design. Among them, the selection and extraction of features were generally carried out manually. In recent years, the rise of the deep learning branch has led to remarkable developments in computer vision and natural language processing, and the trend still continues. Due to its strong generalization ability and performance not inferior to humans in computer vision, it has been introduced into the field of radar emitter recognition, further improving the recognition accuracy. Since deep learning has a strong feature extraction ability, it can directly complete the output from the signal to the result without manual extraction of the parameters. However, sometimes it may not be able to extract the features we expect, so manual extraction of parameters is still a feasible solution.

[0004] Patent "CN107220606A" conducts emitter recognition based on a one-dimensional convolutional neural network. The network mainly extracts the features of the input signal through one-dimensional convolution, and the structure is relatively simple. Patent "CN112115924A" conducts radar emitter recognition based on one-dimensional CNN and LSTM. Aiming at the low accuracy of one-dimensional processing, the CNN network is used to extract local features, and the LSTM network is used to extract global features, which improves the recognition accuracy while ensuring low computational complexity. Patent "CN110147812A" conducts radar emitter recognition based on a dilated residual network. Different from the above two methods that directly use the network for feature extraction, this method first selects time-frequency analysis for manual feature extraction, converts the signal into a two-dimensional time-frequency image and performs preprocessing, and then conducts emitter recognition through a dilated residual network. The time-frequency diagram extracted by this method can effectively reflect the features of the signal and improve the recognition accuracy. However, the computational complexity of time-frequency analysis is high, and the real-time performance of the method is poor.

[0005] With the development and application of deep learning, there is currently a situation of a hundred schools of thought contending in the design framework and deployment framework of neural networks. Due to the characteristics of neural networks, GPU and FPGA stand out due to their own parallel computing characteristics and become the two main neural network edge device deployment platforms. Since it is very convenient to deploy networks through Nvidia's cuda library, GPU is currently the main neural network deployment platform. FPGA has not been eliminated because of its low power consumption and computing speed not inferior to that of GPU, and its biggest weakness lies in the lack of a general method to implement network deployment. The customized network deployment makes the development cycle long, so there is little research on the deployment of radar emitter recognition models. Summary of the Invention

[0006] To solve the technical problems of low recognition rate and poor real-time performance in existing radar emitter recognition, the present invention provides a method and system for radar emitter recognition based on FPGA. The technical solution adopted by the present invention is:

[0007] The first aspect of the present invention provides a method for radar emitter recognition based on FPGA, and the method includes:

[0008] Construct a radar emitter signal data set;

[0009] Perform time-frequency analysis on the radar signals in the radar emitter signal data set to obtain a two-dimensional time-frequency diagram;

[0010] Input the two-dimensional time-frequency diagram into a preset radar emitter recognition network for pre-training to obtain a pre-trained model;

[0011] Adopt a preset optimization strategy to perform parameter quantization processing and parameter fusion processing on the pre-trained model to obtain a radar emitter recognition model;

[0012] Deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive radar emitter signals in real time through the FPGA platform and perform recognition to obtain a recognition result.

[0013] As a preferred solution, the method for constructing a radar emitter data set includes:

[0014] Generate a radar emitter signal data set through MATLAB simulation. The radar emitter signal data set includes twelve different modulation methods, namely cw, lfm, nlfm, bpsk, bfsk, qpsk, qfsk, p1, p2, p3, p4, msk. Equal numbers of samples are generated for each signal at signal-to-noise ratios from -10dB to 8dB at intervals of 2dB.

[0015] As a preferred solution, the method for performing time-frequency analysis on the radar signals in the radar radiation source signal dataset to obtain a two-dimensional time-frequency diagram includes:

[0016] Sampling the radar signal according to a preset data processing clock to obtain AD data;

[0017] Windowing the AD data through a preset window function;

[0018] In the FPGA, performing time-frequency analysis on the AD data through STFT calculation, and the specific formula is:

[0019]

[0020] where x(n) is the input sequence, ω(n) is the window function, and R is the step value.

[0021] As a preferred solution, the preset window function is a Hamming window function.

[0022] As a preferred solution, the method for parameter quantization processing includes:

[0023] According to the characteristics of the FPGA, that is, the quantization bit width of the ADC is 16 bits, so the weight value is quantized to 8 bits and the bias value is quantized to 16 bits;

[0024] Assuming that r represents a floating-point real number and q represents a quantized fixed-point integer, the conversion formula is as follows:

[0025] r = S(q - Z)

[0026]

[0027] where S is the scale, representing the proportional relationship between the real number and the integer, and Z is the zero point, representing the integer corresponding to 0 in the real number after quantization. The calculation method is:

[0028]

[0029] As a preferred solution, the method for parameter fusion processing includes:

[0030] Fusing the convolutional layer and the BN layer;

[0031] For the convolutional layer operation:

[0032] y , ,

[0023] , ,

[0022] , , ,

[0021] , ,

[0020] ,

[0030] ,

[0026] , ,

[0029] ,

[0025] , , ,

[0024] , ,

[0018] ,

[0028] ,

[0027] ,

[0034] ,

[0033] ,

[0017] ,

[0032] , ,

[0031] , conv , , , , , , , , ,

[0019] , = ωx + b

[0033] where ω is the weight, x is the input matrix, b is the bias, and y is the output matrix;

[0034] For the operation of the BN layer:

[0035]

[0036]

[0037] where μ B and σ B 2 are the mean and variance of the input matrix, is the normalized value of the input data, γ and β are the affine parameters of the BN layer, and y i is the output of the BN layer;

[0038] According to the characteristics of the operation, there are:

[0039]

[0040] where is the fused weight, is the fused bias.

[0041] As a preferred solution, the method for deploying and running the radar emitter recognition model through a preset FPGA platform, and then receiving and recognizing the radar emitter signal in real time through the FPGA platform to obtain the recognition result includes:

[0042] Sampling the radar emitter signal according to a preset data processing clock to obtain real-time AD data;

[0043] Windowing the real-time AD data through a preset window function;

[0044] Performing time-frequency analysis on the real-time AD data through STFT calculation in the FPGA to obtain a real-time two-dimensional time-frequency diagram;

[0045] First, the real-time two-dimensional time-frequency diagram is subjected to three convolution operations through a preset ACB module, then passes through the BN layer, and finally the data is fused and output through the ReLu activation layer;

[0046] Next, the data is further subjected to feature extraction through a preset 18-layer ResNet residual network;

[0047] The output of the ResNet residual network is simultaneously subjected to channel evaluation through a preset Squeeze-Excitation module. First, each channel obtains its own weight through an average pooling layer, so that each channel is represented by a value. Then, excitation is performed through two linear layers. Finally, the data passes through the sigmoid activation function to represent the importance of each channel, and then multiplies with the output of the ResNet residual network;

[0048] Finally, the data is passed through a linear layer to obtain the classification result.

[0049] The second aspect of the present invention provides a radar emitter recognition system based on FPGA, and the system includes a dataset construction module, a time-frequency analysis module, a training module, an optimization module, and a signal real-time recognition module;

[0050] The dataset construction module is used to construct a radar emitter signal dataset;

[0051] The time-frequency analysis module is used to perform time-frequency analysis on the radar signals in the radar emitter signal dataset to obtain a two-dimensional time-frequency diagram;

[0052] The training module is used to input the two-dimensional time-frequency diagram into a preset radar emitter recognition network for pre-training to obtain a pre-trained model;

[0053] The optimization module is used to perform parameter quantization processing and parameter fusion processing on the pre-trained model by using a preset optimization strategy to obtain a radar emitter recognition model;

[0054] The signal real-time recognition module is used to deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive radar emitter signals in real time through the FPGA platform and perform recognition to obtain a recognition result.

[0055] The third aspect of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the foregoing method for recognizing radar emitters based on FPGA are implemented.

[0056] The fourth aspect of the present invention provides a computer device, including a storage medium, a processor, and a computer program stored in the storage medium and executable by the processor. When the computer program is executed by the processor, the steps of the foregoing method for recognizing radar emitters based on FPGA are implemented.

[0057] Compared with the prior art, the beneficial effects of the present invention are:

[0058] The present invention designs an efficient two-dimensional neural network to replace the traditional one-dimensional neural network to recognize radar emitter signals, and improves the real-time performance of time-frequency analysis and network inference through the FPGA platform, realizing efficient and accurate recognition of radar emitter signals. Description of the Drawings

[0059] Figure 1 It is a flowchart of a method for recognizing radar emitters based on FPGA provided in this embodiment;

[0060] Figure 2The structure diagram of the radar radiation source recognition network provided by this embodiment;

[0061] Figure 3 The schematic diagram of one-dimensional pipeline linear operation provided by this embodiment;

[0062] Figure 4 The schematic diagram of the operation of conventional convolution provided by this embodiment;

[0063] Figure 5 The schematic diagram of the operation of depthwise separable convolution provided by this embodiment;

[0064] Figure 6 The schematic diagram of the operation of single-channel depth convolution provided by this embodiment;

[0065] Figure 7 The schematic diagram of the operation of point convolution provided by this embodiment;

[0066] Figure 8 The schematic diagram of the operation of the linear layer provided by this embodiment;

[0067] Figure 9 The schematic diagram of the FPGA model deployment provided by this embodiment. Detailed implementation manners

[0068] The drawings are only for illustrative purposes and cannot be construed as limitations on the present invention;

[0069] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the embodiments of the present application.

[0070] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. The singular forms "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0071] When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects and do not have to be used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0072] In addition, in the description of the present application, unless otherwise specified, "a plurality of" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0073] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0074] Embodiment 1

[0075] Please refer to Figure 1 , this embodiment provides a method for identifying radar radiation sources based on FPGA, and the method includes:

[0076] S1: Construct a radar radiation source signal data set;

[0077] In a specific embodiment, the method for constructing a radar radiation source data set includes:

[0078] Generate a radar radiation source signal data set through MATLAB simulation. The radar radiation source signal data set includes twelve different modulation methods, namely cw, lfm, nlfm, bpsk, bfsk, qpsk, qfsk, p1, p2, p3, p4, msk. Equal numbers of samples are generated for each signal at a signal-to-noise ratio interval of 2 dB from -10 dB to 8 dB.

[0079] S2: Perform time-frequency analysis on the radar signals in the radar radiation source signal data set to obtain a two-dimensional time-frequency diagram;

[0080] In a specific embodiment, the method for performing time-frequency analysis on the radar signals in the radar radiation source signal data set to obtain a two-dimensional time-frequency diagram includes:

[0081] Sample the radar signal according to the preset data processing clock to obtain AD data;

[0082] Perform windowing on the AD data through a preset window function;

[0083] In the FPGA, perform time-frequency analysis on the AD data through STFT calculation. The specific formula is:

[0084]

[0085] where x(n) is the input sequence, ω(n) is the window function, and R is the step value.

[0086] In a specific embodiment, the preset window function is a Hamming window function.

[0087] S3: Input the two-dimensional time-frequency diagram into a preset radar emitter recognition network for pre-training to obtain a pre-trained model;

[0088] S4: Adopt a preset optimization strategy to perform parameter quantization processing and parameter fusion processing on the pre-trained model to obtain a radar emitter recognition model;

[0089] In a specific embodiment, the method of parameter quantization processing includes:

[0090] According to the characteristics of the FPGA, that is, the quantization bit width of the ADC is 16 bits, so the weight value is quantized to 8 bits and the bias value is quantized to 16 bits;

[0091] Assume that r represents a floating-point real number and q represents the quantized fixed-point integer. The conversion formula is as follows:

[0092] r = S(q - Z)

[0093]

[0094] where S is the scale, representing the proportional relationship between the real number and the integer, and Z is the zero point, representing the integer corresponding to 0 in the real number after quantization. The calculation method is:

[0095]

[0096] The method of parameter fusion processing includes:

[0097] Fuse the convolutional layer and the BN layer;

[0098] For the convolutional layer operation, there is:

[0099] y conv = ωx + b

[0100] where ω is the weight, x is the input matrix, b is the bias, and y is the output matrix;

[0101] The operations on the BN layer are as follows:

[0102]

[0103] where μ B and σ B 2 are the mean and variance of the input matrix, is the normalized value of the input data, γ and β are the affine parameters of the BN layer, and y i is the output of the BN layer;

[0104] According to the characteristics of the operations, we have:

[0105]

[0106] where is the fused weight, is the fused bias.

[0107] S5: Deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive and identify radar emitter signals in real time through the FPGA platform to obtain an identification result;

[0108] In a specific embodiment, the method of deploying and running the radar emitter recognition model through a preset FPGA platform, and then receiving and identifying radar emitter signals in real time through the FPGA platform to obtain an identification result includes:

[0109] Sample the radar emitter signals according to a preset data processing clock to obtain real-time AD data;

[0110] Perform windowing on the real-time AD data through a preset window function;

[0111] In the FPGA, perform time-frequency analysis on the real-time AD data through STFT calculation to obtain a real-time two-dimensional time-frequency diagram;

[0112] First, pass the real-time two-dimensional time-frequency diagram through a preset ACB module for three convolution operations. The three convolution operations respectively select convolution kernels of 3x3, 1x3, and 3x1. Among them, in the setting of padding, the 3x3 convolution kernel is set to 1, the 1x3 convolution kernel is set to (0,1), the 3x1 convolution kernel is (1,0), and the stride is set to 1; then pass through the BN layer, and finally output after data fusion through the ReLu activation layer;

[0113] Next, further extract features from the data through a preset 18-layer ResNet residual network;

[0114] The output of the ResNet residual network is simultaneously evaluated for channels through a preset Squeeze-Excitation module. First, each channel obtains its respective weight through an average pooling layer, such that each channel is represented by a single value. Then, excitation is performed through two linear layers. The input channel of the first linear layer is set to 64 layers, the output channel is set to 16 layers, and the activation function is set to ReLu. The input channel of the second linear layer is set to 16 layers, the output channel is set to 64 layers. Finally, the data passes through a sigmoid activation function to represent the importance of each channel, and then is multiplied by the output of the ResNet residual network;

[0115] Finally, the data passes through a linear layer with the input channel set to 64 layers and the output channel set to 12 layers to obtain the classification result.

[0116] Example 2

[0117] This example can be regarded as an improvement or extended example based on Example 1. Specifically, it is a method for identifying radar radiation sources based on FPGA, and the method includes:

[0118] Construct a radar radiation source signal data set;

[0119] Specifically, first construct a simulation data set in Matlab R2023a software. The simulation of the data uses real signal parameters and the characteristics of the signal passing through the FPGA hardware platform. The specific parameters are shown in Table 1:

[0120] Table 1

[0121]

[0122]

[0123] Considering the influence of different window functions on time-frequency analysis, mainly the sidelobe effect and signal leakage, the Hamming window is comprehensively selected as the window function, and the formula of the window function is as follows:

[0124]

[0125] Perform time-frequency analysis on the radar signals in the radar radiation source signal data set to obtain a two-dimensional time-frequency diagram;

[0126] Input the two-dimensional time-frequency diagram into a preset radar radiation source recognition network for pre-training to obtain a pre-trained model;

[0127] Adopt a preset optimization strategy to perform parameter quantization processing and parameter fusion processing on the pre-trained model to obtain a radar radiation source recognition model;

[0128] It should be noted that the calculations of the pre-trained model use the tensor data type, that is, the calculations of floating-point numbers float-64. In the actual hardware platform, the calculations of floating-point numbers are very costly. Therefore, the parameters need to be quantized at the end of model construction.

[0129] According to the characteristics of the FPGA, that is, the quantization bit width of the ADC is 16 bits. Therefore, the weight value is quantized to 8 bits, and the bias value is quantized to 16 bits.

[0130] Assume that r represents the floating-point real number and q represents the quantized fixed-point integer. Then the conversion formula is as follows:

[0131] r = S(q - Z)

[0132]

[0133] Among them, S is the scale, representing the proportional relationship between the real number and the integer, and Z is the zero point, representing the integer corresponding to 0 in the real number after quantization. Their calculation methods are:

[0134]

[0135] It should be noted that in the actual deployment of the neural network, due to the characteristics of the operators, different operators can be fused. In this case, the convolutional layer and the BN layer are fused.

[0136] For the convolutional layer operation, there is:

[0137] y conv = ωx + b

[0138] Among them, ω is the weight, x is the input matrix, b is the bias, and y is the output matrix.

[0139] For the operation of the BN layer, there is:

[0140]

[0141] Among them, μ B and σ B 2 are the mean and variance of the input matrix, is the normalized value of the input data, γ and β are the affine parameters of the BN layer, and y i is the output of the BN layer.

[0142] According to the characteristics of the operation, there is:

[0143]

[0144] Among them is the fused weight, Is the bias after fusion.

[0145] Deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive and recognize the radar emitter signal in real time through the FPGA platform to obtain the recognition result;

[0146] In a specific embodiment, the method for deploying and running the radar emitter recognition model through a preset FPGA platform, and then receiving and recognizing the radar emitter signal in real time through the FPGA platform to obtain the recognition result includes:

[0147] Deploy the radar emitter recognition model;

[0148] Sample the radar emitter signal according to a preset data processing clock to obtain real-time AD data;

[0149] It should be noted that the sampling rate of the ADC on the FPGA side is set to 5GHz, 40x decimation, IQ sampling, the quantization bit width is 16bit, the data processing clock is 125MHz, and the data rate is 125MSps. The settings of this part in Matlab are consistent with the settings of the ADC.

[0150] Perform windowing processing on the real-time AD data through a preset window function;

[0151] In the FPGA, perform time-frequency analysis on the real-time AD data through STFT calculation to obtain a real-time two-dimensional time-frequency diagram;

[0152] Please refer to Figure 2 , first pass the real-time two-dimensional time-frequency diagram through a preset ACB module for three convolution operations, then through a BN layer, and finally output after data fusion through a ReLu activation layer;

[0153] Next, further extract features from the data through a preset 18-layer ResNet residual network;

[0154] The output of the ResNet residual network simultaneously passes through a preset Squeeze-Excitation module for channel evaluation. First, each channel obtains its own weight through an average pooling layer, so that each channel is represented by a value. Then, it is excited through two linear layers. Finally, the data passes through a sigmoid activation function to represent the importance of each channel, and then multiplies with the output of the ResNet residual network;

[0155] Finally, obtain the classification result by passing the data through a linear layer.

[0156] Specifically, the method for deploying the radar emitter recognition model includes:

[0157] The deployment of the model is to describe the information of the network in the language of hardware. In the FPGA platform, the model receives time-frequency information and outputs labels corresponding to categories.

[0158] According to the characteristics of the model and the features of the FPGA platform, the deployment of the model can be divided into several steps: convolution operation, linear layer operation, and weight reading.

[0159] Convolution operation:

[0160] The convolution operation is the most important operation in this network, and its essence is multiplication and addition operation.

[0161] As Figure 3 shown, it is a schematic diagram of one-dimensional pipelined linear operation. Each basic operator is a multiplication and addition operation, and this encapsulation in FPGA is called a multiplication accelerator (Multiply-accumulate, MAC), and further encapsulating MAC forms a module. During use, the pipeline receives one input signal each time, and the switch of the MAC is controlled by valid. If the pipeline is fully utilized, the calculation results of the number of MAC layers can be obtained per clock.

[0162] The above module can be directly applied to one-dimensional convolution operation. weight represents the weight of the convolution kernel. As the pipeline progresses, it is equivalent to the movement of data on each convolution kernel. For example, at a certain moment, if each MAC is valid, the data is in the first position in the convolution sum represented by the first MAC and in the last position in the convolution kernel represented by the last MAC. Therefore, at this moment, the output result of the last MAC is the convolution sum represented by this convolution kernel.

[0163] Please refer to Figure 4 , Figure 4 which is a schematic diagram of the operation of a conventional convolution. To simplify the difficulty of hardware deployment and reduce the number of parameters, please refer to Figure 5 ,this invention uses depthwise separable convolution to replace Figure 4 the conventional convolution. Research shows that the depthwise separable convolution has almost the same calculation accuracy while reducing the number of parameters. Therefore, the FPGA implementation of the convolution operation is transformed into the implementation of two parts: depthwise convolution (Depthwise, DW) and pointwise convolution (Pointwise, PW). The following will be analyzed one by one.

[0164] Figure 6 is a schematic diagram of the operation of depthwise separable convolution. Suppose the size of the convolution kernel is C in·KH·KW, the convolution of each channel can be implemented with KH·KW MAC layers. At this time, the data can also be regarded as a one-dimensional sequence in the KW dimension, and the input at this time becomes an input sequence of KH. The difference is that the final output of each one-dimensional sequence needs to pass through an adder.

[0165] When in use, KW - 1 MACs can be combined to form a convolution processing unit (PE), so a total of C in ·KH PEs are required.

[0166] As Figure 7 shown, in point convolution, the size of the convolution kernel is C out ·C in ·1·1. In the figure, the convolution kernel of each output channel in each row has a size of 1·C in ·1·1. By splicing the calculation results of each row, the convolution result of each channel at this position can be obtained. When in use, each row is instantiated as a PE, so a total of C out - 1 PEs need to be instantiated.

[0167] Linear layer operation: The operation of the linear layer is as Figure 8 shown, and this operation can also be represented by the appendix Figure 7 to represent.

[0169] Reading of parameters:

[0170] In actual FPGA deployment, the convolutional layer and the linear layer have parameters of weights and biases. Since the parameters do not change during the operation, the parameters can be stored in advance. On the FPGA, the BRAM IP core is selected to store the parameters.

[0171] In PW, the size of the convolution kernel is C in ·KH·KW, and the corresponding number of MACs is required. Encapsulating KW MACs, a total of C out ·KH PEs are required. In each PE, the size of the weight is 16·KW bit, and the bias is 8·KH bit.

[0172] In DW, the size of the convolution kernel is C out ·Cin·1·1, and the corresponding number of MACs is required. Encapsulating C in MACs, a total of C out PEs are required. In each PE, the size of the weight is 16·C out bit, and the bias is 8·Cout bit.

[0173] In the linear layer, the size of the parameter is C out ·C in , and the corresponding number of MACs is required. Encapsulating C in MACs requires a total of C out PEs. In each PE, the size of the weight is 16·C out bit, and the bias is 8·C out bit.

[0174] The model deployment is as Figure 9 shown, and the overall control is implemented by a state machine. When the convolution module is called, first the weights are called through the Weight_loader module, then they are operated with the data, and the operation results are written into the buffer Ping-ping buffer module. On the other hand, the data passes through the Conv_pw module to obtain the convolution result, which is added to the bias through the Bias_loader module to obtain the final convolution structure, and then written into the Ping-pong buffer for the next step of processing. When performing the Squeeze-Excitation operation, the weights are first configured to the linear layer, the data enters the global average pooling from the buffer to obtain the importance measure of each layer, then a linear operation is performed with the weights, and then the output of the linear layer is obtained through the Bias_loader. Finally, the output of the linear layer is output through a 12-way selector to obtain the corresponding label value.

[0175] Embodiment 3

[0176] This embodiment provides a radar emitter recognition system based on FPGA, and the system includes a dataset construction module, a time-frequency analysis module, a training module, an optimization module, and a signal real-time recognition module;

[0177] The dataset construction module is used to construct a radar emitter signal dataset;

[0178] The time-frequency analysis module is used to perform time-frequency analysis on the radar signals in the radar emitter signal dataset to obtain a two-dimensional time-frequency diagram;

[0179] The training module is used to input the two-dimensional time-frequency diagram into a preset radar emitter recognition network for pre-training to obtain a pre-trained model;

[0180] The optimization module is used to perform parameter quantization processing and parameter fusion processing on the pre-trained model by using a preset optimization strategy to obtain a radar emitter recognition model;

[0181] The signal real-time recognition module is used to deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive radar emitter signals in real time through the FPGA platform and perform recognition to obtain recognition results.

[0182] Embodiment 4

[0183] A computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of a method for identifying radar radiation sources based on FPGA described in Embodiment 1 are implemented.

[0184] Embodiment 5

[0185] A computer device, comprising a storage medium, a processor, and a computer program stored in the storage medium and executable by the processor, and when the computer program is executed by the processor, the steps of a method for identifying radar radiation sources based on FPGA described in Embodiment 1 are implemented.

[0186] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A radar emitter recognition method based on FPGA, characterized in that, The method includes: Constructing a radar emitter signal dataset; Performing time-frequency analysis on the radar signals in the radar emitter signal dataset to obtain a two-dimensional time-frequency diagram; Inputting the two-dimensional time-frequency diagram into a preset radar emitter recognition network for pre-training to obtain a pre-trained model; Using a preset optimization strategy to perform parameter quantization processing and parameter fusion processing on the pre-trained model to obtain a radar emitter recognition model; Deploying and running the radar emitter recognition model through a preset FPGA platform, and then receiving radar emitter signals in real time through the FPGA platform and performing recognition to obtain a recognition result.

2. The method for identifying radar radiation sources based on FPGA according to claim 1, wherein The method for constructing a radar emitter dataset includes: Generating a radar emitter signal dataset through MATLAB simulation. The radar emitter signal dataset includes twelve different modulation methods, namely cw, lfm, nlfm, bpsk, bfsk, qpsk, qfsk, p1, p2, p3, p4, msk. Equal numbers of samples are generated for each signal at signal-to-noise ratios ranging from -10dB to 8dB with an interval of 2dB.

3. A method for identifying radar radiation sources based on FPGA according to claim 1, characterized in that, The method for performing time-frequency analysis on the radar signals in the radar emitter signal dataset to obtain a two-dimensional time-frequency diagram includes: Sampling the radar signals according to a preset data processing clock to obtain AD data; Performing windowing processing on the AD data through a preset window function; In the FPGA, performing time-frequency analysis on the AD data through STFT calculation. The specific formula is: where x(n) is the input sequence, ω(n) is the window function, and R is the step value.

4. The method for identifying a radar radiation source based on FPGA according to claim 3, wherein The preset window function is a Hamming window function.

5. A method for identifying radar radiation sources based on FPGA according to claim 1, characterized in that, The method for the parameter quantization processing includes: According to the characteristics of the FPGA, that is, the quantization bit width of the ADC is 16bit, so the weight value is quantized to 8bit and the bias value is quantized to 16bit; Assuming r represents a floating-point real number and q represents the quantized fixed-point integer, the conversion formula is as follows: r = S(q - Z) where S is the scale, representing the proportional relationship between the real number and the integer, and Z is the zero point, representing the integer corresponding to 0 in the real number after quantization. The calculation method is:

6. The method for identifying a radar radiation source based on FPGA according to claim 1, wherein The method for the parameter fusion processing includes: Fusing the convolutional layer and the BN layer; For the convolutional layer operation: y conv = ωx + b where ω is the weight, x is the input matrix, b is the bias, and y is the output matrix; For the operation of the BN layer: where μ B and σ B 2 are the mean and variance of the input matrix, is the normalized value of the input data, γ and β are the affine parameters of the BN layer, and y i is the output of the BN layer; According to the characteristics of the operation: Among them is the fused weight, is the fused bias.

7. A method for identifying radar radiation sources based on FPGA according to claim 1, characterized in that, The method for deploying and running the radar emitter recognition model through a preset FPGA platform, and then receiving radar emitter signals in real time through the FPGA platform and performing recognition to obtain a recognition result includes: Sampling the radar emitter signals according to a preset data processing clock to obtain real-time AD data; Performing windowing processing on the real-time AD data through a preset window function; In the FPGA, performing time-frequency analysis on the real-time AD data through STFT calculation to obtain a real-time two-dimensional time-frequency diagram; First, passing the real-time two-dimensional time-frequency diagram through a preset ACB module for three convolutional operations, then passing through the BN layer, and finally fusing the data and passing through the ReLu activation layer for output. Next, the data is further used to extract features through a preset 18-layer ResNet residual network; The output of the ResNet residual network simultaneously undergoes channel evaluation through a preset Squeeze-Excitation module. First, each channel obtains its respective weight through an average pooling layer, such that each channel is represented by a value. Then, excitation is performed through two linear layers. Finally, the data passes through a sigmoid activation function to represent the importance of each channel, and then is multiplied by the output of the ResNet residual network; Finally, the data passes through a linear layer to obtain the classification result.

8. A radar emitter recognition system based on FPGA, characterized in that The system includes a dataset construction module, a time-frequency analysis module, a training module, an optimization module, and a signal real-time recognition module; The dataset construction module is used to construct a radar emitter signal dataset; The time-frequency analysis module is used to perform time-frequency analysis on the radar signals in the radar emitter signal dataset to obtain a two-dimensional time-frequency diagram; The training module is used to input the two-dimensional time-frequency diagram into a preset radar emitter recognition network for pre-training to obtain a pre-trained model; The optimization module is used to perform parameter quantization processing and parameter fusion processing on the pre-trained model using a preset optimization strategy to obtain a radar emitter recognition model; The signal real-time recognition module is used to deploy and run the radar emitter recognition model through a preset FPGA platform, and then receive radar emitter signals in real time through the FPGA platform and perform recognition to obtain a recognition result.

9. A computer-readable storage medium storing a computer program thereon, characterized in that: When the computer program is executed by a processor, it implements the steps of a method for identifying radar emitters based on FPGA according to any one of claims 1 to 7.

10. A computer device, characterized in that: It includes a storage medium, a processor, and a computer program stored in the storage medium and executable by the processor. When the computer program is executed by the processor, it implements the steps of a method for identifying radar emitters based on FPGA according to any one of claims 1 to 7.

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