EDIF netlist-level circuit analysis method based on Virtuoso
By automatically refreshing the CDF parameters in the EDIF netlist-level circuit using program1.il written in Virtuoso, the problem of inconsistent parameters after import is solved, and the accuracy and efficiency of circuit analysis are improved.
Patent Information
- Application Number
- CN202510582270.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-07
- Publication Date
- 2025-08-01
AI Technical Summary
When performing EDIF netlist-level circuit analysis in the Cadence Virtuoso environment, the parameter values in the exported cdl netlist are inconsistent with the parameter values displayed in the circuit diagram, which affects the accuracy and efficiency of the circuit analysis.
Virtuoso automatically traverses the design units in the target Library library through program script file program1.il written using SKILL IDE, locates device instances and refreshes the value of the callback function defined in the CDF parameter list using the evalstring function to ensure parameter consistency.
Improves the accuracy and efficiency of circuit analysis, ensures the consistency of imported EDIF netlist-level circuit parameters, and is suitable for various PDKs without modifying the existing PDK interface.
Smart Images
Figure CN120409368A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to an EDIF netlist-level circuit analysis method based on Virtuoso. Background Art
[0002] Hierux is an EDA (Electronic Design Automation) software tool commonly used for chip reverse analysis. It can hierarchically process the extracted netlist and divide it into different levels and modules according to the functional and structural characteristics of the circuit, making the circuit structure clearer. The circuit structure sorted out by Hierux can be exported as an EDIF (Electronic Design Interchange Format) file through the EDIF function, and some are also called EDF (Electronic Design Format) files. This EDIF file can play a role in transferring and exchanging circuit design data, facilitating continued work between different EDA software tools.
[0003] Cadence Virtuoso is a customized integrated circuit (IC) design platform, mainly used for the design, simulation, and verification of analog / mixed-signal (AMS), radio frequency (RF), and digital customized circuits. It provides a full-process tool chain from schematic design to physical layout implementation and is widely adopted by global semiconductor companies, foundries, and design institutions. Importing the EDIF file output by Hierux into the Cadence Virtuoso environment can perform subsequent circuit analysis and design to meet circuit design requirements. Since among the PDKs (Process Design Kits) provided by different manufacturers, some parameter values are not directly given but are obtained through specific calculation methods based on other relevant parameters. This calculation method ensures that in different design scenarios, these parameters can be automatically adjusted according to the changes in other relevant parameters to meet the specific requirements and constraints of process design. However, the instances generated after importing the EDIF netlist-level circuit into Virtuoso cannot automatically refresh the values of this part of the dependency relationship, resulting in inconsistent parameter values between the exported cdl netlist and the parameter values shown in the circuit diagram, thus affecting the subsequent circuit analysis of the EDIF file and the accuracy and efficiency of circuit analysis. Summary of the Invention
[0004] In view of the above problems and technical requirements, this application proposes an EDIF netlist-level circuit analysis method based on Virtuoso. The technical solution of this application is as follows:
[0005] An EDIF netlist-level circuit analysis method based on Virtuoso. The EDIF netlist-level circuit analysis method implemented by loading the program script file program1.il pre-written using SKILL IDE in Virtuoso includes:
[0006] Use the foreach function to sequentially traverse each design unit in each target Library library called by the imported EDIF netlist-level circuit, and locate the device instances from the target PDK in the design unit as the target device instances;
[0007] Obtain the CDF parameter list of the target device instances in the design unit;
[0008] Based on the imported EDIF netlist-level circuit, use the evalstring function to refresh the values of the CDF parameters that define the callback function in the CDF parameter list of the target device instances;
[0009] After completing the CDF parameter value refresh for all target device instances of all design units in the target Library library, perform circuit analysis on the EDIF netlist-level circuit after the parameter refresh.
[0010] A further technical solution thereof is that obtaining the CDF parameter list of the target device instances in the design unit includes:
[0011] The obtained CDF parameter list contains all CDF parameters of the target device instances defined by the target PDK;
[0012] Or, the obtained CDF parameter list contains the CDF parameters of the target device instances in the imported EDIF netlist-level circuit.
[0013] A further technical solution thereof is that obtaining the CDF parameters of the target device instances in the imported EDIF netlist-level circuit to obtain the CDF parameter list includes:
[0014] Initialize the CDF parameter list to be empty, use the inst->prop instruction to sequentially traverse each CDF parameter of the target device instances in the imported EDIF netlist-level circuit, and add the parameter name of each traversed CDF parameter to the CDF parameter list until the CDF parameter list is obtained after the traversal is completed.
[0015] A further technical solution thereof is that obtaining all CDF parameters of the target device instances defined by the target PDK to obtain the CDF parameter list includes:
[0016] Initialize the CDF parameter list to be empty. Obtain all CDF parameter objects of the target device instance defined by the target PDK through the cdfGetInstCDF function. Use the cdf->parameters instruction to traverse each CDF parameter in the CDF parameter object in sequence, and add the parameter name of each traversed CDF parameter to the CDF parameter list until the CDF parameter list is obtained after the traversal is completed.
[0017] Its further technical solution is that refreshing the value of the CDF parameter that defines the callback function in the CDF parameter list of the target device instance using the evalstring function includes:
[0018] Use the foreach function to traverse each parameter name in the CDF parameter list of the target device instance in sequence. When it is determined that the CDF parameter corresponding to the currently traversed parameter name defines a callback function, use the evalstring function to refresh the value of the CDF parameter corresponding to the currently traversed parameter name; otherwise, continue to traverse the next parameter name in the CDF parameter list.
[0019] Its further technical solution is that detecting whether the CDF parameter corresponding to the currently traversed parameter name defines a callback function includes:
[0020] Use the cdfGetBaseCellCDF function to obtain all CDF parameter objects of the design cell of the target device instance in the target PDK. Different CDF parameters in the CDF parameter object have their own parameter attributes and are distinguished by their respective parameter names;
[0021] Use cdfFindParamByName to obtain the parameter attribute of the CDF parameter corresponding to the currently traversed parameter name in the CDF parameter object;
[0022] Detect whether the parameter attribute of the CDF parameter corresponding to the currently traversed parameter name in the CDF parameter object defines a callback function.
[0023] Its further technical solution is that locating the device instance from the target PDK in the design cell as the target device instance includes:
[0024] Use dbOpenCellViewByType to read the schematic view of the currently traversed design cell, and use the member function to detect whether there is a device instance from the target PDK in the schematic view;
[0025] When a device instance from the target PDK is detected in the schematic view, further determine the device instances from the target PDK contained in the currently traversed design unit as the target device instances;
[0026] When no device instance from the target PDK is detected in the schematic view, continue to traverse the next design unit until all design units in the target Library are traversed.
[0027] A further technical solution thereof is that determining the device instances from the target PDK contained in the currently traversed design unit as the target device instances includes:
[0028] Use the dbReopen function to open the cellview of the currently traversed design unit in a writable manner;
[0029] Locate the device instances in the cellview of the currently traversed design unit whose library name libname is the same as the name of the target PDK as the target device instances in the currently traversed design unit.
[0030] A further technical solution thereof is that the EDIF netlist-level circuit analysis method further includes:
[0031] Obtain the configuration parameters input by the user through the user GUI interface, and determine the target Library according to the configuration parameters; when multiple target Libraries are determined according to the library configuration parameters, use the foreach function to traverse each design unit in each target Library in turn.
[0032] A further technical solution thereof is that the program script file program1.il is pre-written into a parameter refresh tool drop-down menu of Virtuoso by using the SKILL IDE and mounted on the CIW window to obtain the program script file program2.il, and the program script file program2.il is added to the Virtuoso startup file.cdsinit; the implementation of the EDIF netlist-level circuit analysis method by Virtuoso loading the program script file program1.il includes:
[0033] After Virtuoso starts, it loads the startup file.cdsinit and executes the program script file program2.il to display the parameter refresh tool drop-down menu on the CIW window. When a trigger operation on the parameter refresh tool drop-down menu is received, execute the program script file program1.il to execute the EDIF netlist-level circuit analysis method.
[0034] The beneficial technical effects of this application are:
[0035] The present application discloses a method for analyzing an EDIF netlist-level circuit based on Virtuoso. By executing a program script file program1.il written in advance using SKILL IDE, Virtuoso can automatically traverse each design unit cell in the target Library library, and locate the device instances from the target PDK in each design unit cell as the target device instances ins. Then, based on the imported EDIF netlist-level circuit, the evalstring function is used to refresh the values of the CDF parameters that define callback functions in the CDF parameter list of the target device instances ins. After completing the parameter refresh to maintain parameter consistency, the EDIF netlist-level circuit is analyzed. This method extends its automated operation function using the secondary development interface of Virtuoso, and adds a preprocessing operation of parameter refresh before analyzing the imported EDIF netlist-level circuit, which is beneficial to improving the accuracy and efficiency of subsequent circuit analysis. Brief Description of the Drawings
[0036] Figure 1 It is a flowchart of the method for analyzing an EDIF netlist-level circuit according to an embodiment of the present application. Detailed Embodiments
[0037] The following further describes the detailed embodiments of the present application with reference to the drawings.
[0038] The present application discloses a method for analyzing an EDIF netlist-level circuit based on Virtuoso. This EDIF netlist-level circuit analysis method is automatically implemented by the Virtuoso software tool executing the program script file program1.il, and this program script file program1.il is written in advance using SKILL IDE.
[0039] After importing the EDIF netlist-level circuit into Virtuoso, trigger Virtuoso to execute the program script file program1.il to perform circuit analysis on the imported EDIF netlist-level circuit according to the following method, including the following steps. Please refer to Figure 1 the flowchart:
[0040] Step 1: Use the foreach function to sequentially traverse each design unit cell called by the imported EDIF netlist-level circuit in each target Library library, and locate the device instances from the target PDK in each design unit cell as the target device instances ins.
[0041] For each traversed design cell, first use dbOpenCellViewByType to read the schematic view of the currently traversed design cell, and use the member function to check whether there is a device instance from the target PDK in the schematic view. In the SKILL language, the member function is used to check whether an element exists in a list. In this step, the member function is used to check whether the name of the target PDK exists in the schematic view. If it is detected, it means that there is a device instance from the target PDK in the schematic view. Otherwise, it is determined that there is no device instance from the target PDK in the schematic view. The target PDK here is determined according to the actual PDK selected. For example, a common target PDK is umc28hpc.
[0042] When it is detected that there is no device instance from the target PDK in the schematic view, the design unit cell is no longer processed further, but the next design unit is traversed until all design units in the target library are traversed.
[0043] When a device instance from the target PDK is detected in the schematic view, the device instance from the target PDK contained in the currently traversed design unit is further determined as the target device instance. This includes: using the dbReopen function to open the cellview of the currently traversed design unit cell in a writable manner, and then locating the device instance in the cellview of the currently traversed design unit whose library name libname is consistent with the name of the target PDK as the target device instance in the currently traversed design unit. This is specifically achieved by calling the rexMatchP function.
[0044] By traversing in sequence according to the above method, you can find the design unit cells in the target library that contain device instances from the target PDK, and determine the target device instances of these design unit cells respectively.
[0045] On this basis, there are one or more target libraries. When there are multiple target libraries, use the foreach function to traverse each target library in turn, and traverse each target library according to the method in step 1 to determine the target device instance.
[0046] In one embodiment, when Virtuoso is triggered to execute the program script file program1.il, it first jumps to the user GUI interface, where the user can input configuration parameters, including the name of the target Library. Correspondingly, Virtuoso obtains the configuration parameters input by the user through the user GUI interface and determines the target Library to be traversed according to the configuration parameters.
[0047] Step 2: Obtain the CDF parameter list of each target device instance in the currently traversed design unit. The obtained CDF parameter list of the target device instance includes the parameter names of multiple CDF parameters. In actual applications, there are two cases:
[0048] The first case: The obtained CDF parameter list contains all the CDF parameters of the target device instance defined by the target PDK. In this way, the obtained CDF parameter list has higher parameter integrity and avoids missing CDF parameters. The obtaining method includes: initializing the CDF parameter list to be empty, obtaining all CDF parameter objects of the target device instance defined by the target PDK through the cdfGetInstCDF function, using the cdf->parameters instruction to sequentially traverse each CDF parameter in the CDF parameter object, and adding the parameter name of each traversed CDF parameter to the CDF parameter list until the CDF parameter list is obtained after the traversal is completed. In the case of a comprehensive update or check, it is necessary to trigger all relevant callback functions at one time to ensure the consistency of all parameters. For example, when batch modifying parameters or generating a netlist, this method is usually used to achieve this.
[0049] The second case: The obtained CDF parameter list contains the CDF parameters of the target device instance in the imported EDIF netlist-level circuit. Compared with the first case, the CDF parameter list obtained in this case may only contain some of the CDF parameters of the target device instance defined by the target PDK. In this way, the data volume of the obtained CDF parameter list is smaller, which is beneficial to improving the processing efficiency. Obtaining method: Initialize the CDF parameter list to be empty, use the inst->prop instruction to sequentially traverse each CDF parameter of the target device instance in the imported EDIF netlist-level circuit, and add the parameter name of each traversed CDF parameter to the CDF parameter list until the CDF parameter list is obtained after the traversal is completed.
[0050] In actual implementation, Virtuoso executes according to one of the situations by default. Alternatively, if the configuration parameters that the user can input in the user GUI interface also include mode parameters, then Virtuoso obtains the configuration parameters input by the user through the user GUI interface, and determines whether to adopt the first situation or the second situation according to the mode parameters in the configuration parameters, which has higher flexibility.
[0051] Step 3: Based on the imported EDIF netlist-level circuit, use the evalstring function to refresh the value of the CDF parameter that defines the callback function in the CDF parameter list of the target device instance.
[0052] As described above, only the parameter names of each CDF parameter are recorded in the CDF parameter list. First, use the foreach function to traverse the parameter names of each CDF parameter in the CDF parameter list of the target device instance in turn. For each parameter name traversed:
[0053] Detect whether the CDF parameter corresponding to the parameter name defines a callback function, including: use the cdfGetBaseCellCDF function to obtain all CDF parameter objects of the design unit of the target device instance in the target PDK. Different CDF parameters in the CDF parameter object have their own parameter attributes and are distinguished by their respective parameter names. The parameter attributes of each CDF parameter record various attributes of the CDF parameter, including basic information, constraint conditions, behavior control and other attributes. Then use cdfFindParamByName to obtain the parameter attributes of the CDF parameter corresponding to the currently traversed parameter name in the CDF parameter object, and determine whether the parameter attributes of the CDF parameter corresponding to the currently traversed parameter name in the CDF parameter object define a callback function.
[0054] When it is determined that the CDF parameter corresponding to the currently traversed parameter name defines a callback function, it means that the CDF parameter corresponding to the parameter name has a callback attribute. Use the evalstring function to refresh the value of the CDF parameter corresponding to the currently traversed parameter name, that is, use the evalstring function to recalculate the value of the callback function of the CDF parameter corresponding to the currently traversed parameter name to refresh the value of the CDF parameter.
[0055] When it is determined that the CDF parameter corresponding to the currently traversed parameter name does not define a callback function, it means that the CDF parameter corresponding to the parameter name does not have a callback attribute, and then continue to traverse the next parameter name in the CDF parameter list.
[0056] In the CDF parameters of the PDK, the role of defining the callback function is as follows:
[0057] (1) Implement parameter association and automatic calculation: Callback functions can be used to establish association relationships between parameters. When the value of a parameter changes, the callback function can be used to automatically trigger the calculation and update of other related parameters, ensuring the consistency and correctness of the parameters.
[0058] (2) Perform parameter verification and constraint checking: When the user inputs or modifies a parameter value, the callback function can be used to perform verification operations, that is, to check whether the input parameter value is within the allowed range and whether it meets specific design rules and constraint conditions. Otherwise, a warning will be given or it will be blocked, which helps to ensure the feasibility and reliability of the design.
[0059] Therefore, CDF parameters without a defined callback function and without the callback attribute do not have the above-mentioned associations and constraints, and there will be no parameter inconsistency.
[0060] For example, in an instance, a certain parameter of a certain instance in the EDIF netlist-level circuit exported by Hierux is defined as w = 0.35u. When importing this EDIF netlist-level circuit into Virtuoso, it will find the w parameter in the CDF parameters of this instance and then assign the value 0.35u to the w parameter. However, for the exported cdl netlist, for example, the value of w is fw, and the value of fw = iPar("w") / iPar("fingers"). Its value cannot be modified on the interface and should be automatically calculated based on the w parameter and the fingers parameter. At this time, it is necessary to trigger the callback of the w parameter to refresh the value of fw to 350n. When the EDIF netlist-level circuit is imported, only the value of w is assigned. The above method of the present application triggers it to be refreshed, so that the associated value is updated.
[0061] Step 4, after the CDF parameter value refreshing of all target device instances of all design units in the target Library library is completed, that is, after the value refreshing of the CDF parameters with defined callback functions in all target Library libraries is completed according to the above steps 1 to 3, it is determined that the parameters in the cdl netlist and the parameters displayed in the circuit diagram have reached consistency. At this time, subsequent circuit analysis is performed on the EDIF netlist-level circuit after parameter refreshing, effectively avoiding the influence and interference of parameter inconsistency on circuit analysis. The specific subsequent circuit analysis method can be carried out according to actual analysis requirements, and the present application will not elaborate on this.
[0062] Based on the EDIF netlist-level circuit analysis method provided in this application, Virtuoso will first perform pre-processing operations for parameter refresh on the imported EDIF netlist-level circuit before performing circuit analysis. Although some PDKs currently provide interfaces for parameter refresh, such as TSMC (TSMC) provides the TSMC PDK Tools->Update design (instance) CDF interface for parameter refresh, most mainstream PDKs do not provide this function. The method provided in this application uses the SKILL language for secondary development to write the program script file program1.il. Without the need to modify or expand the functions of the existing PDK, Virtuoso can automatically complete the pre-processing operations for parameter refresh. This method is compatible with various PDKs, has a wide range of applications, and has good application effects.
[0063] Furthermore, after writing the program script file program1.il according to the application logic of the EDIF netlist-level circuit analysis method to be implemented, use SKILL IDE to write the program script file program1.il into Virtuoso's parameter refresh tool drop-down menu and mount it on the CIW window to obtain the program script file program2.il, and add the program script file program2.il to Virtuoso's startup file .cdsinit. After Virtuoso starts and loads the startup file .cdsinit, it can automatically execute the program script file program2.il, so that the parameter refresh tool drop-down menu is displayed on the CIW window. When the user needs to trigger the parameter refresh operation after importing the EDIF netlist-level circuit, the parameter refresh tool drop-down menu on the CIW window can be triggered. When Virtuoso receives the trigger operation acting on the parameter refresh tool drop-down menu, it automatically executes the program script file program1.il to perform the above-mentioned EDIF netlist-level circuit analysis method, which is convenient for application.
[0064] The above description is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the scope of protection of the present application.
Claims
1. A Virtuoso-based EDIF netlist-level circuit analysis method, characterized in that, The EDIF netlist-level circuit analysis method implemented by loading the program script file program1.il pre-written using the SKILL IDE in Virtuoso includes: Using the foreach function to sequentially traverse each design unit in the target Library library called by the imported EDIF netlist-level circuit, and locating the device instances from the target PDK in the design unit as the target device instances; Obtaining the CDF parameter list of the target device instances in the design unit; Based on the imported EDIF netlist-level circuit, using the evalstring function to refresh the values of the CDF parameters that define callback functions in the CDF parameter list of the target device instances; After completing the refresh of the CDF parameter values for all target device instances of all design units in the target Library library, perform circuit analysis on the EDIF netlist-level circuit after the parameter refresh.
2. The EDIF netlist-level circuit analysis method according to claim 1, wherein Obtaining the CDF parameter list of the target device instances in the design unit includes: The obtained CDF parameter list contains all CDF parameters of the target device instances defined by the target PDK; Or, the obtained CDF parameter list contains the CDF parameters of the target device instances in the imported EDIF netlist-level circuit.
3. The EDIF netlist-level circuit analysis method according to claim 2, wherein Obtaining the CDF parameters of the target device instances in the imported EDIF netlist-level circuit to obtain the CDF parameter list includes: Initializing the CDF parameter list to be empty, using the inst->prop instruction to sequentially traverse each CDF parameter of the target device instances in the imported EDIF netlist-level circuit, and adding the parameter names of each traversed CDF parameter to the CDF parameter list until the CDF parameter list is obtained after the traversal is completed.
4. The EDIF netlist-level circuit analysis method according to claim 2, wherein, Obtaining all CDF parameters of the target device instances defined by the target PDK to obtain the CDF parameter list includes: Initializing the CDF parameter list to be empty, obtaining all CDF parameter objects of the target device instances defined by the target PDK through the cdfGetInstCDF function, using the cdf->parameters instruction to sequentially traverse each CDF parameter in the CDF parameter objects, and adding the parameter names of each traversed CDF parameter to the CDF parameter list until the CDF parameter list is obtained after the traversal is completed.
5. The EDIF netlist-level circuit analysis method according to claim 1, wherein Using the evalstring function to refresh the values of the CDF parameters that define callback functions in the CDF parameter list of the target device instances includes: Using the foreach function to sequentially traverse the parameter names of each CDF parameter in the CDF parameter list of the target device instances. When it is determined that the CDF parameter corresponding to the currently traversed parameter name defines a callback function, use the evalstring function to refresh the value of the CDF parameter corresponding to the currently traversed parameter name, otherwise continue to traverse the next parameter name in the CDF parameter list.
6. The EDIF netlist-level circuit analysis method according to claim 5, wherein Detecting whether the CDF parameter corresponding to the currently traversed parameter name defines a callback function includes: Use the cdfGetBaseCellCDF function to obtain all CDF parameter objects of the design cell of the target device instance in the target PDK. Different CDF parameters in the CDF parameter object have their own parameter attributes and are distinguished by their respective parameter names; Use cdfFindParamByName to obtain the parameter attributes of the CDF parameter corresponding to the currently traversed parameter name in the CDF parameter object; Detect whether the parameter attributes of the CDF parameter corresponding to the currently traversed parameter name in the CDF parameter object define a callback function.
7. The EDIF netlist-level circuit analysis method according to claim 1, wherein Locating the device instance from the target PDK in the design cell as the target device instance includes: Use dbOpenCellViewByType to read the schematic view of the currently traversed design cell, and use the member function to detect whether there is a device instance from the target PDK in the schematic view; When it is detected that there is a device instance from the target PDK in the schematic view, further determine the device instance from the target PDK included in the currently traversed design cell as the target device instance; When it is detected that there is no device instance from the target PDK in the schematic view, continue to traverse the next design cell until all design cells in the target Library library are traversed.
8. The EDIF netlist-level circuit analysis method according to claim 7, characterized in that Determining the device instance from the target PDK included in the currently traversed design cell as the target device instance includes: Use the dbReopen function to open the cellview of the currently traversed design cell in a writable manner; Locate the device instance in the cellview of the currently traversed design cell whose library name libname is the same as the name of the target PDK as the target device instance in the currently traversed design cell.
9. The EDIF netlist-level circuit analysis method according to claim 1, characterized in that The EDIF netlist-level circuit analysis method further includes: Obtain the configuration parameters input by the user through the user GUI interface, and determine the target Library library according to the configuration parameters; when multiple target Library libraries are determined according to the library configuration parameters, use the foreach function to traverse each design cell in each target Library library in turn.
10. The EDIF netlist-level circuit analysis method according to claim 1, wherein Previously use the SKILL IDE to write the program script file program1.il as a parameter refresh tool drop-down menu of Virtuoso and mount it on the CIW window to obtain the program script file program2.il, and add the program script file program2.il to the startup file.cdsinit of Virtuoso; Virtuoso loads the program script file program1.il to implement the EDIF netlist-level circuit analysis method, including: After Virtuoso starts, it loads the startup file.cdsinit and executes the program script file program2.il to display the parameter refresh tool drop-down menu on the CIW window. When a trigger operation acting on the parameter refresh tool drop-down menu is received, it executes the program script file program1.il to execute the EDIF netlist-level circuit analysis method.