Access verification method and device and medium

Abstract

The invention discloses an access verification method and device and a medium, and relates to the technical field of computers. Aiming at the problem that the verification accuracy is influenced due to the interference of other modules when the correctness of the NVMe controller accessing a host side annular queue is verified at present, the invention provides an access verification method which comprises the following steps: directly intercepting data directly received and transmitted by the NVMe controller from a bus at an inlet end and an outlet end of the NVMe controller, and extracting CQE and SQE from the data. Therefore, the obtained CQE and SQE are only related to the NVMe controller, the interference of other modules can be avoided, and the accuracy is higher when the CQE and SQE are used for correctly verifying that the NVMe controller accesses the host side annular queue. Moreover, according to the method, correct verification of the CQE and the SQE is realized in two aspects of verifying the address and the field, so that more comprehensive and accurate NVMe controller access verification is realized, and the verification accuracy is further improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and particularly to an access verification method, apparatus, and medium. Background Art

[0002] As an important part of ensuring the correctness of chip design, chip front-end verification has strong practical significance for verifying the correctness of the NVMe (a logical device interface specification) controller's access to the host-side ring queue. In related technologies, the commonly used verification method is to directly read the Submission Queue Entry (SQE) and Completion Queue Entry (CQE) at the source address and destination address to verify the correctness of data transmission.

[0003] However, this verification method is affected by other modules on the data path. For example, although the NVMe controller has written the correct CQE into the correct memory of the host, command requests from other modules may accidentally write new data to this memory address, which may cause the CQE data comparison to fail, thereby affecting the accuracy of verification. Similar problems also exist for the verification of SQE.

[0004] Therefore, those skilled in the art now urgently need an access verification method to solve the problem that when verifying the correctness of the NVMe controller's access to the host-side ring queue, the verification accuracy is affected by interference from other modules. Summary of the Invention

[0005] The purpose of the present invention is to provide an access verification method, apparatus, and medium to solve the problem that when verifying the correctness of the NVMe controller's access, the verification accuracy is affected by interference from other modules.

[0006] To solve the above technical problems, the present invention provides an access verification method, including:

[0007] Respectively intercept the data transmitted on the buses connected to the inlet end and the outlet end of the NVMe controller;

[0008] Respectively extract from the intercepted data the submission queue entries and completion queue entries for the NVMe controller to communicate with the host, and the submission queue entries and the completion queue entries for the NVMe controller to communicate with the disk;

[0009] According to the submission queue entries and the completion queue entries, verify the correctness of the NVMe controller's access to the wrap-around addresses of the host submission queue and completion queue, and verify the field correctness of the NVMe controller reading the host submission queue entries and replying to the host completion queue entries.

[0010] In a possible embodiment, according to the submission queue entry and the completion queue entry, verifying the correctness of the NVMe controller accessing the host submission queue and the completion queue wrap-around addresses includes:

[0011] Extracting the submission queue address corresponding to the host in the submission queue entry and the completion queue address corresponding to the host in the completion queue entry;

[0012] Checking whether the submission queue address is consistent with the corresponding theoretical address. If so, it is determined that the NVMe controller accessing the host submission queue wrap-around address is correct;

[0013] Checking whether the completion queue address is consistent with the corresponding theoretical address. If so, it is determined that the NVMe controller accessing the host completion queue wrap-around address is correct;

[0014] Wherein, the theoretical address is determined by the base address of the host memory allocation and the queue depth when the host creates the submission queue / the completion queue.

[0015] In a possible embodiment, the submission queue includes: a management submission queue and an input / output submission queue;

[0016] The submission queue address includes: a management submission queue address and an input / output submission queue address;

[0017] The completion queue includes: a management completion queue and an input / output completion queue;

[0018] The completion queue address includes: a management completion queue address and an input / output completion queue address;

[0019] The extracting the submission queue address corresponding to the host in the submission queue entry and the completion queue address corresponding to the host in the completion queue entry further includes:

[0020] Extracting the submission queue number of the input / output submission queue address and extracting the completion queue number of the input / output completion queue;

[0021] The theoretical address corresponding to the input / output submission queue address / the input / output completion queue is further determined according to the submission queue number / the completion queue number.

[0022] In a possible embodiment, respectively extracting from the intercepted data the submission queue entry and the completion queue entry for the NVMe controller to communicate with the host, and the submission queue entry and the completion queue entry for the NVMe controller to communicate with the disk includes:

[0023] Extract all addresses from the intercepted data;

[0024] Determine whether each of the addresses is within the address range corresponding to the submission queue / the completion queue;

[0025] If so, save the address as the submission queue address / the completion queue address to the queue associated with the submission queue entry / the completion queue entry queue;

[0026] Wherein, the address range corresponding to the submission queue / the completion queue is determined by the base address, the queue depth, and the number of queues allocated by the host memory when the host creates the submission queue / the completion queue.

[0027] In a possible embodiment, the address range corresponding to the input / output submission queue / the input / output completion queue is further determined according to the submission queue number / the completion queue number;

[0028] When the address corresponds to the input / output submission queue address / the input / output completion queue, the address is saved to the queue associated with the corresponding submission queue number / the completion queue number.

[0029] In a possible embodiment, verifying the field correctness of the NVMe controller reading the host submission queue entry and replying to the host completion queue entry according to the submission queue entry and the completion queue entry includes:

[0030] Extract the field information in the host corresponding submission queue entry as the first submission field, and extract the field information in the disk corresponding submission queue entry as the second submission field;

[0031] Compare whether the first submission field and the second submission field are the same. If so, determine that the NVMe controller reads the host submission queue entry field correctly;

[0032] Extract the field information in the host corresponding completion queue entry as the first completion field, and extract the field information in the disk corresponding completion queue entry as the second completion field;

[0033] Verify whether the update of the NVMe controller to the completion queue entry field is correct according to the first completion field and the second completion field. If so, determine that the NVMe controller replies to the host completion queue entry field correctly.

[0034] In a possible embodiment, both the first completion field and the second completion field include: a phase flag bit field, a head pointer field, and other fields;

[0035] Verifying whether the update of the completion queue entry field by the NVMe controller is correct according to the first completion field and the second completion field includes:

[0036] Determining whether the phase flag bit field in the second completion field is correctly inverted relative to the first completion field; if so, determining that the update of the phase flag bit field is correct;

[0037] Verifying whether the head pointer field in the second completion field is correctly updated relative to the first completion field through the root complex VIP;

[0038] Performing a global segment comparison on other fields in the first completion field and the second completion field; if they are consistent, determining that the update of the other fields is correct;

[0039] Wherein, when the phase flag bit field, the head pointer field, and the other fields are all updated correctly, it is determined that the update of the completion queue entry field by the NVMe controller is correct.

[0040] In a possible embodiment, the first completion field and the second completion field further include: a submission queue number field;

[0041] Verifying whether the update of the completion queue entry field by the NVMe controller is correct according to the first completion field and the second completion field further includes:

[0042] Determining the corresponding submission queue number according to the completion queue address in the completion queue entry;

[0043] Querying the submission queue number pre-bound with the completion queue number;

[0044] Comparing whether the bound submission queue number and the submission queue number field are consistent; if so, determining that the update of the submission queue number field is correct;

[0045] Wherein, when the phase flag bit field, the head pointer field, the other fields, and the submission queue number field are all updated correctly, it is determined that the update of the completion queue entry field by the NVMe controller is correct.

[0046] To solve the above technical problems, the present invention further provides an access verification device, including:

[0047] An interception module, configured to respectively intercept data transmitted on the buses connected to the entry end and the exit end of the NVMe controller;

[0048] An extraction module, configured to respectively extract the submission queue entries and completion queue entries for the NVMe controller to communicate and transmit with the host, and the submission queue entries and the completion queue entries for the NVMe controller to communicate and transmit with the disk from the intercepted data;

[0049] A verification module, configured to verify the correctness of the NVMe controller accessing the host submission queue and completion queue wrap-around addresses according to the submission queue entries and the completion queue entries, and verify the field correctness of the NVMe controller reading the host submission queue entries and replying to the host completion queue entries.

[0050] To solve the above technical problems, the present invention further provides an access verification device, including:

[0051] A memory, configured to store a computer program;

[0052] A processor, configured to implement the steps of the above-mentioned access verification method when executing the computer program.

[0053] To solve the above technical problems, the present invention further provides a non-volatile storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned access verification method are implemented.

[0054] An access verification method provided by the present invention directly intercepts the data directly transmitted and received by the NVMe controller from the bus at the entrance end and the exit end of the NVMe controller, and extracts CQEs and SQEs therefrom. The obtained CQEs and SQEs are only related to the NVMe controller, which can avoid the interference of other modules, and has higher accuracy when used for correctly verifying the NVMe controller accessing the host-side circular queue. Moreover, this method realizes the correct verification of CQEs and SQEs by verifying both the address and the field, so as to realize a more comprehensive and accurate access verification of the NVMe controller, and further improve the verification accuracy.

[0055] The access verification device and the non-volatile storage medium provided by the present invention correspond to the above method, and have the same effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] To more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0057] Figure 1 A verification framework diagram of an access verification method provided by an embodiment of the present invention;

[0058] Figure 2 Flowchart of an access verification method provided by an embodiment of the present invention;

[0059] Figure 3 Schematic diagram of a host queue bottoming out and wrapping around provided by an embodiment of the present invention;

[0060] Figure 4 Schematic diagram of the flipping of the Phase Tag field in a CQE provided by an embodiment of the present invention;

[0061] Figure 5 Flowchart of an address verification scheme provided by an embodiment of the present invention;

[0062] Figure 6 Flowchart of a field verification scheme provided by an embodiment of the present invention;

[0063] Figure 7 Structural diagram of an access verification device provided by an embodiment of the present invention;

[0064] Figure 8 Structural diagram of another access verification device provided by an embodiment of the present invention. Detailed implementation manners

[0065] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0066] The core of the present invention is to provide an access verification method, device and medium.

[0067] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0068] In the related art, to verify the correctness of an NVMe (a logical device interface specification) controller accessing the host-side ring queue, it is usually to directly read the Submission Queue Entries (SQEs) and Completion Queue Entries (CQEs) at the source address and the destination address to achieve the correctness verification of data transmission. However, since there are other modules in the data path leading to the host memory, the correct CQEs written by the NVMe controller may be changed by other modules. At this time, an abnormal problem may occur where the NVMe controller writes correctly but the verification fails. After the error occurs, relevant personnel will immediately check whether there is a problem with the NVMe controller, even if the error has nothing to do with the NVMe controller, which undoubtedly reduces the efficiency of troubleshooting design problems.

[0069] To solve the above problems, the present invention provides an access verification method, and its application architecture and verification framework are as Figure 1 shown, and the flow of the method steps is as Figure 2 shown, including:

[0070] S1: Intercept the data transmitted on the buses connected to the inlet end and the outlet end of the NVMe controller respectively.

[0071] S2: Extract from the intercepted data the submission queue entries and completion queue entries for the NVMe controller to communicate with the host, as well as the submission queue entries and completion queue entries for the NVMe controller to communicate with the disk.

[0072] S3: According to the submission queue entries and completion queue entries, verify the correctness of the NVMe controller accessing the host submission queue and the completion queue wrap-around addresses, and verify the field correctness of the NVMe controller reading the host submission queue entries and replying to the host completion queue entries.

[0073] It should be noted that the inlet end of the NVMe controller refers to the port for receiving commands, and the corresponding core component is the Submission Queue (SQ). The outlet end of the NVMe controller refers to the port for feeding back results, and the corresponding core component is the Completion Queue (CQ).

[0074] From Figure 1 it is not difficult to see that although this method verifies the correctness of the NVMe controller accessing the host queue, it also involves the NVMe controller and the disk (such as Figure 1Data transmission of the solid-state drive (SSD) therein. For both the data interaction between the NVMe controller and the host and the data interaction between the NVMe controller and the disk, the two-way data transmission is achieved through a bus (such as the PCIe bus). Therefore, there are actually two groups of the inlet and outlet ends involved by the NVMe controller, one group is relative to the host side, and the other group is relative to the disk side. The data captured in step S1 is the data at these two groups of inlet and outlet ends. In other words, step S1 also captures the data transmitted between the NVMe controller and the host and the disk. However, the data is captured from the side of the port close to the NVMe controller in the data path to avoid interference from other modules.

[0075] After the data intercepted in step S1, step S2 can parse the intercepted data based on the communication protocol on which the data path established between the NVMe controller and the host and the disk is based, and extract the SQE and CQE therein. It should be noted that the directions of SQE and CQE are both for the host. Therefore, the data extracted from the disk transmitted to the NVMe controller still corresponds to CQ, and the data transmitted from the NVMe controller to the disk still corresponds to SQ. And, regarding how to parse the data in step S2, it needs to be determined according to the communication protocol used for the communication between the NVMe controller and the host and the disk. This embodiment does not limit this. However, as long as it is an existing communication protocol, it is always known to parse the data packet transmitted in the bus back to the original data based on the communication protocol and extract the SQE and CQE therefrom. Therefore, this embodiment does not elaborate herein.

[0076] It is not difficult to understand that after the above steps S1 and S2, the CQE and SQE for verifying the correctness of the NVMe controller accessing the host queue can already be obtained. Moreover, the CQE and SQE obtained based on this method are directly obtained from the NVMe controller port and will not be affected by other modules or factors, and can most directly reflect the NVMe protocol consistency when the NVMe controller interacts with the host. Therefore, no matter what method is used to verify the CQE and SQE subsequently, compared with the verification scheme in the related art, this method can avoid the interference brought by other modules or factors in the data path, thereby improving the verification accuracy. In other words, this embodiment does not limit how to implement the verification of CQE and SQE in step S3. The verification method in the related art or any other verification method can be used, and the purpose of improving the verification accuracy can be achieved.

[0077] As described above, this method directly captures data at the input and output ends of the NVMe controller to obtain the CQE and SQE that most directly reflect the input and output of the NVMe controller, avoiding interference caused by other modules or factors in the data path. Therefore, the correctness verification of the NVMe controller's access to the host queue is realized accordingly, and higher accuracy can also be achieved. This can avoid interference from causing relevant personnel to incorrectly troubleshoot the design problems of the NVMe controller, thereby improving the verification efficiency of the NVMe controller.

[0078] On the other hand, although the above embodiments have illustrated that the effect of improving the verification accuracy brought by this method is mainly due to steps S1 and S2, there is no limitation on the specific implementation of step S3, and the CQE and SQE verification methods consistent with those in the related art can be adopted. However, the present invention also provides another possible CQE and SQE verification method.

[0079] It is not difficult to know from the above method that the correctness verification of the access to the NVMe controller in this method can be specifically divided into the following two major parts:

[0080] 1. Verify the correctness of the NVMe controller's access to the host SQ / CQ queue wrap-around address;

[0081] 2. Verify the correctness of the NVMe controller's reading of the host SQE and reply to the host CQE fields.

[0082] Then, this method will also be described separately in terms of "address verification" and "field verification" in the following. First, the "address verification" part will be described:

[0083] Based on the above, this embodiment first provides a possible implementation scheme for the above first part (i.e., address verification):

[0084] The above step S3 specifically includes:

[0085] S31-1: Extract the submission queue address in the host corresponding submission queue entry and the completion queue address in the host corresponding completion queue entry.

[0086] S31-2: Check whether the submission queue address is consistent with the corresponding theoretical address. If so, it is determined that the NVMe controller's access to the host submission queue wrap-around address is correct.

[0087] S31-3: Check whether the completion queue address is consistent with the corresponding theoretical address. If so, it is determined that the NVMe controller's access to the host completion queue wrap-around address is correct.

[0088] Among them, the theoretical address is determined by the base address of the host memory allocation and the queue depth when the host creates a submission queue / completion queue. Additionally, there is a parallel relationship between steps S31-2 and S31-3, and there is no requirement for the order of execution.

[0089] First, based on the principle of the NVMe controller accessing the host queue, when the host creates an SQ and a CQ, its address range is determined by the base address (base addr ), queue depth (queue depth ), and the number of queues (queue num ). Therefore, on the premise of knowing the above information, the address of each SQ or CQ can also be calculated, that is, the theoretical address of the SQ or CQ. Furthermore, by comparing the intercepted SQ address with the theoretically calculated SQ address, it can be known whether the NVMe controller correctly accesses the host SQ address, and the CQ address verification is the same.

[0090] However, it should also be noted that as Figure 3 shown, when the NVMe controller accesses the host SQ, it accesses the corresponding host memory address according to the value of the current SQ head doorbell (HDBL) register. When the host SQ is full, the host will write SQE again from the top of the SQ, that is, the value of the SQ tail doorbell (TDBL) register will start from 0 again, and the data will start to wrap around from the bottom.

[0091] It can be seen from this that when the value of the SQ HDBL register accessed by the NVMe controller also reaches the queue maximum value (queue depth -1), it will also start from 0 again. At this time, the SQ address accessed by the NVMe controller will also start from the starting point of the base address SQ addr . Based on this and the above calculation of the theoretical address, accurate address verification can still be ensured when the address sequence increases to exceed queue depth .

[0092] Based on the above embodiments, this embodiment further provides a more advanced implementation scheme:

[0093] The submission queue includes: a management submission queue and an input / output submission queue;

[0094] The submission queue address includes: a management submission queue address and an input / output submission queue address;

[0095] The completion queue includes: a management completion queue and an input / output completion queue;

[0096] The completion queue address includes: a management completion queue address and an input / output completion queue address.

[0097] Correspondingly, step S2 specifically further includes:

[0098] Extract the submission queue number of the input / output submission queue address and the completion queue number of the input / output completion queue.

[0099] The theoretical address corresponding to the input / output submission queue address / input / output completion queue is also determined according to the submission queue number / completion queue number.

[0100] That is, this embodiment provides a more complete address verification method, further dividing SQ into an administrative submission queue (ASQ) and an input / output submission queue (IOSQ), and further dividing CQ into an administrative completion queue (ACQ) and an input / output completion queue (IOCQ). Among them, there is usually only one ASQ, and it is generally located at the head of the SQ address range. There are usually more than one IOSQ, and they need to be distinguished by the SQ number (sq_id). And the address ranges of different IOSQs are generally also related to sq_id. The same applies to ACQ and IOCQ, which will not be elaborated in this embodiment.

[0101] As can be seen from the above, this method further subdivides SQ and CQ, and specifically determines their theoretical addresses according to the differences between ASQ and IOSQ, ACQ and IOCQ, so as to achieve more accurate address verification.

[0102] On the other hand, in addition to the SQ and CQ address verification methods provided in the above embodiments, this embodiment also provides a possible implementation for obtaining the SQ and CQ addresses. Step S2 specifically further includes:

[0103] S21-1: Extract all addresses from the intercepted data.

[0104] S21-2: Respectively determine whether each address is within the address range corresponding to the submission queue / completion queue; if so, go to step S21-3.

[0105] S21-3: Use the address as the submission queue address / completion queue address and save it to the queue associated with the submission queue entry / completion queue entry queue.

[0106] Among them, the address range corresponding to the submission queue / completion queue is determined by the base address of the host memory allocation, the queue depth, and the number of queues when the host creates the submission queue / completion queue.

[0107] In the above embodiments, it has been explained that the address ranges of SQ and CQ are determined by the base address (base addr ), queue depth (queue depth ), and number of queues (queue num) are jointly determined. Therefore, after the SQ and CQ are created in the host memory, the address ranges of the SQ and CQ can be calculated based on the above information. If the address in the intercepted data falls within the corresponding address range, the data can be considered an SQ address or CQ address. Based on this, this embodiment can achieve rapid and accurate extraction of SQ addresses and CQ addresses in intercepted data.

[0108] Furthermore, in order to achieve more complete verification in the above embodiment, SQ is divided into ASQ and IOSQ, and CQ is divided into ACQ and IOCQ for address verification respectively. This embodiment also provides an adaptive solution for extracting SQ addresses and CQ addresses during data interception:

[0109] The address range corresponding to the I / O submission queue / I / O completion queue is also determined based on the submission queue number / completion queue number.

[0110] When the address corresponds to an input / output submission queue address / input / output completion queue, the address is saved in the queue associated with the corresponding submission queue number / completion queue number.

[0111] That is, this embodiment further divides the SQ address range into the ASQ address range and the IOSQ address range based on the differences between ASQs and IOSQs (their different locations within the SQ address range). Furthermore, based on the IOSQ's sq_id, the address ranges of different IOSQs are further distinguished. Based on this, this embodiment can extract and distinguish ASQs and different IOSQs (distinguished by sq_id) during data extraction in step S2. The same principle applies to the extraction and distinction of CQ addresses, facilitating more complete and accurate verification of correctness in subsequent step S3.

[0112] On the other hand, this embodiment also provides a possible implementation plan for the second part (i.e., field verification) mentioned above. That is, the above step S3 further includes:

[0113] S32-1: Extract field information from a submission queue entry corresponding to the host as a first submission field, and extract field information from a submission queue entry corresponding to the disk as a second submission field.

[0114] S32-2: Compare the first submission field and the second submission field to see if they are the same. If so, determine that the NVMe controller reads the host submission queue entry field correctly.

[0115] S32-3: Extract the field information in the completion queue entry corresponding to the host as the first completion field, and extract the field information in the completion queue entry corresponding to the disk as the second completion field.

[0116] S32-4: According to the first completion field and the second completion field, verify whether the update of the completion queue entry field by the NVMe controller is correct. If so, determine that the NVMe controller correctly replies to the host with the completion queue entry field.

[0117] Different from the address verification in the above embodiments, field verification requires the use of CQE and SQE transmitted between the NVMe controller and the disk. The above first submission field, second submission field, first completion field, and second completion field are used to distinguish the SQE and CQE transmitted by the NVMe controller when interacting with the host and the disk respectively.

[0118] As another supplement to the above address verification, this embodiment is used to implement field verification, and verify the correctness of the NVMe controller accessing the host queue from another aspect. The SQE and CQE used for field verification need to be obtained not only from the host side but also from the disk side to obtain the two states of the SQE and CQE before and after passing through the NVMe controller, so as to accurately determine whether the NVMe controller correctly updates the SQE and CQE fields.

[0119] It should be noted that for the verification of the SQE field, it is mainly to compare the SQE (SQE ref ) monitored from the transaction layer packet (TLP packet) with the SQE (SQE act ) actually read and then output by the NVMe controller. For the fields specified by the NVMe protocol, the NVMe controller usually does not perform any processing, but these are also the fields that need to be key verified, because their correctness will directly affect the data interaction between the host and the hard disk, including information such as command identifier (CID), namespace identifier (NSID), physical region page (PRP), etc. If the operation of the reserved field of the SQE by the NVMe controller is not considered, the SQE ref and SQE act can be directly compared in all fields. If the comparison is incorrect, it indicates that there is an incorrect operation of the SQE field by the NVMe controller.

[0120] However, for CQE, CQE is assembled by the hardware on the disk side and then replied to the host through the NVMe controller. In this process, the NVMe controller is usually responsible for updating the phase tag and head pointer fields in the CQE. Therefore, in this method, it is necessary to focus on confirming whether the phase tag field and head pointer field in the first completion field and the second completion field correspond, that is, whether the NVMe controller updates correctly. For other fields in the CQE, the NVMe controller generally does not perform updates, so the entire field can be compared to determine whether there are problems.

[0121] Based on the above, this embodiment adaptively provides a further implementation solution on the basis of the above embodiment:

[0122] Both the first completion field and the second completion field include: a phase flag (Phase Tag) field, a head pointer (Head Pointer) field, and other fields.

[0123] Then the above step S32-4 specifically includes:

[0124] S32-41: Determine whether the phase flag field in the second completion field is correctly flipped relative to the first completion field; if so, determine that the phase flag field is updated correctly.

[0125] S32-42: Verify whether the head pointer field in the second completion field is correctly updated relative to the first completion field through the root complex VIP.

[0126] S32-43: Perform a global segment comparison on the other fields in the first completion field and the second completion field; if they are consistent, determine that the other fields are updated correctly.

[0127] Among them, when the phase flag field, the head pointer field, and the other fields are all updated correctly, it is determined that the NVMe controller updates the completion queue entry field correctly.

[0128] As can be seen from the above, for the field verification of the CQE, this embodiment performs targeted verification on the three field parts that make up the complete CQE field. Among them, the Phase Tag field and the Head Pointer field that the NVMe controller will update are key-verified.

[0129] For the Phase Tag field, mainly verify whether it is correctly flipped. The flipping of the Phase Tag field is as Figure 4 shown. In the definition of the NVMe protocol, the Phase Tag field is initialized to 0. When the NVMe controller replies to the host with a new CQE, the controller should flip the Phase Tag field in the CQE. If it is the first write to the host CQ, the Phase Tag field should be set to 1. When the host-side CQ is full and a new CQE needs to be written again from the top of the CQ, that is, when it reaches the bottom and wraps around, the controller needs to set the Phase Tag field in the CQE to 0.

[0130] For the Head Pointer field, due to its characteristic of real-time dynamic change, it is not easy to re-design the verification logic. Therefore, in this embodiment, the existing Root Complex (RC) Verification Intellectual Property (VIP) is utilized to implement the verification of the Head Pointer field, greatly reducing the complexity of this method and making this method easier to implement.

[0131] On the other hand, in the address verification scheme given in the above embodiment, there is an implementation scheme for further subdividing SQ and CQ. In response to this, this embodiment also provides an adaptive field verification scheme: the First Completion Field and the Second Completion Field further include: a Submission Queue Number Field.

[0132] Then the above step S32-4 specifically further includes:

[0133] S32-44: Determine the corresponding Completion Queue Number according to the Completion Queue Address in the Completion Queue Entry.

[0134] S32-45: Query the Submission Queue Number pre-bound with the Completion Queue Number.

[0135] S32-46: Compare whether the bound Submission Queue Number and the Submission Queue Number Field are consistent. If so, determine that the update of the Submission Queue Number Field is correct.

[0136] Among them, when the Phase Flag Field, the Head Pointer Field, other fields, and the Submission Queue Number Field are all updated correctly, it is determined that the update of the Completion Queue Entry Field by the NVMe controller is correct.

[0137] It should be noted that this method only has this verification scheme for the fields of the IOCQ after CQ is subdivided, and the verified field is the SQ Identifier (SQID) field. This is determined by the fact that in practical applications, the NVMe controller is also responsible for updating the SQID field of the CQE. Therefore, in this embodiment, the SQID field can be verified through the address accessed by this CQE: First, calculate the CQ number to which this CQE belongs according to the CQ addr Then query the binding relationship between CQ and SQ, obtain the corresponding SQ number according to this binding relationship, compare this number with the SQID field in the CQE. If there is an error, it indicates that there is a problem with the update of the SQID field by the NVMe controller. That is to say, this embodiment also provides a more comprehensive verification scheme in terms of field verification for the subdivided SQ and CQ, further improving the accuracy and completeness of verification.

[0138] To better illustrate an access verification method provided in the above embodiments of the present invention, the following further describes the solution provided in the above embodiments with reference to examples:

[0139] First, it is not difficult to know from the above method that the verification of the access correctness of the NVMe controller in this method can be specifically divided into the following two major parts:

[0140] 1. Verify the correctness of the NVMe controller accessing the host SQ / CQ queue wrap-around address;

[0141] 2. Verify the correctness of the NVMe controller reading the host SQE and replying to the host CQE fields.

[0142] Then, the subsequent embodiments will also be described separately in terms of "address verification" and "field verification":

[0143] I. Address verification:

[0144] 1). Obtaining the SQ and CQ addresses;

[0145] From the above-mentioned embodiments of step S2, it can be seen that when the host creates SQ and CQ, their addresses are determined by the base address (base addr ), queue depth (queue depth ), and queue number (queue num ) allocated by the host memory. Then, the address ranges where the SQ and CQ addresses should be located can be calculated accordingly, and the SQ address and CQ address can be extracted from the intercepted data. The specific calculation and judgment process are as follows:

[0146] For SQ, its address range (SQ addr ) can be expressed as follows:

[0147] (1);

[0148] Among them, 0x40 represents the number of bytes (byte) of an SQE, and values other than 0x40 can also be taken in other scenarios.

[0149] Also, from the above embodiments, in order to provide a more complete verification method, the present invention also distinguishes between ASQ and IOSQ, and ACQ and IOCQ, and further subdivides the address ranges accordingly. In this embodiment, ASQ and IOSQ are taken as examples for illustration first. Assuming that the queue depth of ASQ and IOSQ is the same and the address ranges are continuous, the address range of ASQ (ASQ addr ) can be expressed as follows:

[0150] (2);

[0151] The address range of IOSQ (IOSQ addr ) can be expressed as follows:

[0152]

[0153] (3);

[0154] In addition, IOSQ also needs to distinguish different numbers (ie sq_id) SQ addresses, that is, from the obtained IOSQ addr To determine the sq_id that the NVMe controller is going to access, in order to accurately verify each SQ, this requires the IOSQ obtained addr Further calculations are as follows:

[0155] (4);

[0156] The “ / ” in the above formula means to find the quotient. After calculating sq_id, IOSQ addr Just save it to the queue associated with sq_id.

[0157] The determination of the CQ address range is similar to that of the SQ. This embodiment omits the intermediate derivation process and directly provides the following CQ address range:

[0158] For ACQ:

[0159] (5);

[0160] 0x10 indicates the number of bytes in a CQE, and values other than 0x10 may also be used in other scenarios.

[0161] For IOCQ:

[0162]

[0163] (6);

[0164] Calculation of CQ number cq_id:

[0165] (7);

[0166] 2) Check the SQ and CQ addresses;

[0167] When the NVMe controller accesses the host SQ, it accesses the corresponding host memory address according to the value of the current SQ HDBL register. When the host SQ is full, the host will write SQE again from the top of the SQ, that is, the value of the SQ TDBL register will start from 0 again, and the data will start to wrap around from the bottom, as Figure 3 shown.

[0168] When the value of the SQ HDBL register accessed by the NVMe controller also reaches the queue maximum value (queue depth -1), it will also start from 0 again. At this time, the SQ address accessed by the NVMe controller will also start from the addr start of the SQ. Therefore, in order to ensure that the NVMe controller correctly accesses the host SQ address, the collected SQ addr can be logically judged as follows.

[0169] For the ASQ, when its address sequence is less than or equal to queue depth , it can be compared with the theoretical address one by one, expressed as follows:

[0170] (8);

[0171] Among them, ASQ addr [i] represents the theoretical address of the ASQ, and i represents the collected address sequence. When its address sequence gradually increases and exceeds queue depth , its theoretical address is as follows:

[0172] (9);

[0173] For the IOSQ, the check of the address also needs to consider sq_id, so its check logic is different from that of the ASQ, and can be expressed as follows

[0174] (10);

[0175] (11);

[0176] Among them, IOSQ addr [sq_id][i] represents the theoretical address of the IOSQ numbered sq_id. Equation (10) represents the situation when the address sequence is less than queue depth , and expression (11) represents the situation when the address sequence is greater than queue depth .

[0177] Furthermore, the theoretical addresses of the ACQ and IOCQ are the same as those of the ASQ and IOSQ, and can be checked according to the following expressions:

[0178] (12);

[0179] (13);

[0180] (14);

[0181] (15);

[0182] Wherein, ACQ addr [i] represents the theoretical address of ACQ; IOCQ addr [cq_id][i] represents the theoretical address of IOCQ with the number cq_id. Equations (12) and (13) respectively represent the cases when the address sequence of ACQ is less than or equal to queue depth and greater than queue depth . Equations (14) and (15) respectively represent the cases when the address sequence of IOCQ addr is less than or equal to queue depth and greater than queue depth .

[0183] According to the above process, the correctness of the NVMe controller accessing the host SQ and CQ addresses can be verified, Figure 5 which is the process of verifying the correctness of the SQ and CQ addresses as described above.

[0184] II. Field Verification:

[0185] 1) Acquisition of SQE and CQE fields;

[0186] For SQE, since its read request and actual field transmission are respectively in the memory read request packet (MRD packet) and the completion packet with data (CPLD packet), it is necessary to combine the MRD packet and the CPLD packet to obtain SQE. First, through SQ in the MRD packet addr , to determine which sq_id the NVMe controller accesses this time (refer to Equation 4). If it is ASQ, the problem of sq_id does not need to be considered. In addition, the length (a key field in the TLP packet) of this access can also be obtained through the MRD packet. According to the length, the quantity information of the SQE read this time can be known, and according to the length, the real data and the total quantity of the SQE read this time can be obtained from the CPLD packet. Saving them to the queue associated with sq_id in sequence can be used for subsequent comparison work.

[0187] For CQE, its reply request and field transmission are both saved in the memory write request packet (MWR packet), so only by monitoring the MWR packet can the field information of CQE be obtained. In actual operation, first according to CQ in the MWR packetaddr , to determine which cq_id the CQE replied by the NVMe controller this time belongs to (refer to Equation 7). If it is an ACQ, the issue of cq_id does not need to be considered either. After determining which cq_id the CQE replied this time belongs to, according to the length information in the MWR packet, the complete number of CQEs and the field content can be obtained from the payload array in the MWR packet.

[0188] 2) Verification of the correctness of the SQE field;

[0189] For the verification of the SQE field, the above embodiments have illustrated that it is mainly to compare the SQE (SQE ref ) monitored from the transaction layer packet (TLP packet) with the SQE (SQE act ) actually read and then output by the NVMe controller. When not considering the operation of the SQE reserved field segment by the NVMe controller, the SQE ref and the SQE act can be directly compared in all fields. If the comparison is incorrect, it indicates that the NVMe controller has incorrect operations on the SQE fields.

[0190] 3) Verification of the correctness of the CQE field;

[0191] The above embodiments have illustrated that CQEs can generally be divided into: Phase Tag, SQ Head Pointer, and other fields. Among them, due to the real-time dynamic change characteristics of the Head Pointer field, it can be verified by the RC VIP. And the other fields can be verified based on the global segment comparison, so this embodiment will not elaborate. This embodiment focuses on how to verify the Phase Tag:

[0192] For the Phase Tag, the collected CQEs can be taken out from the queue in turn. For the first N (N = queue depth ) CQEs, verify whether the data on the 16th bit of the third double word (dw3) is equal to 1; then for the CQEs between N and 2N, verify whether the 16th bit of its dw3 is equal to 0; and so on for the subsequent ones. For the CQEs between 2N and 3N, it flips back to 1 again. Therefore, for any number of CQEs, the following formula can be used for judgment:

[0193] (16);

[0194] In the formula, cqe numIndicates the serial number of the current CQE. dw3

[16] represents the 16th bit of dw3 in the CQE, i.e., PhaseTag. The symbol " / " refers to the quotient operation, the symbol "%" refers to the remainder operation, and the symbol "~" refers to the bitwise inversion operation. It should be noted that in Equation (16), the reason for subtracting 1 from cqe num is because the host queue starts counting from 0. If Equation (16) holds, it indicates that the NVMe controller's flipping process of the Phase Tag is correct.

[0195] Finally, based on the field verification scheme provided in the above embodiments, there is a Figure 6 field verification process as shown.

[0196] In addition to the embodiments of the access verification method provided in the above embodiments, the present invention also provides an embodiment corresponding to a computer program product. A computer program product includes computer programs / instructions, and when the computer programs / instructions are executed by a processor, the steps of the access verification method described in any of the above embodiments can be implemented.

[0197] Since the embodiments of the computer program product part correspond to the embodiments of the method part, for the embodiments of the computer program product part, please refer to the description of the embodiments of the method part, and will not be elaborated here.

[0198] In the above embodiments, an access verification method is described in detail. The present invention also provides an embodiment corresponding to an access verification device. It should be noted that the present invention describes the embodiments of the device part from two perspectives, one is from the perspective of functional modules, and the other is from the perspective of hardware.

[0199] From the perspective of functional modules, as Figure 7 shown, this embodiment provides an access verification device, including:

[0200] Interception module 11, configured to intercept the data transmitted on the buses connected to the inlet end and the outlet end of the NVMe controller respectively;

[0201] Extraction module 12, configured to extract the submission queue entries and completion queue entries for the communication between the NVMe controller and the host, and the submission queue entries and completion queue entries for the communication between the NVMe controller and the disk from the intercepted data respectively;

[0202] Verification module 13, configured to verify the correctness of the NVMe controller's access to the host submission queue and completion queue wrap-around addresses according to the submission queue entries and completion queue entries, and verify the field correctness of the NVMe controller's reading of the host submission queue entries and replying to the host completion queue entries.

[0203] Since the embodiments in the apparatus part correspond to those in the method part, please refer to the descriptions of the embodiments in the method part for the embodiments in the apparatus part, which will not be elaborated here.

[0204] Figure 8 The structural diagram of an access verification apparatus provided by another embodiment of the present invention is as Figure 8 shown. An access verification apparatus includes: a memory 20 for storing computer programs;

[0205] a processor 21 for implementing the steps of an access verification method as described in the above embodiment when executing the computer program.

[0206] The access verification apparatus provided in this embodiment may include, but is not limited to, a mobile terminal, a personal computer, a workstation, etc.

[0207] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), or a programmable logic array. The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may further include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0208] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201. After the computer program is loaded and executed by the processor 21, it can implement the relevant steps of an access verification method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, an access verification method, etc. [[ID=\\(1\\)]] [[ID=\\(2\\)]]

[0209] [[ID=\\(3\\)]]In some embodiments, an access verification device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26. [[ID=\\(4\\)]] [[ID=\\(5\\)]]

[0210] [[ID=\\(6\\)]]Those skilled in the art can understand that [[ID=\\(7\\)]] Figure 8 [[ID=\\(8\\)]]the structure shown in does not constitute a limitation on an access verification device, and it may include more or fewer components than shown in the figure. [[ID=\\(9\\)]] [[ID=\\(10\\)]]

[0211] [[ID=\\(11\\)]]An access verification device provided by an embodiment of the present invention includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: an access verification method. [[ID=\\(12\\)]] [[ID=\\(13\\)]]

[0212] [[ID=\\(14\\)]]Finally, the present invention also provides an embodiment corresponding to a non-volatile storage medium. A computer program is stored on the non-volatile storage medium, and when the computer program is executed by the processor, it implements the steps recorded in the foregoing method embodiments. [[ID=\\(15\\)]] [[ID=\\(16\\)]]

[0213] [[ID=\\(17\\)]]It can be understood that if the method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and executes all or part of the steps of the methods described in various embodiments of the present invention. And the foregoing storage medium includes: USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs, etc., which can store program codes. [[ID=\\(18\\)]] [[ID=\\(19\\)]]

[0214] The above has introduced in detail an access verification method, device, and medium provided by the present invention. The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For related parts, reference can be made to the description in the method part. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

[0215] It should also be noted that in this specification, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article, or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of another identical element in the process, method, article, or device comprising the said element.

Claims

1. An access verification method, characterized in that, Including: Intercepting the data transmitted on the buses connected to the entry end and the exit end of the NVMe controller respectively; Respectively extracting the submission queue entries and completion queue entries for communication between the NVMe controller and the host, and the submission queue entries and the completion queue entries for communication between the NVMe controller and the disk from the intercepted data; According to the submission queue entries and the completion queue entries, verifying the correctness of the NVMe controller accessing the host submission queue and completion queue wrap-around addresses, and verifying the field correctness of the NVMe controller reading the host submission queue entries and replying to the host completion queue entries.

2. The access verification method according to claim 1, wherein According to the submission queue entries and the completion queue entries, verifying the correctness of the NVMe controller accessing the host submission queue and completion queue wrap-around addresses includes: Extracting the submission queue address corresponding to the submission queue entry in the host and the completion queue address corresponding to the completion queue entry in the host; Checking whether the submission queue address is consistent with the corresponding theoretical address. If so, determining that the NVMe controller accessing the host submission queue wrap-around address is correct; Checking whether the completion queue address is consistent with the corresponding theoretical address. If so, determining that the NVMe controller accessing the host completion queue wrap-around address is correct; Wherein, the theoretical address is determined by the base address of the host memory allocation and the queue depth when the host creates the submission queue / the completion queue.

3. The access verification method according to claim 2, characterized in that, The submission queue includes: an administrative submission queue and an input / output submission queue; The submission queue address includes: an administrative submission queue address and an input / output submission queue address; The completion queue includes: an administrative completion queue and an input / output completion queue; The completion queue address includes: an administrative completion queue address and an input / output completion queue address; The extracting the submission queue address corresponding to the submission queue entry in the host and the completion queue address corresponding to the completion queue entry in the host further includes: Extracting the submission queue number of the input / output submission queue address and extracting the completion queue number of the input / output completion queue; The theoretical address corresponding to the input / output submission queue address / the input / output completion queue is also determined according to the submission queue number / the completion queue number.

4. The access verification method according to claim 3, wherein Respectively extracting the submission queue entries and completion queue entries for communication between the NVMe controller and the host, and the submission queue entries and the completion queue entries for communication between the NVMe controller and the disk from the intercepted data includes: Extracting all addresses from the intercepted data; Respectively determining whether each address is within the address range corresponding to the submission queue / the completion queue; If so, taking the address as the submission queue address / the completion queue address and saving it to the queue associated with the submission queue entry / the completion queue entry queue; Wherein, the address range corresponding to the submission queue / the completion queue is determined by the base address of the host memory allocation, the queue depth and the number of queues when the host creates the submission queue / the completion queue.

5. The access verification method according to claim 4, wherein The address range corresponding to the input / output submission queue / the input / output completion queue is also determined according to the submission queue number / the completion queue number; When the address corresponds to the input / output submission queue address / the input / output completion queue, the address is saved to the queue associated with the corresponding submission queue number / completion queue number.

6. The access verification method according to any one of claims 3 to 5, characterized in that According to the submission queue entry and the completion queue entry, verifying the field correctness of the NVMe controller reading the submission queue entry from the host and replying the completion queue entry to the host includes: Extracting the field information in the submission queue entry corresponding to the host as the first submission field, and extracting the field information in the submission queue entry corresponding to the disk as the second submission field; Comparing whether the first submission field and the second submission field are the same. If so, it is determined that the NVMe controller reads the submission queue entry field from the host correctly; Extracting the field information in the completion queue entry corresponding to the host as the first completion field, and extracting the field information in the completion queue entry corresponding to the disk as the second completion field; According to the first completion field and the second completion field, verifying whether the update of the completion queue entry field by the NVMe controller is correct. If so, it is determined that the NVMe controller replies the completion queue entry field to the host correctly.

7. The access verification method according to claim 6, wherein Both the first completion field and the second completion field include: a phase flag bit field, a head pointer field, and other fields; According to the first completion field and the second completion field, verifying whether the update of the completion queue entry field by the NVMe controller is correct includes: Judging whether the phase flag bit field in the second completion field is correctly flipped relative to the first completion field; if so, it is determined that the phase flag bit field is updated correctly; Verifying whether the head pointer field in the second completion field is correctly updated relative to the first completion field through the root complex VIP; Performing a global segment comparison on the other fields in the first completion field and the second completion field; if they are consistent, it is determined that the other fields are updated correctly; Among them, when the phase flag bit field, the head pointer field, and the other fields are all updated correctly, it is determined that the update of the completion queue entry field by the NVMe controller is correct.

8. The access verification method according to claim 7, wherein Both the first completion field and the second completion field further include: a submission queue number field; According to the first completion field and the second completion field, verifying whether the update of the completion queue entry field by the NVMe controller is correct further includes: Determining the corresponding completion queue number according to the completion queue address in the completion queue entry; Querying the submission queue number pre-bound with the completion queue number; Comparing whether the bound submission queue number and the submission queue number field are consistent. If so, it is determined that the submission queue number field is updated correctly; Wherein, when the stage flag bit field, the head pointer field, the other fields, and the submission queue number field are all updated correctly, it is determined that the NVMe controller updates the completion queue entry field correctly.

9. An access verification device, characterized in that, Comprising: An interception module, configured to respectively intercept data transmitted on the buses connected to the inlet end and the outlet end of the NVMe controller; An extraction module, configured to respectively extract the submission queue entries and completion queue entries transmitted between the NVMe controller and the host, and the submission queue entries and the completion queue entries transmitted between the NVMe controller and the disk from the intercepted data; A verification module, configured to verify the correctness of the NVMe controller accessing the host submission queue and the completion queue wrap-around addresses according to the submission queue entries and the completion queue entries, and verify the field correctness of the NVMe controller reading the host submission queue entries and replying to the host completion queue entries.

10. An access verification device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to implement the steps of the access verification method according to any one of claims 1 to 8 when executing the computer program.

11. A non-volatile storage medium, characterized in that, A computer program is stored on the non-volatile storage medium, and when the computer program is executed by a processor, the steps of the access verification method according to any one of claims 1 to 8 are implemented.

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