Hybrid simulation method for same interface, electronic equipment and storage medium

Abstract

The invention relates to the technical field of chip design, in particular to a hybrid simulation method for the same interface, electronic equipment and a storage medium, a verification platform allocates independent and non-overlapping address fields for each DMA module; the verification platform judges whether the current destination address is in the address field or not, if yes, the operation OPi to which the current data corresponding to the current destination address belongs is determined as DMA operation, and a non-joint simulation mode is entered; wherein the non-joint simulation mode is used for comparing whether the final copy result of the OPi in the second verification model is the same as the final copy result of the OPi in the first verification model or not; if not, entering a joint simulation mode; wherein the joint simulation mode is used for comparing whether the current data corresponding to the current destination address in the second verification model is the same as the current data in the first verification model or not. The problem that the code amount is increased due to synchronization is avoided, the calculation amount of comparison is greatly reduced, and the development period is shortened.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a hybrid simulation method, an electronic device, and a storage medium for the same interface. Background Art

[0002] With the continuous development of integrated circuit technology, the complexity of control modules has increased day by day, and the coordinated work between internal modules thereof has put forward higher requirements for interface synchronization. When verifying a control module, it is often necessary to use co-simulation (cosim) technology to verify the synchronization logic of the same interface. For the direct memory access (DMA) module inside the control module, since it uses the same interface as other parts for data input and output, this puts strict synchronization requirements on the reference model (Cmodel) and RTL model for verification.

[0003] Specifically, the Cmodel and RTL models need to synchronize each operation precisely to accurately simulate the actual operation situation and detect potential problems. The Cmodel is a model running at the software level, mainly focusing on the implementation of system functions. Its operation is based on resources such as the processor of a computer, and there are no limitations of physical factors such as wiring delay and gate delay in the hardware circuit. The RTL describes the specific implementation of the hardware circuit, and delays will occur when signals are transmitted in the hardware circuit and logical gates perform operations. These delays will reduce the data processing speed. Therefore, the data processing speed of the Cmodel is greater than that of the RTL. When the RTL completes the copying of a piece of data, it is timely compared with the data of the Cmodel. If the two are consistent, it means that the copying operation of the current piece of data is correct; otherwise, an error is reported. In fact, there are multiple DMA modules in the control module, and the DMA module and other modules in the control module will share the same interface. At this time, there will be a situation where multiple modules compete for the same interface, that is, the data in the same interface includes DMA data and data of other modules, and the data of different modules are intertwined. For this situation, the current verification requires that each operation of the same interface in the Cmodel and RTL be completely synchronized, which will result in a very large amount of Cmodel code; at the same time, in this case, the verification logic of the DMA uses the verification logic of other modules, and it is necessary to identify whether the current data is DMA data when verifying the DMA, resulting in a very slow verification process and thus a long development cycle. Therefore, there is an urgent need for a method that can shorten the development cycle without increasing the amount of Cmodel code. Summary of the Invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is: a hybrid simulation method for the same interface, the method comprising the following steps: S100, The verification platform assigns independent and non-overlapping address segments to each DMA module.

[0005] S200, Obtain a first verification model and a second verification model, where the first verification model is a functional model of the chip to be verified, and the second verification model is a hardware model of the same chip to be verified.

[0006] S300, When the verification platform sends a DMA operation request req to the first verification model and the second verification model respectively, the req carries an incentive stim, a source address Saddr, a destination address Daddr, and a copied data length size; wherein, the DMA operation request is used to copy the data at the Saddr to the Daddr under the action of the stim.

[0007] S400, The verification platform determines whether the current destination address Daddr of the second verification model at the i-th interface interf i is within the address segment. If it is within the allocated address segment, determine the operation OP i corresponding to the current pen of data as a DMA operation, and enter the non-union simulation mode; wherein, the non-union simulation mode is used to compare whether the final copy result of the OP i in the second verification model is the same as the final copy result of the OP i in the first verification model; if it is not within the allocated address segment, enter the union simulation mode; wherein, the union simulation mode is used to compare whether the current pen of data corresponding to the Daddr i in the second verification model is the same as the current pen of data in the first verification model. i i

[0008]

[0009] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one segment of program is stored, and the at least one instruction or the at least one segment of program is loaded and executed by a processor to implement the above method.

[0010] In addition, the present invention also provides an electronic device, including a processor and the above non-transitory computer-readable storage medium.

[0010] The present invention has at least the following beneficial effects: The present invention provides a hybrid simulation method, an electronic device, and a storage medium for the same interface. The method allocates independent and non-overlapping address segments for each DMA module through a verification platform. If the current address is within the allocated address segment, it is determined as a DMA operation, and the result of the DMA operation is compared when the current DMA operation is completed; otherwise, the result is compared when each piece of data is completed. This avoids the problem of expanding the code amount due to synchronization, and greatly reduces the calculation amount of comparison by comparing the DMA operation results, speeds up the verification process, and shortens the development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0012] Figure 1 It is a flowchart of a hybrid simulation method for the same interface provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0014] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meaning as commonly understood by those of ordinary skill in the art.

[0015] Please refer to Figure 1 , which shows a hybrid simulation method for the same interface. The method includes the following steps: S100, the verification platform allocates independent and non-overlapping address segments for each DMA module.

[0016] Among them, the verification platform is a platform for performing Design Verification of the chip. According to the chip design specifications, a large number of test cases are written and then run on the verification platform to verify whether various functions of the chip are correctly implemented. The verification platform can generate various excitation signals, input them into the verification model of the chip design to be verified, and at the same time monitor the output response to determine whether it meets the expectations.

[0017] Among them, the DMA (Direct Memory Access) module is used to enable external devices to directly transfer data with the memory without passing through the CPU. The essence of DMA operation is to transfer data from one storage location (source address) to another storage location (destination address).

[0018] In one implementation, when there are M DMA modules in the chip to be tested, in S100, when allocating address segments for the M DMA modules {DMA1, DMA2, …, DMA j , …, DMA M}, where DMA j is the j-th DMA module, and the value range of j is from 1 to M, it further includes: S110, obtain the size of the address segment to be allocated for each DMA module, denoted as {offset1, offset2, …, offset j , …, offset M}, and offset j is the size of the address segment of DMA j ; S120, maintain a free address space list, and the free address space list records information of all available continuous free address segments in the system, and each free address segment is represented by a start address and a length; S130, traverse the free address space list to find whether there is a continuous free address segment whose length is sufficient to accommodate the total address segment size required by the M DMA modules, where the size of the total address segment offset_total = offset1 + offset2 + … offset j … + offset M ; S131, if a continuous free address segment with a length not less than offset_total is found in the free address space list, assume the start address of the continuous free address segment is start_addr, and allocate address segments for the M DMA modules in sequence. Among them, for DMA j allocate an address segment starting from start_addr + ∑ i=1 j-1 offset i with a length of offset j ; after the allocation is completed, update the free address space list, remove the allocated address segment from the free address space list, and if there is a remaining part of the free address segment after the allocation, update its start address and length information.

[0019] S132. If a continuous free address segment with sufficient length is not found, a greedy algorithm is used to allocate space for the address segments of multiple DMA modules to reduce fragmentation. The specific steps are as follows: S1321. Sort the M DMA modules in descending order according to the size of the address segments to be allocated to obtain a new ordered DMA S1 ,DMA S2 , …,DMA SM , where offset S1 ≥offset S2 ≥…≥offset SM ; Select the free address segment with the smallest starting address from the free address space list, and set its starting address as cur_start_addr and length as cur_len; S1322. Try to allocate address segments for the sorted DMA modules in sequence: For the first DMA module DMA S1 , if cur_len≥offset S1 , then allocate the address segment with a length of offset S1 starting from cur_start_addr to DMA S1 , and update cur_start_addr = cur_start_addr + offset S1 , cur_len = cur_len - offset S1 . For the k-th DMA module in the new order DMA Sk , if cur_len≥offset Sk , then continue to allocate the address segment with a length of offset Sk starting from cur_start_addr to DMA Sk , and update cur_start_addr and cur_len in the same way; otherwise, stop the allocation attempt in the current free address segment, select the next free address segment with the smallest starting address from the free address space list, and repeat the above allocation process. After each address segment allocation, update the free address space list, remove the allocated free address segment, or update the starting address and length information of the remaining free address segment.

[0020] S1323. Repeat step S1322 until all DMA modules have been attempted for allocation.

[0021] The address segment allocation method provided in steps S110 - 130 can reasonably allocate address segments to M DMA modules under different address space conditions, so as to allocate multiple DMA address segments to continuous spaces to reduce fragmentation. It should be noted that other ways of allocating address segments also fall within the protection scope of the present invention.

[0022] S200, obtain a first verification model and a second verification model, where the first verification model is a functional model of the chip to be verified, and the second verification model is a hardware model of the same chip to be verified.

[0023] Among them, the first verification model and the second verification model are different verification models of the same chip to be verified, so they have the same interface and the same input stimuli.

[0024] In one implementation, the first verification model is a Cmodel model, a SystemC model, a Python model, or a gate - level netlist verification model, etc. Other types of verification models also fall within the protection scope of the present invention.

[0025] In one implementation, the second verification model is an RTL (Register Transfer Level model) or a VHDL (Very - High - Speed Integrated Circuit Hardware Description Language model). Other types of register transfer level verification modules all fall within the protection scope of the present invention.

[0026] S300, when the verification platform sends a DMA operation request req to the first verification model and the second verification model respectively, the req carries stimuli stim, source address Saddr, destination address Daddr, and the length size of the data to be copied; where the DMA operation request is used to copy the data at the Saddr to the Daddr under the action of the stim.

[0027] Among them, the stimuli are a set of signal combinations used to control the DMA operation behavior, including clock signals, enable signals, control signals, etc., which are used to simulate different working scenarios and conditions and drive the DMA module to operate as expected.

[0028] Among them, the source address is the address from which the DMA operation reads data, which is an address in memory or a peripheral device.

[0029] Among them, the destination address is the address to which the DMA operation writes data, which is also an address in memory or a peripheral device.

[0030] Among them, the data length is the amount of data to be copied in the DMA operation.

[0031] In one embodiment, the DMA operation request req is used to request to copy data from one area of the memory to another area, or to request to transfer data in the peripheral to the memory, or to request to transfer data in the memory to the peripheral. Other types of DMA operation requests also fall within the protection scope of the present invention.

[0032] S400, the verification platform determines whether the current destination address Daddr i of the second verification model at the i-th interface interf i is within the address segment. If it is within the allocated address segment, determine the operation OP i to which the current pen data corresponding to Daddr i belongs as a DMA operation, and enter the non-union simulation mode; wherein, the non-union simulation mode is used to compare the final copy result of the OP i in the second verification model with the final copy result of the OP i in the first verification model to see if they are the same; if it is not within the allocated address segment, enter the union simulation mode; wherein, the union simulation mode is used to compare the current pen data corresponding to Daddr i in the second verification model with the current pen data in the first verification model to see if they are the same.

[0033] In one embodiment, when the address segments allocated to all DMA modules are allocated to a continuous free address segment, S400 further includes the step of determining whether Daddr i is within the address segment: comparing Daddr i with the dedicated address segment. When Daddr i falls within the dedicated address segment, determine that Daddr i is within the address segment.

[0034] In one embodiment, when all DMA modules are not allocated to a continuous free address segment, S400 further includes the step of determining whether Daddr i is within the address segment: comparing Daddr i with the multiple address segments allocated to all DMA modules respectively. When Daddr i falls within one of the address segments, determine that Daddr i is within the address segment.

[0035] Among them, each DMA operation includes multiple pieces of data. Assume that when a DMA operation includes U pieces of data, the DMA operation is completed when all these U pieces of data are completed.

[0036] It should be noted that for DMA operations, the final copy results of each DMA operation are compared in the non-union simulation mode; for non-DMA operations, whether each piece of data is the same is compared in the union simulation mode. Therefore, by using the non-union simulation mode to verify the correctness of DMA operations, not only can the problem of expanding the code volume due to the synchronization of DMA operations between the first verification model and the second model be avoided without affecting other verification processes of the system, but also the need to frequently compare the correctness of the intermediate copy process is eliminated, significantly reducing the comparison calculation amount.

[0037] In summary, the present invention provides a hybrid simulation method with the same interface, which allocates independent and non-overlapping address segments for each DMA module through a verification platform. If the current address is within the allocated address segment, it is determined as a DMA operation, and the result of the DMA operation is compared when the current DMA operation is completed; otherwise, the result is compared when each piece of data is completed; the problem of expanding the code volume due to synchronization is avoided, and the comparison calculation amount is significantly reduced by comparing the DMA operation results, accelerating the verification process and shortening the development cycle.

[0038] An embodiment of the present invention further provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one segment of a program related to a method for implementing a method in the method embodiment. The at least one instruction or the at least one segment of the program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0039] An embodiment of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0040] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product runs on an electronic device, the program code is used to cause the electronic device to execute the steps in the method according to various exemplary embodiments of the present invention described above in this specification.

[0041] Those skilled in the art can clearly understand that for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0042] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration purposes and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention disclosed is defined by the appended claims.

Claims

1. A hybrid simulation method for the same interface, characterized in that The method includes the following steps: S100, the verification platform assigns independent and non-overlapping address segments to each DMA module; S200, obtain a first verification model and a second verification model, wherein the first verification model is a functional model of the chip to be verified, and the second verification model is a hardware model of the same chip to be verified; S300, when the verification platform sends DMA operation requests req to the first verification model and the second verification model respectively, the req carries an incentive stim, a source address Saddr, a destination address Daddr, and a length size of the data to be copied; wherein, the DMA operation request is used to copy the data at the Saddr to the Daddr under the action of the stim; S400, the verification platform determines that the second verification model is in the i-th interface interface i The current destination address Daddr i Is it within the address segment? If it is within the allocated address segment, determine the Daddr i The operation OP to which the current data belongs i For DMA operation, enter the non-joint simulation mode; wherein, the non-joint simulation mode is used to compare the OP in the second verification model i The final replication results and the first validation model described in OP i The final copy result is the same; if it is not in the allocated address segment, enter the joint simulation mode; wherein the joint simulation mode is used to compare the Daddr in the second verification model i Whether the corresponding current record data is the same as the current record data in the first verification model.

2. The method according to claim 1, wherein When all the address segments allocated by the DMA modules are allocated within a continuous free address segment, S400 further includes a step of determining whether Daddr i is within the address segment: comparing Daddr i with a dedicated address segment, and when Daddr i falls within the dedicated address segment, determining that Daddr i is within the address segment.

3. The method according to claim 1, characterized in that, When all DMA modules are not assigned to a continuous free address segment, S400 further includes a step of determining whether Daddr i is within the address segment: comparing Daddr i with each of the multiple address segments assigned to all DMA modules respectively. When Daddr i falls into one of the address segments, it is determined that Daddr i is within the address segment.

4. The method according to claim 1, wherein When there are M DMA modules in the chip to be tested, in S100, when allocating address segments for the M DMA modules {DMA1, DMA2, …, DMA j , …, DMA M}, where DMA j is the j-th DMA module, and the value range of j is from 1 to M, further including: S110. Obtain the size of the address segment to be allocated for each DMA module, denoted as {offset1, offset2, …, offset j , …, offset M}, where offset j is the size of the address segment of the DMA j module; S120, maintain a free address space list, which records information of all available continuous free address segments in the system, and each free address segment is represented by a start address and a length; S130, traverse the free address space list to find if there is a continuous free address segment whose length is sufficient to accommodate the total address segment size required by the M DMA modules, where the size of the total address segment offset_total = offset1 + offset2 + … offset j … + offset M ; S131, if a continuous free address segment with a length not less than offset_total is found in the free address space list, set the start address of the continuous free address segment as start_addr, and allocate address segments to the M DMA modules in sequence. Among them, for DMA j allocation starts from start_addr + ∑ i=1 j-1 offset i and the length of the address segment is offset j . After the allocation is completed, update the free address space list, remove the allocated address segment from the free address space list. If there is a remaining part of the free address segment after the allocation, update its start address and length information.

5. The method according to claim 4, wherein S130 further includes: S132, if a continuous free address segment with sufficient length is not found, a greedy algorithm is used to allocate space for the address segments of multiple DMA modules.

6. The method according to claim 5, characterized in that, S132 further includes: S1321, sort the M DMA modules in descending order according to the size of the address segments to be allocated, obtaining a new sequential DMA S1 , DMA S2 , …, DMA SM , where offset S1 ≥ offset S2 ≥ … ≥ offset SM ; select the free address segment with the smallest starting address from the list of free address spaces, set its starting address as cur_start_addr, and its length as cur_len; S1322. Try to allocate address segments to the sorted DMA modules in sequence: For the first DMA module DMA S1 , if cur_len ≥ offset S1 , then allocate the address segment starting from cur_start_addr with a length of offset S1 to DMA S1 , update cur_start_addr = cur_start_addr + offset S1 , cur_len = cur_len - offset S1 ; For the k-th DMA module in the new order DMA Sk , if cur_len ≥ offset Sk , then continue to allocate the address segment starting from cur_start_addr with a length of offset Sk to DMA Sk , and also update cur_start_addr and cur_len; Otherwise, stop the allocation attempt for the current free address segment, select the next free address segment with the smallest starting address from the free address space list, and repeat the above allocation process; After each address segment allocation, update the free address space list, remove the allocated free address segments, or update the starting address and length information of the remaining free address segments; S1323, repeat step S1322 until all DMA modules have tried to allocate.

7. The method according to claim 1, characterized in that, The first verification model is a Cmodel model, and the second verification model is an RTL model.

8. The method according to claim 1, wherein The req is used to request to copy data from one area of the memory to another area, or to request to transfer data in a peripheral to the memory, or to request to transfer data in the memory to a peripheral.

9. A non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by a processor to implement the method according to any one of claims 1-8.

10. An electronic device, characterized in that, It includes a processor and the non-transitory computer-readable storage medium described in claim 9.

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