Connection point arrangement method for core particle interface and core particle system

Abstract

The invention provides a connection point arrangement method for core particle interfaces and a core particle system.The method comprises the steps that a core particle boundary and the total number M of groups to be arranged are obtained, the core particle boundary represents an area where connection points on core particles can be arranged, and the total number of groups is the sum of the number of groups of all parallel interfaces of the core particles; dividing a plurality of non-overlapping grouping exclusive areas N in the boundary of the core particles according to the total number M of groups, N being greater than or equal to M; a corresponding packet exclusive area is matched for each packet, connection points of the corresponding packet are arranged in each packet exclusive area, and the connection points of each packet comprise data connection points and redundant connection points; according to the method, the connection points of the same group are arranged in a more concentrated manner, so that concentrated faults appear in the same group with a higher probability, and the fault-tolerant capability of the parallel interface is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit (IC) design, specifically to the field of connection point layout of integrated circuits, and more specifically, to a method for arranging connection points for a chiplet interface and a chiplet system. Background Art

[0002] With the progress of packaging technology, the size and pitch of the connection points (bumps) of chiplets are continuously decreasing, and the connection point resources of chiplets are becoming more abundant. Therefore, data transmission between chiplets tends to use a parallel interface that consumes a large amount of connection point resources. Since there may be a connection (channel) failure between two connection points during the manufacturing and packaging processes of chiplets, if no fault tolerance measures are taken, as long as one channel fails, the entire parallel interface will fail. Therefore, the mainstream approach is to group the parallel interface and add redundant channels within the group. When only a small number of channels in the group are damaged, the redundant channels can be used for repair; the groups do not interfere with each other, that is, if a large number of channels in a certain group are damaged and cannot be repaired, the transmission of other groups will not be affected. This method can effectively improve the fault tolerance of the parallel interface.

[0003] However, the current arrangement of the connection points of the parallel interface still adopts a serpentine arrangement, as Figure 1 shown. Suppose Figure 1 there are multiple groups. It can be seen that the connection points of all groups are arranged in a serpentine path (refer to the blue arrow) within the chiplet boundary in sequence. When arranging, if the connection points of one group are arranged, the connection points of the next group will be arranged immediately. Since channel failures are often concentrated, that is, when one channel is damaged, the probability of the channels around it being damaged is higher. It is possible to have Figure 1 the situation where 7 connection points (assuming C5, C11, C12 in group 3, D5, D11, D12 in group 4, and E5 in group 5) within the red hexagon range shown are damaged simultaneously. At this time, assuming that each group has only 1 redundant channel, then two groups will not be able to be used (because groups 3 and 4 cannot be used due to the number of damaged channels exceeding the number of redundant channels (each group has 1 redundant channel)). It can be seen that if the connection points of each group are arranged in a serpentine sequence within the chiplet boundary, when a problem occurs at a certain position of the chiplet, it is easy to cause multiple groups near this position to be damaged simultaneously, and the fault tolerance for concentrated channel damage is poor.

[0004] It should be noted that: This background technology is only used to introduce relevant information of the present invention to facilitate understanding of the technical solution of the present invention, but it does not necessarily mean that the relevant information is prior art. The relevant information is submitted and disclosed together with the solution of the present invention. Without evidence showing that the relevant information has been publicly available before the filing date of the present invention, the relevant information should not be regarded as prior art. Summary of the Invention

[0005] Therefore, the object of the present invention is to overcome the defects of the above-mentioned prior art and provide a connection point arrangement method for chiplets interfaces and a chiplet system.

[0006] The object of the present invention is achieved by the following technical solutions:

[0007] According to a first aspect of the present invention, there is provided a connection point arrangement method for chiplets interfaces, including: obtaining the chiplet boundary and the total number of groups M to be laid out, where the chiplet boundary represents the layout area of connection points on the chiplet, and the total number of groups is the sum of the number of groups of all parallel interfaces of the chiplet; within the chiplet boundary, dividing out a plurality of non-overlapping group exclusive areas N, where N is greater than or equal to M; matching each group with a corresponding group exclusive area, and arranging the connection points of the corresponding group within each group exclusive area, and the connection points of each group include data connection points and redundant connection points.

[0008] Optionally, when dividing out N non-overlapping group exclusive areas, ensure that there are more than 2 group exclusive areas in the length direction of the chiplet boundary and more than 2 group exclusive areas in the width direction of the chiplet boundary.

[0009] Optionally, the shapes of all group exclusive areas of the same chiplet are the same, and the shape of the group exclusive area is a regular hexagon, a parallelogram, a rectangle or a circle.

[0010] Optionally, data connection points and redundant connection points are set within the group exclusive area of each group. The data connection points serve as the connection points of relevant channels within the parallel interface, and the redundant connection points serve as backups of the data connection points. One or more redundant connection points are set within each group exclusive area.

[0011] Optionally, the data connection points of each group are arranged around the group exclusive area, and the redundant connection points are arranged in the middle of the group exclusive area.

[0012] Optionally, two or more redundant connection points are set within the group exclusive area of each group.

[0013] Optionally, the method further includes: setting a functional gap in at least part of the area between the grouped exclusive areas, the width of the functional gap exceeding the size of a connection point, and power supply connection points and / or ground connection points are arranged in the functional gap. The technical solution of this embodiment can at least achieve the following beneficial technical effects: Since there are functional gaps between each grouped exclusive area, and power supply connection points or ground connection points are arranged in each functional gap, multiple redundant power supply connection points and ground connection points can be arranged on the entire die, greatly reducing the possibility of complete failure of the power supply or ground function.

[0014] According to a second aspect of the present invention, there is provided a die system, which includes a plurality of dies, and the connection points of the dies in the die system are arranged according to the method of the first aspect. Among them, the die system is configured to use a dynamic switching mechanism to ensure the data transmission process without stopping the machine. The dynamic switching mechanism includes: when transmitting data through the parallel interfaces of each pair of dies, monitoring whether the data transmitted by each group in the parallel interfaces is abnormal. If so, starting a verification mechanism for the abnormal group, detecting the faulty data connection points and their corresponding channels in the abnormal group, and switching the faulty connection points and their corresponding channels to redundant connection points and their corresponding channels.

[0015] Optionally, the verification mechanism includes: suspending the data transmission task of the abnormal group, and at the same time using other groups of the parallel interface to which the abnormal group belongs for reduced-speed data transmission; sending pre-set verification data on each channel of the abnormal group, and the verification data is known to both the sender and the receiver; on each channel, respectively comparing whether the received verification data is consistent with the pre-set verification data, and if not, the channel is a faulty channel, and its corresponding data connection point is used as the faulty connection point.

[0016] Optionally, the dynamic switching mechanism includes: after detecting the faulty connection points, judging whether the number of faulty connection points in the abnormal group is less than or equal to the redundant connection points of the abnormal group. If so, matching redundant connection points for the faulty connection points one by one; switching the faulty connection points and their corresponding channels to the redundant connection points and their corresponding channels matched for them. Description of the Drawings

[0017] The following further describes the embodiments of the present invention with reference to the drawings, where:

[0018] Figure 1 It is a schematic diagram of the connection points arranged in a serpentine shape in the existing die;

[0019] Figure 2 It is a schematic flowchart of the method for arranging connection points for the die interface according to the embodiment of the present invention;

[0020] Figure 3Simplified schematic diagram of arranging connection points according to the connection point arrangement method of an embodiment of the present invention. Detailed implementation manners

[0021] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below through specific embodiments with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] As mentioned in the background art section, if the connection points of each group are arranged in a serpentine pattern in turn within the Chiplet boundary, when a problem occurs at a certain position of the Chiplet, it is easy to cause multiple groups near that position to be damaged simultaneously, and the fault tolerance ability for concentrated channel damage is relatively poor. In response to this, the present invention sets the layout area of each group as an exclusive area for the group, and arranges the connection points of the corresponding group within the exclusive area for the group. Thus, the connection points of the same group can be arranged more concentratedly, so that concentrated faults will occur within the same group with a higher probability, thereby improving the fault tolerance ability of the parallel interface.

[0023] It can minimize the distance between adjacent connection points to a greater extent while maintaining sufficient physical isolation to avoid fault spread.

[0024] Before specifically introducing the embodiments of the present invention, some terms used therein are explained as follows:

[0025] A parallel interface is an interconnection interface used to achieve high-speed data transmission between Chiplets. Each Chiplet will be connected to different other Chiplets, and one or more parallel interfaces are set as needed. Each parallel interface is provided with multiple groups, and each group has multiple connection points.

[0026] A connection point refers to an electrical connection point between a Chiplet and an Interposer or a packaging substrate. The connection point can be in the form of a bump or a non-protruding bonding point (such as a copper-copper bonded connection point). A bump is a small protruding structure (a micro metal structure) with a pitch that can reach 30-60 microns or even smaller, so it is also called a micro-bump. Micro-bumps are widely used in 2.5D and 3D packaging technologies to achieve the connection between Chiplets and Interposers or substrates.

[0027] A channel is a path for transmitting signals between two connection points connecting different Chiplets. Usually, channel faults may occur due to reasons such as oxidation or fracture of the connection points (such as caused by temperature changes, mechanical stress, etc.).

[0028] According to an embodiment of the present invention, a method for arranging connection points for a Chiplet interface is provided. Refer to Figure 2, including steps S1, S2, and S3. To better understand the present invention, the following will specifically describe each step in detail with reference to specific embodiments.

[0029] Step S1: Obtain the die boundary and the total number of groups M to be placed, where the die boundary represents the placeable area of the connection points on the die, and the total number of groups is the sum of the number of groups of all parallel interfaces of the die.

[0030] According to an embodiment of the present invention, the die boundary can be a rectangular or square area, and when obtaining the die boundary, its length and width dimensions can be obtained. Assume that the total number of parallel interfaces of a die is Z, and the number of groups of parallel interfaces is , then the total number of groups , where Z is an integer greater than or equal to 1, is an integer greater than or equal to 2.

[0031] Step S2: Divide a plurality of non-overlapping group exclusive areas N within the die boundary, where N is greater than or equal to M.

[0032] According to an embodiment of the present invention, the number of N is equal to M, and a group exclusive area is divided for each group.

[0033] According to an embodiment of the present invention, in some cases, if the number of connection points of each group varies greatly, such as the difference exceeds a preset quantity threshold, a reference quantity B can also be set. Divide the number of connection points of each group by the reference quantity and round up to obtain the number of group exclusive areas of the group; the sum of the number of group exclusive areas of all groups is N. Thus, one or more group exclusive areas can be divided for each group. On the one hand, the size of each group exclusive area can be balanced, and on the other hand, the physical isolation effect can be further improved, reducing the possibility of multiple groups failing simultaneously.

[0034] According to an embodiment of the present invention, when dividing N non-overlapping group exclusive areas, ensure that there are more than 2 group exclusive areas in the length direction of the die boundary and more than 2 group exclusive areas in the width direction of the die boundary. See Figure 3 , and the black hexagons are the group exclusive areas (for simplicity, only 4 group exclusive areas are drawn as a schematic).

[0035] According to an embodiment of the present invention, the shapes of all group exclusive areas of the same die are the same, and the shape of the group exclusive area is a regular hexagon, a parallelogram hexagon, a rectangle, or a circle. Preferably, a square, a regular hexagon, or a parallelogram hexagon is more conducive to uniform arrangement within the die boundary.

[0036] Step S3: Match a corresponding group exclusive area for each group, and arrange a connection point of the corresponding group in each group exclusive area. The connection point of each group includes a data connection point and a redundant connection point.

[0037] According to one embodiment of the present invention, at least one group-exclusive region is matched to each group, and each group-exclusive region can only match one group. For example, suppose a chip has two parallel interfaces. Each group of the first parallel interface has 16 connection points, while each group of the second parallel interface has 32 connection points. A unified group-exclusive region capable of accommodating all 16 connection points can be created. Each group of the first parallel interface matches one group-exclusive region, while each group of the second parallel interface matches two group-exclusive regions. Each group's connection points can include only data connection points and redundant connection points. Connection points for other functions can be placed within functional gaps. Data connection points serve as connection points for related channels within the parallel interface, while redundant connection points serve as backups for data connection points. One or more redundant connection points are provided within each group-exclusive region. The present invention allows for the introduction of a certain number of redundant connection points within each group-exclusive region. The number of redundant connection points can be flexibly configured based on the system's fault tolerance requirements. It is generally recommended to introduce one to two redundant connection points within each group-exclusive region.

[0038] According to one embodiment of the present invention, the connection points of each group may include a data connection point, a redundant connection point, a power supply connection point, and a ground connection point.

[0039] According to one embodiment of the present invention, if each group has only one group exclusive area, each group is matched one-to-one with the group exclusive area. Then, data connection points and redundant connection points are evenly distributed in each group exclusive area. The positions of data connection points and redundant connection points can be set randomly. Alternatively, in order to maximize the distance between the redundant connection points of different groups, the data connection points of each group are arranged around the group exclusive area, and the redundant connection points are arranged in the middle of the group exclusive area, thereby reducing the impact of regional concentrated failures on the redundant connection points of multiple groups at the same time, and ensuring the fault tolerance of the parallel interface. For example, see Figure 3, taking the shape of the grouped exclusive area as a hexagon as an example, assuming that each group of the parallel interface contains 16 data channels, concentrating the connection points corresponding to the 16 data channels within one grouped exclusive area, and additionally setting one redundant connection point, one power supply connection point (or power connection point) and one ground connection point (or ground connection point) within each grouped exclusive area. The grouped exclusive areas can be arranged in the middle of the chip without overlap, and there will be some gaps at the edges of the grouped exclusive areas. These gaps can be used to place the connection points corresponding to signals such as power supply, ground, clock, and control. Or, more than two redundant connection points are set within the grouped exclusive area of each group. Schematically, the data connection points and a part of the redundant connection points of this group are arranged around the grouped exclusive area, and the remaining redundant connection points are arranged in the middle of the grouped exclusive area; thereby increasing the distance between one or more redundant connection points to better prevent the failure of the entire group's function. Or, more than 2 redundant connection points can also be evenly set at equal angles along the center point of the hexagon.

[0040] According to an embodiment of the present invention, if each group has multiple grouped exclusive areas (assuming D), the connection points of this group can be evenly divided into D adjacent grouped exclusive areas. Then, the connection points obtained by each are evenly arranged within the D adjacent grouped exclusive areas. If a group corresponds to D grouped exclusive areas, it is recommended that when setting the number of redundant connection points for each group, set the number of its redundant connection points as an integer multiple of D, and divide more than 1 redundant connection point within each grouped exclusive area, thereby further reducing the possibility of a single group failure and ensuring the reliability of the data transmission performance of the die.

[0041] According to an embodiment of the present invention, the method further includes: setting other functional connection points for realizing the die between the gaps of the grouped exclusive areas and / or between the gaps between the die boundary and the grouped exclusive areas. See Figure 3 , for example: power supply connection point VDD, ground connection point GND, connection point Vld for transmitting handshake signals, etc. Preferably, functional gaps are set in at least part of the area between the grouped exclusive areas, the width of the functional gap exceeds the size of one connection point, and a power supply connection point and / or a ground connection point are set within the functional gap. As Figure 3 the gaps between Group 1 and Group 3, and between Group 2 and Group 4 are functional gaps, in which there are power supply connection point VDD and ground connection point GND. Since there are functional gaps between each grouped exclusive area, and a power supply connection point or a ground connection point is set within each functional gap, multiple redundant power supply connection points and ground connection points can be set on the entire die, greatly reducing the possibility of complete failure of the power supply or ground function.

[0042] The following briefly explains why the solution of the present invention can improve the fault tolerance ability of parallel interface groups. Still taking the hexagon-shaped exclusive area of a group as an example, as Figure 3 shown by the red hexagon in the upper left corner, if a concentrated connection point failure occurs, it is very likely to be within a group. Only when the failure area is at the junction of multiple groups is it possible to damage multiple groups, as Figure 3 shown by the red hexagon between Group 1 and Group 3. This probability is relatively low. In addition, even if the failure area is at the junction of three groups, the number of failed connection points allocated to each group will be relatively small, and there is a higher probability that redundant connection points can be used for repair.

[0043] According to an embodiment of the present invention, there is also provided a chiplet system, which includes multiple chiplets. The connection points of the chiplets in the chiplet system are arranged according to the connection point arrangement method for chiplet interfaces in the foregoing embodiment. Among them, the chiplet system is configured to use a dynamic switching mechanism to ensure the data transmission process without stopping. The dynamic switching mechanism includes: when transmitting data through the parallel interfaces of each pair of chiplets, monitoring whether the data transmitted by each group in the parallel interface is abnormal. If so, a verification mechanism is started for the abnormal group to detect the faulty data connection points and their corresponding channels in the abnormal group, and switch the faulty connection points and their corresponding channels to the redundant connection points and their corresponding channels. The technical solution of this embodiment can at least achieve the following beneficial technical effects: on the one hand, the chiplets with connection points arranged by the connection point arrangement method can better reduce the probability of multiple groups failing simultaneously; on the other hand, the faults of each group can be verified and switched separately to minimize the impact on the data transmission of other groups as much as possible.

[0044] According to an embodiment of the present invention, the verification mechanism includes: suspending the data transmission task of the abnormal group, and at the same time using the other groups in the parallel interface to which the abnormal group belongs to perform data transmission at a reduced speed; sending preset verification data on each channel of the abnormal group, and this verification data is known to both the sender and the receiver; on each channel, respectively compare whether the received verification data is consistent with the preset verification data. If not, the channel is a faulty channel, and its corresponding data connection point is used as the faulty connection point. This method uses preset verification data to quickly perform fault verification on each channel to locate the faulty channel.

[0045] According to an embodiment of the present invention, the dynamic switching mechanism further includes: after detecting the faulty connection points, judging whether the number of faulty connection points in the abnormal group is less than or equal to the redundant connection points of the abnormal group. If so, matching redundant connection points for the faulty connection points one by one; switching the faulty connection points and their corresponding channels to the redundant connection points and their corresponding channels matched for them.

[0046] Generally speaking, in the present invention, the connection points of each parallel interface are divided into several grouped exclusive regions, and each region contains a certain number of connection points. The advantage of the hexagonal arrangement is that it can minimize the distance between adjacent connection points while maintaining sufficient physical isolation to avoid the spread of faults.

[0047] It should be noted that although the above steps are described in a specific order, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order, as long as the required functions can be achieved.

[0048] The present invention can be a system, a method, and / or a computer program product. The computer program product can include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0049] The computer-readable storage medium can be a tangible device that retains and stores instructions for use by an instruction execution device. The computer-readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in a groove having instructions stored thereon, and any suitable combination of the foregoing.

[0050] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the disclosed embodiments.

Claims

1. A method for arranging connection points for chiplet interfaces, characterized in that, Including: Obtain the die boundary and the total number of groups M to be placed, where the die boundary represents the placeable area of the connection points on the die, and the total number of groups is the sum of the number of groups of all parallel interfaces of the die; Within the die boundary, divide multiple non-overlapping group exclusive areas N according to the total number of groups M, where N is greater than or equal to M; Match each group with a corresponding group exclusive area, and arrange the connection points of the corresponding group within each group exclusive area. The connection points of each group include data connection points and redundant connection points.

2. The method according to claim 1, wherein When dividing N non-overlapping group exclusive areas, limit the size of the group exclusive areas to ensure that more than 2 group exclusive areas can be accommodated in the length direction of the die boundary, and more than 2 group exclusive areas can also be arranged in the width direction of the die boundary.

3. The method according to claim 1, wherein The shapes of all group exclusive areas of the same die are the same. The shape of the group exclusive area is a regular hexagon, a parallelogram hexagon, a rectangle or a circle.

4. The method according to claim 1, wherein Data connection points and redundant connection points are set within the group exclusive area of each group. The data connection points serve as the connection points of the relevant channels within the parallel interface, and the redundant connection points serve as backups of the data connection points. One or more redundant connection points are set within each group exclusive area.

5. The method according to claim 4, wherein The data connection points of each group are arranged around the group exclusive area, and the redundant connection points are arranged in the middle of the group exclusive area.

6. The method according to claim 4, wherein Two or more redundant connection points are set within the group exclusive area of each group.

7. The method according to any one of claims 1 to 6, characterized in that The method further includes: setting functional gaps in at least part of the areas between the group exclusive areas. The width of the functional gap exceeds the size of one connection point, and power supply connection points and / or ground connection points are set within the functional gap.

8. A chiplet system, comprising a plurality of chiplets, characterized in that, The connection points of the die within the die system are arranged according to the method of one of claims 1-7, where The die system is configured to use a dynamic switching mechanism to ensure the data transmission process without stopping the machine. The dynamic switching mechanism includes: When transmitting data through the parallel interfaces of each pair of dies, monitor whether the data transmitted by each group in the parallel interface is abnormal. If so, start a verification mechanism for the abnormal group to detect the faulty data connection points and their corresponding channels in the abnormal group; Switch the faulty connection points and their corresponding channels to the redundant connection points and their corresponding channels.

9. The system according to claim 8, wherein The verification mechanism includes: Suspend the data transmission task of the abnormal group, and at the same time use other groups of the parallel interface to which the abnormal group belongs for reduced-speed data transmission; Send pre-set verification data on each channel of the abnormal group. The verification data is known to both the sender and the receiver; On each channel, compare whether the received verification data is consistent with the pre-set verification data respectively. If not, the channel is a faulty channel, and its corresponding data connection point is used as the faulty connection point.

10. The method according to claim 9, characterized in that, The dynamic switching mechanism includes: After detecting the faulty connection points, determine whether the number of faulty connection points in the abnormal group is less than or equal to the redundant connection points of the abnormal group. If so, match redundant connection points for the faulty connection points one by one; Switch the faulty connection points and their corresponding channels to the redundant connection points and their corresponding channels matched for them.

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