Silicon-based quantum device based on Ge / GeSi planar substrate structure and preparation method thereof

Abstract

The invention relates to the technical field of quantum devices, in particular to a silicon-based quantum device based on a Ge / GeSi planar substrate structure and a preparation method of the silicon-based quantum device, a Ge / GeSi planar substrate comprises a silicon layer, a germanium layer, a germanium-silicon strain buffer layer and a GeSi / Ge / GeSi sandwich structure from bottom to top, a bit carrier is a hole at a Ge-SiGe interface, due to the anisotropy of natural large spin orbit interaction and magnetic field interaction, the traditional spin quantum bit for spin control can be realized only by an alternating electric field, and the spin jump bit can also be realized by jumping spin among different quantum dots; the preparation method of the silicon-based quantum device comprises the steps of novel multi-layer stacked electrode structure design, global and local alignment marking, metal source and drain electrode and internal and external electrode separate processing, bridging connection layer process, full-layer covering type dielectric layer and insulating layer growth, wire binding structure optimization, local dielectric layer etching and the like, so that the process thermal budget is reduced, the process steps are simplified, and the production efficiency is improved. And the device noise and the device yield are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum devices, and particularly to a silicon-based quantum device based on a Ge / GeSi planar substrate structure and a preparation method thereof. Background Art

[0002] Among many quantum computing implementation paths, silicon-based quantum computing has become one of the most promising systems for realizing a universal quantum computer due to its long spin qubit coherence time, compatibility of micro-nano processing with traditional CMOS processes, and support for all-electric control.

[0003] Currently, there are mainly two schemes for silicon-based quantum computing. One is to use doped active atoms in a silicon-based substrate as qubit carriers. This scheme currently has problems such as uncertain positions of doped atoms and uncertain numbers of active atoms, which affect large-scale integration. At the same time, the yield is low and mass production is difficult. The other is to induce quantum dots in the substrate material through gate electrodes (gates).

[0004] According to different substrate materials, gate electrode-based silicon-based quantum computing can be further divided into Ge / GeSi core - wrapped nanowire structures, Ge / GeSi roof nanowire structures, and Si-MOS, Si / SiGe, Ge / GeSi planar structures. Among them, the naturally formed nanowire structures such as Ge / GeSi core - wrapped and Ge / GeSi roof have randomly distributed grown nanowires, making it difficult to scale up. Si-MOS and Si / SiGe use electrons induced by gate electrodes at the Si and SiO2 interface or the Si and SiGe interface as qubit carriers, and there are problems such as difficulty in realizing ohmic contact, strict requirements for the size of process electrodes and large process electrode density, and the need for an additional micro-magnet gradient magnetic field for qubit manipulation, resulting in problems such as low leakage yield of the device, large electrical noise, and difficulty in forming quantum dots, and it is even more difficult to achieve large-scale mass production of silicon-based quantum computing chips.

[0005] Therefore, the prior art still needs to be improved and developed. Summary of the Invention

[0006] In view of the above deficiencies of the prior art, the purpose of the present invention is to provide a silicon-based quantum device based on a Ge / GeSi planar substrate structure and a preparation method thereof, aiming to solve the detailed process problems such as difficulty in realizing ohmic contact, strict requirements for the size of process electrodes and large process electrode density, the need for an additional micro-magnet gradient magnetic field for qubit manipulation, low gate leakage yield, large electrical noise, and difficulty in forming quantum dots, as well as the problems of arrayed and large-scale processing in existing gate electrode-based silicon-based quantum devices.

[0007] The technical solution of the present invention is as follows:

[0008] A silicon-based quantum device based on a Ge / GeSi planar substrate structure, comprising a silicon layer, a germanium layer, a germanium-silicon strain buffer layer, a GeSi / Ge / GeSi sandwich structure layer, a source electrode and a drain electrode that are stacked in sequence from bottom to top and are in contact with the GeSi / Ge / GeSi sandwich structure, and a first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a third dielectric layer, a third gate layer, an insulating layer and a plurality of wire bonding electrode layers that are stacked in sequence from bottom to top on the GeSi / Ge / GeSi sandwich structure layer;

[0009] Part of the first dielectric layer is in contact with the source electrode and the drain electrode; part of the second dielectric layer is in contact with the first dielectric layer; part of the third dielectric layer is in contact with the second dielectric layer; and a plurality of wire bonding electrode layers are respectively connected to the source electrode, the drain electrode, the first gate layer, the second gate layer and the third gate layer.

[0010] For the silicon-based quantum device based on the Ge / GeSi planar substrate structure, the thickness of the silicon layer is 200 um - 800 um; the thickness of the germanium layer is 0.5 um - 5 um; the thickness of the germanium-silicon strain buffer layer is 0.3 um - 3 um; the GeSi / Ge / GeSi sandwich structure layer is composed of a first GeSi layer, a first Ge layer and a second GeSi layer from bottom to top; the thickness of the first GeSi layer is 50 nm - 500 nm, the thickness of the first Ge layer is 10 nm - 100 nm, and the thickness of the second GeSi layer is 10 nm - 100 nm. The qubit carrier is the hole carriers at the interface between the first Ge layer and the second SiGe layer, which can not only realize the traditional spin qubits with all-electric control relying on the electric dipole resonance, but also realize the spin-hopping qubits by the spin hopping between different quantum dots.

[0011] For the silicon-based quantum device based on the Ge / GeSi planar substrate structure, wherein the thickness of the source electrode is 20 nm - 100 nm; the thickness of the drain electrode is 20 nm - 100 nm; the thickness of the first dielectric layer is 5 nm - 20 nm; the thickness of the second dielectric layer is 5 nm - 20 nm; the thickness of the third dielectric layer is 5 nm - 20 nm.

[0012] For the silicon-based quantum device based on the Ge / GeSi planar substrate structure, wherein the thickness of the first gate layer is 20 nm - 100 nm; the thickness of the second gate layer is 20 nm - 100 nm; the thickness of the third gate layer is 20 nm - 100 nm; the thickness of the insulating layer is 100 nm - 3 μm; the thickness of the wire bonding electrode layer is 100 nm - 3 μm.

[0013] The silicon-based quantum device based on the Ge / GeSi planar substrate structure, wherein the materials of the source electrode and the drain electrode are independently selected from one of Al, Pd, Pt, Ti, Au or an alloy of at least two of them; the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are independently selected from one of alumina, hafnium oxide, zirconium oxide.

[0014] The silicon-based quantum device based on the Ge / GeSi planar substrate structure, wherein the materials of the first gate layer, the second gate layer and the third gate layer are independently selected from one of Al, Pd, Pt, Ti, Au or an alloy of at least two of them; the material of the insulating layer is selected from silicon dioxide or silicon nitride; the material of the wire bonding electrode layer is selected from one of Al, Pd, Pt, Ti, Au or an alloy of at least two of them.

[0015] A preparation method of a silicon-based quantum device based on the Ge / GeSi planar substrate structure, comprising the steps of:

[0016] Providing a germanium-silicon / germanium / germanium-silicon heterostructure substrate, and performing global alignment marking and local alignment marking processing to obtain an alignment marking substrate;

[0017] Performing electron beam exposure on the alignment marking substrate, then processing internal source-drain electrodes and external source-drain electrodes, and performing annealing treatment to obtain a device precursor;

[0018] Successively forming a first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a third dielectric layer, a third gate layer, an insulating layer and a plurality of wire bonding electrode layers on the device precursor to obtain a silicon-based quantum device.

[0019] The preparation method of the silicon-based quantum device based on the Ge / GeSi planar substrate structure, wherein the temperature of the annealing treatment is 250°C - 450°C, and the time of the annealing treatment is 5s - 300s.

[0020] The preparation method of the silicon-based quantum device based on the Ge / GeSi planar substrate structure, wherein the interval of the global alignment marking is at least 10 mm or more, and the interval of the local alignment marking is less than 1 mm; the global alignment marking and local alignment marking processing are realized by ultraviolet exposure or electron beam exposure. The global alignment marking and local alignment marking take into account high precision and arrayed large-scale processing.

[0021] The preparation method of the silicon-based quantum device based on the Ge / GeSi planar substrate structure, wherein the internal source-drain electrodes and the external source-drain electrodes are independently prepared by electron beam exposure and electrode evaporation. Using this method to prepare the internal source-drain electrodes and the external source-drain electrodes can take into account electrode resolution and process yield.

[0022] Preparation method of silicon-based quantum device based on Ge / GeSi planar substrate structure, wherein the novel stacked gate structure design restricts the two-dimensional plane to a one-dimensional nanowire through the first gate layer, which can effectively shield various environmental noises, reduce device noise, and more easily form electrical quantum dots.

[0023] Preparation method of silicon-based quantum device based on Ge / GeSi planar substrate structure, wherein the internal gate and the external gate in the silicon-based quantum device are connected by a bridging process; the internal gate and the external gate form an overlapping region, and the exposure area of the bridging electrode is controlled within the electrode areas corresponding to the internal gate and the external gate. The bridging process reduces the damage of argon ion bombardment to the dielectric layer and improves the gate leakage yield.

[0024] Preparation method of silicon-based quantum device based on Ge / GeSi planar substrate structure, wherein the growth modes of the first dielectric layer, the second dielectric layer, the third dielectric layer and the insulating layer are all maskless full-layer coverage growth, which ensures the pollution-free growth interface and reduces the electrical noise introduced by the growth of the dielectric layer and the insulating layer.

[0025] Preparation method of silicon-based quantum device based on Ge / GeSi planar substrate structure, wherein, before forming a plurality of the wire bonding electrode layers, local position etching treatment is further included for the first dielectric layer, the second dielectric layer, the third dielectric layer and the insulating layer in the region covered by the wire bonding electrode layer, so as to realize the extraction of the electrical structure while ensuring that the core structure of the device is protected by the dielectric layer and the insulating layer.

[0026] Beneficial effects: The present invention provides a silicon-based quantum device based on a Ge / GeSi planar substrate structure and a preparation method thereof. The silicon-based quantum device based on the Ge / GeSi planar substrate structure includes a silicon layer, a germanium layer, a germanium-silicon strain buffer layer, a GeSi / Ge / GeSi sandwich structure layer, a source electrode and a drain electrode in contact with the GeSi / Ge / GeSi sandwich structure layer, and a first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a third dielectric layer, a third gate layer, an insulating layer, and several wire bonding electrode layers stacked on the GeSi / Ge / GeSi sandwich structure layer from bottom to top in sequence; a part of the first dielectric layer is in contact with the source electrode and the drain electrode; a part of the second dielectric layer is in contact with the first dielectric layer; a part of the third dielectric layer is in contact with the second dielectric layer; several wire bonding electrode layers are respectively connected to the source electrode, the drain electrode, the first gate layer, the second gate layer, and the third gate layer. The present invention adopts a Ge / GeSi planar substrate structure, and the bit carrier is the hole carriers at the Ge-SiGe interface. The naturally existing large spin-orbit interaction of holes enables it to utilize the electric dipole of the holes themselves. Under the drive of an alternating electric field, a traditional spin qubit with all-electric control can be realized by relying on electric dipole resonance; at the same time, it also ensures that the g-factor of the Zeeman splitting of different bits can be adjusted by using a local electric field, thereby adjusting the resonance frequencies of different bits, avoiding frequency crosstalk, and realizing the addressability of the bits. Moreover, the interaction between the hole carriers and the magnetic field has great anisotropy, and the spin can be realized to jump between different quantum dots (hopping), thereby realizing a spin-hopping qubit. Compared with traditional spin qubits, the spin-hopping qubit manipulation only requires a low-frequency baseband signal and has lower power consumption. Based on the Ge / GeSi planar substrate structure, the present invention has invented a series of preparation methods for arraying and scaling up silicon-based quantum device arrays, including: taking into account both global alignment marks and local alignment marks for high-precision and arrayed and scaled processing, directly and rapidly annealing the metal source-drain electrodes to form an electron reservoir, which not only reduces the process thermal budget but also simplifies the process steps, designing a new stacked gate structure to reduce device noise, separately processing the internal and external electrodes to take into account both electrode resolution and process yield, the bridge connection layer process to improve the gate leakage yield, the full-layer coverage dielectric layer growth to ensure interlayer noise, the optimized wire bonding structure, local dielectric layer etching, and the full-coverage growth of a thick insulating layer to ensure the packaging yield, etc., providing important technical support for silicon-based gate electrode quantum computing and quantum chips, etc. Description of the Drawings

[0027] Figure 1 It is a schematic structural diagram of a silicon-based quantum device based on a Ge / GeSi planar substrate structure according to the present invention;

[0028] Figure 2 It is a schematic structural diagram of a silicon-based quantum device with a typical three-quantum dot structure;

[0029] Figure 3 For other three - quantum - dot structures and six - quantum - dot structures, including schematic diagrams of structures with two - layer gates, three - layer gates, and structures with different numbers of gate layers;

[0030] Figure 4 Schematic diagram of the stacked electrodes of Crossbar;

[0031] Figure 5 Schematic diagram of the Ge / GeSi planar substrate structure;

[0032] Figure 6 Schematic diagram of the global alignment mark (left) and local alignment mark (right);

[0033] Figure 7 Schematic diagram of the processing flow of the silicon - based quantum device based on the Ge / GeSi planar substrate structure;

[0034] Figure 8 Schematic diagram of the processing flow of the global alignment mark and local alignment mark;

[0035] Figure 9 Schematic diagram of the processing flow of the internal source - drain electrodes;

[0036] Figure 10 Schematic diagram of the process for checking the electrical conductivity and physical connectivity of the dummy wafer;

[0037] Figure 11 Schematic diagram of the dielectric layer etching process. Detailed implementation manners

[0038] The present invention provides a silicon - based quantum device based on a Ge / GeSi planar substrate structure and a preparation method thereof. To make the objectives, technical solutions, and effects of the present invention clearer and more definite, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] Those skilled in the art of the present technology can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the general understanding of those of ordinary skill in the technical field to which the present invention belongs. It should also be understood that terms such as those defined in a general dictionary should be understood as having a meaning consistent with the meaning in the context of the prior art, and will not be interpreted with an idealized or overly formal meaning unless specifically defined as here.

[0040] As Figure 1As shown in the figure, the present invention provides a silicon-based quantum device based on a Ge / GeSi planar substrate structure, including a silicon layer, a germanium layer, a germanium-silicon strain buffer layer, a GeSi / Ge / GeSi sandwich structure layer, a source electrode and a drain electrode that are stacked in sequence from bottom to top and are in contact with the GeSi / Ge / GeSi sandwich structure layer, and a first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a third dielectric layer, a third gate layer, an insulating layer, and several wire bonding electrode layers that are stacked in sequence from bottom to top on the GeSi / Ge / GeSi sandwich structure layer;

[0041] Part of the first dielectric layer is in contact with the source electrode and the drain electrode; part of the second dielectric layer is in contact with the first dielectric layer; part of the third dielectric layer is in contact with the second dielectric layer; several wire bonding electrode layers are respectively connected to the source electrode, the drain electrode, the first gate layer, the second gate layer, and the third gate layer.

[0042] In this embodiment, the silicon layer, the germanium layer, the germanium-silicon strain buffer layer, and the GeSi / Ge / GeSi sandwich structure layer that are stacked in sequence from bottom to top are used as the substrate structure, and a Ge / GeSi planar substrate structure is adopted. The bit carrier is the hole carrier at the Ge-SiGe interface. The large spin-orbit interaction naturally existing in the hole enables it to utilize the electric dipole of the hole itself. Under the drive of an alternating electric field, a traditional spin qubit that can be fully electrically controlled can be realized by relying on electric dipole resonance; at the same time, it also ensures that the g factor of the Zeeman splitting of different bits can be adjusted by using a local electric field, thereby adjusting the resonance frequencies of different bits, avoiding frequency crosstalk, and realizing the addressability of the bits. Moreover, the extremely large anisotropy of the interaction between the hole carrier and the magnetic field can realize the hopping of the spin between different quantum dots, thereby realizing a spin-hopping qubit. Compared with the traditional spin qubit, the spin-hopping qubit manipulation only requires a low-frequency baseband signal and has lower power consumption. Based on the Ge / GeSi planar substrate structure, the present invention has invented a series of adapted methods for fabricating silicon-based quantum device arrays on a large scale, including: taking into account both global alignment marks and local alignment marks for high-precision and large-scale array processing, directly and rapidly annealing the metal source-drain electrodes to form an electron reservoir, which not only reduces the process thermal budget but also simplifies the process steps, designing a new stacked gate structure to reduce device noise, separately processing the inner and outer electrodes to take into account both electrode resolution and process yield, the bridge connection layer process to improve the gate leakage yield, the full-layer coverage dielectric layer growth to ensure interlayer noise, the optimized wire bonding structure, the local dielectric layer etching, and the full-coverage growth of the thick insulating layer to ensure the packaging yield, etc. It provides important technical support for silicon-based gate electrode quantum computing and quantum chips, etc.

[0043] Specifically, the silicon-based quantum device based on the Ge / GeSi planar substrate structure can achieve arrayed and large-scale processing. That is, the Ge / GeSi planar substrate structure can be used for device processing on the entire two-dimensional plane. Quantum dots can be formed at any position on the two-dimensional plane through device processes, without the randomness problem of nanowires grown by natural physical methods. Therefore, there are no physical limit nodes in the device position design and arrayed and large-scale design in the overall process. As long as the wafer is large enough, arbitrary scale expansion can be achieved, breaking through the limit of physical expansion. Moreover, the qubit carrier in this structure is the hole carriers at the Ge-SiGe interface. The naturally existing large spin-orbit interaction of holes enables it to utilize the electric dipole of the holes themselves. Driven by an alternating electric field, traditional spin qubits with all-electric control can be achieved relying on electric dipole resonance. At the same time, the large spin-orbit interaction also ensures that the g-factor of the Zeeman splitting of different qubits can be adjusted using a local electric field, thereby adjusting the resonance frequencies of different qubits to avoid frequency crosstalk and achieve qubit addressability. Therefore, the qubit driving and addressability of this silicon-based quantum device do not require micro-magnets, which ensures that the quantum device based on the Ge / GeSi planar substrate structure does not require the process of micro-magnets, greatly reducing the difficulty of qubit scale expansion. Moreover, the interaction between the hole carriers and the magnetic field has extremely large anisotropy, which can achieve the hopping of spins between different quantum dots, thereby realizing spin-hopping qubits. Compared with traditional spin qubits, spin-hopping qubit manipulation can achieve spin manipulation in a low magnetic field environment and only requires the use of low-frequency baseband signals, with lower power consumption, which is beneficial to the large-scale expansion of qubits and the improvement of the fidelity of single-qubit gates and two-qubit gates.

[0044] In some embodiments, the silicon-based quantum device based on the Ge / GeSi planar substrate structure can not only form a stacked structure as shown in Figure 1 but also form stacked structures as shown in Figure 2 , Figure 3 and Figure 4 as well as various other stacked structures, and is not limited by the number of stacked electrode layers. As shown in Figure 2 , it confines the two-dimensional plane to a one-dimensional nanowire through the first gate layer, and finally confines the one-dimensional nanowire to a zero-dimensional quantum dot by combining subsequent gates. This structure is applied to the Ge / GeSi planar substrate structure for the first time. Therefore, quantum dots are completely formed electrically, which is easier to integrate and expand compared with the physical definition of nanowires, and the regulation of quantum dots is also more flexible. In addition, the mobility of the two-dimensional hole gas in the Ge / GeSi planar substrate structure is very high, reaching 2×10 6 cm 2 / (Vs), with lower requirements for the electrode line width, making it easier to realize device processing and large-scale integration.

[0045] In some embodiments, such as Figure 5 shown, the thickness of the silicon layer is 200 um - 800 um; the thickness of the germanium layer is 0.5 um - 5 um; the thickness of the germanium-silicon strain buffer layer is 0.3 um - 3 um; the sandwich structure layer of GeSi / Ge / GeSi consists of a first GeSi layer, a first Ge layer, and a second GeSi layer from bottom to top; the first GeSi layer (Ge x Si 1-x (x = 0.7 - 1.0)) has a thickness of 50 nm - 500 nm, the thickness of the first Ge layer is 10 nm - 100 nm, and the second GeSi layer (Ge x Si 1-x (x = 0.7 - 1.0)) has a thickness of 10 nm - 100 nm. The substrate structure obtained with the above thicknesses has a unique energy band structure, forming a two-dimensional plane - two-dimensional hole gas between the germanium layer and the two germanium-silicon layers to form quantum dots, thereby enabling confinement of the quantum dots in the Z direction. Moreover, the qubit carrier is the hole carrier at the interface between the middle Ge layer and the second SiGe layer, which can not only realize traditional spin qubits with all-electric control relying on electric dipole resonance, but also realize spin-hopping qubits through the hopping of spins between different quantum dots.

[0046] In a preferred embodiment, the thickness of the first GeSi layer is 300 nm; the thickness of the first Ge layer is 30 nm; the thickness of the second GeSi layer is 50 nm. As Figure 5 shown, a quantum well structure is formed between the germanium layer and the two germanium-silicon layers, confining the quantum dots in the vertical direction. Therefore, holes will accumulate in the germanium plane between the two germanium-silicon layer planes to form a two-dimensional hole gas.

[0047] In some embodiments, the thickness of the source electrode is 20 nm - 100 nm; the thickness of the drain electrode is 20 nm - 100 nm; the thickness of the first dielectric layer is 5 nm - 20 nm; the thickness of the second dielectric layer is 5 nm - 20 nm; the thickness of the third dielectric layer is 5 nm - 20 nm.

[0048] In a preferred embodiment, the thickness of the source electrode is 30 nm; the thickness of the drain electrode is 30 nm; the thickness of the first dielectric layer is 10 nm; the thickness of the second dielectric layer is 10 nm; the thickness of the third dielectric layer is 10 nm.

[0049] In some embodiments, the thickness of the first gate layer is 20 nm - 100 nm; the thickness of the second gate layer is 20 nm - 100 nm; the thickness of the third gate layer is 20 nm - 100 nm; the thickness of the insulating layer is 100 nm - 3 μm; the thickness of the wire bonding electrode layer is 100 nm - 3 μm. The thickness of the wire bonding electrode layer being at least one hundred nanometers ensures the success rate of wire bonding.

[0050] In a preferred embodiment, the thickness of the first gate layer is 40 nm; the thickness of the second gate layer is 50 nm; the thickness of the third gate layer is 60 nm; the thickness of the insulating layer is 1 μm; the thickness of the wire bonding electrode layer is 350 nm.

[0051] In some embodiments, the materials of the source electrode and the drain electrode are independently selected from one of Al, Pd, Pt, Ti, Au or an alloy of at least two of them; the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are independently selected from one of aluminum oxide, hafnium oxide, and zirconium oxide.

[0052] In some embodiments, the materials of the first gate layer, the second gate layer, and the third gate layer are independently selected from one of Al, Pd, Pt, Ti, Au or an alloy of at least two of them; the material of the insulating layer is selected from silicon dioxide or silicon nitride; the material of the wire bonding electrode layer is selected from one of Al, Pd, Pt, Ti, Au or an alloy of at least two of them.

[0053] In addition, the present invention also provides a method for manufacturing a silicon-based quantum device based on a Ge / GeSi planar substrate structure, including the steps of:

[0054] Step S10: Provide a germanium-silicon / germanium / germanium-silicon heterostructure substrate, and perform global alignment marking and local alignment marking processing to obtain an alignment-marked substrate;

[0055] Step S20: Perform electron beam lithography on the alignment-marked substrate, then process the internal source-drain electrodes and the external source-drain electrodes, and perform annealing treatment to obtain a device precursor;

[0056] Step S30: Sequentially form a first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a third dielectric layer, a third gate layer, an insulating layer, and a plurality of wire bonding electrode layers on the device precursor to obtain a silicon-based quantum device.

[0057] In this embodiment, the source and drain electrodes of the silicon-based quantum device are the first-layer processed electrodes, which are in direct contact with the substrate material, directly extend to the most core area of the device, and can directly realize the function of the hole reservoir. Moreover, global alignment marks and local alignment marks are processed on the germanium-silicon / germanium / germanium-silicon heterostructure substrate to form reliable global alignment mark and local alignment mark shapes, taking into account convenient positioning and alignment accuracy. The overlay error can be less than 10 nm, and at the same time, an automated overlay process for global alignment marks and local alignment marks can be realized to achieve arrayed and large-scale processing. At the same time, in the formation of specific micro-nano electrodes, the internal electrodes and external electrodes are exposed and coated separately to balance the electrode resolution and yield.

[0058] Specifically, as Figure 2 shown is the classical three-quantum dot structure designed by using the preparation method. In Figure 2 , except for the marked source and drain electrodes, the rest represent gates of different levels. This design method of the source and drain electrodes is essentially different from that of the source and drain electrodes of electron-type silicon-based quantum computing devices. The formation of the source and drain electrodes of electron-type silicon-based quantum computing devices requires the assistance of gates to extend the electron reservoir to the most core area of the device, that is, compared with Figure 2 , the electrodes marked as the source and drain electrodes also need to be a certain layer of the gate. In this way, the processing requires an additional processing of the insulating dielectric layer and internal and external electrodes, making the steps more cumbersome. Moreover, the source and drain electrodes formed with the assistance of gates may have an insufficiently obvious reduction in the potential barrier, resulting in difficulty in acting as an electron reservoir. At the same time, the gate-assisted electron reservoir requires a relatively high gate-assisted voltage, which will affect the control ability of other gates and there are many problems in practical applications. The direct formation method of the metal electrode source and drain of the present invention overcomes the above difficulties, simplifies the processing steps, and facilitates subsequent potential barrier regulation. Moreover, the first gate layer is composed of three electrodes with a relatively large area and parallel to the core part, which can shield the electrical noise signals in the non-device core area of the substrate, thereby realizing high-quality quantum dots and improving various bit indexes.

[0059] In some embodiments, the temperature of the annealing treatment is 250°C - 450°C, and the time of the annealing treatment is 5 s - 300 s. Through rapid annealing treatment, an ohmic contact between the internal source-drain electrodes and the Ge / GeSi two-dimensional hole gas can be formed, reducing the contact barrier. Ohmic contact can be achieved by using low-temperature annealing, without the need for ion implantation and high-temperature annealing. When using this preparation method to prepare silicon-based quantum devices, the formation of ohmic contact does not require complex ion implantation processes and high-temperature (higher than 700°C) rapid annealing processes. Only rapid annealing at a relatively low temperature in a mixed gas atmosphere of nitrogen and hydrogen is required after forming nano-scale ohmic contact electrodes to achieve an ideal ohmic contact. Since high-temperature rapid annealing will damage the properties of the two-dimensional hole gas at the Ge / SiGe interface or even cause the disappearance of this interface, the method of using metal electrodes and low-temperature rapid annealing solves the problems that may be caused by high-temperature annealing. At the same time, this preparation method does not require an ion implantation step, and arrayed and large-scale processing can be more conveniently achieved.

[0060] In some embodiments, the interval of the global alignment marks is at least 10 mm or more, and the interval of the local alignment marks is less than 1 mm; the global alignment marks and the local alignment marks are processed by using ultraviolet exposure or electron beam exposure. The global alignment marks and the local alignment marks can take into account both high precision and arrayed and large-scale processing. As Figure 6 shown, the global alignment marks and the local alignment marks need to cover the substrate surface. At the center formed by each local alignment mark, the processing of the core region of the quantum device starts. The overall processing steps of the quantum device are carried out sequentially from bottom to top. The trapping formation and transport measurement of quantum dots are realized through the stacking of source-drain electrodes and two or three layers of gate electrodes. In the Z direction, the quantum dots are restricted by the energy band structure. In the two-dimensional structure in the XY direction, the transport direction of holes is controlled by using source-drain electrodes (abbreviated as SD). The two-dimensional hole gas is restricted to zero-dimensional quantum dots through multiple layers of gates. Finally, the energy levels of the quantum dots and the spin directions of the trapped holes are regulated by adjusting the corresponding gate voltages, thereby realizing silicon-based single-bit, two-bit, and multi-bit devices. Through this structure, complete electrical control of quantum dots can be achieved. Compared with the method of physically defining nanowires, the present invention is easier to integrate and expand, and the regulation of quantum dots is also more flexible.

[0061] Specifically, the flow chart of the preparation method is as Figure 7As shown in the figure, 1) First, prepare the substrate, and then perform global alignment marks and local alignment marks processing on the substrate. After processing the internal source-drain electrodes of the SD using electron beam lithography, process the external source-drain electrodes, and perform rapid annealing to form ohmic contacts. Conduct conductivity inspection and physical connectivity inspection on the co-processed dummy wafer; 2) Then perform atomic layer deposition of the dielectric layer (taking alumina as an example), and then perform electron beam lithography to process the internal gate electrodes and external gate electrodes. Then check the conductivity and physical connectivity of the dummy wafer. Repeat step 2) until the processing of multiple dielectric layers and gates is completed. Then perform etching of the insulating dielectric layer in the wire bonding electrode area, growth of silicon oxide, lead out all large electrode structures, and process the wire bonding large electrodes. Conduct conductivity testing and leakage testing on the wire bonding electrode dummy wafer. Finally, perform electrical testing feedback on the silicon-based quantum device.

[0062] It should be noted that the dummy wafer has both a structure exactly the same as that of the formal device and a structure with direct connection of the internal source-drain electrodes. The design, processing, and inspection of the dummy wafer minimize the influence of random factors during the processing and ensure the success rate of the device.

[0063] In some embodiments, the minimum width dimension of the global alignment mark is 1 μm, and the dimension of the local alignment mark is 500 nm. Both can be achieved using ultraviolet lithography and electron beam lithography.

[0064] Specifically, as Figure 8 shown, step S10 includes the steps of: spin-coating with an adhesion promoter, rinsing and drying with water, then spin-coating with a positive photoresist or electron glue, then baking and completing ultraviolet lithography or electron beam lithography at a preset power (60 W power), and finally removing the exposed area through development, evaporating metal electrodes (Ti, Cr, Au, Pd, Pt) by electron beam evaporation, and completely removing the photoresist or electron glue with NMP solution to complete the stripping of the excess metal to form global alignment marks and local alignment marks. Since there are no marks for alignment and overlay on the substrate before ultraviolet lithography or electron beam lithography, before exposure, it is necessary to accurately find the geometric center of the substrate according to the size and shape of the substrate on the corresponding exposure equipment and set this geometric center as the center of the overall exposure area.

[0065] In some embodiments, both the internal source-drain electrodes and the external source-drain electrodes are independently prepared by electron beam lithography and electrode evaporation. Using this method to prepare the internal source-drain electrodes and the external source-drain electrodes can take into account both electrode resolution and process yield.

[0066] In some embodiments, the step S20 performs electron beam exposure on the alignment mark substrate to process the internal source and drain electrodes, which specifically includes: after completing the processing of the global alignment mark and the local alignment mark, the device electrodes are processed using the global alignment mark and the local alignment mark. The processing flow is as Figure 9 shown. First, the internal source and drain electrodes and the dummy structure source and drain are processed. The purpose of this step is to finally form the internal electrodes of the source and drain. At present, it is difficult for conventional ultraviolet exposure equipment to achieve the processing ability of the line width of the internal electrodes of the source and drain. Therefore, electron beam exposure is used to process the internal source and drain electrodes. The processing flow is as follows: First, a tackifier is spin-coated to increase the adhesion between the electron beam resist and the substrate. After spin-coating, it is rinsed with deionized water for 1 minute and then dried. Then, PMMA electron beam resist is spin-coated and baked on a hot plate at 180 °C. After baking, it is placed in an electron beam exposure machine. Using the global alignment mark and the local alignment mark, the precise positioning and focusing of the required exposure area are completed, and then the electron beam resist is precisely exposed. After exposure, the structure of the internal electrode is obtained. Then, it is developed at a low temperature in a developing solution (MIBK) and fixed with an isopropyl alcohol solution. After the exposure and development of the internal extension structure are completed, it is placed in a hydrofluoric acid solution, and the silicon dioxide insulating layer on the substrate surface is etched away by wet etching. Immediately after etching, it is placed in a coating machine and evacuated to a specified high vacuum, and then the ohmic contact electrodes (source and drain, taking Al as an example) are evaporated. After evaporation, the sample is placed in an acetone solution and heated to remove the excess metal part. After stripping the excess metal, it is immediately rinsed with acetone and isopropyl alcohol solutions and dried with nitrogen, and the processing of the internal source and drain is completed.

[0067] In some embodiments, the step S20 processes the external source and drain electrodes of the internal source and drain electrodes, which specifically includes: after the internal source and drain electrodes are formed, it is also necessary to connect the internal source and drain electrodes to the external source and drain electrodes to form an external electrode with a minimum width of about 2 μm and a thickness of about 100 nm (the thickness is determined by a profilometer), so as to realize the extraction of the internal source and drain electrodes. Therefore, this step needs to process the external source and drain electrodes of the formal device and the dummy. The overall processing steps of the external source and drain electrodes are basically the same as those of the internal source and drain electrodes, and the main differences are as follows: (1) Since the minimum line width of the exposure structure in this step is 2 μm, ultraviolet exposure can be selected but is not limited to for the exposure in this step; (2) When aligning the exposure in this step, only the global alignment mark needs to be used, and the local alignment mark does not need to be used; (3) After the development in this step is completed, wet etching treatment with an HF solution is not required before putting it into the coating machine; (4) When the types of ohmic contact electrodes are metals such as Al and Pd that are easily oxidized by air, before evaporating the electrodes after evacuating the coating machine to a specified high vacuum in this step, it is necessary to first perform argon plasma vertical bombardment for a certain period of time to remove the natural oxide layer formed on the surface of the internal source and drain electrodes in the third step, so as to form a direct metal contact with the subsequently grown electrodes and achieve electrical conduction.

[0068] In some embodiments, after the preparation of the internal source-drain electrodes and the external source-drain electrodes is completed, the electrical conductivity and physical connectivity of the dummy wafers are checked to ensure that there are no problems in these two aspects for the formal devices. The specific process is as Figure 10 shown.

[0069] Specifically, the check of the electrical conductivity of the dummy wafers mainly checks the structure directly connected to the internal source-drain electrodes processed simultaneously in the step S20. Since the directly connected internal source-drain electrodes have been led out through the external source-drain electrodes at this time, the corresponding resistance value can be directly measured by using a room-temperature probe station or a wire bonding method in combination with an electrical source meter. If the resistance value is greater than 1 KOhms, it is determined that there is a problem with the electrical connectivity between the internal source-drain electrodes and the external source-drain electrodes, and the processing of the formal devices needs to be terminated, the reason should be found out, and the processing should be restarted. The check of the physical connectivity of the dummy wafers mainly checks whether the internal source-drain electrodes and the external source-drain electrodes of the dummy wafers at specific positions are physically connected under an electron microscope. If it is found that all the dummy wafers are not connected, it can be determined that the alignment mark selection during the exposure process is incorrect, and the processing of the formal devices needs to be terminated, the reason should be found out, and the processing should be restarted; if it is found that all the dummy wafers are connected normally, but there is a problem with the check of the electrical conductivity of the dummy wafers, it can be determined that there is a problem with the argon plasma bombardment before the growth of the external source-drain electrodes.

[0070] In some embodiments, the novel stacked gate structure design can effectively shield various environmental noises, reduce device noise, and more easily form electrical quantum dots by restricting a two-dimensional plane to a one-dimensional nanowire through a first gate layer.

[0071] In some embodiments, after the rapid annealing is completed, an insulating dielectric layer between the multi-layer stacked electrodes needs to be grown. The insulating dielectric layer is grown by atomic layer deposition, which can ensure the denseness and conformal growth of the grown insulating dielectric layer, ensure good coverage of the dielectric layer on the steps, and reduce the leakage between the multi-layer stacked electrodes. The specific process is as follows: directly put the device precursor and the dummy wafer into the atomic layer deposition equipment cavity, and select a suitable growth temperature and final thickness to complete the atomic layer deposition growth of the first dielectric layer. Preferably, the precursor is pure water or oxygen plasma and trimethylaluminum or tetrakis(dimethylamino)hafnium.

[0072] After the preparation of the first dielectric layer is completed, the processing of the internal and external electrodes of the first gate layer and the inspection of the corresponding dummy wafers are completed according to the process of checking the electrical conductivity and physical connectivity of the internal source-drain electrodes, external source-drain electrodes, and dummy wafers. The differences in processing the internal and external electrodes of the first gate layer are as follows: (1) The internal first gate layer does not need to be wet-etched with hydrofluoric acid solution before being put into the coating equipment; (2) Argon plasma bombardment cannot be used for the evaporation of the external first gate layer because argon plasma bombardment will etch the first dielectric layer, resulting in the risk of the external first gate layer being connected to the substrate; When the metal type of the internal first gate layer electrode is an electrode material such as aluminum or palladium that is easily oxidized by air, in order to ensure the electrical connectivity between the internal first gate layer and the external first gate layer, after the external first gate layer is completed, a connection layer needs to be exposed again (the exposure area needs to be strictly controlled on the electrodes of the internal first gate layer and the external first gate layer). Argon plasma bombardment is required when evaporating the connection layer to connect the internal first gate layer and the external first gate layer while avoiding etching the first dielectric layer; (3) The metal type evaporated on the internal first gate layer can be replaced with metals such as gold and platinum other than aluminum or palladium; (4) When the metal type evaporated on the internal first gate layer is replaced with a metal other than aluminum or palladium, argon plasma bombardment may not be required before evaporating the external first gate layer.

[0073] In some embodiments, the internal gate and the external gate in the silicon-based quantum device are connected using a bridging process; the internal gate and the external gate form an overlapping region, and the exposure area of the bridging electrode is controlled within the electrode regions corresponding to the internal gate and the external gate. The bridging process reduces the damage to the dielectric layer caused by argon ion bombardment and improves the gate leakage yield.

[0074] In some embodiments, after the internal and external source-drain electrodes, the first dielectric layer, and the internal and external first gate layers are completed, leakage inspection and ohmic contact resistance inspection need to be performed on the dummy wafers specifically used for leakage inspection and ohmic contact inspection during simultaneous processing. The specific process is as follows: By means of wire bonding or a cryogenic probe station, the external electrodes of the source-drain and the external electrodes of the first gate layer are led to a measurement source meter, and at a temperature of 4 Kelvin, the leakage voltage of the first gate layer relative to the source-drain is measured, and whether the carrier channel of the field-effect transistor with the same process as the dummy wafer can be switched within this leakage voltage is measured. If the inspection result shows that the absolute value of the leakage voltage of more than 50% of the dummy wafers is less than 1V, and within the gate voltage with an absolute value less than 1V, the carrier channel of the field-effect transistor dummy wafer with the same process cannot be switched, the overall process needs to start from the first step again.

[0075] After the leakage check and ohmic contact resistance check are successfully passed, it can be shown that the basic process of this batch of processing has passed. Subsequently, the growth of the second dielectric layer, the internal electrodes of the second gate layer, the external electrodes of the second gate layer, the conductivity check and physical connectivity check of the second gate layer spacer, the leakage check of the second dielectric layer, the growth of the third dielectric layer, the internal electrodes of the third gate layer, the external electrodes of the third gate layer, the conductivity check and physical connectivity check of the third gate layer spacer, the leakage check of the third dielectric layer, etc. can be completed according to the cyclic steps of the first dielectric layer, the first gate layer, the leakage check and the ohmic contact resistance check, as Figure 1 shown in the bottom-up processing steps except for the wire bonding electrodes.

[0076] In this embodiment, the growth methods of the first dielectric layer, the second dielectric layer, the third dielectric layer and the insulating layer are all maskless full-layer coverage growth, without experiencing the exposure and stripping process, which ensures the pollution-free growth interface, reduces the electrical noise introduced by the growth of the dielectric layer and the insulating layer, and ensures the high quality of the dielectric layer.

[0077] In some embodiments, before forming several of the wire bonding electrode layers, local position etching treatment is further included for the first dielectric layer, the second dielectric layer, the third dielectric layer and the insulating layer in the area covered by the wire bonding electrode layer, so as to realize the extraction of the electrical structure while ensuring that the core structure of the device is protected by the dielectric layer and the insulating layer.

[0078] Specifically, after the core electrodes are processed, epitaxial wire bonding electrodes convenient for wire bonding need to be processed. Before processing the epitaxial wire bonding electrodes, the multi-layer alumina or hafnium oxide in the area where the epitaxial wire bonding electrodes are set as required needs to be etched first. The existence of the multi-layer alumina or hafnium oxide makes the success rate of the final wire bonding relatively low. Therefore, etching the multi-layer alumina or hafnium oxide in the wire bonding area in advance can improve the success rate of wire bonding and the yield of the device. The specific dielectric layer etching process is as Figure 11 shown: First, spin-coat an adhesion promoter to improve the adhesion between the photoresist and the substrate, rinse with water for 1 minute, then spin-coat the photoresist and bake it. After baking, use an ultraviolet lithography device to expose the area where the epitaxial wire bonding electrodes are pre-set. After exposure, develop in the developer solution and fix with deionized water. Finally, etch the sample with a diluted hydrofluoric acid solution, rinse with water after etching, and dry with nitrogen to complete the alumina etching. After etching, a profiler is needed to test the overall etching thickness to ensure that the multi-layer alumina or hafnium oxide is completely etched.

[0079] In some embodiments, after the etching of the multi-layer alumina or hafnium oxide in the preset area of the epitaxial wire-bonding electrode is completed, in order to avoid direct contact between the epitaxial wire-bonding electrode and the substrate, a new insulating layer needs to be grown for insulation treatment. The specific process is as follows: The formal device and the dummy wafer after the etching treatment are directly placed into the cavity of a plasma-enhanced chemical vapor deposition (PECVD) equipment to grow the insulating layer. Taking the insulating layer as silicon oxide as an example, the chemical reactants are SiH4 (silane) and O2 (oxygen), and the growth thickness is 200 nanometers. At the same time, the silicon oxide grown in this step can protect the core electrode completed before the etching treatment and prevent the erosion of the electrode by water and oxygen; it can also ensure that all the gates after wire bonding are still insulated from the substrate with an absolute leakage voltage of more than 3V, increasing the controllability of each gate. Up to this point, the source-drain electrodes, the first gate layer, the second gate layer, and the third gate layer processed above are all wrapped by silicon oxide and dielectric layers of different layers (such as Figure 1 shown). In order to realize the electrical connection between these electrodes and the wire-bonding electrode in the subsequent process, it is necessary to expose the local areas of these electrodes (the exposed area range shall not exceed the original electrode range). The method used is ultraviolet exposure and dry etching. The specific steps are as follows: First, spin-coat the tackifier, flush with water, then spin-coat the photoresist and bake it. Expose the local exposed areas of the corresponding electrodes of the formal device and the dummy wafer through ultraviolet lithography, and then develop and fix the image. Next, put it into the PECVD equipment for the etching of silicon oxide and multi-layer dielectric layers, and use the plasma atmosphere generated by fluorine-based gas for dry etching. After the etching is completed, put it into an acetone solution to clean the residual photoresist, and finally rinse it with acetone and isopropyl alcohol solutions and dry it. Use a profilometer to measure the etching thickness to ensure that all the silicon oxide and multi-layer dielectric layers in the exposed area are etched.

[0080] Then, after ensuring that the etching thickness is sufficient, it is necessary to process the epitaxial wire-bonding electrode to facilitate subsequent wire bonding. The epitaxial wire-bonding electrode is formed by exposure and evaporation, and the exposed area needs to include the etching area in the previous step. The specific steps are as follows: First, spin-coat the tackifier, flush with water, spin-coat the photoresist, and bake it. Expose the epitaxial wire-bonding electrode area through ultraviolet lithography. After the exposure is completed, develop, fix the image, and put it into the coating equipment. After the coating machine pumps the vacuum to the specified high vacuum and before starting the electrode growth, it is necessary to perform argon plasma vertical bombardment for a certain period of time to remove the possible natural oxide layer on the electrode surface, which can make the subsequent grown epitaxial wire-bonding electrode and the internal core electrode have better conductive connection. Next, grow an electrode with a thickness of 350 nanometers to form the epitaxial wire-bonding electrode. After the coating is completed, put it into an acetone solution for stripping, rinse it with acetone and isopropyl alcohol solutions, and dry it. Use a profilometer to determine the coating thickness.

[0081] Finally, it is necessary to test the accompanying wafers for corresponding test conductivity to determine the electrical connectivity of the bonding electrodes and each layer of external electrodes (such as source-drain external electrodes, first gate layer external electrodes, second gate layer external electrodes, third gate layer external electrodes, etc.). When it is determined that the conductivity is okay, it is also necessary to continue testing the leakage voltage between the bonding electrodes connected to the first gate layer external electrode, the second gate layer external electrode, and the third gate layer external electrode and the bonding electrode connected to the source-drain external electrode to prevent direct conduction and ensure that there is no severe lateral or vertical over-etching of all the silicon oxides and multi-layer dielectric layers in the exposed area.

[0082] In some embodiments, after the silicon-based quantum device is obtained in step S30, electrical test feedback is performed on it, including the steps of: first, testing in the 4K temperature range to preliminarily understand the performance of the quantum device and determine whether another annealing is needed to improve the ohmic contact. If the on-state resistance is too large, high-temperature annealing is performed to promote the contact between the ohmic contact metal and the germanium-silicon two-dimensional electron gas. If there is no problem, enter the mK temperature range and wait for further testing.

[0083] In summary, a silicon-based quantum device based on a Ge / GeSi planar substrate structure and a preparation method thereof provided by the present invention. The silicon-based quantum device based on the Ge / GeSi planar substrate structure includes a silicon layer, a germanium layer, a germanium-silicon strain buffer layer, a GeSi / Ge / GeSi sandwich structure layer, a source electrode and a drain electrode in contact with the GeSi / Ge / GeSi sandwich structure layer, and a first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a third dielectric layer, a third gate layer, an insulating layer, and a plurality of wire bonding electrode layers stacked on the GeSi / Ge / GeSi sandwich structure layer from bottom to top in sequence; a part of the first dielectric layer is in contact with the source electrode and the drain electrode; a part of the second dielectric layer is in contact with the first dielectric layer; a part of the third dielectric layer is in contact with the second dielectric layer; the plurality of wire bonding electrode layers are respectively connected to the source electrode, the drain electrode, the first gate layer, the second gate layer, and the third gate layer. The present invention adopts a Ge / GeSi planar substrate structure, and the bit carrier is the hole carriers at the Ge-SiGe interface. The large spin-orbit interaction naturally existing in holes enables it to utilize the electric dipole of the holes themselves. Under the drive of an alternating electric field, a traditional spin qubit with all-electric control can be realized relying on electric dipole resonance; at the same time, it also ensures that the g factor of the Zeeman splitting of different bits can be adjusted by using a local electric field, thereby adjusting the resonance frequencies of different bits, avoiding frequency crosstalk, and realizing the addressability of the bits. Moreover, the great anisotropy of the interaction between the hole carriers and the magnetic field can realize the hopping of spins between different quantum dots, thereby realizing a spin-hopping qubit. Compared with traditional spin qubits, the spin-hopping qubit manipulation only requires a low-frequency baseband signal and has lower power consumption. Based on the Ge / GeSi planar substrate structure, the present invention has invented a series of adapted methods for the arrayed and large-scale preparation of silicon-based quantum device arrays, including: taking into account both global alignment marks and local alignment marks for high-precision and arrayed and large-scale processing, directly and rapidly annealing the metal source and drain electrodes to form an electron reservoir, which not only reduces the process thermal budget but also simplifies the process steps, designing a new stacked gate structure to reduce device noise, separately processing the internal and external electrodes to take into account the electrode resolution and process yield, using a bridging connection layer process to improve the gate leakage yield, growing a full-layer coverage dielectric layer to ensure interlayer noise, an optimized wire bonding structure, local dielectric layer etching, and full-coverage growth of a thick insulating layer to ensure the packaging yield, etc., providing important technical support for silicon-based gate electrode quantum computing and quantum chips, etc.

[0084] It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above description. All such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A silicon-based quantum device based on a Ge / GeSi planar substrate structure, characterized in that It includes a silicon layer, a germanium layer, a germanium-silicon strain buffer layer, a sandwich structure layer of GeSi / Ge / GeSi, source and drain electrodes in contact with the GeSi / Ge / GeSi sandwich structure, which are stacked in sequence from bottom to top, and a first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a third dielectric layer, a third gate layer, an insulating layer and a plurality of wire bonding electrode layers, which are stacked in sequence from bottom to top on the GeSi / Ge / GeSi sandwich structure layer; Part of the first dielectric layer is in contact with the source and the drain; part of the second dielectric layer is in contact with the first dielectric layer; part of the third dielectric layer is in contact with the second dielectric layer; and the plurality of wire bonding electrode layers are respectively connected to the source, the drain, the first gate layer, the second gate layer and the third gate layer.

2. The silicon-based quantum device based on the Ge / GeSi planar substrate structure according to claim 1, wherein The thickness of the silicon layer is 200um - 800um; the thickness of the germanium layer is 0.5um - 5um; the thickness of the germanium-silicon strain buffer layer is 0.3um - 3um; the GeSi / Ge / GeSi sandwich structure layer is composed of a first GeSi layer, a first Ge layer and a second GeSi layer from bottom to top; the thickness of the first GeSi layer is 50nm - 500nm, the thickness of the first Ge layer is 10nm - 100nm, and the thickness of the second GeSi layer is 10nm - 100nm.

3. The silicon-based quantum device based on the Ge / GeSi planar substrate structure according to claim 1, wherein The thickness of the source is 20nm - 100nm; the thickness of the drain is 20nm - 100nm; the thickness of the first dielectric layer is 5nm - 20nm; the thickness of the second dielectric layer is 5nm - 20nm; the thickness of the third dielectric layer is 5nm - 20nm; the thickness of the first gate layer is 20nm - 100nm; the thickness of the second gate layer is 20nm - 100nm; the thickness of the third gate layer is 20nm - 100nm; the thickness of the insulating layer is 100nm - 3μm; the thickness of the wire bonding electrode layer is 100nm - 3μm.

4. The silicon-based quantum device based on the Ge / GeSi planar substrate structure according to claim 1, wherein The materials of the source and the drain are independently selected from one or an alloy of at least two of Al, Pd, Pt, Ti, Au; the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are independently selected from one of aluminum oxide, hafnium oxide, zirconium oxide; the materials of the first gate layer, the second gate layer and the third gate layer are independently selected from one or an alloy of at least two of Al, Pd, Pt, Ti, Au; the material of the insulating layer is selected from silicon dioxide or silicon nitride; the material of the wire bonding electrode layer is selected from one or an alloy of at least two of Al, Pd, Pt, Ti, Au.

5. A method for preparing a silicon-based quantum device based on a Ge / GeSi planar substrate structure as described in any one of claims 1-4, characterized in that, It includes steps: Providing a germanium-silicon / germanium / germanium-silicon heterostructure substrate, and performing global alignment marking and local alignment marking processing to obtain an alignment marking substrate; Performing electron beam exposure on the alignment marking substrate, then processing internal source and drain electrodes and external source and drain electrodes, and performing annealing treatment to obtain a device precursor; A first dielectric layer, a first gate layer, a second dielectric layer, a second gate layer, a third dielectric layer, a third gate layer, an insulating layer, and a plurality of wire bonding electrode layers are sequentially formed on the device precursor to obtain a silicon-based quantum device.

6. The manufacturing method of the silicon-based quantum device based on the Ge / GeSi planar substrate structure according to claim 5, characterized in that, The temperature of the annealing treatment is 250°C - 450°C, and the time of the annealing treatment is 5 s - 300 s.

7. The manufacturing method of the silicon-based quantum device based on the Ge / GeSi planar substrate structure according to claim 5, characterized in that, The interval of the global alignment marks is at least 10 mm or more, the interval of the local alignment marks is less than 1 mm, and the global alignment marks and the local alignment marks cover the entire 4-inch - 12-inch substrate; the global alignment marks and the local alignment marks are processed by ultraviolet exposure or electron beam exposure.

8. The manufacturing method of the silicon-based quantum device based on the Ge / GeSi planar substrate structure according to claim 5, characterized in that, The internal gate and the external gate in the silicon-based quantum device are connected using a bridging process; the internal gate and the external gate form an overlapping region, and the exposure region of the bridging electrode is controlled within the electrode regions corresponding to the internal gate and the external gate.

9. The manufacturing method of the silicon-based quantum device based on the Ge / GeSi planar substrate structure according to claim 5, characterized in that The growth modes of the first dielectric layer, the second dielectric layer, the third dielectric layer, and the insulating layer are all maskless full-layer coverage growth.

10. The manufacturing method of the silicon-based quantum device based on the Ge / GeSi planar substrate structure according to claim 5, characterized in that, Before forming the plurality of wire bonding electrode layers, it further includes performing a local position etching treatment on the first dielectric layer, the second dielectric layer, the third dielectric layer, and the insulating layer within the region covered by the wire bonding electrode layers.

Images