Display panel and driving method thereof

Abstract

The invention provides a display panel and a driving method thereof. The pixel circuit comprises a driving transistor (used for generating a driving current according to a data signal to drive a light-emitting element to emit light), a data writing transistor (used for transmitting the data signal), and a storage capacitor (used for storing charges of a grid electrode of the driving transistor) electrically connected to the grid electrode of the driving transistor. The driving transistor and the data write-in transistor are both metal oxide transistors, and active layers of the driving transistor and the data write-in transistor are both included in a first active layer located on a substrate. A first metal part in a first metal layer located on the side, away from the substrate, of the first active layer, a grid electrode of the data writing transistor, a first polar plate of the storage capacitor and a second metal part are sequentially arranged in the first direction. The first distance between the grid electrode of the data writing transistor and the first metal part is smaller than the second distance between the grid electrode of the data writing transistor and the second metal part, and the capacitance of the storage capacitor is improved while the risk of display abnormity is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and more particularly to a display panel and a driving method thereof. Background Art

[0002] AMOLED (Active-Matrix Organic Light-Emitting Diode) display panels have advantages such as fast response speed, high contrast ratio, and wide viewing angle.

[0003] Among them, the data writing transistors in the conventional pixel circuits of AMOLED display panels are generally LTPS (Low Temperature Poly-Silicon) transistors, resulting in relatively large leakage current of the data writing transistors, making it easy for the data voltages of other rows to be written into the pixel circuits of this row, and thus the risk of abnormal display is relatively high. Summary of the Invention

[0004] The present invention provides a display panel and a driving method thereof to reduce the risk of abnormal display of AMOLED display panels.

[0005] An embodiment of the present invention provides a display panel, including a plurality of sub-pixels, each sub-pixel including a light-emitting element and a pixel circuit electrically connected thereto. The pixel circuit includes:

[0006] A driving transistor for generating a driving current according to a data signal to drive the light-emitting element to emit light, the driving transistor being a metal oxide transistor;

[0007] A data writing transistor electrically connected to the driving transistor for transmitting the data signal, the data writing transistor being a metal oxide transistor;

[0008] A storage capacitor electrically connected to the gate of the driving transistor for storing the charge of the gate of the driving transistor;

[0009] The display panel includes:

[0010] A substrate;

[0011] A first active layer located on the substrate, including the active layer of the driving transistor and the active layer of the data writing transistor;

[0012] A first metal layer located on the side of the first active layer away from the substrate. The first metal layer includes a first metal part and a second metal part, and the first electrode plate of the storage capacitor and the gate of the data writing transistor are located between the first metal part and the second metal part;

[0013] Among them, in the first metal layer, the first metal part, the gate of the data writing transistor, the first electrode plate of the storage capacitor, and the second metal part are arranged in sequence along the first direction. In the first direction, the first distance between the gate of the data writing transistor and the first metal part is smaller than the second distance between the gate of the data writing transistor and the second metal part.

[0014] An embodiment of the present invention further provides a driving method for a display panel, which is applied to the above display panel. The driving method of the display panel includes:

[0015] The data writing transistor is turned on, so that the data signal is transmitted through the data writing transistor to one of the source and drain of the driving transistor.

[0016] The data writing transistor is turned off, and the compensation transistor electrically connected between the other of the source and drain of the driving transistor and the gate of the driving transistor is turned on, so that the signal of one of the source and drain of the driving transistor is transmitted through the driving transistor and the compensation transistor to the gate of the driving transistor until the driving transistor is turned off, so that the storage capacitor stores the charge of the gate of the driving transistor.

[0017] An embodiment of the present invention further provides a driving method for a display panel. The display panel includes a plurality of sub-pixels, and the sub-pixels include a light-emitting element and a pixel circuit electrically connected. The pixel circuit includes:

[0018] A driving transistor, configured to generate a driving current according to a data signal to drive the light-emitting element to emit light. The driving transistor is a metal oxide transistor.

[0019] A data writing transistor, electrically connected to the driving transistor, for transmitting the data signal. The data writing transistor is a metal oxide transistor.

[0020] A storage capacitor, electrically connected to the gate of the driving transistor, for storing the charge of the gate of the driving transistor.

[0021] A first switching transistor, electrically connected between a first voltage line and the other of the source and drain of the driving transistor.

[0022] A second switching transistor, electrically connected between one of the source and drain of the driving transistor and the light-emitting element.

[0023] The driving method of the display panel includes:

[0024] The data writing transistor is turned on, so that the data signal is transmitted through the data writing transistor to one of the source and drain of the driving transistor;

[0025] The data writing transistor is turned off, and the compensation transistor electrically connected between the other of the source and drain of the driving transistor and the gate of the driving transistor is turned on, so that the signal of one of the source and drain of the driving transistor is transmitted through the driving transistor and the compensation transistor to the gate of the driving transistor until the driving transistor is turned off, so that the storage capacitor stores the charge of the gate of the driving transistor;

[0026] The first switching transistor and the second switching transistor are turned on simultaneously, so that the driving transistor generates a driving current according to the data signal to drive the light emitting element to emit light.

[0027] The present invention provides a display panel and a driving method thereof. The pixel circuit therein includes: a driving transistor for generating a driving current according to a data signal to drive the light emitting element to emit light; a data writing transistor electrically connected to the driving transistor for transmitting the data signal. Both the driving transistor and the data writing transistor are metal oxide transistors, and the active layers of both are included in a first active layer located on a substrate; a storage capacitor electrically connected to the gate of the driving transistor for storing the charge of the gate of the driving transistor. Wherein, a first metal part in a first metal layer on a side of the first active layer away from the substrate, the gate of the data writing transistor, the first electrode plate of the storage capacitor, and a second metal part are arranged in sequence along a first direction. By setting a first distance between the gate of the data writing transistor and the first metal part to be smaller than a second distance between the gate of the data writing transistor and the second metal part in the first direction, the capacitance of the storage capacitor is increased while reducing the risk of display abnormality. Description of the Drawings

[0028] Figure 1 It is a schematic diagram of the architecture of the display panel and the display device to which the display panel belongs provided by the embodiment of the present invention.

[0029] Figure 2 It is the circuit of the pixel circuit provided by the embodiment of the present invention.

[0030] Figure 3 It is a cross-sectional view of the display panel provided by the embodiment of the present invention.

[0031] Figures 4 to 6 , Figures 8 to 9 , Figure 11 , Figure 13 , Figures 15 to 16It is a layout diagram of a single layer of the middle partial film layer of the display panel provided by an embodiment of the present invention.

[0032] Figure 7 , Figure 10 , Figure 12 , Figure 14 , Figure 17 It is a layout diagram of a multi-layer stack of the middle partial film layer of the display panel provided by an embodiment of the present invention.

[0033] Figure 18 , Figure 20 It is a flowchart of the driving method of the display panel provided by an embodiment of the present invention.

[0034] Figure 19 Waveform diagrams of some signals in the pixel circuit provided by an embodiment of the present invention.

[0035] Figures 21 to 25 Respectively Figure 7 , Figure 10 , Figure 12 , Figure 14 , Figure 17 Corresponding grayscale diagrams. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0037] In the description of the present invention, terms such as "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In this article, the source and drain of the transistor are not distinguished, and the two can be exchanged. In addition, it should be noted that the accompanying drawings only provide structures that are relatively closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the invention points clear at a glance, rather than indicating that the actual device is the same as the attached Figure 1 model, and it is not a limitation of the actual device.

[0038] References to "embodiments" in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the invention. The phrase does not necessarily refer to the same embodiment at every occurrence in the specification, nor are they independent or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0039] The present invention provides a display panel, which includes, but is not limited to, the following embodiments and combinations of the following embodiments.

[0040] In some embodiments, in combination with Figures 1 to 4 As shown, the display panel 100 includes a plurality of sub-pixels Pi. The sub-pixels Pi include a light-emitting element Di and a pixel circuit electrically connected thereto. The pixel circuit includes: a driving transistor T1 for generating a driving current according to a data signal data to drive the light-emitting element Di to emit light. The driving transistor T1 is a metal oxide transistor; a data writing transistor T2 electrically connected to the driving transistor T1 for transmitting the data signal data. The data writing transistor T2 is a metal oxide transistor; a storage capacitor Cst electrically connected to the gate of the driving transistor T1 (for example, its top gate GE35, electrically connected to the first node Q) for storing the charge of the gate of the driving transistor T1; wherein, the first metal layer GE3 in the display panel 100 includes a first metal portion GE31, a second metal portion GE32, and a first electrode plate GE33 of the storage capacitor Cst (electrically connected to the first node Q) located between the first metal portion GE31 and the second metal portion GE32, and the gate of the data writing transistor T2 (for example, the top gate GE34 of the data writing transistor T2); wherein, as Figure 4 As shown, in the first metal layer GE3, the first metal portion GE31, the gate of the data writing transistor T2 (for example, its top gate GE34), the first electrode plate GE33 of the storage capacitor Cst, and the second metal portion GE32 are arranged in sequence along the first direction D1. In the first direction D1, the first distance d1 between the gate of the data writing transistor T2 (for example, its top gate GE34) and the first metal portion GE31 is less than the second distance d2 between the gate of the data writing transistor T2 (for example, its top gate GE34) and the second metal portion GE32.

[0041] Among them, the display panel 100 can be a self-luminous display panel, that is, the display panel 100 performs screen display by the self-luminescence of the light-emitting element Di in the sub-pixel Pi.

[0042] Specifically, as Figure 1As shown, the display panel 100 can be included in the display device 200. The display device 200 can include a timing controller 201 and a source driver 202. The gate driver 203 can be independent of the display panel 100 or formed on the substrate of the display panel 100 to form a gate driving circuit (illustrated by the latter case here). Each gate driving unit in the gate driver 203 is electrically connected between the timing controller 201 and the corresponding plurality of sub-pixels Pi, and is used to output a gate signal gate transmitted to the corresponding plurality of sub-pixels Pi; the source driver 202 is electrically connected between the timing controller 201 and the corresponding plurality of sub-pixels P, and is used to output the above data signal data transmitted to the corresponding plurality of sub-pixels P.

[0043] For ease of description, here, it is taken as an example that a plurality of sub-pixels Pi are arranged in an array of N rows and M columns (both N and M are positive integers).

[0044] The gate driving circuit at least includes N levels of gate driving units respectively connected to N gate lines (GL1 to GLN). The N levels of gate driving units respectively generate N levels of gate signals gate. The N gate pulses in the N levels of gate signals gate respectively used to turn on the transistors in the N rows of sub-pixels Pi can be arranged in sequence on the time axis to sequentially turn on the N rows of sub-pixels Pi. Each of the M data signals data includes N data voltages corresponding to the N sub-pixels Pi in the same column. When each row of sub-pixels Pi is turned on, the M data lines (DL1 to DLM) respectively receive the M data voltages of the M sub-pixels Pi in this row, so that the plurality of data voltages act on the plurality of sub-pixels Pi in this row to realize the light emission of the plurality of light-emitting elements Di in the M sub-pixels Pi in this row. By analogy, the light emission of the light-emitting elements Di in all rows can be sequentially controlled to present a complete picture.

[0045] It can be understood that in this embodiment, the data writing transistor T2 for transmitting the data signal data is a metal oxide transistor, so that the data writing transistor T2 has a lower leakage rate when it is turned off. Therefore, when the corresponding data line (one of DL1 to DLM) transmits the data voltages of other rows, the data writing transistor T2 in this row can be turned off better, reducing the risk that the data voltages of other rows are written into at least one of the gate, source, and drain of the driving transistor T1 through the data writing transistor T2 in this row, thereby reducing the risk of display abnormality.

[0046] However, as Figure 2 shown, since the data writing transistor T2 is a metal oxide transistor, the gate of the data writing transistor T2 (such as its top gate GE34) will be arranged on the same layer as the first electrode plate GE33 of the storage capacitor Cst (both belong to the first metal layer GE3), causing a certain compression of the size of the first electrode plate GE33.

[0047] Specifically, the display panel 100 includes: a substrate 301; a first active layer Ox located on the substrate 301, including an active layer Ox1 of the driving transistor T1 and an active layer Ox2 of the data writing transistor T2; a first metal layer GE3 located on a side of the first active layer Ox away from the substrate 301, the first metal layer GE3 including a first metal portion GE31 and a second metal portion GE32, a first electrode plate GE33 of the storage capacitor Cst, and a gate of the data writing transistor T2 (e.g., its top gate GE34) located between the first metal portion GE31 and the second metal portion GE32.

[0048] It can be understood that in this embodiment, based on the fact that in the first metal layer GE3, the first metal portion GE31, the gate of the data writing transistor T2 (e.g., its top gate GE34), the first electrode plate GE33 of the storage capacitor Cst, and the second metal portion GE32 are arranged in sequence along the first direction D1. In the first direction D1, a first distance d1 between the gate of the data writing transistor T2 (e.g., its top gate GE34) and the first metal portion GE31 is set to be less than a second distance d2 between the gate of the data writing transistor T2 (e.g., its top gate GE34) and the second metal portion GE32, so that the first distance d1 between the top gate GE34 of the data writing transistor T2 and the first metal portion GE31 is set to be smaller, that is, the top gate GE34 of the data writing transistor T2 is arranged closer to the first metal portion GE31. Correspondingly, the reserved second distance d2 between the top gate GE34 of the data writing transistor T2 and the second metal portion GE32 can be larger. Furthermore, the size of the first electrode plate GE33 in the first direction D1 can be set to be larger, which is beneficial to forming a first electrode plate GE33 with a larger size, thus being beneficial to forming a storage capacitor Cst with a larger capacitance value, thereby improving the stability of charge storage in the gate of the driving transistor T1, and thus improving the flash screen phenomenon under variable refresh rates and the brightness unevenness phenomenon caused by different attenuation degrees of signal lines at different positions in the plane.

[0049] Among them, in combination with Figures 1 to 4 As shown, the first distance d1 is greater than or equal to 1.4 micrometers and less than or equal to 3.4 micrometers. Among them, the value range of the first distance d1 in this embodiment can be understood as the distance range between two metal lines that an exposure machine can distinguish when manufacturing the first metal layer GE3, that is, in this embodiment, the first distance d1 is set small enough, so that while satisfying the normal exposure of the exposure machine to form multiple metal lines, the second distance d2 can be large enough.

[0050] In some embodiments, in combination with Figures 2 to 4As shown, the first electrode GE33 is electrically connected to the gate of the driving transistor T1 (for example, its top gate GE35), and the first metal layer GE3 also includes the gate of the driving transistor T1 (for example, its top gate GE35) arranged in contact with the first electrode GE33; wherein, in the first metal layer GE3, the gate of the driving transistor T1 (for example, its top gate GE35) and the first electrode GE33 are arranged along a second direction D2, and the second direction D2 intersects with the first direction D1 (here it is only indicated that the two are perpendicular).

[0051] It can be understood that the first electrode plate GE33 of the storage capacitor Cst in this embodiment is electrically connected to the top gate GE35 of the driving transistor T1 to store the charge of the gate of the driving transistor T1. Figure 4 As shown, the first electrode GE33 and the top gate GE35 of the driving transistor T1 can both be included in the first metal layer GE3, and the two are arranged in contact to achieve electrical connection between the two. At the same time, in order to avoid squeezing the size of the first electrode GE33 in the first direction D1 like the top gate GE34 of the data writing transistor T2, the top gate GE35 of the driving transistor T1 and the first electrode GE33 can be arranged along the second direction D2. It can be considered that the side of the first electrode GE33 close to the top gate GE35 of the driving transistor T1 originally has a blank area considering the interference with other metal film layers. Therefore, setting the top gate GE35 of the driving transistor T1 in this area can also utilize this blank area while avoiding compressing the size of the first electrode GE33 in the first direction D1.

[0052] In some embodiments, combined Figures 2 to 7 As shown, the driving transistor T1 is a metal oxide transistor, and the gate of the driving transistor T1 includes a top gate GE35 and a bottom gate GE21 of the driving transistor T1. The top gate GE35 of the driving transistor T1 is located on a side of the active layer Ox1 of the driving transistor T1 away from the substrate 301, and the bottom gate GE21 of the driving transistor T1 is located on a side of the active layer Ox1 of the driving transistor T1 close to the substrate 301; wherein, the first metal layer GE3 includes the top gate GE35 of the driving transistor T1; the display panel 100 further includes: a second metal layer GE2, located on a side of the first active layer Ox close to the substrate 301, the second metal layer GE2 includes the bottom gate GE21 of the driving transistor T1 and a first portion GE22 of the second plate of the storage capacitor Cst, and the first portion GE22 of the second plate is arranged opposite to the first plate GE33.

[0053] It can be understood that the driving transistor T1 in this embodiment is also a metal-oxide transistor, which not only makes the driving transistor T1 have a small leakage rate when it is turned off, so that the potential change of its gate due to leakage is small, reducing the risk of screen flicker, but also the driving transistor T1 has a small hysteresis effect on the threshold voltage, improving the image retention phenomenon. Moreover, the working partial voltage of the driving transistor T1 is small, reducing the power consumption of the display panel 100.

[0054] Furthermore, the driving transistor T1 in this embodiment has a top-bottom double-gate structure. Through the collaborative regulation of the double gates, the carrier mobility and current driving ability can be enhanced; at the same time, the double-gate structure can reduce the interface scattering to improve the electron mobility. At the same time, by independently adjusting the top-gate and bottom-gate voltages, the threshold voltage can be flexibly adjusted to compensate for the threshold voltage drift caused by process deviation or environmental changes (such as temperature fluctuations); at the same time, the double gates can more thoroughly deplete the residual carriers in the channel in the off state, reducing the leakage current; at the same time, the double-gate structure enhances the electrostatic control of the gate over the channel, making the subthreshold swing close to the theoretical limit and achieving a sharper switching; at the same time, if there are defects (such as oxygen vacancies) in the dielectric layer on one side of the top gate or bottom gate, the other gate can compensate for the electric field non-uniformity, improving the device yield; at the same time, the double-gate structure can balance the mechanical stress and reduce the performance degradation during bending; at the same time, although metal oxides are sensitive to light, the double-gate structure can reduce the light-induced threshold voltage shift through the electric field shielding effect.

[0055] Furthermore, as shown in Figures 2 to 8 one of the source SD11 (electrically connected to the third node A) and the drain SD12 (electrically connected to the fourth node B) of the driving transistor T1 (here, the drain SD12 is taken as an example for illustration) is electrically connected to the bottom gate GE21 of the driving transistor T1. Among them, the drain SD12 of the driving transistor T1 is directly connected to its bottom gate GE21, and the change in the voltage of its drain SD12 can be synchronously transmitted to the voltage of its bottom gate GE21, making the voltage difference between the two approach zero, and the parasitic capacitance between the two is shielded and cannot affect the voltage of its bottom gate GE21 through capacitive coupling, reducing the switching delay.

[0056] Specifically, based on the fact that the gate of the driving transistor T1 in this embodiment includes its top gate GE35 and bottom gate GE21, the top gate GE35 of the driving transistor T1 is set to be included in the first metal layer GE3, that is, the top gate GE35 of the driving transistor T1 is in contact with the first electrode plate GE33 for electrical connection, and the second metal layer GE2 containing the bottom gate GE21 of the driving transistor T1 is also set to include the first part GE22 of the second electrode plate for forming the storage capacitor Cst (electrically connected to the second node C), so as to realize the reuse of the second metal layer GE2.

[0057] In some embodiments, in combination with Figures 2 to 10 As shown, the second part GE41 of the second electrode plate is located on a side of the first electrode plate GE33 away from the first part GE22 of the second electrode plate and is disposed opposite to the first electrode plate GE33. The second part GE41 of the second electrode plate is electrically connected to the first part GE22 of the second electrode plate through a via hole.

[0058] It should be noted that, in combination with Figure 3 and Figure 5 as shown, Figure 3 it can be understood as Figure 5 a cross-sectional view of the bottom gate GE21 of the driving transistor T1 in along the first direction D1. Therefore, Figure 3 the first part GE22 of the second electrode plate is not shown in . It can be considered that Figure 3 in , the first part GE22 of the second electrode plate is behind the bottom gate GE21 of the driving transistor T1.

[0059] It can be understood that the second electrode plate in this embodiment further includes a second part GE41 (such as included in the fourth metal layer GE4) that is also disposed opposite to the first electrode plate GE33. The second part GE41 and the first part GE22 of the second electrode plate are electrically connected, so that the facing area between the second electrode plate and the first electrode plate GE33 is increased, thereby increasing the capacitance of the storage capacitor Cst. Among them, the position of the via hole required for electrically connecting the second part GE41 of the second electrode plate and the first part GE22 of the second electrode plate in this embodiment is not limited.

[0060] In some embodiments, in combination with Figures 2 to 12 , the gate of the data writing transistor T2 includes the top gate GE34 and the bottom gate GE11 of the data writing transistor T2. The top gate GE34 of the data writing transistor T2 is located on a side of the active layer Ox2 of the data writing transistor T2 away from the substrate 301, and the bottom gate GE11 of the data writing transistor T2 is located on a side of the active layer Ox2 of the data writing transistor T2 close to the substrate 301. Among them, the first metal layer GE3 includes the top gate GE34 of the data writing transistor T2, and the bottom gate GE11 of the data writing transistor T2 is located on a side of the bottom gate GE21 of the driving transistor T1 close to the substrate 301.

[0061] Among them, the advantages of the data writing transistor T2 having a top-bottom double-gate structure can refer to the related description above about the driving transistor T1 having a top-bottom double-gate structure.

[0062] Among them, in combination with Figure 3 and Figure 6As shown, the active layer Ox2 of the data writing transistor T2 and the active layer Ox1 of the driving transistor T1 can be provided in the same layer (both belong to the first active layer Ox) because both materials include metal oxide.

[0063] Among them, combined Figure 3 and Figure 8 As shown, the source SD13 (electrically connected to the fifth node D) and the drain SD14 (electrically connected to the fourth node B) of the data writing transistor T2 and the source SD11 (electrically connected to the third node A) and the drain SD12 (electrically connected to the fourth node B) of the driving transistor T1 are all made of metal materials. In order to reduce the number of film layers, the two can also be set in the same layer (both belong to the first source and drain layer SD1).

[0064] Among them, in order to reduce the interference with the potential of the bottom gate GE21 of the driving transistor T1, in this embodiment, the bottom gate GE11 of the data write transistor T2 is set on the side of the bottom gate GE21 of the driving transistor T1 close to the substrate 301, that is, a separate metal layer is used to make the bottom gate GE11 of the data write transistor T2; further, considering that the driving transistor T1 requires a sufficiently large driving force compared with the data write transistor T2, the material of the bottom gate GE11 of the data write transistor T2 and the metal layer (third metal layer GE1) to which it belongs can include but is not limited to Mo, and the material of the bottom gate GE21 of the driving transistor T1 and the second metal layer GE2 to which it belongs can include but is not limited to Ti.

[0065] In some embodiments, combined Figures 2 to 14 As shown, the pixel circuit further includes: a first switch transistor T5, electrically connected between the first voltage line VDD and the other of the source SD11 (electrically connected to the third node A) and the drain SD12 (electrically connected to the fourth node B) of the driving transistor T1 (the source SD11 is used as an example); the first switch transistor T5 is electrically connected between the source SD11 (electrically connected to the third node A) and the drain SD12 (electrically connected to the fourth node B) of the driving transistor T1 (the drain SD12 is used as an example) and the light-emitting element Di; wherein the first switch transistor T5 and the second switch transistor T6 are both low-temperature polysilicon transistors; the display panel 100 further includes: a third metal layer GE1, located on a side of the second metal layer GE2 close to the substrate 301, the third metal layer GE1 including the bottom gate GE11 of the data write transistor T2, the gate GE12 of the first switch transistor T5, and the gate GE13 of the second switch transistor T6.

[0066] Among them, such as Figure 2As shown, by controlling the conduction or non-conduction of both the first switching transistor T5 and the second switching transistor T6, a current path is formed or not formed between the first voltage line VDD and the second voltage line VSS (electrically connected to the light-emitting element Di for example), thereby providing a path for the formation of the driving current.

[0067] It can be understood that the gate GE12 of the first switching transistor T5 and the gate GE13 of the second switching transistor T6 in this embodiment can be arranged on the same layer as the bottom gate GE11 of the data writing transistor T2 (both belong to the third metal layer GE1), thereby avoiding the need to set a separate film layer for manufacturing the gate GE12 of the first switching transistor T5 and the gate GE13 of the second switching transistor T6, which is beneficial to the development of the thin and light of the display panel 100.

[0068] Among them, since both the first switching transistor T5 and the second switching transistor T6 are low-temperature polysilicon transistors, the constituent materials of their active layers can be the same. Therefore, as Figure 12 shown, the active layer Po1 of the first switching transistor T5 and the active layer Po2 of the second switching transistor T6 can be arranged on the same layer (both belong to the second active layer Po) to reduce the number of film layers.

[0069] Similarly, in combination with Figure 3 、 Figure 8 and Figure 14 shown, the source SD19 (electrically connected to the seventh node F) and the drain SD110 (electrically connected to the third node A) of the first switching transistor T5, the source SD111 (electrically connected to the fourth node B) and the drain SD112 (electrically connected to the second node C) of the second switching transistor T6 can also be arranged on the same layer as the source SD13 (electrically connected to the fifth node D) and the drain SD14 (electrically connected to the fourth node B) of the data writing transistor T2 (both belong to the first source-drain layer SD1).

[0070] Furthermore, in combination with Figure 2 、 Figure 11 、 Figure 13 and Figure 14 shown, the gate GE12 of the first switching transistor T5 includes two first sub-gates GE121 that are on the same layer and spaced apart, and the gate GE13 of the second switching transistor T6 includes two second sub-gates GE131 that are on the same layer and spaced apart. Correspondingly, the active layer Po1 of the first switching transistor T5 can include two first sub-channel portions Po11 respectively corresponding to the two first sub-gates GE121, and the active layer Po2 of the second switching transistor T6 can include two second sub-channel portions Po21 respectively corresponding to the two second sub-gates GE131. Each first sub-channel portion Po11 is disposed opposite to the corresponding first sub-gate GE121, and each first sub-channel portion Po11 is disposed opposite to the corresponding first sub-gate GE121.

[0071] Among them, the first switching transistor T5 and the second switching transistor T6 are in a series dual-gate structure, which can also reduce the leakage rate when they are in the cut-off state.

[0072] In some embodiments, in combination with Figures 2 to 12 As shown, the pixel circuit further includes: a reset transistor T4 electrically connected to the light-emitting element Di; a compensation transistor T3 electrically connected between the source SD11 (electrically connected to the third node A) and the drain SD12 (electrically connected to the fourth node B) of the driving transistor T1 (here, the source SD11 is taken as an example for illustration) and the gate of the driving transistor T1 (for example, its top gate GE35, electrically connected to the first node Q); among them, both the reset transistor T4 and the compensation transistor T3 are metal oxide transistors; among them, the first metal part GE31 is the gate of the reset transistor T4, and the second metal part GE32 is the gate of the compensation transistor T3.

[0073] Among them, as Figure 2 shown, the second node C can be reset by controlling whether the reset transistor T4 is turned on or off, and the first node Q can be reset by controlling whether the compensation transistor T3 is turned on or off.

[0074] Among them, the reset transistor T4 and the compensation transistor T3 can also be metal oxide transistors.

[0075] Specifically, in combination with Figures 2 to 12 shown, the gate of the reset transistor T4 includes the top gate (i.e., the first metal part GE31) and the bottom gate GE14 of the reset transistor, and the compensation transistor T3 includes the top gate (i.e., the second metal part GE32) and the bottom gate GE15 of the compensation transistor T3; among them, the top gate (i.e., the second metal part GE32) of the reset transistor T4, the top gate (i.e., the second metal part GE32) of the compensation transistor T3, and the top gate GE34 of the data writing transistor T2 are arranged on the same layer, the bottom gate GE14 of the reset transistor T4, the bottom gate GE15 of the compensation transistor T3, and the bottom gate GE11 of the data writing transistor T2 are arranged on the same layer, and the active layer Ox3 of the reset transistor T4, the active layer Ox4 of the compensation transistor T3, and the active layer Ox2 of the data writing transistor T2 are arranged on the same layer.

[0076] It can be understood that in combination with Figure 3 , Figure 4 and Figure 12As shown, in order to reduce the number of film layers, the top gate of the reset transistor T4 (i.e., the first metal portion GE31), the top gate of the compensation transistor T3 (i.e., the second metal portion GE32) and the top gate GE34 of the data write transistor T2 can be set in the same layer (all belong to the first metal layer GE3); similarly, combined with Figure 3 、 Figure 6 and Figure 12 As shown, the active layer Ox3 of the reset transistor T4, the active layer Ox4 of the compensation transistor T3 and the active layer Ox2 of the data writing transistor T2 can be set in the same layer (all belong to the first active layer Ox); similarly, combined with Figure 3 、 Figure 11 and Figure 12 As shown, the bottom gate GE14 of the reset transistor T4, the bottom gate GE15 of the compensation transistor T3 and the bottom gate GE11 of the data writing transistor T2 can be arranged in the same layer (all belong to the third metal layer GE1); similarly, combined with Figure 3 、 Figure 8 and Figure 12 As shown, the source SD15 (electrically connected to the sixth node E) and the drain SD16 (electrically connected to the second node C) of the reset transistor T4, the source SD17 (electrically connected to the third node A) and the drain SD18 (electrically connected to the first node Q) of the compensation transistor T3 can also be set in the same layer as the source SD13 (electrically connected to the fifth node D) and the drain SD14 (electrically connected to the fourth node B) of the data write transistor T2 (all belonging to the first source and drain layer SD1).

[0077] In some embodiments, combined Figures 2 to 14 As shown, one of the source SD15 and the drain SD16 of the reset transistor T4 (the source SD15 is used as an example here) is electrically connected to the reset line VI, and the other of the source SD15 and the drain SD16 of the reset transistor T4 (the drain SD16 is used as an example here) is electrically connected to the light-emitting element Di; wherein, the first metal layer GE3 also includes the reset line VI located on the side of the first metal part GE31 away from the first electrode GE33.

[0078] It is understood that, since one of the source SD15 and the drain SD16 of the reset transistor T4 in the multiple sub-pixels Pi is electrically connected to the reset line VI to apply the reset signal, a reset line VI can be provided for each row of multiple sub-pixels Pi to provide a reset signal to the multiple sub-pixels Pi in the same row. This embodiment uses the reset line VI located near the upper edge of the first metal layer GE3 as an example, but this is not limiting.

[0079] Further, combined Figure 2 、 Figure 3 、 Figure 5 、Figure 8 , Figure 9 , Figure 10 , Figure 15 and Figure 16 As shown in Figure 8 , Figure 9 , Figure 10 , Figure 15 , and Figure 16 , the display panel 100 may further include a second source-drain layer SD2 located above and insulated from the first source-drain layer SD1, and a third source-drain layer SD3 located above and insulated from the second source-drain layer SD2. A first overlapping portion SD21 may be provided in the portion of the second source-drain layer SD2 corresponding to the first electrode plate GE33, a second overlapping portion SD31 may be provided in the portion of the third source-drain layer SD3 corresponding to the first electrode plate GE33, and a third overlapping portion SD113 may be provided in the portion of the first source-drain layer SD1 corresponding to the first electrode plate GE33. Among them, the second part GE41 of the second electrode plate is electrically connected to the second overlapping portion SD31 through the third overlapping portion, the first overlapping portion SD21 (and the vias between every two adjacent ones), correspondingly, the first part GE22 of the second electrode plate may also be electrically connected to the second overlapping portion SD31 through the corresponding multiple overlapping portions and the vias between every two adjacent ones, so as to realize the electrical connection of the second part GE41 and the first part GE22 of the second electrode plate.

[0080] It should be noted that Figures 11 to 16 schematically shows the first sub-pixel Pi1, the second sub-pixel Pi2, and the third sub-pixel Pi3 that are continuously arranged in the same row and have different colors. Among them, for the convenience of circuit layout, the first sub-pixel Pi1 and the second sub-pixel Pi2 may be axially symmetrically arranged, and the second sub-pixel Pi2 and the third sub-pixel Pi3 may be axially symmetrically arranged.

[0081] Furthermore, as shown in combination with Figure 2 , Figure 3 , Figure 15 , and Figure 16 , the third source-drain layer SD3 may include a plurality of data lines DATA (such as including DL1 to DLM) corresponding to multiple columns of sub-pixels Pi. The data lines DATA may be electrically connected to the corresponding data writing transistors T2 through the fifth node D. Further still, a plurality of corresponding data connection lines may be provided for the plurality of data lines DATA near at least one of the left edge and the right edge of the display area, so as to reduce the size of the fan-shaped area in the second direction D2. Each data connection line may include a first data connection line FIAA_L arranged in parallel with the corresponding data line DATA (for example, extending along the first direction D1), and a corresponding second data connection line FIAA_H (for example, extending along the second direction D2) electrically connecting the two. Among them, the first data connection line FIAA_L may belong to the third source-drain layer SD3, and the second data connection line FIAA_H may belong to the second source-drain layer SD2.

[0082] As shown in Figure 17 ​​​​​​​​As shown, it is a layout diagram after the above-mentioned multiple film layers are stacked in sequence from bottom to top as the second active layer Po, the third metal layer GE1, the second metal layer GE2, the first active layer Ox, the first metal layer GE3, the fourth metal layer GE4, the first source-drain layer SD1, the second source-drain layer SD2, and the third source-drain layer SD3.

[0083] Further, as Figure 3 shown, the substrate 301 may include a first substrate 3011, a second substrate 3012, and a protective layer 3013 located therebetween. The materials of the first substrate 3011 and the second substrate 3012 may be, but are not limited to, polyimide. The protective layer 3013 is used to prevent water and oxygen from permeating, improve mechanical strength, or achieve electrical isolation. A first buffer layer 302 and a second buffer layer 303 may be sequentially disposed on the substrate 301. The first buffer layer 302 may be a composite buffer layer, which may include inorganic, organic hybrid materials, and nanocomposite materials. The second buffer layer 303 may include organic materials or inorganic materials.

[0084] A first insulating layer 304 is provided between the second active layer Po and the third metal layer GE1, a second insulating layer 305 is provided between the third metal layer GE1 and the second metal layer GE2, a first interlayer dielectric layer 306 is provided between the second metal layer GE2 and the first active layer Ox, a third insulating layer 307 is provided between the first active layer Ox and the first metal layer GE3, a fourth insulating layer 308 is provided between the first metal layer GE3 and the fourth metal layer GE4, a second interlayer dielectric layer 309 is provided between the fourth metal layer GE4 and the first source-drain layer SD1, a first planarization layer 310 is provided between the first source-drain layer SD1 and the second source-drain layer SD2, a second planarization layer 311 is provided between the second source-drain layer SD2 and the third source-drain layer SD3, and a third planarization layer 312 may be provided on the third source-drain layer SD3.

[0085] Among them, the above-mentioned multiple insulating layers are used to isolate the corresponding gates and corresponding channels to form field effect control, and their dielectric constants may be greater than 7; the above-mentioned multiple interlayer dielectric layers are used to isolate different metal layers, prevent short circuits, and planarize the surface, and their dielectric constants may be less than 4; the above-mentioned multiple planarization layers can achieve mechanical planarization, and their materials may be, but are not limited to, organic polymers.

[0086] It should be noted that the above-mentioned Figure 7 , Figure 10 , Figure 12 , Figure 14 , Figure 17 are color drawings of the layout of the multi-layer stack of some film layers in the display panel provided by the embodiments of the present invention. Structures with the same color in each drawing belong to the same film layer, and the name of the film layer may refer to the name represented by the corresponding label in the parentheses.

[0087] To better illustrate the light-emitting principle of the above-mentioned display panel 100 and the sub-pixels Pi therein, the present invention also provides a driving method for the display panel, which is applied to the display panel 100 described in any of the above, as Figure 18 shown, including but not limited to the following steps:

[0088] S1, the data writing transistor is turned on, so that the data signal is transmitted to one of the source and drain of the driving transistor through the data writing transistor;

[0089] S2, the data writing transistor is turned off, and the compensation transistor electrically connected between the other of the source and drain of the driving transistor and the gate of the driving transistor is turned on, so that the signal of one of the source and drain of the driving transistor is transmitted to the gate of the driving transistor through the driving transistor and the compensation transistor until the driving transistor is turned off, so that the storage capacitor stores the charge of the gate of the driving transistor.

[0090] Wherein, after the above step S2, it may include but not limited to the following steps:

[0091] S3, the first switching transistor and the second switching transistor are turned on simultaneously, so that the driving transistor generates a driving current according to the data signal to drive the light-emitting element to emit light.

[0092] Based on the above step S3, before the above step S1, it may include but not limited to the following steps:

[0093] S01, the compensation transistor and the first switching transistor are both turned on, so that the first voltage signal transmitted by the first voltage line is transmitted to the gate of the driving transistor through the first switching transistor and the compensation transistor;

[0094] S02, the compensation transistor is turned on, the first switching transistor is turned off, and the storage capacitor maintains the potential of the other of the source and drain of the driving transistor and the potential of the gate of the driving transistor to be the first voltage signal.

[0095] Wherein, before the above step S1, it may include but not limited to the following steps:

[0096] S03, the reset transistor is turned on, so that the reset signal transmitted by the reset line is transmitted to the light-emitting element Di through the reset transistor.

[0097] Specifically, to better illustrate the multiple steps in the above driving method of the display panel, in combination with Figure 2 and Figure 19 shown, Figure 2The sub-pixel Pi shown may include, but is not limited to, the following working phases:

[0098] In phase t1, the first gate signal em1 transmitted by the first gate line EM1 is at the corresponding low potential, the second gate signal em2 transmitted by the second gate line EM2 is at the corresponding high potential, and the third gate signal nscan1 transmitted by the third gate line NSCAN1 is at the corresponding high potential. Therefore, the first switching transistor T5, the reset transistor T4, and the compensation transistor T3 are turned on. The first voltage signal vdd transmitted by the first voltage line VDD is transmitted to the first node Q through the first switching transistor T5 and the compensation transistor T3 to reset it. Moreover, the reset signal vi transmitted by the reset line VI is transmitted to the third node C through the reset transistor T4 to reset it;

[0099] That is to say, phase t1 includes the above-mentioned step S01 and step S03. In this phase, the potential of the first node Q (the gate of the driving transistor) is reset by the first voltage signal vdd, and the potential of the third node C (the anode of the light-emitting element Di) is reset by the reset signal vi;

[0100] In phase t2, compared with phase t1, the first gate signal em1 becomes the corresponding high potential, and the first switching transistor T5 is turned off. The storage capacitor Cst maintains the signals of both the first node Q and the third node A as the first voltage signal vdd;

[0101] That is to say, phase t2 includes the above-mentioned step S02. In this phase, the compensation transistor T3 is turned on, so that a current path is formed between the first node Q and the third node A, and the potentials of both the first node Q and the third node A are maintained by the storage capacitor Cst;

[0102] In phase t3, the second gate signal em2 is at the corresponding high potential, the third gate signal nscan1 is at the corresponding high potential, and the fourth gate signal nscan2 transmitted by the fourth gate line NSCAN2 is at the corresponding high potential. The reset transistor T4, the compensation transistor T3, and the data writing transistor T2 are turned on. The potential of the third node C is maintained at the potential of the reset signal, and the data signal data is transmitted to the gate of the driving transistor T1 (i.e., the first node Q) through the data writing transistor T2, the driving transistor T1, and the compensation transistor T3;

[0103] That is to say, phase t3 includes the above-mentioned step S1. In this phase, the data signal data is transmitted to the gate of the driving transistor T1 (i.e., the first node Q) through the compensation transistor T3 and the data writing transistor T2;

[0104] In stage t4, compared with stage t3, the fourth gate signal nscan2 becomes the corresponding low potential, the data writing transistor T2 is turned off, but the compensation transistor T3 is turned on. The data signal data written at the fourth node B before continues to be transmitted to the gate of the driving transistor T1 (i.e., the first node Q) until the signal at the first node Q is data + Vth and the driving transistor T1 is turned off. Vth is the threshold voltage of the driving transistor T1. At this time, the storage capacitor Cst maintains the signal at the first node Q as data + Vth;

[0105] That is to say, stage t3 includes the above-mentioned step S2. In this stage, through the compensation transistor T3, the data signal data is transmitted to the first plate of the storage capacitor Cst (i.e., the first node Q), and the discharge of the storage capacitor Cst is continuously carried out to improve the compensation effect of the threshold voltage of the driving transistor T1;

[0106] In stage t5, the first gate signal em1 is the corresponding low potential, the fourth gate signal nscan2 is the corresponding low potential, both the first switching transistor T5 and the second switching transistor T6 are turned on, and a current path is formed between the first voltage line VDD and the second voltage line VSS, so that the driving transistor T1 generates a driving current flowing through this current path. The magnitude of the driving current is k×(data + Vth - vi - Vth)2 = k×(data - vi)2;

[0107] That is to say, stage t4 includes the above-mentioned step S3. In this stage, a current path for the driving current is formed through the first switching transistor T5 and the second switching transistor T6.

[0108] Combined with the above analysis, in the embodiment of the present invention, since the gates of the first switching transistor T5 and the second switching transistor T6 are respectively affected by different types of first gate signal em1 and second gate signal em2, and the pulses of the two gate signals are different, even if the starting moments of their pulses are different to reset the potential of the third node C (the anode of the light-emitting element Di) in stage t1, the ending moments of their pulses can be the same so that at the end of stage t4, it can immediately enter stage t5 to form a current path for the driving current, avoiding the delay in forming the current path for the driving current due to the different ending moments of their pulses, and improving the brightness of the light-emitting element Di or prolonging the lifespan of the light-emitting element Di.

[0109] As can be analyzed from the above, stage t4 must be after the third gate signal nscan1 changes from the corresponding high potential to the corresponding low potential. In the embodiments of the present invention, since the third gate signal nscan1 is at the corresponding high potential from stage t1 to stage t4, the end time of the third gate signal nscan1 can be earlier, avoiding the situation where the third gate signal nscan1 is at the corresponding low potential between stage t1 and stage t4, which may cause a delay in the end time of the third gate signal nscan1, thereby achieving an earlier start time of stage t5 and improving the brightness of the light-emitting element Di or extending the lifespan of the light-emitting element Di.

[0110] The present invention also provides a driving method for a display panel, which is applied to the display panel 100. As Figure 2 shown, the display panel 100 includes a plurality of sub-pixels Pi. The sub-pixel Pi includes a light-emitting element Di and a pixel circuit connected electrically. The pixel circuit includes: a driving transistor T1 for generating a driving current according to a data signal data to drive the light-emitting element Di to emit light. The driving transistor T1 is a metal-oxide transistor; a data writing transistor T2 electrically connected to the driving transistor T1 for transmitting the data signal data. The data writing transistor T2 is a metal-oxide transistor; a storage capacitor Cst electrically connected to the gate of the driving transistor T1 for storing the charge of the gate of the driving transistor T1.

[0111] As Figure 20 shown, the driving method of the display panel includes but is not limited to the above steps S1 to S3.

[0112] On the one hand, in the above step S2, through the compensation transistor T3, the data signal data is transmitted to the first electrode plate (i.e., the first node Q) of the storage capacitor Cst, and the storage capacitor Cst is continuously discharged to improve the compensation effect of the threshold voltage of the driving transistor T1.

[0113] On the other hand, in the above step S3, since the gates of the first switching transistor T5 and the second switching transistor T6 are respectively affected by different types of first gate signal em1 and second gate signal em2, and the pulses of the two gate signals are different, even if the start times of their pulses are different to reset the potential of the third node C (the anode of the light-emitting element Di) at stage t1, the end times of their pulses can be the same so that at the end time of stage t4, it can immediately enter stage t5 to form a current path for the driving current, avoiding a delay in forming the current path for the driving current due to different end times of their pulses, and improving the brightness of the light-emitting element Di or extending the lifespan of the light-emitting element Di.

[0114] Further, for the specific details of the above driving method of the display panel, reference can also be made to the relevant discussion on the driving method of the display panel in the foregoing text.

[0115] In this article, specific examples are used to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A display panel, characterized in that, It includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting element and a pixel circuit which are electrically connected. The pixel circuit includes: A driving transistor for generating a driving current according to a data signal to drive the light-emitting element to emit light. The driving transistor is a metal-oxide transistor; A data writing transistor electrically connected to the driving transistor for transmitting the data signal. The data writing transistor is a metal-oxide transistor; A storage capacitor electrically connected to the gate of the driving transistor for storing the charge of the gate of the driving transistor; The display panel includes: A substrate; A first active layer located on the substrate, including the active layer of the driving transistor and the active layer of the data writing transistor; A first metal layer located on the side of the first active layer away from the substrate. The first metal layer includes a first metal portion and a second metal portion. The first electrode plate of the storage capacitor and the gate of the data writing transistor are located between the first metal portion and the second metal portion; Wherein, in the first metal layer, the first metal portion, the gate of the data writing transistor, the first electrode plate of the storage capacitor, and the second metal portion are arranged in sequence along a first direction. In the first direction, a first distance between the gate of the data writing transistor and the first metal portion is less than a second distance between the gate of the data writing transistor and the second metal portion.

2. The display panel according to claim 1, wherein The first electrode plate of the storage capacitor is electrically connected to the gate of the driving transistor. The first metal layer further includes the gate of the driving transistor which is in contact with the first electrode plate; Wherein, in the first metal layer, the gate of the driving transistor and the first electrode plate are arranged along a second direction, and the second direction intersects with the first direction.

3. The display panel according to claim 2, characterized in that, The gate of the driving transistor includes the top gate and the bottom gate of the driving transistor. The top gate of the driving transistor is located on the side of the active layer of the driving transistor away from the substrate, and the bottom gate of the driving transistor is located on the side of the active layer of the driving transistor close to the substrate; Wherein, the first metal layer includes the top gate of the driving transistor; The display panel further includes: A second metal layer located on the side of the first active layer close to the substrate. The second metal layer includes the bottom gate of the driving transistor and a first part of the second electrode plate of the storage capacitor. The first part of the second electrode plate is arranged opposite to the first electrode plate.

4. The display panel according to claim 3, characterized in that, A second part of the second electrode plate is located on the side away from the first part of the second electrode plate and is arranged opposite to the first electrode plate. The second part of the second electrode plate is electrically connected to the first part of the second electrode plate through a via hole.

5. The display panel according to claim 3, characterized in that, One of the source and the drain of the driving transistor is electrically connected to the bottom gate of the driving transistor.

6. The display panel according to claim 3, wherein The gate of the data writing transistor includes the top gate and the bottom gate of the data writing transistor. The top gate of the data writing transistor is located on the side of the active layer of the data writing transistor away from the substrate, and the bottom gate of the data writing transistor is located on the side of the active layer of the data writing transistor close to the substrate; Among them, the first metal layer includes the top gate of the data writing transistor, and the bottom gate of the data writing transistor is located on the side of the bottom gate of the driving transistor close to the substrate.

7. The display panel according to claim 6, wherein, The pixel circuit further includes: A first switching transistor, electrically connected between a first voltage line and the other of the source and drain of the driving transistor; A second switching transistor, electrically connected between one of the source and drain of the driving transistor and the light-emitting element; Among them, both the first switching transistor and the second switching transistor are low-temperature polysilicon transistors; The display panel further includes: A third metal layer, located on the side of the second metal layer close to the substrate, and the third metal layer includes the bottom gate of the data writing transistor, the gate of the first switching transistor, and the gate of the second switching transistor.

8. The display panel according to claim 7, wherein The gate of the first switching transistor includes two first sub-gates that are in the same layer and spaced apart, and the gate of the second switching transistor includes two second sub-gates that are in the same layer and spaced apart.

9. The display panel according to any one of claims 1 to 8, characterized in that, The pixel circuit further includes: A reset transistor, electrically connected to the light-emitting element, and the first metal part is the gate of the reset transistor; A compensation transistor, electrically connected between the other of the source and drain of the driving transistor and the gate of the driving transistor. Both the reset transistor and the compensation transistor are metal oxide transistors, and the second metal part is the gate of the compensation transistor.

10. The display panel according to claim 9, characterized in that, One of the source and drain of the reset transistor is electrically connected to a reset line, and the other of the source and drain of the reset transistor is electrically connected to the light-emitting element; Among them, the first metal layer further includes the reset line located on the side of the first metal part away from the first electrode plate.

11. The display panel according to claim 9, wherein, The gate of the reset transistor includes the top gate and the bottom gate of the reset transistor, and the compensation transistor includes the top gate and the bottom gate of the compensation transistor; Among them, the top gates of the reset transistor, the compensation transistor, and the data writing transistor are arranged in the same layer, the bottom gates of the reset transistor, the compensation transistor, and the data writing transistor are arranged in the same layer, and the active layers of the reset transistor, the compensation transistor, and the data writing transistor are arranged in the same layer.

12. The display panel according to any one of claims 1 to 8, characterized in that, The first pitch is greater than or equal to 1.4 micrometers and less than or equal to 3.4 micrometers.

13. A driving method for a display panel, characterized in that The display panel includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting element and a pixel circuit connected electrically, and the pixel circuit includes: A driving transistor, configured to generate a driving current according to a data signal to drive the light-emitting element to emit light, and the driving transistor is a metal oxide transistor; A data writing transistor, electrically connected to the driving transistor, and configured to transmit the data signal, and the data writing transistor is a metal oxide transistor; A storage capacitor, electrically connected to the gate of the driving transistor, and configured to store the charge of the gate of the driving transistor; The display panel includes: A substrate; A first active layer, located on the substrate, and includes the active layer of the driving transistor and the active layer of the data writing transistor; The first metal layer is located on a side of the first active layer away from the substrate. The first metal layer includes a first metal portion and a second metal portion. A first electrode plate of the storage capacitor and a gate of the data writing transistor are located between the first metal portion and the second metal portion; Wherein, in the first metal layer, the first metal portion, the gate of the data writing transistor, the first electrode plate of the storage capacitor, and the second metal portion are arranged in sequence along a first direction. In the first direction, a first distance between the gate of the data writing transistor and the first metal portion is less than a second distance between the gate of the data writing transistor and the second metal portion; The driving method of the display panel includes: The data writing transistor is turned on, so that the data signal is transmitted through the data writing transistor to one of the source and the drain of the driving transistor; The data writing transistor is turned off, and a compensation transistor electrically connected between the other of the source and the drain of the driving transistor and the gate of the driving transistor is turned on, so that a signal of one of the source and the drain of the driving transistor is transmitted to the gate of the driving transistor through the driving transistor and the compensation transistor until the driving transistor is turned off, so that the storage capacitor stores the charge of the gate of the driving transistor.

14. The driving method of the display panel according to claim 13, wherein, The pixel circuit further includes: A first switching transistor electrically connected between a first voltage line and the other of the source and the drain of the driving transistor; A second switching transistor electrically connected between one of the source and the drain of the driving transistor and the light-emitting element; Wherein, after the step that the signal of one of the source and the drain of the driving transistor is transmitted to the gate of the driving transistor through the driving transistor and the compensation transistor until the driving transistor is turned off, it includes: The first switching transistor and the second switching transistor are turned on simultaneously, so that the driving transistor generates a driving current according to the data signal to drive the light-emitting element to emit light.

15. The driving method of the display panel according to claim 14, wherein Before the step that the data writing transistor is turned on, it includes: The compensation transistor and the first switching transistor are both turned on, so that a first voltage signal transmitted by the first voltage line is transmitted to the gate of the driving transistor through the first switching transistor and the compensation transistor; The compensation transistor is turned on, the first switching transistor is turned off, and the storage capacitor maintains the potential of the other of the source and the drain of the driving transistor and the potential of the gate of the driving transistor to be the first voltage signal.

16. The driving method of the display panel according to any one of claims 13 to 15, characterized in that, The pixel circuit further includes: A reset transistor electrically connected between the light-emitting element and a reset line; Wherein, before the step that the data writing transistor is turned on, it includes: The reset transistor is turned on, so that a reset signal transmitted by the reset line is transmitted to the light-emitting element through the reset transistor.

17. A driving method for a display panel, characterized in that, The display panel includes a plurality of sub-pixels. The sub-pixels include a light-emitting element and a pixel circuit that are electrically connected. The pixel circuit includes: A driving transistor, configured to generate a driving current according to a data signal to drive the light-emitting element to emit light, wherein the driving transistor is a metal-oxide transistor; A data writing transistor, electrically connected to the driving transistor, configured to transmit the data signal, wherein the data writing transistor is a metal-oxide transistor; A storage capacitor, electrically connected to the gate of the driving transistor, configured to store the charge of the gate of the driving transistor; A first switching transistor, electrically connected between a first voltage line and the other of the source and drain of the driving transistor; A second switching transistor, electrically connected between one of the source and drain of the driving transistor and the light-emitting element; The driving method of the display panel includes: Turning on the data writing transistor to enable the data signal to be transmitted through the data writing transistor to one of the source and drain of the driving transistor; Turning off the data writing transistor, turning on a compensation transistor electrically connected between the other of the source and drain of the driving transistor and the gate of the driving transistor, so that the signal of one of the source and drain of the driving transistor is transmitted to the gate of the driving transistor through the driving transistor and the compensation transistor until the driving transistor is turned off, so that the storage capacitor stores the charge of the gate of the driving transistor; Turning on the first switching transistor and the second switching transistor simultaneously, so that the driving transistor generates a driving current according to the data signal to drive the light-emitting element to emit light.

18. The driving method of the display panel according to claim 17, wherein Before the step of turning on the data writing transistor, it includes: Turning on both the compensation transistor and the first switching transistor, so that the first voltage signal transmitted by the first voltage line is transmitted to the gate of the driving transistor through the first switching transistor and the compensation transistor; Turning on the compensation transistor, turning off the first switching transistor, and maintaining the potential of the other of the source and drain of the driving transistor and the potential of the gate of the driving transistor as the first voltage signal by the storage capacitor.

19. The driving method of the display panel according to claim 17 or 18, characterized in that, The pixel circuit further includes: A reset transistor, electrically connected between the light-emitting element and a reset line; Wherein, before the step of turning on the data writing transistor, it includes: Turning on the reset transistor, so that the reset signal transmitted by the reset line is transmitted to the light-emitting element through the reset transistor.

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