Clock signal driver and memory system including same

Abstract

A clock signal driver and a memory system including the same are provided. The clock signal driver includes a driver circuit configured to generate an output clock signal in response to a combination of an input clock signal, a delay control signal, and a supply voltage. The driver circuit includes a main driver circuit configured to: generate an output clock signal in response to an input clock signal; and a replica circuit having a structure equivalent to that of the main driver circuit; the replica circuit is configured to generate a replica clock signal equivalent to the output clock signal in response to the input clock signal. A delay control circuit is also provided, and the delay control circuit is responsive to the replica clock signal. The delay control circuit is configured to generate a delay control signal for correcting a delay change in the output clock signal, the delay change in the output clock signal being caused by a change in a voltage level of the supply voltage.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0015822, filed on Feb. 1, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0002] Example embodiments generally relate to an integrated circuit memory device, and more particularly, to a clock signal driver and a memory system including the clock signal driver. Background Art

[0003] Memory devices, such as synchronous dynamic random access memory (DRAM) devices, generally operate in synchronization with an external clock signal. As the operating speed of the memory device increases, the memory device may include a clock signal driver for controlling the timing of the clock signal to obtain a timing budget.

[0004] Recently, as the size of metal-oxide-semiconductor (MOS) transistors included in the clock signal driver has decreased, the delay of the clock signal has become more sensitive to changes in the power supply voltage and temperature. Accordingly, research is being conducted to more accurately control the timing of the clock signals so that they are less susceptible to changes in the power supply voltage and temperature. Summary of the Invention

[0005] At least one example embodiment of the present disclosure provides a clock signal driver and a memory system including the clock signal driver, the clock signal driver being capable of generating an output clock signal having a substantially constant output timing that is less susceptible to fluctuations in the power supply voltage.

[0006] According to an embodiment, a clock signal driver includes: a driver circuit configured to generate an output clock signal in response to a combination of an input clock signal, a delay control signal, and a power supply voltage. The driver circuit includes: a main driver circuit configured to generate an output clock signal in response to the input clock signal; and a replica circuit having a structure equivalent to that of the main driver circuit, the replica circuit being configured to generate a replica clock signal equivalent to the output clock signal in response to the input clock signal. A delay control circuit is also provided, and the delay control circuit responds to the replica clock signal. The delay control circuit is configured to generate a delay control signal for correcting a delay change of the output clock signal, the delay change of the output clock signal being caused by a change in the voltage level of the power supply voltage.

[0007] According to another embodiment, a memory system is provided, which includes a clock signal driver, a plurality of memory devices, and a host device. The clock signal driver is configured to generate an output clock signal based on an input clock signal. The plurality of memory devices are configured to receive the output clock signal from the clock signal driver and operate based on the output clock signal. The host device is configured to supply the input clock signal to the clock signal driver and control the clock signal driver and the plurality of memory devices. Advantageously, the clock signal driver includes a driver circuit and a delay control circuit. The driver circuit is configured to operate based on a power supply voltage and generate the output clock signal based on the input clock signal and a delay control signal. The driver circuit includes a main driver circuit and a matching replication circuit. The main driver circuit is configured to generate the output clock signal, and the replication circuit having the same structure as the main driver circuit is configured to generate a replication clock signal identical to the output clock signal. The delay control circuit is configured to generate a delay control signal for correcting a delay change of the output clock signal based on the replication clock signal. The delay change of the output clock signal occurs according to a change in the voltage level of the power supply voltage.

[0008] According to a further embodiment, a clock signal driver includes a driver circuit and a delay control circuit. The driver circuit is configured to operate based on a power supply voltage and generate an output clock signal based on an input clock signal and a delay control signal. The driver circuit includes a control circuit, a main driver operation circuit, a main driver circuit, and a replication circuit. The control circuit is configured to receive the input clock signal and generate a first clock signal by adjusting the phase or delay of the input clock signal. The main driver operation circuit is configured to generate a second clock signal based on the first clock signal and the delay control signal. The main driver circuit is configured to generate the output clock signal based on the second clock signal. The replication circuit has the same structure as the main driver circuit and is configured to generate a replication clock signal identical to the output clock signal. The delay control circuit is configured to operate based on a first voltage that is different from the power supply voltage and has a constant voltage level. The delay control circuit includes a flip-flop and a logic calculation circuit. The flip-flop is configured to output a result signal based on the replication clock signal and a unit pulse signal. The logic calculation circuit is configured to generate the unit pulse signal and generate a delay control signal for correcting a delay change of the output clock signal based on the result signal. The delay change of the output clock signal occurs according to a change in the voltage level of the power supply voltage.

[0009] Advantageously, in the clock signal driver according to the exemplary embodiment, the delay according to the change in the voltage level of the power supply voltage of the output clock signal can be controlled by a delay control circuit that is not affected by the power supply voltage. Accordingly, during the wafer test process, the delay control circuit can measure the change in the delay of the replicated clock signal that occurs according to the change in the voltage level of the power supply voltage, and can reflect (or compensate for) the change in the delay of the driver circuit. When the clock signal driver operates after the wafer test process, the driver circuit can output the output clock signal such that the delay of the output clock signal generated for each voltage level of the power supply voltage is constant. Accordingly, regardless of the voltage level of the power supply voltage, the output clock signal can have a constant output timing, and the operational stability of the clock signal driver can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram showing a clock signal driver according to an exemplary embodiment.

[0012] Figure 2 and Figure 3 is a timing diagram for describing the clock signal driver according to an exemplary embodiment.

[0013] Figure 4 is a detailed electrical schematic diagram showing an example of a main driver circuit and a replication circuit included in a clock signal driver according to an exemplary embodiment.

[0014] Figure 5 is an electrical schematic diagram of a delay control circuit included in a clock signal driver according to an exemplary embodiment.

[0015] Figure 6 、 Figure 7 、 Figure 8 and Figure 9 are timing diagrams for describing the operation of a delay control circuit included in a clock signal driver according to an exemplary embodiment.

[0016] Figure 10 is a block diagram showing an example of a clock signal driver according to an exemplary embodiment.

[0017] Figure 11 is a detailed electrical schematic diagram showing an example of a main driver operation circuit included in a clock signal driver according to an exemplary embodiment.

[0018] Figure 12 and Figure 13It is a diagram for describing a main driver operation circuit included in a clock signal driver according to an exemplary embodiment.

[0019] Figure 14 and Figure 15 It is a block diagram showing an example of a clock signal driver according to an exemplary embodiment.

[0020] Figure 16 and Figure 17 It is a block diagram showing an example of a control circuit included in a clock signal driver according to an exemplary embodiment.

[0021] Figure 18 It is a block diagram showing a memory system according to an exemplary embodiment.

[0022] Figure 19 and Figure 20 It is a diagram for describing a clock signal driver according to an exemplary embodiment.

[0023] Figure 21 It is a diagram showing a dual in-line memory module (DIMM) implementation of a clock signal driver according to an exemplary embodiment.

[0024] Figure 22 It is a block diagram showing an example of a data chip included in a memory module included in a memory system according to an exemplary embodiment.

[0025] Figure 23 It is an example of an electrical die sorting (EDS) process that can be performed when manufacturing a non-volatile memory device. Detailed Description

[0026] Various exemplary embodiments will be described more fully with reference to the accompanying drawings that illustrate embodiments. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, like reference numerals refer to like elements.

[0027] Figure 1 It is a block diagram showing a clock signal driver according to an exemplary embodiment. Referring to Figure 1 , the clock signal driver 10 includes a delay control circuit 100 and a driver circuit 200. The driver circuit 200 includes a main driver circuit (MD) 210 and a replication circuit (RC) 220.

[0028] The driver circuit 200 operates based on the power supply voltage VDD. For example, the driver circuit 200 can generate an output clock signal QCK having at least one characteristic based on the magnitude of the power supply voltage VDD. For example, the delay or phase of the output clock signal QCK can change according to a change in the voltage level of the power supply voltage VDD. For example, the delay or phase of the output clock signal QCK can represent the time difference between the time point when the input clock signal DCK is applied and the time point when the output clock signal QCK is output.

[0029] For example, the delay control circuit 100 can operate based on a first voltage VDDIO that "is different from the power supply voltage VDD and has a constant voltage level with substantially no fluctuations". For example, the delay control circuit 100 can be powered by the first voltage VDDIO. For example, when operating at a constant voltage level, the delay control circuit 100 can independently measure and correct the delay of the output clock signal QCK without being affected by a change in the power supply voltage VDD.

[0030] For example, a change in the voltage level of the power supply voltage VDD can occur due to an automatic test equipment (ATE) that is used to test the clock signal driver 10 during a wafer test (e.g., wafer-level test) process of the clock signal driver 10. For example, the voltage level of the power supply voltage VDD can be changed to multiple operating voltage levels of multiple memory devices connected to the clock signal driver 10.

[0031] The driver circuit 200 generates the output clock signal QCK based on the input clock signal DCK and the delay control signal DCS. The operation of generating the output clock signal QCK will be described with reference to Figures 6 to 9 the description of the operation of generating the output clock signal QCK.

[0032] The main driver circuit 210 generates the output clock signal QCK. For example, the main driver circuit 210 can generate the output clock signal QCK in response to the input clock signal DCK. For example, the main driver circuit 210 can perform an amplification operation to generate the output clock signal QCK, and the output clock signal QCK is provided to multiple memory devices connected to the clock signal driver 10. For example, the main driver circuit 210 can be referred to as an output driver or a transmitter.

[0033] The replica circuit 220 has the same structure as the main driver circuit 210 (e.g., has an equivalent structure to the main driver circuit 210), and generates a replica clock signal RCK that is substantially the same (e.g., equivalent) to the output clock signal QCK (e.g., in response to the input clock signal DCK). For example, when the replica circuit 220 has the same structure as the main driver circuit 210, the replica circuit 220 can generate a replica clock signal RCK having the same phase and frequency as the output clock signal QCK. For example, the delay between the input clock signal DCK and the output clock signal QCK and the delay between the input clock signal DCK and the replica clock signal RCK can be the same. As will be more fully explained below, reference will be made to Figure 4 describe the configurations of the main driver circuit 210 and the replica circuit 220.

[0034] The delay control circuit 100 generates a delay control signal DCS for correcting a delay change of the output clock signal QCK based on the replica clock signal RCK, and the delay change of the output clock signal QCK occurs according to a change in the voltage level of the power supply voltage VDD. Reference will be made to Figure 5 describe the configuration of the delay control circuit 100.

[0035] For ease of illustration only, Figure 1 the input clock signal DCK, the output clock signal QCK, and the replica clock signal RCK are shown as single-ended signals; however, the example embodiments are not limited thereto. Hereinafter, the example embodiments will be described based on an example in which the input clock signal DCK, the output clock signal QCK, and the replica clock signal RCK are differential signals.

[0036] In the clock signal driver 10 according to the example embodiments, the delay control circuit 100 can operate based on the first voltage VDDIO without being affected by the power supply voltage VDD, so that the delay control circuit 100 can control the delay change of the output clock signal QCK that occurs according to the change in the voltage level of the power supply voltage VDD. During the wafer test process, the delay control circuit 100 can measure the delay change of the replica clock signal RCK that occurs according to the change in the voltage level of the power supply voltage VDD, and can reflect (or compensate for) the delay change in the driver circuit 200. When the clock signal driver 10 operates after the wafer test process, the driver circuit 200 can output the output clock signal QCK such that the delay of the output clock signal QCK generated for each voltage level of the power supply voltage VDD is constant. Therefore, regardless of the voltage level of the power supply voltage VDD, the output clock signal QCK can have a constant output timing, and the operation stability of the clock signal driver 10 can be improved.

[0037] Figure 2 and Figure 3is a diagram for describing a clock signal driver according to an exemplary embodiment. Refer to Figure 2 , the first time interval CLK_DLY can represent the time difference from when the input clock signals DCK_t and DCK_c are applied to the clock signal driver to when the output clock signals QCK_t and QCK_c are output from the clock signal driver. For example, the time points at which the output clock signals QCK_t and QCK_c are output from the clock signal driver can be substantially the same as the time points at which the output clock signals QCK_t and QCK_c transition to a logic high level or a logic low level.

[0038] For example, the host device can apply the input clock signals DCK_t and DCK_c to the clock signal driver and can request the output of the output clock signals QCK_t and QCK_c after the first time interval CLK_DLY (e.g., a predetermined delay), regardless of the change in the voltage level of the power supply voltage. The clock signal driver according to the exemplary embodiment can perform an operation of delay control in which, regardless of the change in the voltage level of the power supply voltage, the output clock signals QCK_t and QCK_c are output after the first time interval CLK_DLY has elapsed from the time point when the input clock signals DCK_t and DCK_c are applied to the clock signal driver.

[0039] Refer to Figure 3 , an example of the output clock signal QCK_t corresponding to different voltage levels of the power supply voltage VDD is shown. For example, the multiple voltage levels of the power supply voltage VDD can be or can include a first voltage level (e.g., about 0.7V), a second voltage level (e.g., about 0.8V), a third voltage level (e.g., about 0.9V), a fourth voltage level (e.g., about 1.0V), a fifth voltage level (e.g., about 1.1V), a sixth voltage level (e.g., about 1.2V), a seventh voltage level (e.g., about 1.3V), an eighth voltage level (e.g., about 1.4V), and a ninth voltage level (e.g., about 1.5V).

[0040] For example, the operation of delay control can be performed such that the output clock signal QCK_t is output after the first time interval CLK_DLY has elapsed from the first time point T1, where the first time point T1 indicates the time point at which the input clock signal is input (or applied) to the clock signal driver.

[0041] Hereinafter, exemplary embodiments will be described based on the second time point T2 being the time point after the first time interval CLK_DLY has elapsed from the first time point T1. For example, the second time point T2 can represent the time point at which the output clock signal QCK_t is output when the power supply voltage VDD has the first voltage level (about 0.7V). For example, as will be referred to Figures 6 to 9As described, the clock signal driver can set a delay control signal such that when the power supply voltage VDD has a second voltage level to a ninth voltage level (about 0.8V, ……, 1.5V), the output clock signal QCK_t is output at a second time point T2. As a result, regardless of the change in the voltage level of the power supply voltage VDD, an output clock signal QCK_t with a constant output timing can be generated by delaying the output clock signal QCK_t based on the delay control signal.

[0042] For example, as the voltage level of the power supply voltage VDD becomes lower, the delay (or time interval) from the first time point T1 to the time point when the output clock signal QCK_t is output can become longer (or larger). For example, the delay dl2 of the output clock signal QCK_t when the power supply voltage VDD has an eighth voltage level (about 1.4V) can be longer than the delay dl1 of the output clock signal QCK_t when the power supply voltage VDD has a ninth voltage level (about 1.5V). Therefore, as will be described with reference to Figures 6 to 9 As described, the clock signal driver according to the exemplary embodiment can set the delay control signal such that as the voltage level of the power supply voltage VDD becomes higher, the amount of delay added to correct the output clock signal QCK_t becomes larger.

[0043] However, the exemplary embodiment is not limited thereto. For example, as will be described with reference to Figure 19 As described, the delay control signal can be set such that when the power supply voltage VDD has a fifth voltage level (about 1.1V), the time point is selected as a reference time point, the phase of the output clock signal QCK_t is delayed when the power supply voltage VDD has a sixth voltage level to a ninth voltage level (about 1.2V, ……, 1.5V), and the phase of the output clock signal QCK_t is advanced when the power supply voltage VDD has a first voltage level to a fourth voltage level (about 0.7V, ……, 1.0V).

[0044] Figure 4 is a circuit diagram showing an example of a main driver circuit and a replica circuit included in a clock signal driver according to an exemplary embodiment. Referring to Figure 4 , the main driver circuit 210_1 and the replica circuit 220_1 can represent Figure 1 an exemplary embodiment of the main driver circuit 210 and the replica circuit 220 in

[0045] As shown, the main driver circuit 210_1 may include a pull-up driver circuit 210_11, a pull-down driver circuit 210_12, a pull-up resistor RU1, and a pull-down resistor RD1. The pull-up driver circuit 210_11 may include a plurality of p-type metal oxide semiconductor (PMOS) transistors connected in parallel. The pull-down driver circuit 210_12 may include a plurality of n-type metal oxide semiconductor (NMOS) transistors connected in parallel. The pull-up resistor RU1 may be connected between the drains of the plurality of PMOS transistors and the output node OND1. The pull-down resistor RD1 may be connected between the drains of the plurality of NMOS transistors and the output node OND1. The main driver circuit 210_1 may receive the second clock signals CK2_t and CK2_c, and may generate output clock signals QCK_t and QCK_c by amplifying the second clock signals CK2_t and CK2_c through the pull-up driver circuit 210_11 and the pull-down driver circuit 210_12. For example, the second clock signals CK2_t and CK2_c may be referred to as the main driver input clock signals.

[0046] For example, the replication circuit 220_1 may be the same as the main driver circuit 210_1. For example, the replication circuit 220_1 may include a pull-up driver circuit 220_11, a pull-down driver circuit 220_12, a pull-up resistor RU2, and a pull-down resistor RD2. The pull-up driver circuit 220_11 may include a plurality of PMOS transistors connected in parallel. The pull-down driver circuit 220_12 may include a plurality of NMOS transistors connected in parallel. The pull-up resistor RU2 may be connected between the drains of the plurality of PMOS transistors and the output node OND2. The pull-down resistor RD2 may be connected between the drains of the plurality of NMOS transistors and the output node OND2. The replication circuit 220_1 may receive the second clock signals CK2_t and CK2_c, and may generate replication clock signals RCK_t, RCK_c by amplifying the second clock signals CK2_t and CK2_c via the pull-up driver circuit 220_11 and the pull-down driver circuit 220_12. Accordingly, the timing information of the replication clock signals RCK_t and RCK_c and the timing information of the output clock signals QCK_t and QCK_c may be the same. For example, the timing information may include the delay with respect to the input clock signals.

[0047] Figure 5 is a diagram showing an example of a delay control circuit included in a clock signal driver according to an exemplary embodiment. Referring to Figure 5 , the delay control circuit 100_1 may represent Figure 1Example embodiments of the delay control circuit 100 therein. The delay control circuit 100_1 may include a flip-flop 110 and a logic calculation circuit 120. For example, the flip-flop 110 may include a D flip-flop, but the example embodiments are not limited thereto. For example, the logic calculation circuit 120 may include a circuit configuration for generating a delay control signal DCS. For example, the logic calculation circuit 120 may further include a circuit configuration for performing an operation of changing Figure 1 the device setting value of the driver circuit 200 therein.

[0048] As shown, the flip-flop 110 may receive a replicated clock signal RCK_t. For example, not only a clock signal driver operating with a single-ended signal, but also a clock signal driver operating with a differential signal may not use a clock signal (e.g., RCK_c) complementary to the replicated clock signal RCK_t in the delay control circuit 100_1. And, the logic calculation circuit 120 may generate a unit pulse signal D_PULSE (e.g., as feedback to the flip-flop 110). In some embodiments, the unit pulse signal D_PULSE may have an active time interval corresponding to 1 unit interval (UI) of data that is input to and output from a memory device operating based on an output clock signal.

[0049] The flip-flop 110 may output a result signal RS based on the replicated clock signal RCK_t and the unit pulse signal D_PULSE. As shown, the flip-flop 110 may include a clock terminal CLK that receives the replicated clock signal RCK_t, an input terminal D that receives the unit pulse signal D_PULSE, and an output terminal Q that outputs the result signal RS. In some embodiments, the logic calculation circuit 120 may generate a delay control signal DCS based on the result signal RS. A detailed operation of generating the delay control signal DCS will be described with reference to Figures 6 to 9 FIGs.

[0050] Figure 6 、 Figure 7 、 Figure 8 and Figure 9 are diagrams for describing the operation of the delay control circuit included in a clock signal driver according to an example embodiment. Referring to Figures 5 to 9, showing an operation of generating a result signal RS based on a replicated clock signal RCK_t, and showing an operation of generating an output clock signal QCK_t' corrected by "a unit pulse signal D_PULSE generated based on the result signal RS". For example, the power supply voltage VDD may have a plurality of voltage levels, and the plurality of voltage levels may be or may include a first voltage level (about 0.7V), a second voltage level (about 0.8V), a third voltage level (about 0.9V), a fourth voltage level (about 1.0V), a fifth voltage level (about 1.1V), a sixth voltage level (about 1.2V), a seventh voltage level (about 1.3V), an eighth voltage level (about 1.4V), and a ninth voltage level (about 1.5V).

[0051] As Figure 6 shown, the delay of the replicated clock signal RCK_t from the time point when the input clock signal is applied may be different from each other according to the voltage level of the power supply voltage VDD. For example, as described above, the replicated clock signal RCK_t and the output clock signal QCK_t are substantially the same, so the replicated clock signal RCK_t corresponding to the plurality of voltage levels of the power supply voltage VDD may be substantially the same as the configuration of the output clock signal QCK_t described with reference to Figure 3 For example, the unit pulse signal D_PULSE may have an activation time interval corresponding to 1 UI. For example, the activation time interval may represent the time interval during which the unit pulse signal D_PULSE has a logic high level.

[0052] For example, the activation time interval of the unit pulse signal D_PULSE may be set long enough to detect a change in delay according to a change in the voltage level of the power supply voltage VDD. Specifically, the activation time interval of the unit pulse signal D_PULSE may be set to be longer than the delay difference DD between the replicated clock signal RCK_t when the power supply voltage VDD has the first voltage level (about 0.7V) and the replicated clock signal RCK_t when the power supply voltage VDD has the second voltage level (about 0.8V). Although the exemplary embodiments are described based on the case where the unit pulse signal D_PULSE has an activation time interval corresponding to 1 UI, the exemplary embodiments are not limited thereto, and the activation time interval of the unit pulse signal D_PULSE may be set differently according to the exemplary embodiments.

[0053] Although the example embodiments are described based on the case where the starting point of the activation time interval of the unit pulse signal D_PULSE is between the positive clock edge of the replica clock signal RCK_t when the power supply voltage VDD has the eighth voltage level (about 1.4V) and the positive clock edge of the replica clock signal RCK_t when the power supply voltage VDD has the seventh voltage level (about 1.3V), the example embodiments are not limited thereto, and the starting point of the activation time interval of the unit pulse signal D_PULSE can be set differently according to the example embodiments.

[0054] As Figure 7 shown, the flip-flop 110 can output the result signal RS based on the unit pulse signal D_PULSE and the replica clock signal RCK_t. In addition, the logic level of the result signal RS can be synchronized with the logic level of the unit pulse signal D_PULSE at the positive clock edge of the replica clock signal RCK_t.

[0055] As Figure 8 shown, the logic calculation circuit 120 can set or generate a delay control signal by analyzing the result signal RS. For example, the logic calculation circuit 120 can store a plurality of transition points (e.g., transition time points or time points) t1, t2, t3, t4, t5, t6, and t7 representing the time points at which the result signal RS transitions. For example, the time point at which the result signal RS transitions can represent the time point at which the result signal RS transitions from a logic low level to a logic high level. However, the example embodiments are not limited thereto, and the result signal RS can indicate the transition time point from a logic high level to a logic low level. In some example embodiments, the logic calculation circuit 120 can also include a storage unit that stores the plurality of transition points t1, t2, t3, t4, t5, t6, and t7.

[0056] According to some embodiments, the logic calculation circuit 120 can set or generate a delay control signal based on the plurality of transition time points t1, t2, t3, t4, t5, t6, and t7. Hereinafter, the example embodiments will be described based on the example of setting the seventh time point t7 as the reference time point RT and unifying the delay between the output clock signal and the input clock signal. The output clock signal can correspond to the second voltage level to the ninth voltage level (about 0.8V,..., 1.5V) of the power supply voltage VDD.

[0057] Advantageously, the delay control signal can be set such that Figure 1The driver circuit 200 therein delays the output clock signal by different amounts of delay according to the voltage level of the power supply voltage VDD. For example, when the power supply voltage VDD has a second voltage level (about 0.8V), the delay control signal can be set such that the output clock signal is delayed by a time interval between the seventh time point t7 and the sixth time point t6. And when the power supply voltage VDD has a third voltage level (about 0.9V), the delay control signal can be set such that the output clock signal is delayed by a time interval between the seventh time point t7 and the fifth time point t5. In addition, when the power supply voltage VDD has fourth, fifth, sixth, and seventh voltage levels (about 1.0V, 1.1V, 1.2V, and 1.3V), the delay control signal can be set such that the output clock signal is delayed as in the case where the power supply voltage VDD has the second and third voltage levels (about 0.8V and 0.9V).

[0058] Next, when the power supply voltage VDD has eighth and ninth voltage levels (about 1.4V and 1.5V), the result signal RS may not change. For example, when the power supply voltage VDD has eighth and ninth voltage levels (about 1.4V and 1.5V), the amount of delay can be predicted or anticipated from the plurality of transition points t1, t2, t3, t4, t5, t6, and t7. The amount of delay may be proportional to the change in the voltage level of the power supply voltage VDD. For example, since the adjacent voltage levels among the first to ninth voltage levels (about 0.7V,..., 1.5V) of the power supply voltage VDD have a difference of about 0.1V, the time intervals between adjacent transition points among the plurality of transition points (t1, t2, t3, t4, t5, t6, and t7) may all be the same. The time interval between the first time point t1 and the second time point t2, the time interval between the second time point t2 and the third time point t3, the time interval between the third time point t3 and the fourth time point t4, the time interval between the fourth time point t4 and the fifth time point t5, the time interval between the fifth time point t5 and the sixth time point t6, and the time interval between the sixth time point t6 and the seventh time point t7 may all be the same. Therefore, when the power supply voltage VDD has eighth and ninth voltage levels (about 1.4V and 1.5V), the amount of delay can be predicted from the time intervals between adjacent transition points among the plurality of transition points t1, t2, t3, t4, t5, t6, and t7. And when the power supply voltage VDD has the eighth voltage level (about 1.4V), the amount of delay can be seven times the time interval between the seventh time point t7 and the sixth time point t6.

[0059] As Figure 9As shown, the output clock signal QCK_t' whose delay change is corrected based on the delay control signal may have the same delay amount when the power supply voltage VDD has a first voltage level to a ninth voltage level (about 0.7V, ……, 1.5V). As shown, regardless of the first voltage level to the ninth voltage level (about 0.7V, ……, 1.5V) of the power supply voltage VDD, the first time interval CLK_DLY' from the time point when the input clock signal is applied to the clock signal driver to the time point when the output clock signal QCK_t' is output from the clock signal driver may be fixed. The first time interval CLK_DLY' may be substantially the same as Figure 2 the first time interval CLK_DLY in

[0060] Figure 10 FIG. is a block diagram showing an example of a clock signal driver according to an exemplary embodiment. Referring to Figure 10 , the clock signal driver 10a may represent Figure 1 an exemplary embodiment of the clock signal driver 10 of Figure 1 . The clock signal driver 10a may include a delay control circuit 100a and a driver circuit 200a. The driver circuit 200a may include a replication circuit 220a, a control circuit 225, and a transmitter circuit 215. The transmitter circuit 215 may include a main driver circuit 210a and a main driver operation circuit (MDOU) 211. The delay control circuit 100a, the replication circuit 220a, and the main driver circuit 210a may be substantially the same as the delay control circuit 100, the replication circuit 220, and the main driver circuit 210 in Figure 1 respectively. For the sake of brevity, descriptions that are repetitive or overlapping with the description of

[0061] For example, the driver circuit 200a may further include a control circuit 225. The control circuit 225 may receive the input clock signal DCK and generate a first clock signal CK1 by adjusting the phase or delay of the input clock signal DCK. Advantageously, the control circuit 225 may correct the delay difference or fix the phase of the input clock signal DCK according to the transmission path of the input clock signal DCK. The configuration of the control circuit 225 will be described with reference to Figures 18 to 20 .

[0062] The driver circuit 200a may further include a main driver operation circuit 211. For example, the main driver operation circuit 211 may generate a second clock signal CK2 based on the first clock signal CK1 and the delay control signal DCS. The main driver operation circuit 211 may include a pre-driver circuit corresponding to the main driver circuit 210a. The pre-driver circuit may amplify the first clock signal CK1. For example, the pre-driver circuit may be a circuit configuration that generates a signal for driving the main driver circuit 210a.

[0063] The main driver operation circuit 211 may further include a delay unit circuit, and the delay unit circuit may correct a delay change of the output clock signal QCK that occurs according to a change in the voltage level of the power supply voltage. In some embodiments, the delay unit circuit may perform an operation of delay adjustment for "correcting a delay change of the first clock signal CK1 that occurs according to a change in the voltage level of the power supply voltage".

[0064] Reference will be made to Figure 11 describe the configurations of the pre-driver circuit and the delay unit circuit. Here, the delay control signal DCS may include a trimming code (TC) applied to the main driver operation circuit 211 for correcting the delay change of the output clock signal QCK. For example, the trimming code TC may be applied to the delay unit circuit included in the main driver operation circuit 211. For example, the trimming code TC may be a code for determining a correction delay applied by the delay unit circuit to the first clock signal CK1. The delay control signal DCS may further include a register signal RES, and the register signal RES is used to change the device setting value of the driver circuit 200a to additionally correct the delay change of the output clock signal QCK.

[0065] The device setting value may include the gain of the control circuit 225, the intensity of the current flowing through the control circuit 225, and the transistor strength value of the main driver circuit 210a. The transistor strength value of the main driver circuit 210a may refer to the current driving ability of the transistors included in the main driver circuit 210a. And, as will be referred to Figure 16 described, the register signal RES may include a signal for controlling a phase-locked loop (PLL).

[0066] Figure 11 is a circuit diagram showing an example of the main driver operation circuit included in the clock signal driver according to an exemplary embodiment. Refer to Figure 11 and the main driver operation circuit 211_1 may represent Figure 10 an exemplary embodiment of the main driver operation circuit 211 in

[0067] For example, the pre-driver circuit 211_11 may include a plurality of inverters connected in series (or cascaded). Although Figure 11 shows that the pre-driver circuit 211_11 includes four inverters, the exemplary embodiment is not limited thereto, and the number of inverters may be less or more.

[0068] The delay unit circuit 211_12 may include a plurality of variable resistors and a plurality of variable capacitors. Also, the first clock signals CK1_t and CK1_c may be delayed or pulled forward by the plurality of variable resistors and the plurality of variable capacitors such that second clock signals CK2_t and CK2_c are generated. The trimming code (e.g., Figure 10 TC in

[0069] may be a code for determining the resistance of the plurality of variable resistors and the capacitance of the plurality of variable capacitors.

[0070] For example, the plurality of inverters may include a first inverter INV1 and a second inverter INV2, and the output of the first inverter INV1 and the input of the second inverter INV2 may be connected to a first node ND1. For example, the plurality of variable resistors may include a first variable resistor VR1, and the plurality of variable capacitors may include a first variable capacitor VC1. For example, the first variable resistor VR1 and the first variable capacitor VC1 may be connected in series between the first node ND1 and the ground voltage VSS. Figure 11 Although the exemplary embodiments are described based on the case where the first variable resistor VR1 and the first variable capacitor VC1 are connected in series between the first node ND1 and the ground voltage VSS in the main driver operation circuit 211_1 in

[0071] the exemplary embodiments are not limited thereto. For example, the first variable resistor VR1 and the first variable capacitor VC1 may be connected in parallel between the first node ND1 and the ground voltage VSS, or may be directly connected to the internal circuit of the first inverter INV1 or the second inverter INV2 instead of between the first node ND1 and the ground voltage VSS. Figure 10 Although the exemplary embodiments are described based on an RC circuit for correcting a delay change that occurs due to a change in the voltage level of the power supply voltage in the main driver operation circuit 211_1, the exemplary embodiments are not limited thereto. For example, the delay applied to the first clock signals CK1_t and CK1_c may be controlled by adjusting the activation levels of the plurality of transistors included in the plurality of inverters. For example, the trimming code (

[0072] Figure 12 and Figure 13 are diagrams for describing the main driver operation circuit included in the clock signal driver according to the exemplary embodiments. Referring to Figure 12 an example of the correction delay CDL according to a change in the voltage level of the power supply voltage VDD is shown. The correction delay CDL may be a delay applied to the first clock signal (e.g., Figure 10 CK1 in Figure 10The correction delay CDL in (e.g., TC) may include a correction delay CDL corresponding to the voltage level of the supply voltage VDD.

[0073] In some example embodiments, the correction delay CDL may increase (e.g., discretely) as the voltage level of the supply voltage VDD increases. For example, in two cases where the voltage level of the supply voltage VDD is about 0.72V and the voltage level of the supply voltage VDD is about 0.78V, the delay applied to the first clock signal (e.g., Figure 10 CK1 in) may be the same.

[0074] Referring to Figure 13 , an example of the correction delay CDL according to a change in the voltage level of the supply voltage VDD is shown. For the sake of brevity, descriptions that are repetitive or overlapping with the Figure 12 description will be omitted. The correction delay CDL may increase linearly in proportion to the voltage level of the supply voltage VDD. For example, in the case where the voltage level of the supply voltage VDD is about 0.72V and the voltage level of the supply voltage VDD is about 0.78V, the delay applied to the first clock signal (e.g., Figure 10 CK1 in) may be different.

[0075] Figure 14 And Figure 15 are block diagrams showing examples of a clock signal driver according to an example embodiment. Referring to Figure 14 , the clock signal driver 10b may be an example embodiment of the clock signal driver 10 of Figure 1 . Referring to Figure 14 , the clock signal driver 10b includes a delay control circuit 100b and a driver circuit 200b. The driver circuit 200b includes a main driver circuit (MD) 210b and a replica circuit (RC) 220b. Compared with the clock signal driver 10 of Figure 1 , the clock signal driver 10b may further include a storage device 240b. For the sake of brevity, descriptions that are repetitive or overlapping with the Figure 1 description will be omitted.

[0076] The storage device 240b may be a space for storing the trim code TC. For example, the storage device 240b may be provided inside the driver circuit 200b. For example, the trim code TC may be stored in the storage device 240b during the wafer test process and then may be used when operating the clock signal driver 10b. For example, when operating the clock signal driver 10b, the trim code TC corresponding to the voltage level of the supply voltage VDD may be used to adjust the delay of the output clock signal QCK. For example, the storage device 240b may additionally store the register signal RES.

[0077] Referring to Figure 15 , the clock signal driver 10c may be the same asFigure 1 is substantially the same as the clock signal driver 10. The clock signal driver 10c includes a delay control circuit 100c and a driver circuit 200c. The driver circuit 200c includes a main driver circuit (MD) 210c and a replica circuit (RC) 220c. The clock signal driver 10c can exchange signals with a storage device 240c provided outside the clock signal driver 10c. For the sake of brevity, descriptions that are repetitive or overlapping with Figure 1 the description will be omitted. The storage device 240c can be a space for storing a trimming code TC. For example, the storage device 240c can be provided outside the clock signal driver 10c. For example, the trimming code TC can be stored in the storage device 240c during a wafer test process and then can be transferred from the storage device 240c to the clock signal driver 10c when operating the clock signal driver 10c. For example, the clock signal driver 10c can adjust the delay of the output clock signal QCK by referring to the trimming code TC corresponding to the voltage level of the power supply voltage VDD in the storage device 240c when the clock signal driver 10c is operated. For example, different from the trimming code TC, a register signal RES can be stored inside the driver circuit 200c.

[0078] Figure 16 and Figure 17 are block diagrams showing examples of control circuits included in a clock signal driver according to an exemplary embodiment.

[0079] Referring to Figure 16 , the control circuit 225a can be an exemplary embodiment of the control circuit 225 in Figure 10 . The control circuit 225a includes a receiving circuit 221a and a clock signal generating circuit 222a. The clock signal generating circuit 222a includes a clock tree circuit (CLKTREE) 2221a and a phase-locked loop 2222a. The receiving circuit 221a can receive and amplify the input clock signals DCK_t and DCK_c. For example, the receiving circuit 221a can include a plurality of inverters or a plurality of buffers for amplifying the input clock signals DCK_t and DCK_c.

[0080] For example, the clock tree circuit 2221a can be a circuit configuration for correcting the delay difference according to the transmission paths of the input clock signals DCK_t and DCK_c. For example, the clock tree circuit 2221a can be referred to as a clock repeater. For example, the clock tree circuit 2221a can correct the delay difference according to the physical distances between the clock terminals of a plurality of flip-flops and a clock source (e.g., a host device). For example, the plurality of flip-flops can be the flip-flops included in a plurality of memory devices connected to a clock signal driver. The phase-locked loop 2222a can be a circuit configuration for locking the phases of the input clock signals DCK_t and DCK_c. For example, the phase-locked loop 2222a can keep the frequencies of the input clock signals DCK_t and DCK_c constant.

[0081] Referring to Figure 17 , compared with the control circuit 225a of Figure 16 , the control circuit 225b can further include a plurality of switches (denoted as SW1 and SW2 in Figure 17 ) 2223 and 2224. The control circuit 225b can include a receiving circuit 221b and a clock signal generation circuit 222b. For the sake of brevity, descriptions that are repetitive or overlapping with the description of Figure 16 will be omitted. One of the clock tree circuit 2221b and the phase-locked loop 2222b can be selectively operated using the plurality of switches 2223 and 2224. For example, the first clock signals CK1_t and CK1_c can be generated based on one of the clock tree circuit 2221b and the phase-locked loop 2222b.

[0082] Figure 18 is a block diagram showing a memory system according to an exemplary embodiment. Referring to Figure 18 , the memory system 1000 includes a host device 1100, a clock signal driver 1200, and a plurality of memory devices 1300. The clock signal driver 1200 can be substantially the same as the clock signal driver 10 of Figure 1 . For the sake of brevity, descriptions that are repetitive or overlapping with the description of Figures 1 to 17 will be omitted.

[0083] The host device 1100 supplies an input clock signal DCK to the clock signal driver 1200 and controls the clock signal driver 1200 and the plurality of memory devices 1300. For example, when the host device 1100 directly supplies the input clock signal DCK to the plurality of memory devices 1300, the strength of the input clock signal DCK transmitted to the plurality of memory devices 1300 may be weak, and the timing conditions required by the plurality of memory devices 1300 may not be satisfied. Accordingly, the host device 1100 may supply the input clock signal DCK to the clock signal driver 1200, and the clock signal driver 1200 may generate an output clock signal QCK by controlling the signal strength and timing conditions of the input clock signal DCK.

[0084] The host device 1100 may request (or command) that the plurality of memory devices 1300 have constant input / output timing regardless of a change in the voltage level of the power supply voltage. Similarly, the host device 1100 may require that the clock signal driver 1200 have constant output timing regardless of a change in the voltage level of the power supply voltage. For example, the host device 1100 may apply the input clock signal DCK to the clock signal driver 1200 and request that the output clock signal QCK be output after a predetermined delay regardless of a change in the voltage level of the power supply voltage.

[0085] The plurality of memory devices 1300 receive the output clock signal QCK from the clock signal driver 1200 and operate based on the output clock signal QCK. For example, the plurality of memory devices 1300 may be dynamic random access memories (DRAMs).

[0086] Figure 19 and Figure 20 are diagrams for describing a clock signal driver according to an exemplary embodiment. Referring to Figure 19 , an exemplary embodiment will be described based on a case where the output clock signal QCKa_t is requested to be output at a second time point T2a that "indicates a time point at which a first time interval CLK_DLYa has elapsed from a first time point T1a". For example, the first time point T1a may indicate a time point at which the input clock signal is input (or applied) to the clock signal driver. For example, the power supply voltage VDD may have a plurality of voltage levels, where the plurality of voltage levels include a first voltage level (e.g., about 0.7V), a second voltage level (e.g., about 0.8V), a third voltage level (e.g., about 0.9V), a fourth voltage level (e.g., about 1.0V), a fifth voltage level (about 1.1V), a sixth voltage level (e.g., about 1.2V), a seventh voltage level (e.g., about 1.3V), an eighth voltage level (e.g., about 1.4V), and a ninth voltage level (e.g., about 1.5V). For the sake of brevity, descriptions that are repetitive or overlapping with the Figure 3 description will be omitted.

[0087] For example, the second time point T2a may represent the time point when the output clock signal QCKa_t is output when the power supply voltage VDD has a fifth voltage level (about 1.1V). For example, when the power supply voltage VDD has a first voltage level (about 0.7V), the output clock signal QCKa_t may be pulled up. For example, an exemplary embodiment will be described based on the power supply voltage VDD having a first voltage level (about 0.7V) and an output delay from the first time point T1a to the time point when the output clock signal QCKa_t is output being 500 ps. For example, the output delay may be the delay imposed by the driver circuit ( Figure 1 200 in), regardless of the delay control signal. For example, the delay control signal may control the driver circuit ( Figure 1 200 in) such that the output delay is shorter than about 500 ps.

[0088] Referring to Figure 20 , an exemplary embodiment will be described based on the case where the output clock signal QCKb_t is requested to be output at a second time point T2b that "indicates the time point when a first time interval CLK_DLYb has elapsed from the first time point T1b". For example, the first time point T1b may indicate the time point when the input clock signal is input (or applied) to the clock signal driver. For the sake of brevity, descriptions that are repetitive or overlapping with the descriptions of Figure 3 and Figure 19 will be omitted.

[0089] For example, the second time point T2b may be a time point after the time point when the output clock signal QCKb_t is output when the power supply voltage VDD has a first voltage level to a ninth voltage level (about 0.7V, 0.8V,..., 1.5V). When the power supply voltage VDD has a first voltage level (about 0.7V), the output clock signal QCKb_t may be delayed. For example, if the power supply voltage VDD has a first voltage level (about 0.7V) and the output delay from the first time point T1b to the time point when the output clock signal QCKb_t is output is 500 ps, the delay control signal may control the driver circuit ( Figure 1 200 in) such that the output delay is longer than 500 ps.

[0090] Figure 21 is a diagram showing an exemplary embodiment of the clock signal driver according to the exemplary embodiment. Referring to Figure 21, example embodiments are described based on a case where a plurality of memory devices are provided in the form of a memory module including a memory package and a clock signal driver is provided in the form of a buffer chip. The memory module 500 may include a circuit board 501, a buffer chip 590 disposed (mounted) on the circuit board 501, and a plurality of memory devices (or semiconductor memory devices) 601a, 601b, 601c, 601d, 601e, 602a, 602b, 602c, 602d, 602e, 603a, 603b, 603c, 603d, 604a, 604b, 604c, 604d, module resistors (or module resistance parts or module resistance units) 560, 570, a serial presence detect (SPD) chip 580, and a power management integrated circuit (PMIC) 585.

[0091] The buffer chip 590 may control the memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d and the PMIC 585 according to the control of an external memory controller. For example, the buffer chip 590 may be a register clock driver (RCD), and may receive an address ADDR, a command CMD, and data DAT from the memory controller. For example, the RCD may include Figure 1 a clock signal driver 10. For example, the buffer chip 590 may supply a clock signal to the plurality of memory devices 601a, 601b, 601c, 601d, 601e, 602a, 602b, 602c, 602d, 602e, 603a, 603b, 603c, 603d, 604a, 604b, 604c, and 604d.

[0092] The SPD chip 580 may include an electrically erasable programmable read-only memory (EEPROM). The SPD chip 580 may include initial information or device information (DI) of the memory module 500. For example, the SPD chip 580 may include initial information or device information (DI) (such as module type, module configuration, storage capacity, execution environment, etc.) of the memory module 500. When a memory system including the memory module 500 is started, the DI is read from the SPD chip 580, and the memory module 500 is identified / controlled based on the read DI.

[0093] The circuit board 501 can extend between a first edge portion 503 and a second edge portion 505 along a second direction D2 perpendicular to the first direction D1. For example, the circuit board 501 can be a printed circuit board (PCB). The buffer chip 590 can be disposed at the center of the circuit board 501, and the memory devices 601a to 601e and 602a to 602e can be disposed in multiple rows between the buffer chip 590 and the first edge portion 503. The memory devices 603a to 603d and 604a to 604d can be disposed in multiple rows between the buffer chip 590 and the second edge portion 505.

[0094] For example, the semiconductor memory devices 601a to 601e and 602a to 602e can be disposed in multiple rows between the buffer chip 590 and the first edge portion 503, and the semiconductor memory devices 603a to 603d and 604a to 604d can be disposed in multiple rows between the buffer chip 590 and the second edge portion 505. The semiconductor memory devices 601a to 601d, 602a to 602d, 603a to 603d, and 604a to 604d can be referred to as data chips, and the semiconductor memory devices 601e and 602e can be referred to as parity chips.

[0095] The buffer chip 590 can provide command / address signals to the memory devices 601a to 601e through the command / address transmission lines 561, and provide command / address signals to the memory devices 602a to 602e through the command / address transmission lines 563. In addition, the buffer chip 590 can provide command / address signals to the semiconductor memory devices 603a to 603d through the command / address transmission lines 571, and can provide command / address signals to the semiconductor memory devices 604a to 604d through the command / address transmission lines 573.

[0096] The command / address transmission lines 561 and 563 can be commonly connected to a module resistor portion 560 disposed adjacent to the first edge portion 503, and the command / address transmission lines 571 and 573 can be connected to a module resistor unit 570 disposed adjacent to the second edge portion 505. Both the module resistor units 560 and 570 can include termination resistors Rtt / 2 connected to a termination voltage Vtt. Each of the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d can be a DRAM device.

[0097] The SPD chip 580 can be set adjacent to the buffer chip 590, and the PMIC 585 can be set between the memory device 603d and the second edge portion 505. The PMIC 585 can generate a power supply voltage VDD based on the input voltage VIN and supply the power supply voltage VDD to the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d.

[0098] Figure 22 is a block diagram illustrating an example of a data chip included in a memory module included in a memory system according to an example embodiment. Refer to Figure 22 FIG. 2, the data chip 201a may include a control logic circuit 212, an address register 216, a bank control logic circuit 230, a row address multiplexer (RAMUX) 240, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an input / output (I / O) strobe circuit 290, a data I / O buffer 295, an on-die (OD) ECC engine 400a, and / or a refresh counter 245. The data chip 201a may include a single or multiple of each of the above.

[0099] The memory cell array 300 may include first to eighth bank arrays 310 to 380 (e.g., first to eighth bank arrays 310, 320, 330, 340, 350, 360, 370, and 380). The row decoder 260 may include first to eighth bank row decoders 260a to 260h respectively connected to the first to eighth bank arrays 310 to 380. The column decoder 270 may include first to eighth bank column decoders 270a to 270h respectively connected to the first to eighth bank arrays 310 to 380. The sense amplifier unit 285 may include first to eighth bank sense amplifiers 285a to 285h respectively connected to the first to eighth bank arrays 310 to 380.

[0100] The first to eighth bank arrays 310 to 380, the first to eighth bank row decoders 260a to 260h, the first to eighth bank column decoders 270a to 270h, and the first to eighth bank sense amplifiers 285a to 285h may form first to eighth banks. Each of the first to eighth bank arrays 310 to 380 may include a plurality of word lines WL, a plurality of bit lines BTL, and a plurality of memory cells MC formed at intersections of the word lines WL and the bit lines BTL.

[0101] Although Figure 22 data chip 201a is shown as including eight banks, data chip 201a may include any number of banks (e.g., one, two, four, eight, sixteen, or thirty-two banks, or any number between one and thirty-two).

[0102] Address register 216 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller. Address register 216 may provide the received bank address BANK_ADDR to bank control logic circuit 230, may provide the received row address ROW_ADDR to row address multiplexer 240, and may provide the received column address COL_ADDR to column address latch 250.

[0103] Bank control logic circuit 230 may generate bank control signals in response to the bank address BANK_ADDR. One of first bank row decoders 260a through eighth bank row decoders 260h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals, and one of first bank column decoders 270a through eighth bank column decoders 270h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.

[0104] Row address multiplexer 240 may receive the row address ROW_ADDR from address register 216 and may receive a refresh row address REF_ADDR from refresh counter 245. Row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA output from row address multiplexer 240 may be applied to first bank row decoders 260a through eighth bank row decoders 260h.

[0105] One of first bank row decoders 260a through eighth bank row decoders 260h that is activated may decode the row address RA output from row address multiplexer 240 and may activate a word line WL corresponding to the row address RA. For example, the activated bank row decoder may generate a word line drive voltage and may apply the word line drive voltage to the word line WL corresponding to the row address RA.

[0106] The column address latch 250 can receive the column address COL_ADDR from the address register 216 and can temporarily store the received column address COL_ADDR. In some example embodiments, in burst mode, the column address latch 250 can generate a column address incremented from the received column address COL_ADDR. The column address latch 250 can apply the temporarily stored or generated column address to the first bank column decoder 270a to the eighth bank column decoder 270h.

[0107] One of the activated ones among the first bank column decoder 270a to the eighth bank column decoder 270h can decode the column address COL_ADDR output from the column address latch 250 and can control the I / O strobe circuit 290 to output data corresponding to the column address COL_ADDR.

[0108] The I / O strobe circuit 290 can include a circuit for strobing input / output data. The I / O strobe circuit 290 can also include a read data latch for storing data output from the first bank array 310 to the eighth bank array 380, and can also include a write control device for writing data to the first bank array 310 to the eighth bank array 380.

[0109] The codeword CW read from one of the first bank array 310 to the eighth bank array 380 can be sensed by a sense amplifier connected to the bank array from which the codeword CW is read and can be stored in the read data latch. After the on-die ECC engine 400a performs ECC decoding on the codeword CW, the codeword CW stored in the read data latch can be provided to the memory controller via the data I / O buffer 295. The on-die ECC engine 400a can output a decoding status flag DSF. The codeword CW can be provided to the memory controller as a data set (or user data or main data) DQ_BL.

[0110] The data set DQ_BL to be written into one of the first bank array 310 to the eighth bank array 380 can be provided from the memory controller to the data I / O buffer 295 and can be provided from the data I / O buffer 295 to the on-die ECC engine 400a. The on-die ECC engine 400a can perform ECC encoding on the data set DQ_BL to generate parity data. The on-die ECC engine 400a can provide the codeword CW including the data set DQ_BL and the parity data to the I / O strobe circuit 290, and the I / O strobe circuit 290 can write the codeword CW into a sub-page of a target page in one of the bank arrays through a write driver.

[0111] The data I / O buffer 295 can provide the data set DQ_BL from the memory controller to the on-die ECC engine 400a during the write operation of the data chip 201a, and can provide the data set DQ_BL from the on-die ECC engine 400a to the memory controller during the read operation of the data chip 201a.

[0112] The control logic circuit 212 can control the operation of the data chip 201a. For example, the control logic circuit 212 can generate control signals for the data chip 201a to perform write operations and / or read operations. The control logic circuit 212 can include a command decoder 213 that decodes the command CMD received from the memory controller, and a mode register 214 that sets the operation mode of the data chip 201a. In some example embodiments, the operations described herein as being performed by the control logic circuit 212 can be performed by a processing circuit. The command decoder 213 can generate control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc.

[0113] Figure 23 is a diagram for describing the configuration and operation of a clock signal driver according to an example embodiment. Refer to Figure 23 , an example of an electrical die sort (EDS) process performed during the manufacture of a non-volatile memory device is shown. After manufacturing a plurality of non-volatile memory chips by performing an oxidation process, a lithography process, an etching process, a deposition and / or ion implantation process, a metal wiring process, etc. on a wafer, the EDS process can be performed to check whether each non-volatile memory chip has reached a target quality level. For example, electrical tests, wafer aging tests, thermal / cold tests, repair / final tests, etc. can be performed, and finally, defective chips can be identified by inking. For example, the EDS process can be used with substantially the same meaning as the wafer test process. For example, the correction operations described with reference to Figures 6 to 9 can be performed in the EDS process. The correction operation can represent an operation of correcting a change in the delay of an output clock signal that occurs according to a change in the voltage level of the power supply voltage. For example, the EDS process can include a trim code generation operation to correct a change in the delay in the output clock signal according to a plurality of test voltage levels of the power supply voltage.

[0114] For example, Figure 23 the wafer 70 on the left in Figure 23 can represent the wafer before the EDS process,

[0115] In some example embodiments, an EDS test operation may be performed when a non-volatile memory device is manufactured and the EDS test operation may not be performed again thereafter. For example, each non-volatile memory chip (e.g., Figure 5 the non-volatile memory chip 50 in

[0116] Example embodiments may be applied to various electronic devices and systems including a clock signal driver. For example, example embodiments may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a portable video camera, a video player, a navigation device, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, etc.

[0117] The foregoing is illustrative of example embodiments and should not be construed as limiting the example embodiments. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the example embodiments without materially departing from the novel teachings and advantages of the example embodiments.

[0118] Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Accordingly, it will be understood that the foregoing is illustrative of various example embodiments and should not be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A clock signal driver, comprising: A driver circuit configured to generate an output clock signal in response to an input clock signal, a delay control signal, and a power supply voltage, the driver circuit comprising: A main driver circuit configured to generate an output clock signal in response to the input clock signal; and A replication circuit having a structure equivalent to that of the main driver circuit, the replication circuit being configured to generate a replicated clock signal equivalent to the output clock signal in response to the input clock signal; and A delay control circuit configured to generate a delay control signal for correcting a delay change of the output clock signal in response to the replicated clock signal, the delay change of the output clock signal being caused by a change in the voltage level of the power supply voltage.

2. The clock signal driver as claimed in claim 1, wherein, The delay control circuit is powered by a first voltage, the first voltage being different from the power supply voltage and having a constant voltage level.

3. The clock signal driver according to claim 1, wherein During wafer-level testing of the clock signal driver, the delay control signal is generated by the delay control circuit in response to the replicated clock signal.

4. The clock signal driver according to claim 1, wherein, The delay control circuit comprises: A flip-flop configured to output a result signal in response to the replicated clock signal and a unit pulse signal; and A logic calculation circuit configured to generate the unit pulse signal as feedback to the flip-flop and generate the delay control signal based on the result signal.

5. The clock signal driver according to claim 4, Among them, The logic calculation circuit is configured to store a plurality of first time points and generate the delay control signal based on the plurality of first time points; and wherein the plurality of first time points indicate time points at which the result signal transitions between logic levels due to a change in the voltage level of the power supply voltage.

6. The clock signal driver as claimed in claim 4, wherein, The unit pulse signal has an activation time interval corresponding to 1 unit interval of data, the data being input to and output from a memory device operating based on the output clock signal.

7. The clock signal driver according to claim 1, wherein, The driver circuit further comprises: A control circuit configured to receive the input clock signal and generate a first clock signal by adjusting the phase or delay of the input clock signal; and A main driver operation circuit configured to generate a second clock signal in response to the first clock signal and the delay control signal; and wherein the main driver circuit is configured to generate the output clock signal based on the second clock signal, and the replication circuit is configured to generate the replicated clock signal based on the second clock signal.

8. The clock signal driver according to claim 7, wherein, The delay control signal includes a trimming code applied to the main driver operation circuit to correct the delay change of the output clock signal.

9. The clock signal driver according to claim 8, Among them, The delay control signal further includes a register signal for changing a device setting value of the driver circuit to additionally correct the delay change of the output clock signal; and wherein the device setting value includes the gain of the control circuit, the strength of the current flowing through the control circuit, and the transistor strength of the main driver circuit.

10. The clock signal driver according to claim 7, wherein, The main driver operation circuit comprises: A pre-driver circuit configured to amplify the first clock signal; and A delay unit circuit configured to correct the delay change of the output clock signal caused by a change in the voltage level of the power supply voltage.

11. The clock signal driver according to claim 10, Among them, wherein the pre-driver circuit includes a plurality of inverters connected in series; and wherein the delay unit circuit includes a plurality of variable resistors and a plurality of variable capacitors connected to the plurality of inverters.

12. The clock signal driver according to claim 11, Among them, wherein the plurality of inverters includes a first inverter and a second inverter, and the input of the first inverter and the output of the second inverter are connected to a first node; wherein the plurality of variable resistors includes a first variable resistor, and the plurality of variable capacitors includes a first variable capacitor; and wherein the first variable resistor and the first variable capacitor are connected in series between the first node and the ground voltage.

13. The clock signal driver according to claim 10, wherein, The delay unit circuit is configured to apply a delay that increases as the voltage level of the power supply voltage increases to the first clock signal.

14. The clock signal driver according to claim 10, wherein, The delay unit circuit is configured to apply a delay that linearly increases in proportion to the voltage level of the power supply voltage to the first clock signal.

15. The clock signal driver according to claim 7, wherein The control circuit includes: a receiving circuit configured to receive and amplify an input clock signal; a clock tree circuit configured to correct a delay difference according to a transmission path of the input clock signal; and a phase-locked loop configured to lock the phase of the input clock signal.

16. The clock signal driver according to claim 15, wherein, The receiving circuit includes a plurality of buffers configured to amplify the input clock signal.

17. The clock signal driver according to claim 15, wherein, The first clock signal is generated based on one of the clock tree circuit and the phase-locked loop.

18. A memory system, comprising: a clock signal driver configured to generate an output clock signal in response to an input clock signal, the clock signal driver including: a driver circuit configured to operate based on a power supply voltage and generate an output clock signal based on the input clock signal and a delay control signal, the driver circuit including a main driver circuit and a replication circuit, the main driver circuit being configured to generate the output clock signal, the replication circuit having the same structure as the main driver circuit and being configured to generate a replication clock signal identical to the output clock signal, and a delay control circuit configured to generate a delay control signal for correcting a delay change of the output clock signal based on the replication clock signal, the delay change of the output clock signal occurring according to a change in the voltage level of the power supply voltage; a plurality of memory devices configured to receive the output clock signal from the clock signal driver; and a host device configured to supply the input clock signal to the clock signal driver and control the clock signal driver and the plurality of memory devices.

19. The memory system according to claim 18, wherein, Each of the plurality of memory devices is a dynamic random access memory device.

20. A clock signal driver, comprising: a driver circuit configured to operate based on a power supply voltage and generate an output clock signal in response to an input clock signal and a delay control signal, the driver circuit including: a main driver circuit configured to generate the output clock signal in response to the input clock signal; and a replication circuit having the same structure as the main driver circuit and being configured to generate a replication clock signal identical to the output clock signal; and A delay control circuit, configured to: generate a delay control signal for correcting a delay change of an output clock signal in response to a replica clock signal, the delay change of the output clock signal being caused by a change in a voltage level of a power supply voltage.

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