Method and system for balancing warpage stress of fc-pbga circuit
By flip-chip bonding and mounting a heatsink with a square inner cavity and a circular shape in a large-size plastic-encapsulated FC-PBGA circuit, the bonding area is increased and stress is balanced, which solves the chip damage problem caused by warping and improves the reliability and stability of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI ZHONGWEI GAOKE ELECTRONICS
- Filing Date
- 2025-04-27
- Publication Date
- 2026-05-22
Smart Images
Figure CN120413436B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit packaging technology, and in particular to a method and system for balancing the warpage stress of an FC-PBGA circuit. Background Technology
[0002] With the development of integrated circuits, high integration has gradually become the mainstream. Large-size plastic-packaged FC-PBGA circuits are becoming increasingly popular due to their low cost and high integration, and will be one of the important directions for the development of the integrated circuit manufacturing industry. However, their high reliability performance places higher demands on FC-PBGA integrated circuit packaging technology.
[0003] Due to their high coefficient of thermal expansion, plastic substrates are significantly affected by temperature, exhibiting varying degrees of warping with temperature changes. Furthermore, the degree of warping intensifies as the size of the plastic substrate increases. Therefore, during reliability testing of FC-PBGA circuits, especially temperature cycling tests, the plastic substrate repeatedly displays "smiley face" and "crying face" warping patterns. This process can cause fatigue damage to the chip and its solder bumps, ultimately leading to structural integrity issues and electrical connection failures. Therefore, the failure problem caused by warping in large-size plastic-encapsulated FC-PBGA circuits is a pressing issue that needs to be addressed. Summary of the Invention
[0004] The purpose of this invention is to provide a method and system for balancing the warpage stress of FC-PBGA circuits, so as to solve the problems existing in the prior art.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:
[0006] In a first aspect, the present invention provides a method for balancing the warpage stress of an FC-PBGA circuit, the method comprising:
[0007] The chip is flip-chip mounted onto a plastic substrate, and the chip is then fixed in place.
[0008] In response to the chip underfill being fixed, a heat sink is attached to the chip surface; wherein the heat sink is square in shape and has a circular inner cavity;
[0009] By increasing the bonding area between the foot area of the heat sink and the plastic substrate, the vertical stress caused by the warping of the plastic substrate can be balanced.
[0010] Based on the circular inner cavity of the heat sink, the force balance interaction of the circle is combined to balance the horizontal stress generated by the warping of the plastic substrate.
[0011] By balancing the vertical stress caused by the warping of the plastic substrate and the horizontal stress caused by the warping of the plastic substrate, the stress acting on the chip area is minimized.
[0012] In one possible implementation, flip-chip bonding onto a plastic substrate and fixing the chip to the substrate includes:
[0013] The chip is flip-chipped onto a plastic substrate using a flip-chip reflow process, and the chip is fixed by underfill adhesive.
[0014] The curing temperature of the underfill adhesive is controlled at 150-170℃, and the curing time is 90-120 minutes.
[0015] In one possible implementation, the step of attaching the heat sink to the chip surface in response to the chip underfill fixing includes:
[0016] In response to the chip underfill being fixed;
[0017] The foot area of the heat sink is bonded to the plastic substrate with AD adhesive, which serves to fix and dissipate heat.
[0018] The central area of the heat sink is bonded to the surface of the chip using Tim adhesive, serving both heat dissipation and fixation purposes.
[0019] In one possible implementation, the AD adhesive is selected as a thermally conductive adhesive with high bonding strength and good heat dissipation performance, which can resist the warping stress of the plastic substrate through high-strength bonding.
[0020] In one possible implementation, the Tim adhesive is selected as a thermally conductive adhesive with weak bonding strength and good heat dissipation performance, and the warping stress applied to the chip area by the plastic substrate is balanced by low-strength bonding.
[0021] In one possible implementation, the coating thickness of the AD adhesive and the Tim adhesive is 50-100 μm to ensure bonding effect and stress balance.
[0022] In one possible implementation, the cavity based on the heat sink is circular, and the circular shape facilitates force balance interactions to counteract the horizontal stress generated by the warping of the plastic substrate, including:
[0023] Based on the circular shape of the inner cavity of the heat sink, the warping stress area of the plastic substrate is divided into a circle.
[0024] By utilizing the characteristic that the stress direction of a circle is towards the center and the stress is equal in magnitude, the stress balance on the circular plane is canceled out, so as to achieve no horizontal stress acting on the chip area.
[0025] In one possible implementation, before flip-chip bonding onto the plastic substrate, the following is also included:
[0026] The surfaces of the chip and the plastic substrate to be bonded are cleaned and pretreated to remove surface contaminants.
[0027] In one possible implementation, the chip has an external dimension of 5mm×5mm to 30mm×30mm, the heat sink has an external dimension of 10mm×10mm to 50mm×50mm, and the heat sink is made of copper alloy or Alsic.
[0028] Secondly, the present invention provides a system for balancing the warpage stress of an FC-PBGA circuit, the system comprising:
[0029] An execution module is used to flip-chip onto a plastic substrate and fix the chip underside.
[0030] The execution module is further configured to attach a heat sink to the surface of the chip after the chip substrate is fixed; wherein the heat sink is square in shape and has a circular inner cavity;
[0031] A balancing module is used to balance the vertical stress caused by the warping of the plastic substrate by increasing the bonding area between the foot area of the heat sink and the plastic substrate.
[0032] The balancing module is also used to balance the horizontal stress generated by the warping of the plastic substrate, based on the circular shape of the inner cavity of the heat sink and the force balance interaction of the circle.
[0033] A control module is used to minimize the stress acting on the chip region by balancing the vertical stress caused by the warping of the plastic substrate and the horizontal stress caused by the warping of the plastic substrate.
[0034] The control module is electrically connected to the execution module and the balancing module to send control signals to the execution module and the balancing module and to receive feedback signals from the balancing module, thereby achieving control of stress balance.
[0035] The beneficial effects of the technical solution provided by this invention include at least the following:
[0036] This technical solution involves flip-chip mounting onto a plastic substrate for underfill fixation. Following chip underfill fixation, a heat sink is mounted onto the chip surface. The heat sink has a square shape and a circular inner cavity. By increasing the bonding area between the foot area of the heat sink and the plastic substrate, the vertical stress caused by substrate warping is balanced. The circular inner cavity of the heat sink, combined with the force balance interaction of the circle, balances the horizontal stress caused by substrate warping. By balancing both the vertical and horizontal stresses caused by substrate warping, the stress acting on the chip area is minimized. This avoids stress damage to the chip area. By improving the heat sink structure design to balance and reduce warping stress, the failure risk during reliability testing is reduced. Attached Figure Description
[0037] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.
[0038] Figure 1 A flowchart illustrating a method for balancing warpage stress in an FC-PBGA circuit according to an exemplary embodiment of the present invention is shown.
[0039] Figure 2 A schematic diagram of an FC-PBGA circuit according to an exemplary embodiment of the present invention is shown; wherein, Figure 2 (a) Front view, Figure 2 (b) is the exploded view of the main view.
[0040] Figure 3 This diagram illustrates a mounting schematic of an FC-PBGA circuit according to an exemplary embodiment of the present invention; wherein, Figure 3 (a) is a top view of the plastic substrate and chip before mounting. Figure 3 (b) is a top view of the heatsink before mounting.
[0041] Figure 4 This diagram illustrates the mechanical distribution of an FC-PBGA circuit according to an exemplary embodiment of the present invention; wherein, Figure 4 (a) is a schematic diagram of the mechanical distribution under any cross-section along the vertical direction of the plastic substrate. Figure 4 (b) is a schematic diagram of the mechanical distribution of the heat sink in the horizontal direction.
[0042] Figure 5 A structural block diagram of a warpage stress balancing system for an FC-PBGA circuit provided by an exemplary embodiment of the present invention is shown. Detailed Implementation
[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0044] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0045] Figure 1 The flowchart illustrates a method for balancing warpage stress in an FC-PBGA circuit according to an exemplary embodiment of the present invention. The method includes:
[0046] Step 101: Flip-mount the chip onto the plastic substrate and fix the chip to the bottom.
[0047] In this embodiment of the application, the chip is flip-chip mounted on a plastic substrate and the chip is fixed by underfill, including: flip-chip mounted on a plastic substrate based on a flip-chip reflow process, and the chip is fixed by underfill adhesive; wherein the curing temperature of the underfill adhesive is controlled at 150-170℃ and the curing time is 90-120min.
[0048] In this embodiment of the application, before flip-chip is flip-chip onto plastic substrate, the method further includes: cleaning pretreatment of the surfaces of the chip and plastic substrate to be bonded to remove surface contaminants.
[0049] In this embodiment, when the chip is flip-chip mounted on a plastic substrate and underfilled for fixation, the flip-chip reflow process uses solder balls to achieve electrical interconnection between the chip bumps and the plastic substrate pads, shortening the signal path to improve performance. At the same time, the underfill adhesive fills the gap between the chip and the plastic substrate, forming a rigid support layer to disperse stress, enhance interface bonding, and prevent the solder balls from cracking due to stress concentration. The cleaning pretreatment removes contaminants from the chip and substrate surfaces to be bonded, ensuring the metallurgical bonding quality between the solder balls and the substrate pads and the wettability of the underfill adhesive, thus avoiding bonding failure or void defects.
[0050] Step 102: In response to the chip underfill fixation, the heat sink is attached to the chip surface; wherein the heat sink is square in shape and circular in inner cavity.
[0051] Optionally, the chip has a size of 5mm×5mm to 30mm×30mm, and the heat sink has a size of 10mm×10mm to 50mm×50mm.
[0052] In one example Figure 2 A schematic diagram of an FC-PBGA circuit according to an exemplary embodiment of the present invention is shown; wherein, Figure 2 (a) Front view, Figure 2 (b) is the exploded front view. The FC-PBGA circuit includes a plastic substrate 1, a chip 2 with bumps, and a heat sink 3 with a square shape and a circular inner cavity. The plastic substrate 1 has a size of 50mm×50mm, the chip 2 has a size of 30mm×30mm, and the heat sink 3 has a size of 50mm×50mm.
[0053] In this embodiment, in response to the chip underfill fixation, the heat sink is attached to the chip surface, including: in response to the chip underfill fixation; bonding the foot area of the heat sink to the plastic substrate with AD adhesive for fixation and heat dissipation; and bonding the center area of the heat sink to the chip surface with Tim adhesive for heat dissipation and fixation. The AD adhesive is a thermally conductive adhesive with high bonding strength and good heat dissipation performance, using high-strength bonding to counteract the warping stress of the plastic substrate. The Tim adhesive is a thermally conductive adhesive with weak bonding strength and good heat dissipation performance, using low-strength bonding to balance the warping stress applied to the chip area by the plastic substrate. The application thickness of the AD adhesive and Tim adhesive is 50-100 μm to ensure bonding effect and stress balance.
[0054] In one example Figure 3 This diagram illustrates a mounting schematic of an FC-PBGA circuit according to an exemplary embodiment of the present invention; wherein, Figure 3 (a) is a top view of the plastic substrate and chip before mounting. Figure 3 (b) is a top view of the heat sink before mounting. The foot area of the heat sink 3 is bonded to the A area of the plastic substrate 1 by AD glue dispensing (as shown in the dotted circle area), and the center area of the heat sink 3 is bonded to the B area of the chip 2 by Tim glue dispensing (as shown in the dotted circle area).
[0055] In this embodiment, in response to the mounting of the heat sink after the chip underfill is fixed, the foot area of the heat sink is bonded to the plastic substrate with high-strength AD adhesive, using its rigid connection to counteract the vertical stress of the plastic substrate warping. At the same time, the central area is bonded to the chip surface with low-strength Tim adhesive, using the slight deformation of the adhesive layer to buffer the horizontal shear stress. The dual adhesive layer design forms a "rigid edge anchoring + flexible center buffering" structure. The AD adhesive and Tim adhesive are made of high thermal conductivity materials to take into account heat dissipation, and the coating thickness is controlled at 50-100μm to ensure the bonding effect and stress balance. The heat sink is larger than the chip to expand the stress application area.
[0056] It is worth mentioning that the Foot area of the heat sink refers to the edge area on the heat sink that is bonded to the plastic substrate with high-strength thermally conductive adhesive. It is mainly used to fix the heat sink, enhance heat dissipation performance, and balance the vertical stress caused by the warping of the plastic substrate by increasing the bonding area.
[0057] Preferably, the heat sink is made of copper alloy or ALSI, and the surface can be nickel-plated to improve heat dissipation efficiency and adhesion to the thermally conductive adhesive. At the same time, the rigid support of the metal material enhances the resistance to warping of the plastic substrate.
[0058] Step 103: Increase the bonding area between the foot area of the heat sink and the plastic substrate to balance the vertical stress caused by the warping of the plastic substrate.
[0059] In this embodiment, when the vertical stress is balanced by increasing the bonding area between the foot area of the heat sink and the plastic substrate, the stress-area inverse relationship in mechanical principle is utilized. Expanding the contact area can reduce the stress load per unit area and prevent detachment due to stress exceeding the strength of the adhesive layer. The rigid structure of the heat sink acts as a "stress raft" to diffuse the vertical stress generated by the warping of the plastic substrate to the entire plane of the plastic substrate. Force balance is achieved by utilizing the strength of the substrate structure, thereby reducing the vertical stress component acting on the chip.
[0060] Step 104: Based on the circular shape of the inner cavity of the heat sink, the force balance interaction of the circle is combined to balance the horizontal stress generated by the warping of the plastic substrate.
[0061] In this embodiment, based on the circular shape of the inner cavity of the heat sink, the force balance interaction of the circle is combined to balance the horizontal stress generated by the warping of the plastic substrate. This includes: dividing the warping stress area of the plastic substrate into circles based on the circular shape of the inner cavity of the heat sink; utilizing the characteristic that the stress direction of the circle points to the center and is equal in magnitude, the stress balance on the circular plane cancels out, so as to achieve no horizontal stress acting on the chip area.
[0062] Step 105: By balancing the vertical stress caused by the warping of the plastic substrate and the horizontal stress caused by the warping of the plastic substrate, the stress acting on the chip area is minimized.
[0063] Specifically, FC-PBGA circuits have high requirements and need to pass reliability tests. When subjected to temperature changes such as temperature cycling and thermal shock, the plastic substrate, due to its large coefficient of thermal expansion, will warp in a "smiley face" or "sad face" shape under high and low temperature changes, i.e., warping stress will be generated. When this stress is transferred to the chip or the chip bump soldering area, it will increase the risk of failure. This application sets the center of the plastic substrate as the reference, the warping of the plastic substrate is "sad face", and the inner cavity of the heat sink is circular. Figure 4 This diagram illustrates the mechanical distribution of an FC-PBGA circuit according to an exemplary embodiment of the present invention. Figure 4(a) is a schematic diagram of the mechanical distribution under any cross-section along the vertical direction of the plastic substrate. The warping stress F generated at both ends of the plastic substrate on any cross-section is symmetrical and equal. The warping stress F can be decomposed into horizontal stress F1=F*Sinθ and vertical stress F2=F*Cosθ. Due to the large area A region (see Figure 3 High-strength thermally conductive adhesive is used for bonding, and the vertical stress F2 is applied to the heat sink and counteracted by the rigidity of the heat sink itself; Figure 4 (b) is a schematic diagram of the mechanical distribution of the heat sink in the horizontal direction. A centrally symmetrical (centered on the circle) horizontal stress is distributed on the heat sink with the inner cavity circle as the boundary. These stresses balance and cancel each other out, so F1 = 0. Therefore, no horizontal stress acts on the chip area, which greatly reduces the stress impact of substrate warping on the chip area. This can be understood to also apply to plastic substrates with "smiley face" warping.
[0064] In this embodiment, a multi-level stress buffer system is formed by balancing vertical and horizontal stress to minimize the stress in the chip area: the bottom filler provides rigid support, the AD adhesive provides high-strength anchoring, the Tim adhesive provides flexible buffering, and the heat sink provides both thermal conductivity and mechanical support. Combined with the elastic deformation of the substrate, the stress on the chip bumps is reduced to within the material tolerance threshold. According to tests, this solution can reduce the stress in the chip area by more than 60% compared with traditional processes, effectively cope with temperature cycling, thermal shock and other conditions, and significantly improve the stability of the device in long-term use through reliability assessment.
[0065] Figure 5 This diagram illustrates a structural block diagram of a warpage stress balancing system for an FC-PBGA circuit according to an exemplary embodiment of the present invention. The FC-PBGA circuit warpage stress balancing system includes:
[0066] The execution module 501 is used to flip-chip onto a plastic substrate and fix the chip underside.
[0067] The execution module 501 is also used to attach a heat sink to the chip surface in response to the chip underfill fixing; wherein the heat sink is square in shape and circular in inner cavity;
[0068] The balancing module 502 is used to balance the vertical stress caused by the warping of the plastic substrate by increasing the bonding area between the foot area of the heat sink and the plastic substrate.
[0069] The balancing module 502 is also used to balance the horizontal stress caused by the warping of the plastic substrate by combining the circular internal cavity of the heat sink with the force balancing interaction of the circle.
[0070] The control module 503 is used to control the stress acting on the chip area to be minimized by balancing the vertical stress caused by the warping of the plastic substrate and the horizontal stress caused by the warping of the plastic substrate.
[0071] The control module 503 is electrically connected to the execution module 501 and the balance module 502 to send control signals to the execution module 501 and the balance module 502 and to receive feedback signals from the balance module 502, thereby realizing the control of stress balance.
[0072] In one example, the control module can be a microcontroller (MCU). It acquires feedback signals from the stress sensors in the balancing module through an integrated ADC (analog-to-digital converter), calculates the signals using a built-in algorithm, and then controls the actions of the execution module through GPIO (general purpose input / output interface) or PWM (pulse width modulation) signals, thereby dynamically adjusting the stress balancing process.
[0073] In one possible implementation, the chip is flip-chip mounted on a plastic substrate, and the chip is fixed in place, including:
[0074] The chip is flip-chip onto a plastic substrate using a flip-chip reflow process, and the chip is fixed by underfill adhesive. The curing temperature of the underfill adhesive is controlled at 150-170℃, and the curing time is 90-120 minutes.
[0075] In one possible implementation, in response to the chip underfill being fixed, the heat sink is mounted onto the chip surface, including:
[0076] In response to the chip underfill fixation;
[0077] The foot area of the heat sink is bonded to the plastic substrate with AD adhesive, which serves to fix and dissipate heat.
[0078] The central area of the heat sink is bonded to the chip surface with Tim adhesive, serving both to fix the chip and dissipate heat.
[0079] In one possible implementation, the AD adhesive is a thermally conductive adhesive with high bonding strength and good heat dissipation performance, which counteracts the warping stress of the plastic substrate through high-strength bonding.
[0080] In one possible implementation, Tim adhesive is selected as a thermally conductive adhesive with weak bonding strength and good heat dissipation performance, which balances the warping stress applied to the chip area by the plastic substrate through low-strength bonding.
[0081] In one possible implementation, the coating thickness of AD adhesive and Tim adhesive is 50-100μm to ensure bonding effect and stress balance.
[0082] In one possible implementation, the inner cavity of the heat sink is circular, and the circular shape is used to balance the horizontal stress caused by the warping of the plastic substrate, including:
[0083] Based on the circular inner cavity of the heat sink, the warping stress area of the plastic substrate is divided into a circle.
[0084] By utilizing the characteristic that the stress direction of a circle is towards the center and the stress is equal in magnitude, the stress balance on the circular plane is canceled out, so as to achieve no horizontal stress acting on the chip area.
[0085] In one possible implementation, before flip-chip bonding onto the plastic substrate, the following is also included:
[0086] The surfaces of the chip and the plastic substrate to be bonded are cleaned and pretreated to remove surface contaminants.
[0087] In one possible implementation, the chip has a size of 5mm×5mm to 30mm×30mm, and the heat sink has a size of 10mm×10mm to 50mm×50mm, wherein the heat sink is made of copper alloy or Alsic.
[0088] It should be noted that the FC-PBGA circuit warpage stress balancing system provided in the above embodiments is only an example of the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the system can be divided into different functional modules to complete all or part of the functions described above.
[0089] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand this disclosure, and are not intended to limit the scope of the invention.
[0090] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this disclosure.
[0091] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and this disclosure does not limit them.
[0092] Unless otherwise stated, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0093] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.
Claims
1. A method for balancing warpage stress in an FC-PBGA circuit, characterized in that, The method includes: The chip is flip-chip mounted onto a plastic substrate, and the chip is then fixed in place. In response to the chip underfill being fixed, a heat sink is attached to the chip surface; wherein the heat sink is square in shape and has a circular inner cavity; By increasing the bonding area between the foot area of the heat sink and the plastic substrate, the vertical stress caused by the warping of the plastic substrate can be balanced. Based on the circular inner cavity of the heat sink, the force balance interaction of the circle is combined to balance the horizontal stress generated by the warping of the plastic substrate. By balancing the vertical stress caused by the warping of the plastic substrate and the horizontal stress caused by the warping of the plastic substrate, the stress acting on the chip area is minimized. The inner cavity of the heat sink is circular, and the circular shape facilitates force balance to counteract the horizontal stress caused by the warping of the plastic substrate, including: Based on the circular shape of the inner cavity of the heat sink, the warping stress area of the plastic substrate is divided into a circle. By utilizing the characteristic that the stress direction of a circle is towards the center and the stress is equal in magnitude, the stress balance on the circular plane is canceled out, so as to achieve no horizontal stress acting on the chip area.
2. The method for balancing the warpage stress of an FC-PBGA circuit according to claim 1, characterized in that, The step of flip-chipping onto a plastic substrate and fixing the chip to the substrate includes: The chip is flip-chipped onto a plastic substrate using a flip-chip reflow process, and the chip is fixed by underfill adhesive. The curing temperature of the underfill adhesive is controlled at 150-170℃, and the curing time is 90-120 minutes.
3. The method for balancing the warpage stress of an FC-PBGA circuit according to claim 1, characterized in that, The step of mounting a heat sink onto the chip surface in response to the chip underfill fixation includes: In response to the chip underfill being fixed; The foot area of the heat sink is bonded to the plastic substrate with AD adhesive, which serves to fix and dissipate heat. The central area of the heat sink is bonded to the surface of the chip using Tim adhesive, serving both heat dissipation and fixation purposes.
4. The method for balancing the warpage stress of an FC-PBGA circuit according to claim 3, characterized in that, The AD adhesive is a thermally conductive adhesive with high bonding strength and good heat dissipation performance, which can resist the warping stress of the plastic substrate through high-strength bonding.
5. The method for balancing the warpage stress of an FC-PBGA circuit according to claim 3, characterized in that, The Tim adhesive is a thermally conductive adhesive with low bonding strength and good heat dissipation performance. It balances the warping stress applied to the chip area by the plastic substrate through low-strength bonding.
6. The method for balancing the warpage stress of an FC-PBGA circuit according to claim 3, characterized in that, The coating thickness of the AD adhesive and the Tim adhesive is 50-100μm to ensure bonding effect and stress balance.
7. The method for balancing the warpage stress of an FC-PBGA circuit according to claim 1, characterized in that, Before flip-chip bonding onto the plastic substrate, the process also includes: The surfaces of the chip and the plastic substrate to be bonded are cleaned and pretreated to remove surface contaminants.
8. The method for balancing the warpage stress of an FC-PBGA circuit according to claim 1, characterized in that, The chip has an external dimension of 5mm×5mm to 30mm×30mm, and the heat sink has an external dimension of 10mm×10mm to 50mm×50mm. The heat sink is made of copper alloy or Alsic.
9. A system for balancing warpage stress in an FC-PBGA circuit, characterized in that, The system includes: An execution module is used to flip-chip onto a plastic substrate and fix the chip underside. The execution module is further configured to attach a heat sink to the surface of the chip after the chip substrate is fixed; wherein the heat sink is square in shape and has a circular inner cavity; A balancing module is used to balance the vertical stress caused by the warping of the plastic substrate by increasing the bonding area between the foot area of the heat sink and the plastic substrate. The balancing module is also used to balance the horizontal stress generated by the warping of the plastic substrate, based on the circular shape of the inner cavity of the heat sink and the force balance interaction of the circle. A control module is used to minimize the stress acting on the chip region by balancing the vertical stress caused by the warping of the plastic substrate and the horizontal stress caused by the warping of the plastic substrate. The control module is electrically connected to the execution module and the balancing module to send control signals to the execution module and the balancing module and to receive feedback signals from the balancing module, thereby achieving control of stress balance.