Operational amplifier and input stage circuit thereof

Abstract

The invention provides an operational amplifier and an input stage circuit thereof. The input stage circuit for the operational amplifier comprises: an input stage differential pair for providing differential input to the operational amplifier; the input voltage sampling circuit is used for sampling input voltage and providing the input voltage to the input stage differential pair and the input voltage sampling circuit; the input bias current compensation circuit obtains current from an upper end current source, obtains voltage from the input voltage sampling circuit, and compensates the bias current of the input stage differential pair based on the obtained current and voltage; the upper end current source is used for providing current for the input stage differential pair and the input voltage sampling circuit; and the lower end current source is used for providing current for the input stage differential pair and the input voltage sampling circuit. The compensation of input bias current is realized by adopting an input voltage synchronous compensation technology; in addition, the compensated current value does not change along with the change of the input voltage theoretically, and wider applicability is realized.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to an operational amplifier and its input stage circuit. Background Art

[0002] With the development of semiconductor technology, most operational amplifiers (abbreviated as "op-amps") exist in the form of single chips. There are a wide variety of op-amps, which are widely used in the electronics industry. In an actual circuit, it usually combines with a feedback network to form a certain functional module. In addition, it is an amplifier with a special coupling circuit and feedback. Its output signal can be the result of mathematical operations such as addition, subtraction, differentiation, or integration of the input signal. Since it was early applied in analog computers to implement mathematical operations, it got the name "operational amplifier".

[0003] Generally speaking, to make the operational amplifier obtain better performance, such as larger bandwidth, higher slew rate, lower noise, etc., it is necessary to increase the tail current, which will lead to an increase in the input bias current. However, the input bias current will generate an additional offset voltage drop at the input end, resulting in an offset error at the output end. This error may have little impact in most applications and can be ignored, but in some precision applications, it may cause a decrease in output accuracy and even affect the normal operation of the circuit; in addition, when the input end of the amplifier is grounded through a resistor, the input bias current will generate an unwanted input voltage on the resistor. This voltage will be amplified by the amplifier, further affecting the output result; moreover, in the case of a high source impedance, the input bias current will cause the source voltage to be lower than expected, thus affecting the stability of the circuit. Especially in applications that require high precision and stability, a high input bias current may cause abnormal behavior or failure of the circuit. Therefore, currently, a compensation circuit is often used to compensate for the input bias current, but there are still defects, that is, when the input voltage changes, the bias current will also change in the same proportion, and it cannot meet the requirements of low bias current or even zero bias current in some high-precision application scenarios. Therefore, a more effective and accurate input bias current compensation method is needed. Summary of the Invention

[0004] Aiming at the deficiencies in the prior art, the present invention provides an operational amplifier and its input stage circuit, which mainly solves the problem that there is a lack of a more effective and accurate input bias current compensation method in the prior art.

[0005] The object of the present invention is achieved through the following solutions:

[0006] In a first aspect, according to an embodiment of the present invention, there is provided an input stage circuit for an operational amplifier, including: an input stage differential pair for providing a differential input to the operational amplifier; an input voltage sampling circuit for sampling an input voltage and supplying it to the input stage differential pair and the input voltage sampling circuit; an input bias current compensation circuit for obtaining a current from an upper current source, obtaining a voltage from the input voltage sampling circuit, and compensating the bias current of the input stage differential pair based on the obtained current and voltage; an upper current source for supplying a current to the input stage differential pair and the input voltage sampling circuit; and a lower current source for supplying a current to the input stage differential pair and the input voltage sampling circuit.

[0007] According to an embodiment of the present invention, the input stage differential pair includes: a first N-type transistor having a base connected to a positive terminal input bias current and an emitter connected to the lower current source; a second N-type transistor having a base connected to a negative terminal input bias current and an emitter connected to the lower current source; a first P-type transistor having a base connected to a positive terminal input bias current and an emitter connected to the upper current source; and a second P-type transistor having a base connected to a negative terminal input bias current and an emitter connected to the upper current source.

[0008] According to an embodiment of the present invention, the input voltage sampling circuit includes: a tenth N-type transistor having a base connected to the upper current source, an emitter connected to the emitter of a tenth P-type transistor, and a collector connected to a positive power supply; and a tenth P-type transistor having a base connected to the lower current source and a collector connected to a negative power supply.

[0009] According to an embodiment of the present invention, the input bias current compensation circuit includes: a fifth P-type transistor, whose base and collector are connected to the collector of a ninth N-type transistor, and whose emitter is connected to a positive power supply; a sixth P-type transistor, whose base is connected to the base of the fifth P-type transistor, whose emitter is connected to the positive power supply, and whose collector is connected to the positive terminal input bias current; a seventh P-type transistor, whose base is connected to the base of the fifth P-type transistor, whose emitter is connected to the positive power supply, and whose collector is connected to the negative terminal input bias current; a ninth N-type transistor, whose base is connected to the emitter of a tenth N-type transistor, and whose emitter is connected to the emitter of a ninth P-type transistor; a ninth P-type transistor, whose base is connected to the emitter of the tenth N-type transistor, and whose collector is connected to the collector and base of a fifth N-type transistor; an eighth N-type transistor, whose base is connected to the emitter of the ninth N-type transistor, whose emitter is connected to the lower current source, and whose collector is connected to the positive power supply; an eighth P-type transistor, whose base is connected to the emitter of the ninth N-type transistor, whose emitter is connected to the upper current source, and whose collector is connected to the negative power supply; a fifth N-type transistor, whose emitter is connected to the negative power supply; a sixth N-type transistor, whose base is connected to the base of the fifth N-type transistor, whose emitter is connected to the negative power supply, and whose collector is connected to the positive terminal input bias current; a seventh N-type transistor, whose base is connected to the base of the fifth N-type transistor, whose emitter is connected to the negative power supply, and whose collector is connected to the negative terminal input bias current.

[0010] According to an embodiment of the present invention, the upper current source includes: a third P-type transistor, whose base is connected to the first conduction voltage, and whose emitter is connected to the positive power supply; a fourth P-type transistor, whose base is connected to the first conduction voltage, and whose emitter is connected to the positive power supply.

[0011] According to an embodiment of the present invention, the upper current source further includes: a third resistor, connected between the third P-type transistor and the positive power supply; a fourth resistor, connected between the fourth P-type transistor and the positive power supply.

[0012] According to an embodiment of the present invention, the fourth resistor is a variable resistance resistor.

[0013] According to an embodiment of the present invention, the lower current source includes: a third N-type transistor, whose base is connected to the second conduction voltage, and whose emitter is connected to the negative power supply; a fourth N-type transistor, whose base is connected to the second conduction voltage, and whose emitter is connected to the negative power supply.

[0014] According to an embodiment of the present invention, the lower current source further includes: a first resistor, connected between the third N-type transistor and the negative power supply; a second resistor, connected between the fourth N-type transistor and the negative power supply.

[0015] According to an embodiment of the present invention, the second resistor is a variable resistance resistor.

[0016] In a second aspect, according to another embodiment of the present invention, there is provided an operational amplifier, including an input stage circuit for an operational amplifier as described in the first aspect, and further comprising: an eleventh P-type transistor, whose base and collector are connected to the collector of the first N-type transistor, and whose emitter is connected to the positive power supply; a twelfth P-type transistor, whose base is connected to the collector of the first N-type transistor, whose emitter is connected to the positive power supply, and whose collector is connected to the collector of the second N-type transistor and serves as the output terminal.

[0017] In a third aspect, according to still another embodiment of the present invention, there is provided an operational amplifier, including an input stage circuit for an operational amplifier as described in the first aspect, and further comprising: an eleventh P-type transistor, whose base and collector are connected to the first current source, and whose emitter is connected to the positive power supply via the eleventh resistor; a twelfth P-type transistor, whose base is connected to the base of the eleventh P-type transistor, whose emitter is connected to the positive power supply via the twelfth resistor, and whose collector is connected to the output terminal; an eleventh N-type transistor, whose base and collector are connected to the second current source, and whose emitter is connected to the negative power supply via the thirteenth resistor; a twelfth N-type transistor, whose base is connected to the second current source, whose emitter is connected to the negative power supply via the fourteenth resistor, and whose collector is connected to the output terminal.

[0018] In a fourth aspect, according to still another embodiment of the present invention, there is provided an operational amplifier, including an input stage circuit for an operational amplifier as described in the first aspect, and further comprising: a fifth resistor, connected between the positive power supply and the collector of the first N-type transistor, and one end thereof is connected to the negative input terminal of the operational amplifier; a sixth resistor, connected between the positive power supply and the collector of the second N-type transistor, and one end thereof is connected to the positive input terminal of the operational amplifier.

[0019] Compared with the prior art, the present invention has the following beneficial effects: By adopting the input voltage synchronous compensation technology, the compensation of the input bias current is realized; in addition, the compensated current value theoretically does not change with the change of the input voltage, achieving a wider applicability. For operational amplifiers with an input bias current lower than 1 nA, the input voltage synchronous compensation technology has great performance advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following further describes the embodiments of the present invention with reference to the accompanying drawings:

[0021] Figure 1 is a structural diagram of a typical operational amplifier circuit in the prior art;

[0022] Figure 2It is a circuit structure diagram of an operational amplifier circuit with an input bias current compensation circuit typical in the prior art;

[0023] Figure 3 It is a circuit structure diagram of the input stage circuit of the operational amplifier according to an embodiment of the present invention;

[0024] Figure 4 It is a circuit structure diagram of the operational amplifier according to an embodiment of the present invention;

[0025] Figure 5 It is a circuit structure diagram of another operational amplifier according to an embodiment of the present invention;

[0026] Figure 6 It is a circuit structure diagram of yet another operational amplifier according to an embodiment of the present invention. Detailed implementation manners

[0027] [[ID=2))Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "coupled", "connected", and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit", "receive", and "communicate" and their derivatives encompass direct and indirect communication. The terms "comprise" and "include" and their derivatives mean including but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with" and its derivatives mean including, included within, interconnected, containing, contained within, connected or coupled with, communicating with, cooperating with, interwoven, juxtaposed, adjacent, bound or bound to, having, having an attribute, having a relationship or having a relationship with, etc. The term "controller" refers to any device, system, or part thereof that controls at least one operation. Such a controller can be implemented in hardware, or in a combination of hardware and software and / or firmware. The functions associated with any particular controller can be centralized or distributed, whether local or remote. The phrase "at least one", when used in conjunction with a list of items, means that different combinations of one or more of the listed items can be used, and it may only be necessary to have one item in the list. For example, "at least one of A, B, C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0028] Definitions of other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many cases, if not most cases, such definitions apply to the prior and future use of the words and phrases so defined.

[0029] In this patent document, the application combinations of modules and the hierarchical divisions of sub-modules are only for illustration purposes. Without departing from the scope of the present disclosure, the application combinations of modules and the hierarchical divisions of sub-modules can have different forms.

[0030] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0031] To better understand the present invention, first review the operational amplifiers in the prior art.

[0032] As Figure 1 shown, a typical operational amplifier structure is presented, where N1 and N2 are the input-stage differential pair, N3 provides the tail current, R1 and R2 are the input-stage loads, and A is the post-stage amplification circuit.

[0033] In the present invention, PX (the XP-type transistor, such as the first / second / third P-type transistor) represents a certain PNP device, where P represents the PNP bipolar transistor symbol, X represents the device number, and the numbers are Arabic numerals such as 1, 2, 3, etc.; NX (the XN-type transistor, such as the first / second / third N-type transistor) represents a certain NPN device, where N represents the NPN bipolar transistor symbol, X represents the device number, and the numbers are Arabic numerals such as 1, 2, 3, etc.; RX (the Xth resistor) represents a certain resistance element, where R represents the resistance element symbol, X represents the element number, and the numbers are Arabic numerals such as 1, 2, 3, etc.; VCC is the positive power supply of the chip, VEE is the negative power supply of the chip; IN+ is the positive input terminal of the operational amplifier, IN- is the negative input terminal of the operational amplifier, and OUT is the output terminal of the operational amplifier.

[0034] As Figure 1 shown, for matching purposes, usually K N1N2 = K R1R2 = 1.

[0035] In the present invention, K XYXZ represents the ratio of the emitter areas of bipolar transistor devices XY and XZ, where X represents the device type, being P or N; X and Y respectively represent two active device numbers, which are Arabic numerals such as 1, 2, 3, etc.

[0036] In the present invention, K RXRY represents the ratio of the resistance value R X to the resistance value R Y , where R represents the resistance element symbol, and X and Y respectively represent two resistance element numbers, which are Arabic numerals such as 1, 2, 3, etc.

[0037] AsFigure 1 As shown, I N1B = I N2B = I N3C / (2β N ). I N1B and I N2B are the input bias currents of the operational amplifier, and I N3C is the tail current of the differential pair.

[0038] In the present invention, I PXY represents the current of a certain port of a certain PNP device, where I represents the current symbol, and in the subscript PXY, P represents the PNP bipolar transistor symbol, X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.; Y represents the port of the device, which are C (collector), B (base), and E (emitter) respectively. I NXY represents the current of a certain port of a certain NPN device, where I represents the current symbol, and in the subscript NXY, N represents the NPN bipolar transistor symbol, X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.; Y represents the port of the device, which are C (collector), B (base), and E (emitter) respectively.

[0039] In the present invention, β P represents the current amplification factor of the PNP device; β N represents the current amplification factor of the NPN device.

[0040] Generally speaking, to make the operational amplifier obtain better performance, such as larger bandwidth, higher slew rate, lower noise, etc., it is necessary to increase the tail current I N3C , which will lead to an increase in the input bias current.

[0041] For the above structure, as Figure 2 shown is the traditional input bias current compensation method, where K N4N6 = 1, so I N4C = I N6C = K N4N3 I N3C .

[0042] As Figure 2 shown, I N5B ≈ I N4C / β N = K N4N3 I N3C / β N .

[0043] As Figure 2 shown, P1 and P2 form a current mirror, I P2C ≈ K P2P1 I P1C = K P2P1 IN5B ≈K P2P1 K N4N3 I N3C / β N 。

[0044] As Figure 2 shown, for the design K P2P1 K N4N3 = 1 / 2, then I P2C ≈I N3C / (2β N ) = I N1B . Therefore, the compensation circuit formed by N4, N5, P1, and P2 can compensate the input bias current of the positive input terminal.

[0045] As Figure 2 shown, similarly, the compensation circuit formed by N6, N7, P3, and P4 can compensate the input bias current of the negative input terminal.

[0046] As Figure 2 shown, its input bias current compensation method has defects. Assume that the input voltage changes by ΔV IN , then V N3C also changes by ΔV IN .

[0047] In the present invention, V PXY represents the voltage of a certain port of a certain PNP device, where V represents the voltage symbol, and in the subscript PXY, P represents the PNP bipolar transistor symbol, X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.; Y represents the port of the device, which are C (collector), B (base), and E (emitter) respectively. V NXY represents the voltage of a certain port of a certain NPN device, where V represents the voltage symbol, and in the subscript NXY, N represents the NPN bipolar transistor symbol, X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.; Y represents the port of the device, which are C (collector), B (base), and E (emitter) respectively.

[0048] As Figure 2 shown, due to the influence of the Early effect, the input bias current is affected by the input voltage. According to the properties of the transistor, there is:

[0049]

[0050] Calculated,

[0051]

[0052] When V IN does not change, I N1B = I N3C / (2β N ), so IN1B The change amount is:

[0053]

[0054] As Figure 2 shown, the change amount of I P2C is:

[0055]

[0056] In the present invention, V EP represents the Early voltage of the PNP device; V EN represents the Early voltage of the NPN device.

[0057] As Figure 2 shown, when the compensation design is good, there is I P2C ≈I N3C / (2β N ). Substituting this into the expression of ΔI P2C can obtain:

[0058]

[0059] It can be calculated that the change amount of the final input bias current is:

[0060]

[0061] It can be seen that since V EN and 2V EP are not equal, when the input voltage V IN changes, the bias current I IN+ at the positive input terminal also changes, and as ΔV IN increases, ΔI IN+ also increases. Similarly, the bias current I IN- at the negative input terminal also changes in the same proportion.

[0062] To address the above problems, as Figure 3As shown, according to an embodiment of the present invention, an input stage circuit for an operational amplifier is provided, including: an input stage differential pair 100 for providing a differential input to the operational amplifier; an input voltage sampling circuit 200 for sampling the input voltage and providing it to the input stage differential pair 100 and the input voltage sampling circuit 200; an input bias current compensation circuit 200 for obtaining a current from an upper current source 400, obtaining a voltage from the input voltage sampling circuit 300, and compensating the bias current of the input stage differential pair 100 based on the obtained current and voltage; an upper current source 400 for providing a current to the input stage differential pair 100 and the input voltage sampling circuit 200; and a lower current source for providing a current to the input stage differential pair 100 and the input voltage sampling circuit 200.

[0063] By adopting the input voltage synchronous compensation technology, the compensation of the input bias current is achieved; in addition, the compensated current value theoretically does not change with the change of the input voltage, achieving a wider applicability. For operational amplifiers with an input bias current lower than 1 nA, the input voltage synchronous compensation technology has great performance advantages.

[0064] In order to enhance the anti-interference ability of the circuit, improve the common-mode rejection ratio of the circuit, and effectively reduce noise and distortion, an input stage differential pair is adopted. According to an embodiment of the present invention, the input stage differential pair 100 includes: a first N-type transistor, whose base is connected to the positive input bias current and whose emitter is connected to the lower current source; a second N-type transistor, whose base is connected to the negative input bias current and whose emitter is connected to the lower current source; a first P-type transistor, whose base is connected to the positive input bias current and whose emitter is connected to the upper current source; and a second P-type transistor, whose base is connected to the negative input bias current and whose emitter is connected to the upper current source. Specifically, the non-inverting input terminal is connected to the positive extreme of the signal source, while the inverting input terminal is connected to the negative extreme of the signal source. This configuration enables the op-amp to amplify the voltage difference between the two input terminals, thereby achieving precise signal processing. In addition, since the two input terminals respond differently to noise, the differential amplifier can effectively cancel out the common-mode signal, that is, the common noise of the two input terminals. This enables the differential input circuit to maintain a high signal quality even in a harsh electromagnetic environment. In addition, the differential input can also provide a higher signal-to-noise ratio, which is particularly important for applications that require high precision and high reliability.

[0065] In addition, in order to quickly track the change of the input signal and stabilize the value of the output signal during the holding stage, an input voltage sampling circuit is adopted. Referring again to Figure 3, according to an embodiment of the present invention, the input voltage sampling circuit 300 includes: a tenth N-type transistor, whose base is connected to the upper current source, whose emitter is connected to the emitter of the tenth P-type transistor, and whose collector is connected to the positive power supply; a tenth P-type transistor, whose base is connected to the lower current source, and whose collector is connected to the negative power supply. The sampled input voltage is used for subsequent processing by the operational amplifier. For example, bias current compensation is performed specifically.

[0066] In addition, in order to perform bias current compensation for different input voltages, the input bias current compensation circuit is adopted. As Figure 2 shown, according to an embodiment of the present invention, the input bias current compensation circuit 200 includes: a fifth P-type transistor, whose base and collector are connected to the collector of the ninth N-type transistor, and whose emitter is connected to the positive power supply; a sixth P-type transistor, whose base is connected to the base of the fifth P-type transistor, whose emitter is connected to the positive power supply, and whose collector is connected to the positive terminal input bias current; a seventh P-type transistor, whose base is connected to the base of the fifth P-type transistor, whose emitter is connected to the positive power supply, and whose collector is connected to the negative terminal input bias current; a ninth N-type transistor, whose base is connected to the emitter of the tenth N-type transistor, and whose emitter is connected to the emitter of the ninth P-type transistor; a ninth P-type transistor, whose base is connected to the emitter of the tenth N-type transistor, and whose collector is connected to the collector and base of the fifth N-type transistor; an eighth N-type transistor, whose base is connected to the emitter of the ninth N-type transistor, whose emitter is connected to the lower current source, and whose collector is connected to the positive power supply; an eighth P-type transistor, whose base is connected to the emitter of the ninth N-type transistor, whose emitter is connected to the upper current source, and whose collector is connected to the negative power supply; a fifth N-type transistor, whose emitter is connected to the negative power supply; a sixth N-type transistor, whose base is connected to the base of the fifth N-type transistor, whose emitter is connected to the negative power supply, and whose collector is connected to the positive terminal input bias current; a seventh N-type transistor, whose base is connected to the base of the fifth N-type transistor, whose emitter is connected to the negative power supply, and whose collector is connected to the negative terminal input bias current. By adopting the input voltage synchronous compensation technology, the compensation of the input bias current is realized; in addition, the compensated current value theoretically does not change with the change of the input voltage, achieving a wider applicability.

[0067] In order to supply current to the differential input pair and the input bias current compensation circuit, as Figure 3 shown, according to an embodiment of the present invention, the upper current source 400 includes: a third P-type transistor, whose base is connected to the first conduction voltage, and whose emitter is connected to the positive power supply; a fourth P-type transistor, whose base is connected to the first conduction voltage, and whose emitter is connected to the positive power supply. The first conduction voltage is set as the conduction voltage of the third P-type transistor and the fourth P-type transistor.

[0068] Alternatively, in order to limit the current in the circuit and prevent excessive current from burning out components, according to an embodiment of the present invention, the upper current source 400 further includes: a third resistor connected between the third P-type transistor and the positive power supply; a fourth resistor connected between the fourth P-type transistor and the positive power supply. In some cases, resistors can also be used to protect the circuit from overvoltage or overcurrent.

[0069] In addition, in order to further improve the compensation accuracy of the input bias current compensation circuit 200 for the input bias current, according to an embodiment of the present invention, the fourth resistor is a variable resistance resistor.

[0070] In order to provide a tail current to the differential input pair and the input bias current compensation circuit, as Figure 3 shown, according to an embodiment of the present invention, the lower current source 500 includes: a third N-type transistor whose base is connected to the second conduction voltage and whose emitter is connected to the negative power supply; a fourth N-type transistor whose base is connected to the second conduction voltage and whose emitter is connected to the negative power supply. The second conduction voltage is set to the conduction voltages of the third P-type transistor and the fourth P-type transistor.

[0071] Similarly, in order to limit the current in the circuit and prevent excessive current from burning out components, the lower current source 500 further includes: a first resistor connected between the third N-type transistor and the negative power supply; a second resistor connected between the fourth N-type transistor and the negative power supply.

[0072] Similarly, in order to further improve the compensation accuracy of the input bias current compensation circuit 200 for the input bias current, according to an embodiment of the present invention, the second resistor is a variable resistance resistor.

[0073] The working principle of the input stage circuit according to an embodiment of the present invention is as follows.

[0074] As Figure 3 shown, I P1C , I P2C are a set of output currents of this circuit; I N1C , I N2C are another set of output currents of this circuit. One or both sets can be selected as the output according to needs.

[0075] As Figure 3 shown, I P8B ≈I P4C / β P , I N8B ≈I N4C / β N .

[0076] As Figure 3 shown, if IP8B >I N8B , then I P9C ≈I P8B -I N8B , I N9C =0. At this time, due to the mirror image relationship of P5, P6, P7 and the mirror image relationship of N5, N6, N7, there is I P6C =I P7C =0, I N6C =K N6N5 I P9C , I N7C =K N7N5 I P9C .

[0077] As Figure 3 shown, for the consideration of device matching, generally design K P6P7 =K N6N7 =1. Therefore, there is I N6C =I N7C =K N6N5 I P9C =K N6N5 (I P8B -I N8B )=K N6N5 (I P4C / β P -I N4C / β N ).

[0078] As Figure 3 shown, for the consideration of device matching, generally design K P1P2 =K N1N2 =1. Therefore, there is I P1C =I P2C ≈I P3C / 2, I N1C =I N2C ≈I N3C / 2.

[0079] As Figure 3 shown, for the consideration of component matching, generally design K P3P4 =K R4R3 =K N3N4 =K R2R1 , and I P3C =I N3C . Therefore, there is I P4C =I N4C =K N4N3 I N3C .

[0080] As Figure 3 shown, based on the above calculations, the positive terminal input bias current I IN+and the negative terminal input bias current I IN- is equal, and

[0081]

[0082]

[0083] It can be seen that when K N6N5 K N4N3 = 0.5, the input bias current is 0.

[0084] Similarly, as Figure 3 shown, if I P8B < I N8B , when K P6P5 K P4P3 = 0.5, the input bias current is 0.

[0085] As Figure 3 shown, designing K N6N5 K N4N3 = K P6P5 K P4P3 = 0.5 can reduce the input bias current to a very small level. In fact, after appropriately trimming R2 and R4, the input bias current can be reduced below 1 nA, while without input bias current compensation, this value is usually above 1 μA.

[0086] As Figure 3 shown, if I P8B > I N8B , when the input voltage changes by ΔV IN , the change in the base current of N1 is

[0087]

[0088] The change in the base current of P1 is:

[0089]

[0090] As Figure 3 shown, since the BE junction voltage of the triode working in the amplification region is almost constant, therefore, under the action of the input bias current compensation circuit 200 and the input voltage sampling circuit 300, the voltage change amounts at the positive and negative input terminals are equal to the base voltage change amounts of P8 and N8. Thus, the change in the base current of N8 is

[0091]

[0092] The change in the base current of P8 is:

[0093]

[0094] Then the change in the collector current of N6 is:

[0095]

[0096] Therefore, the total change in the bias current at the positive input terminal is:

[0097]

[0098] Similarly, the total change in the bias current at the negative input terminal is also 0.

[0099] Similarly, if I P8B <I N8B , the total change in the bias current at the positive and negative input terminals is also 0.

[0100] In summary, the circuit adopts the input voltage synchronous compensation technology, which not only compensates the input bias current, but also the compensated current value theoretically does not change with the change of the input voltage.

[0101] Taking the Early voltages of NPN and PNP both being 100V and the current gains both being 100 as an example, if the input voltage changes by 10V, the input bias current without compensation measures is 1 μA, and after compensation it is 0. When the input voltage synchronous compensation technology is not adopted, if the input voltage changes by 10V, the input bias current will change by 0.1 μA; when the input voltage synchronous compensation technology is adopted, without considering mismatch and parasitics, the input bias current will not change at all. It can be seen that for operational amplifiers with an input bias current lower than 1 nA, the input voltage synchronous compensation technology has great performance advantages.

[0102] As Figure 4 shown, according to another embodiment of the present invention, an operational amplifier is provided, which includes an input stage circuit for an operational amplifier as described above, and further includes: an eleventh P-type transistor, whose base and collector are connected to the collector of the first N-type transistor, and whose emitter is connected to the positive power supply; a twelfth P-type transistor, whose base is connected to the collector of the first N-type transistor, whose emitter is connected to the positive power supply, and whose collector is connected to the collector of the second N-type transistor and serves as the output terminal. The operational amplifier is a dual-input, single-output operational amplifier.

[0103] As Figure 5As shown, according to another embodiment of the present invention, an operational amplifier is provided, which includes an input stage circuit for an operational amplifier as described above, and further includes: an eleventh P-type transistor, whose base and collector are connected to a first current source, and whose emitter is connected to a positive power supply through an eleventh resistor; a twelfth P-type transistor, whose base is connected to the base of the eleventh P-type transistor, whose emitter is connected to the positive power supply through a twelfth resistor, and whose collector is connected to the output terminal; an eleventh N-type transistor, whose base and collector are connected to a second current source, and whose emitter is connected to a negative power supply through a thirteenth resistor; a twelfth N-type transistor, whose base is connected to the second current source, whose emitter is connected to the negative power supply through a fourteenth resistor, and whose collector is connected to the output terminal. The operational amplifier is a folded input and output rail-to-rail operational amplifier.

[0104] As Figure 6 As shown, according to another embodiment of the present invention, an operational amplifier is provided, which includes an input stage circuit for an operational amplifier as described above, and further includes: a fifth resistor connected between the positive power supply and the collector of the first N-type transistor, and one end of which is connected to the negative input terminal of the operational amplifier; a sixth resistor connected between the positive power supply and the collector of the second N-type transistor, and one end of which is connected to the positive input terminal of the operational amplifier. The operational amplifier is a differential input and single-ended output operational amplifier.

[0105] In summary, for the input stage circuit of the low bias current operational amplifier of the present invention, due to the input bias current compensation function, the input bias current is effectively reduced. By adopting input voltage synchronous compensation, the problem that the input bias current varies with the input voltage in traditional compensation technologies is solved, which has great advantages in low bias current operational amplifiers.

[0106] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An input stage circuit for an operational amplifier, characterized in that, Comprising: An input - stage differential pair for providing a differential input to an operational amplifier; An input - voltage sampling circuit for sampling an input voltage and providing it to the input - stage differential pair and the input - voltage sampling circuit; An input - bias - current compensation circuit that obtains a current from an upper - end current source, obtains a voltage from the input - voltage sampling circuit, and compensates the bias current of the input - stage differential pair based on the obtained current and voltage; An upper - end current source for providing current to the input - stage differential pair and the input - voltage sampling circuit; A lower - end current source for providing current to the input - stage differential pair and the input - voltage sampling circuit.

2. The input stage circuit for an operational amplifier according to claim 1, characterized in that, The input - stage differential pair includes: A first N - type transistor whose base is connected to a positive - terminal input bias current and whose emitter is connected to the lower - end current source; A second N - type transistor whose base is connected to a negative - terminal input bias current and whose emitter is connected to the lower - end current source; A first P - type transistor whose base is connected to a positive - terminal input bias current and whose emitter is connected to the upper - end current source; A second P - type transistor whose base is connected to a negative - terminal input bias current and whose emitter is connected to the upper - end current source.

3. The input stage circuit for an operational amplifier according to claim 1, wherein The input - voltage sampling circuit includes: A tenth N - type transistor whose base is connected to the upper - end current source, whose emitter is connected to the emitter of a tenth P - type transistor, and whose collector is connected to a positive power supply; A tenth P - type transistor whose base is connected to the lower - end current source and whose collector is connected to a negative power supply.

4. The input stage circuit for an operational amplifier according to claim 1, wherein The input - bias - current compensation circuit includes: A fifth P - type transistor whose base and collector are connected to the collector of a ninth N - type transistor and whose emitter is connected to a positive power supply; A sixth P - type transistor whose base is connected to the base of the fifth P - type transistor, whose emitter is connected to a positive power supply, and whose collector is connected to a positive - terminal input bias current; A seventh P - type transistor whose base is connected to the base of the fifth P - type transistor, whose emitter is connected to a positive power supply, and whose collector is connected to a negative - terminal input bias current; A ninth N - type transistor whose base is connected to the emitter of a tenth N - type transistor and whose emitter is connected to the emitter of a ninth P - type transistor; A ninth P - type transistor whose base is connected to the emitter of a tenth N - type transistor and whose collector is connected to the collector and base of a fifth N - type transistor; An eighth N - type transistor whose base is connected to the emitter of a ninth N - type transistor, whose emitter is connected to the lower - end current source, and whose collector is connected to a positive power supply; An eighth P - type transistor whose base is connected to the emitter of a ninth N - type transistor, whose emitter is connected to the upper - end current source, and whose collector is connected to a negative power supply; A fifth N - type transistor whose emitter is connected to a negative power supply; A sixth N - type transistor whose base is connected to the base of the fifth N - type transistor, whose emitter is connected to a negative power supply, and whose collector is connected to a positive - terminal input bias current; A seventh N - type transistor whose base is connected to the base of the fifth N - type transistor, whose emitter is connected to a negative power supply, and whose collector is connected to a negative - terminal input bias current.

5. The input stage circuit for an operational amplifier according to claim 1, characterized in that, The upper - end current source includes: A third P - type transistor whose base is connected to a first conduction voltage and whose emitter is connected to a positive power supply; A fourth P-type transistor, whose base is connected to the first conduction voltage and whose emitter is connected to the positive power supply.

6. The input stage circuit for an operational amplifier according to claim 5, characterized in that, The upper current source further includes: A third resistor connected between the third P-type transistor and the positive power supply; A fourth resistor connected between the fourth P-type transistor and the positive power supply.

7. The input stage circuit for an operational amplifier according to claim 6, characterized in that, The fourth resistor is a variable resistance resistor.

8. The input stage circuit for an operational amplifier according to claim 1, wherein, The lower current source includes: A third N-type transistor, whose base is connected to the second conduction voltage and whose emitter is connected to the negative power supply; A fourth N-type transistor, whose base is connected to the second conduction voltage and whose emitter is connected to the negative power supply.

9. The input stage circuit for an operational amplifier according to claim 8, characterized in that, The lower current source further includes: A first resistor connected between the third N-type transistor and the negative power supply; A second resistor connected between the fourth N-type transistor and the negative power supply.

10. The input stage circuit for an operational amplifier according to claim 9, characterized in that, The second resistor is a variable resistance resistor.

11. An operational amplifier, characterized in that, An input stage circuit for an operational amplifier including any one of claims 1-10 further includes: An eleventh P-type transistor, whose base and collector are connected to the collector of the first N-type transistor and whose emitter is connected to the positive power supply; A twelfth P-type transistor, whose base is connected to the collector of the first N-type transistor, whose emitter is connected to the positive power supply, and whose collector is connected to the collector of the second N-type transistor and serves as the output terminal.

12. An operational amplifier, characterized in that, An input stage circuit for an operational amplifier including any one of claims 1-10 further includes: An eleventh P-type transistor, whose base and collector are connected to the first current source and whose emitter is connected to the positive power supply via an eleventh resistor; A twelfth P-type transistor, whose base is connected to the base of the eleventh P-type transistor, whose emitter is connected to the positive power supply via a twelfth resistor, and whose collector is connected to the output terminal; An eleventh N-type transistor, whose base and collector are connected to the second current source and whose emitter is connected to the negative power supply via a thirteenth resistor; A twelfth N-type transistor, whose base is connected to the second current source, whose emitter is connected to the negative power supply via a fourteenth resistor, and whose collector is connected to the output terminal.

13. An operational amplifier, characterized in that, An input stage circuit for an operational amplifier including any one of claims 1-10 further includes: A fifth resistor connected between the positive power supply and the collector of the first N-type transistor, and one end thereof is connected to the negative input terminal of the operational amplifier; A sixth resistor connected between the positive power supply and the collector of the second N-type transistor, and one end thereof is connected to the positive input terminal of the operational amplifier.

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