Method of manufacturing a semiconductor structure

Abstract

The application relates to the technical field of integrated circuits, in particular to a preparation method of a semiconductor structure. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a first semiconductor intermediate layer on one side of the substrate, the first semiconductor intermediate layer is provided with a groove, the groove is provided with a gate dielectric layer and a gate structure, and the first semiconductor intermediate layer has a first conductive type; performing a patterning treatment on the first semiconductor intermediate layer to form a first opening, the first opening is arranged in a spaced mode with the gate dielectric layer, the first opening extends from the side of the first semiconductor layer away from the substrate to the inside of the first semiconductor layer, and the remaining first semiconductor intermediate layer forms a first semiconductor layer; and filling the first opening to form a second semiconductor layer, the second semiconductor layer has the first conductive type. According to the application, the concentration of the semiconductor layer close to the gate dielectric layer is low, and the concentration of the semiconductor layer far away from the channel is high, so that the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] An IGBT (Insulated Gate Bipolar Transistor) is a power semiconductor device that combines the advantages of a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) and a bipolar junction transistor (BJT). It is widely used in medium- and high-power electronic devices. The IGBT core structure consists of four semiconductor layers (PNPN), primarily comprising the emitter, N-type base (drift region), P-type base, and collector. The gate controls the channel through an oxide layer.

[0003] IGBTs have become a core component of modern power electronics due to their high efficiency and reliability. Therefore, how to further improve the performance of IGBTs has become an important issue that needs to be addressed urgently. Summary of the Invention

[0004] Based on this, it is necessary to provide a method for preparing a semiconductor structure, so as to effectively improve the working performance of the IGBT.

[0005] In order to achieve the above objectives, the present invention provides, in one aspect, a method for preparing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming a first semiconductor intermediate layer on one side of the substrate, wherein the first semiconductor intermediate layer has a trench, a gate dielectric layer and a gate structure are disposed in the trench, and the first semiconductor intermediate layer has a first conductivity type;

[0008] Performing a patterning process on the first semiconductor intermediate layer to form a first opening, wherein the first opening is spaced apart from the gate dielectric layer, and the first opening extends from a side of the first semiconductor layer away from the substrate to an interior of the first semiconductor layer, and the remaining first semiconductor intermediate layer forms a first semiconductor layer;

[0009] The first opening is filled to form a second semiconductor layer, wherein the second semiconductor layer has a first conductivity type.

[0010] In one embodiment, the distance between the sidewall of the first opening and the gate dielectric layer is between 0.1 μm and 1.0 μm.

[0011] In one embodiment, the depth of the first opening is between 0.6 μm and 4.0 μm, and the width of the first opening is between 0.2 μm and 20 μm.

[0012] In one embodiment, before forming the first semiconductor layer on one side of the substrate, the method includes:

[0013] A third semiconductor layer is formed on one side of the substrate, wherein the third semiconductor layer has a second conductivity type.

[0014] In one embodiment, after forming the third semiconductor layer on one side of the substrate, the method further comprises:

[0015] forming a first semiconductor initial layer on a side of the third semiconductor layer away from the substrate;

[0016] Performing a patterning process on the first semiconductor initial layer to form a trench in the first semiconductor initial layer, wherein the trench extends from a side of the first semiconductor initial layer away from the substrate through the third semiconductor layer into the substrate, and the remaining first semiconductor initial layer forms the first semiconductor intermediate layer;

[0017] Filling the trench to form the gate dielectric layer and the gate structure;

[0018] Ion implantation is performed on the first semiconductor intermediate layer.

[0019] In one embodiment, filling the first opening to form the second semiconductor layer includes:

[0020] forming a second semiconductor initial layer in the first opening and on a side of the first semiconductor layer away from the substrate;

[0021] The second semiconductor initial layer located outside the first opening is removed, and the remaining second semiconductor initial layer forms a second semiconductor layer.

[0022] In one embodiment, the second semiconductor layer has an edge region and a central region, and the edge region surrounds the central region;

[0023] After filling the first opening to form the second semiconductor layer, the method includes:

[0024] Implanting ions of the second conductivity type into the edge region to form a doped region in the edge region;

[0025] A first metal layer is formed on a side of the second semiconductor layer and the doped region away from the substrate.

[0026] In one embodiment, before forming the first metal layer on the side of the second semiconductor layer and the doped region away from the substrate, the method includes:

[0027] forming a dielectric material layer on a side of the second semiconductor layer and the doped region away from the substrate;

[0028] Performing a patterning process on the dielectric material layer to form a second opening in the dielectric material layer, wherein the second opening exposes the second semiconductor layer, and the remaining dielectric material layer forms a dielectric layer;

[0029] The first metal layer is formed on a side of the second semiconductor layer and the doped region away from the substrate, comprising:

[0030] A first metal layer is formed in the second opening and on a side of the dielectric layer away from the substrate.

[0031] In one embodiment, the depth of the second opening is in the range of 0.3 μm-0.5 μm, and / or the width of the second opening is in the range of 0.1 μm-4.0 μm.

[0032] In one embodiment, after forming the first metal layer on the side of the second semiconductor layer and the doped region away from the substrate, the method includes:

[0033] forming a fourth semiconductor layer on the other side of the substrate, wherein the fourth semiconductor layer has a second conductivity type;

[0034] forming a fifth semiconductor layer on a side of the fourth semiconductor away from the substrate, wherein the fifth semiconductor layer has a first conductivity type;

[0035] A second metal layer is formed on a side of the fifth semiconductor layer away from the substrate.

[0036] The semiconductor structure has the following beneficial effects: by forming a first opening through patterning the first semiconductor intermediate layer, and then filling the first opening to obtain a second semiconductor layer with the first conductivity type, the concentration near the channel position of the semiconductor structure (Trench IGBT) can be quickly and accurately adjusted, and better device characteristics can be achieved. For example, in this application, the ion concentration of the semiconductor layer near the gate dielectric layer is low, and the ion concentration of the semiconductor layer away from the channel is high, so that the semiconductor structure can normally form a channel depletion layer when the gate control voltage is low, and when a high gate control voltage is applied, the widening of the channel depletion layer is limited by the increase in ion concentration, thereby controlling the channel resistance under high gate control voltage to achieve the effect of controlling the maximum saturation current. It can be understood that the semiconductor structure of the present application is basically not affected by the on-state voltage drop under normal working current. In the case of short circuit, the saturation current capacity of the semiconductor structure can be compressed through the related parameters of the channel. At the same time, the enhanced ion concentration distribution also reduces the lateral parasitic resistance in the body, thereby reducing the conduction of the parasitic PNPN device of the semiconductor structure. Further, the adjusted concentration distribution of the present application can also shorten the widening of the depletion layer in the P-body under voltage, reduce the junction depth of the body, thereby reducing the length of the channel, and further reducing the channel resistance of the semiconductor structure and the internal resistance of the semiconductor structure. Finally, the semiconductor structure provided by the present application has a higher concentration of semiconductor layers away from the channel, which can also compress the lateral widening of the depletion layer and limit its expansion near the high-doped region. Even if the collector voltage increases, the depletion layer widening is blocked by the high-doped region, thereby stabilizing the channel length and preventing the length of the channel from decreasing. In addition, the semiconductor structure provided by the embodiment can significantly reduce the probability of latch-up of the IGBT device. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0038] Figure 1 The flowchart of the preparation method of the semiconductor structure provided in an embodiment;

[0039] Figure 2 The schematic diagram of the semiconductor structure provided in the first embodiment;

[0040] Figure 3 The schematic diagram of the semiconductor structure provided in the second embodiment;

[0041] Figure 4 A schematic diagram of a semiconductor structure provided in a third embodiment;

[0042] Figure 5 is a schematic diagram of a semiconductor structure provided in a fourth embodiment;

[0043] Figure 6 is a schematic diagram of a semiconductor structure provided in a fifth embodiment;

[0044] Figure 7 is a schematic diagram of a semiconductor structure provided in a sixth embodiment;

[0045] Figure 8 is a schematic diagram of a semiconductor structure provided in a seventh embodiment;

[0046] Figure 9 is a schematic diagram of a semiconductor structure provided in an eighth embodiment;

[0047] Figure 10 is a schematic diagram of a semiconductor structure provided in a ninth embodiment;

[0048] Figure 11 is a schematic diagram of a semiconductor structure provided in a tenth embodiment;

[0049] Figure 12 A schematic diagram of a test of a semiconductor structure provided in one embodiment;

[0050] Figure 13 A schematic diagram of a test of a semiconductor structure provided in another embodiment;

[0051] Figure 14 A schematic diagram of testing a semiconductor structure provided in yet another embodiment.

[0052] Explanation of the accompanying drawings: semiconductor structure-100; substrate-110; first semiconductor layer-120; first semiconductor initial layer-121; first semiconductor intermediate layer-122; gate dielectric layer-130; gate structure-131; second semiconductor layer-140; second semiconductor initial layer-141; third semiconductor layer-150; doped region-160; first metal layer-170; second metal layer-171; dielectric layer-180; fourth semiconductor layer-190; fifth semiconductor layer-191; trench-200; first opening-210; second opening-220. DETAILED DESCRIPTION

[0053] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0055] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0056] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0057] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of the regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region illustrated as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions illustrated in the figures are schematic in nature, their shapes do not represent the actual shapes of regions of a device, and are not intended to limit the scope of the invention.

[0059] In one embodiment, see Figure 1 , provides a method for preparing a semiconductor structure 100. The semiconductor structure 100 may include but is not limited to IGBT, Trench MOS (trench MOSFET), SGT MOS (split gate trench MOS), etc. Figures 2 to 11 , the figure is a schematic diagram of an intermediate structure obtained when the semiconductor structure 100 is prepared using the method for preparing the semiconductor structure 100 of the present application. The method for preparing the semiconductor structure 100 may include the following steps:

[0060] Step S100: providing a substrate 110 .

[0061] Step S300 : forming a first semiconductor intermediate layer 122 on one side of the substrate 110 . The first semiconductor intermediate layer 122 has a trench 200 . A gate dielectric layer 130 and a gate structure 131 are disposed in the trench 200 . The first semiconductor intermediate layer 122 has a first conductivity type.

[0062] Step S400: The first semiconductor intermediate layer 122 is patterned to form a first opening 210. The first opening 210 is spaced apart from the gate dielectric layer 130. The first opening 210 extends from the side of the first semiconductor layer 120 away from the substrate 110 to the inside of the first semiconductor layer 120. The remaining first semiconductor intermediate layer 122 forms the first semiconductor layer 120.

[0063] Step S500 : filling the first opening 210 to form a second semiconductor layer 140 , wherein the second semiconductor layer 140 has a first conductivity type.

[0064] In step S100, refer to Figure 1 The substrate 110 can be made of a semiconductor material, an insulating material, or any combination thereof. The substrate 110 can have a single-layer structure or a multi-layer structure. For example, the material of the substrate 110 can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc. Alternatively, for example, the substrate 110 can have a layered structure including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0065] Furthermore, the substrate 110 may be an N-type substrate. This embodiment does not limit the specific doping ions and doping concentration of the substrate 110.

[0066] In step S300, refer to Figures 3 and 4 A gate dielectric layer 130 and a gate structure 131 may be provided within the first semiconductor intermediate layer 122. For example, the gate dielectric layer 130 may be formed of a material with a high-k dielectric constant. For example, the material of the gate dielectric layer 130 may include silicon dioxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0067] The gate structure 131 may include, but is not limited to, any one or more of polysilicon, aluminum, titanium nitride (TiN), titanium (Ti), tungsten silicide (Si2W), and tungsten (W).

[0068] The first semiconductor intermediate layer 122 has a first conductivity type. As an example, the first semiconductor intermediate layer 122 can be subjected to P-type ion implantation. The present embodiment does not limit the specific doping ions and doping concentration of the first semiconductor intermediate layer 122.

[0069] In step S400, referring to Figure 5 The first semiconductor intermediate layer 122 can be etched to form the first opening 210 in the first semiconductor intermediate layer 122. As an example, a patterned mask layer can be formed on the side of the first semiconductor intermediate layer 122 away from the substrate 110, and then the first semiconductor intermediate layer 122 can be etched based on the patterned mask layer to form the first opening 210. Specifically, the first semiconductor intermediate layer 122 can be etched by dry etching or wet etching. The dry etching can include at least any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP).

[0070] In one possible example, the first opening 210 is spaced apart from the gate dielectric layer 130. At this time, the distance between the sidewall of the first opening 210 and the gate dielectric layer 130 can be between 0.1 μm and 1.0 μm. As a preferred example, the distance between the sidewall of the first opening 210 and the gate dielectric layer 130 can be between 0.3 μm and 0.6 μm. The above data are only examples, and in actual embodiments, the distance between the sidewall of the first opening 210 and the gate dielectric layer 130 is not limited by the above data.

[0071] In another possible example, referring to 5, the bottom of the first opening 210 does not expose the substrate 110. That is, the first opening 210 does not etch through the first semiconductor intermediate layer 122. At this time, the depth of the first opening 210 can be between 0.6 μm and 4.0 μm. The width of the first opening 210 is between 0.2 μm and 20 μm. The above data are only examples, and in actual embodiments, the depth and width of the first opening 210 are not limited by the above data.

[0072] In step S500, referring to Figures 6 and 7 The second semiconductor layer 140 can be formed by epitaxial growth or the like. The second semiconductor layer 140 can be a P-type epitaxial layer.

[0073] In one possible example, the thickness of the second semiconductor layer 140 can be between 0.3 μm and 10 μm. The above data are only examples, and in actual embodiments, the thickness of the second semiconductor layer 140 is not limited by the above data.

[0074] In another possible example, the doping concentration of the second semiconductor layer 140 may be 1×10 16 -5×10 19 cm -3 At this time, the second semiconductor layer 140 can be highly doped. The above data are only examples. In actual embodiments, the doping concentration of the second semiconductor layer 140 is not limited to the above data.

[0075] In this embodiment, a first opening 210 is formed by patterning the first semiconductor intermediate layer 122. The first opening 210 can then be filled to form a second semiconductor layer 140 having the first conductivity type. This allows for rapid and precise adjustment of the concentration near the channel of the semiconductor structure 100 (trench IGBT), thereby achieving improved device characteristics. For example, in this application, the ion concentration of the semiconductor layer near the gate dielectric layer 130 is lower, while the ion concentration of the semiconductor layer farther from the channel is higher. This allows the semiconductor structure 100 to properly form a channel depletion layer when the gate control voltage is low. When a higher gate control voltage is applied, the widening of the channel depletion layer is limited by the increase in ion concentration, thereby controlling the channel resistance at the higher gate control voltage, thereby achieving the effect of controlling the maximum saturation current. It can be understood that the on-state voltage drop of the semiconductor structure 100 of this application is substantially unaffected during normal operating current. In situations such as short circuits, the saturation current capability of the semiconductor structure 100 can be reduced by adjusting the relevant channel parameters. At the same time, the enhanced ion concentration distribution will also reduce the lateral parasitic resistance in the body (body region), thereby reducing the conduction of the parasitic PNPN device of the semiconductor structure 100. Furthermore, the concentration distribution adjusted in the present application can also shorten the widening of the depletion layer in the P-body during withstand voltage, and by reducing the junction depth of the body, thereby reducing the length of the channel, thereby reducing the channel resistance of the semiconductor structure 100, and also reducing the internal resistance of the semiconductor structure 100. Finally, the present application sets the concentration of the semiconductor layer away from the channel to be higher, and can also compress the lateral widening of the depletion layer and limit its expansion near the highly doped region. Even if the collector voltage increases, the widening of the depletion layer is blocked by the highly doped region, thereby stabilizing the channel length and preventing the channel length from decreasing.

[0076] Furthermore, IGBT devices are prone to PNPN latch-up at high currents. This occurs because during IGBT operation, hole current flows through the body below the emitter N+ to the hole, where the body below N+ has a certain resistance. When the voltage across this resistance exceeds approximately 0.7V, the front transistor (composed of the collector N+, the body P, and the drift region N) turns on. At this point, the hole current bypasses the hole and flows directly from the body to the N+, causing PNPN latch-up in the IGBT. Conventional technology often reduces the resistance of this resistor. The semiconductor structure 100 provided in this embodiment can also significantly reduce this resistance, thereby reducing the probability of IGBT latch-up.

[0077] In one embodiment, see Figure 2 , before step S300, including:

[0078] Step S200 : forming a third semiconductor layer 150 on one side of the substrate 110 , wherein the third semiconductor layer 150 has a second conductivity type.

[0079] As an example, the third semiconductor layer 150 may be N-type doped. The ion implantation concentration may be 1×10 14 -1×10 19 The above data are only for example. In actual embodiments, the doping concentration of the third semiconductor layer 150 is not limited to the above data. Furthermore, the resistivity of the N-type doped material can be between 0.1 ohm and 300 ohm.

[0080] Of course, step S200 may also include forming a field oxide layer, defining a terminal voltage-resistant region by photolithography, driving a well, forming a terminal voltage-resistant region, defining an active region, and removing the oxide layer outside the active region, etc. This embodiment will not elaborate on this.

[0081] Further, after step S200, please refer to Figure 2 、 Figure 3 and Figure 4 , step S300 may include:

[0082] Step S310 : forming a first semiconductor initial layer 121 on a side of the third semiconductor layer 150 away from the substrate 110 .

[0083] Step S320 : Patterning the first semiconductor initial layer 121 to form a trench 200 in the first semiconductor initial layer 121 . The trench 200 extends from the side of the first semiconductor initial layer 121 away from the substrate 110 through the third semiconductor layer 150 into the substrate 110 . The remaining first semiconductor initial layer 121 forms the first semiconductor intermediate layer 122 .

[0084] Step S330 : filling the trench 200 to form a gate dielectric layer 130 and a gate structure 131 .

[0085] Step S340 : performing ion implantation on the first semiconductor intermediate layer 122 .

[0086] In steps S310 to S320, as an example, a first semiconductor initial layer 121 (e.g., an oxide layer) can be deposited first. Of course, during this process, the oxide layer can be subjected to processes such as heating to form a dense oxide layer. Subsequently, a patterned photoresist layer can be formed on the side of the first semiconductor initial layer 121 away from the substrate 110, and the first semiconductor initial layer 121, the third semiconductor layer 150, and the substrate 110 can be sequentially etched based on the patterned photoresist layer to form the trench 200. It will be understood that a relatively regular trench 200 can be formed by etching in steps, extending from the side of the first semiconductor initial layer 121 away from the substrate 110 through the third semiconductor layer 150 into the substrate 110. At the same time, the oxide layer in the active area can be removed and sacrificial oxidation can be performed to repair the morphology within the trench 200.

[0087] In step S330, as an example, the temperature for forming the gate dielectric layer 130 can be between 900°C and 1200°C. Furthermore, the gate dielectric layer 130 can be an oxide layer. Exemplarily, the gate dielectric layer 130 can be formed using dry oxygen oxidation or wet oxygen oxidation. When forming the gate dielectric layer 130 using wet oxygen oxidation, a chlorine-containing gas (such as DCE) can be added to increase the oxidation rate and reduce defects through chlorine doping. The thickness of the gate dielectric layer 130 can range from 100Å to 2000Å. The above data is for example only. In actual embodiments, the thickness and formation temperature of the gate dielectric layer 130 are not limited to the above data.

[0088] After forming the gate dielectric layer 130, a gate structure 131 may be formed by depositing polysilicon. Of course, to obtain a smoother gate structure 131, the polysilicon may be subjected to processes such as photolithography and etching. This embodiment does not impose any specific limitations on this.

[0089] In step S340 , P-type ion implantation may be performed on the first semiconductor intermediate layer 122 to form a well region.

[0090] In this embodiment, the gate structure 131 is formed first and then P-type ion implantation is performed on the first semiconductor intermediate layer 122 , thereby preventing etching and other processes from affecting ion distribution, thereby improving the performance of the semiconductor structure 100 .

[0091] In one embodiment, see Figure 6 and Figure 7 , step S500 includes:

[0092] Step S510 : forming a second semiconductor initial layer 141 in the first opening 210 and on a side of the first semiconductor layer 120 away from the substrate 110 .

[0093] Step S520 : removing the second semiconductor initial layer 141 outside the first opening 210 , and the remaining second semiconductor initial layer 141 forms the second semiconductor layer 140 .

[0094] In steps S510 to S520, the second semiconductor initial layer 141 can be first deposited on the entire surface, and then the second semiconductor initial layer 141 located outside the first opening 210 can be removed to form the second semiconductor layer 140. As an example, the deposition process can include, but is not limited to, one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high-density plasma deposition (HDP), a plasma-enhanced deposition process, and a spin-on dielectric layer (SOD). As an example, the second semiconductor initial layer 141 located outside the first opening 210 can be removed by chemical mechanical polishing (CMP) or dry etching to obtain a smooth surface, which is conducive to the subsequent formation of other structures.

[0095] In one embodiment, see Figure 8 、 Figure 9 and Figure 10 The second semiconductor layer 140 has an edge region and a central region, and the edge region surrounds the central region. In this case, the edge region can be close to the gate dielectric layer 130. This embodiment does not limit the specific position and size of the edge region and the central region. After step S500, the following steps are included:

[0096] Step S600 : implanting ions of the second conductivity type into the edge region to form a doped region 160 in the edge region.

[0097] Step S800 : forming a first metal layer 170 on a side of the second semiconductor layer 140 and the doped region 160 away from the substrate 110 .

[0098] In step S600, N-type ion implantation may be performed into the edge region to form a doping region 160. As an example, the doping region 160 may serve as an emitter region. This embodiment does not limit the specific doping ions and doping concentration of the doping region 160.

[0099] In step S800, the material of the first metal layer 170 can include cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al), aluminum silicon (AlSi), aluminum silicon copper (AlSiCu), and the like. The embodiment is not limited to the specific material of the first metal layer 170. As an example, the first metal layer 170 can include multiple layers of metal.

[0100] Further, before step S800, the following steps are included:

[0101] Step S700: Forming a dielectric material layer on the side of the second semiconductor layer 140 and the doped region 160 away from the substrate 110.

[0102] Step S710: Performing a patterning process on the dielectric material layer to form a second opening 220 in the dielectric material layer, the second opening 220 exposing the second semiconductor layer 140, and the remaining dielectric material layer forming a dielectric layer 180.

[0103] Correspondingly, step S800 includes:

[0104] Step S810: Forming the first metal layer 170 in the second opening 220 and on the side of the dielectric layer 180 away from the substrate 110.

[0105] In steps S700-S710, the dielectric material layer can be formed on the side of the second semiconductor layer 140 and the doped region 160 away from the substrate 110 by a deposition process. As an example, the material of the dielectric material layer can include silicon oxide, silicon oxynitride, and the like. Of course, the dielectric material layer can be a single layer or multiple layers. Then, a mask layer or a patterned photoresist layer can be formed on the side of the dielectric material layer away from the substrate 110, and the dielectric material layer is etched based on the mask layer or the patterned photoresist layer, thereby forming the second opening 220. It can be understood that at this time, the second opening 220 does not expose the doped region 160.

[0106] In one possible example, the depth of the second opening 220 ranges between 0.3 μm-0.5 μm. In another possible example, the width of the second opening 220 ranges between 0.1 μm-4.0 μm. The above data are only examples, and in actual embodiments, the depth of the second opening 220 and the width of the second opening 220 are not limited to the above data.

[0107] In step S810, the first metal layer 170 can be formed in the second opening 220 and on the side of the dielectric layer 180 away from the substrate 110. It can be understood that at this time, the first metal layer 170 can be a front metal layer. Of course, in this process, a flat surface of the first metal layer 170 can also be obtained by a chemical mechanical polishing process or the like.

[0108] In this embodiment, the dielectric material layer is patterned to form the second opening 220 in the dielectric material layer, so that the position of the first metal layer 170 can be precisely controlled.

[0109] In one embodiment, see Figure 11 After step S800, the following steps are included:

[0110] Step S900 : forming a fourth semiconductor layer 190 on the other side of the substrate 110 , wherein the fourth semiconductor layer 190 has the second conductivity type.

[0111] Step S910 : forming a fifth semiconductor layer 191 on a side of the fourth semiconductor away from the substrate 110 , wherein the fifth semiconductor layer 191 has a first conductivity type.

[0112] Step S920 : forming a second metal layer 171 on a side of the fifth semiconductor layer 191 away from the substrate 110 .

[0113] In steps S900 to S920, the semiconductor structure 100 may be thinned first. Subsequently, N-type ion implantation may be performed from the other side of the substrate 110 to form the fourth semiconductor layer 190. Furthermore, P-type ion implantation may be performed to form the fifth semiconductor layer 191. Finally, a second metal layer 171 may be formed on the side of the fifth semiconductor layer 191 away from the substrate 110. As an example, the second metal layer 171 may be a backside metal layer.

[0114] In this embodiment, a complete IGBT device is obtained by forming the fourth semiconductor layer 190, the fourth semiconductor layer 190, and the second metal layer 171. For example, the IGBT device of the present application may include a back metal layer, a FS (FieldStop) buffer layer, a drift region, a charge storage layer, a P-type well region, a P+-type epitaxial well region, a polysilicon gate structure 131, a gate dielectric layer 130, a dielectric layer, and a front metal layer.

[0115] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0116] Based on the same inventive concept, in one embodiment, a semiconductor structure 100 is provided. The semiconductor structure 100 may include, but is not limited to, an IGBT, a Trench MOS, an SGT MOS, and the like.

[0117] The semiconductor structure 100 may include a substrate 110 , a first semiconductor intermediate layer 122 , a gate dielectric layer 130 , a gate structure 131 , a first semiconductor layer 120 , and a second semiconductor layer 140 .

[0118] The substrate 110 can be made of a semiconductor material, an insulating material, or any combination thereof. The substrate 110 can have a single-layer structure or a multi-layer structure. For example, the material of the substrate 110 can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc. Alternatively, for example, the substrate 110 can have a layered structure including Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator (SiGe-on-insulator).

[0119] Furthermore, the substrate 110 may be an N-type substrate. This embodiment does not limit the specific doping ions and doping concentration of the substrate 110.

[0120] A gate dielectric layer 130 and a gate structure 131 may be disposed within the first semiconductor layer 120. The gate dielectric layer 130 and the gate structure 131 may extend to the substrate 110. For example, the gate dielectric layer 130 may be formed of a material with a high-k dielectric constant. For example, materials for the gate dielectric layer 130 include aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0121] The gate structure 131 may include, but is not limited to, any one or more of polysilicon, titanium nitride (TiN), titanium (Titanium), tungsten silicide (Si2W), and tungsten (W).

[0122] The first semiconductor layer 120 has a first conductivity type. As an example, the first semiconductor layer 120 may be subjected to P-type ion implantation. This embodiment does not limit the specific doping ions and doping concentration of the first semiconductor layer 120.

[0123] The second semiconductor layer 140 may be a P-type epitaxial layer. In one possible embodiment, the second semiconductor layer 140 is spaced apart from the gate dielectric layer 130. At this time, the distance between the sidewall of the second semiconductor layer 140 and the gate dielectric layer 130 may be between 0.1 μm and 1.0 μm. As a preferred embodiment, the distance between the sidewall of the second semiconductor layer 140 and the gate dielectric layer 130 may be between 0.3 μm and 0.6 μm. The above data are for example only. In actual embodiments, the distance between the sidewall of the second semiconductor layer 140 and the gate dielectric layer 130 is not limited to the above data.

[0124] In a possible example, the thickness of the second semiconductor layer 140 may be between 0.3 μm and 10 μm. The above data are only examples. In actual embodiments, the thickness of the second semiconductor layer 140 is not limited to the above data.

[0125] In another possible example, the doping concentration of the second semiconductor layer 140 may be 1×10 16 -5×10 19 cm -3 In this case, the second semiconductor layer 140 may be a highly doped layer. The above data are only examples. In actual embodiments, the doping concentration of the second semiconductor layer 140 is not limited to the above data.

[0126] In this embodiment, the performance of the semiconductor device is improved by disposing a first semiconductor layer 120 and a second semiconductor layer 140 within the semiconductor structure 100. For example, in this application, the concentration of the semiconductor layer near the gate dielectric layer 130 is lower, while the concentration of the semiconductor layer farther from the channel is higher. This allows the semiconductor structure 100 to properly form a channel depletion layer when the gate control voltage is low. However, when a higher gate control voltage is applied, the widening of the channel depletion layer is limited by the increase in concentration, thereby limiting its widening and controlling the channel resistance at the higher gate control voltage to achieve the effect of controlling the maximum saturation current. It can be understood that the on-state voltage drop of the semiconductor structure 100 of this application is substantially unaffected during normal operating current. In short-circuit conditions, the saturation current capability of the semiconductor structure 100 can be reduced by adjusting the relevant channel parameters. Furthermore, the enhanced concentration distribution reduces the lateral parasitic resistance within the body region, thereby reducing the conduction of the parasitic PNPN device of the semiconductor structure 100. Furthermore, the adjusted concentration profile of the present application can also shorten the widening of the depletion layer in the P-body (body region) during withstand voltage. By reducing the junction depth of the body (body region), the length of the channel can be reduced, thereby reducing the channel resistance of the semiconductor structure 100 and also reducing the internal resistance of the semiconductor structure 100. Finally, the present application sets the concentration of the semiconductor layer away from the channel to be higher, which can also compress the lateral widening of the depletion layer and limit its expansion near the highly doped region. Even if the collector voltage increases, the widening of the depletion layer is blocked by the highly doped region, thereby stabilizing the channel length and preventing the channel length from decreasing.

[0127] Furthermore, IGBT devices are prone to PNPN latch-up at high currents. This occurs because during IGBT operation, hole current flows through the body below the emitter N+ to the hole, where the body below N+ has a certain resistance. When the voltage across this resistance exceeds approximately 0.7V, the front-side transistor (composed of the collector N+, the body P, and the drift N) turns on. At this point, the hole current bypasses the hole and flows directly from the body to the N+, causing PNPN latch-up in the IGBT. Conventional technology often reduces this resistance by lowering the value of this resistor. The semiconductor structure 100 provided in this embodiment can also significantly reduce this resistance, thereby reducing the probability of IGBT latch-up.

[0128] It can be understood that the semiconductor structure 100 obtained by using the method for preparing the semiconductor structure 100 provided in one or more embodiments of the present application and combinations thereof is within the scope of protection of the present application.

[0129] See also Figure 12 、 Figure 13 as well as Figure 14 . Figure 12In the figure, the left side shows the test results of the semiconductor structure 100 provided by the present application, and the right side shows the test results of the semiconductor structure in the conventional technology. As can be seen from the figure, under the same gate and collector voltages, the semiconductor structure 100 provided by the present application can significantly reduce the problem of shortening the channel length due to the influence of the depletion layer, thereby controlling the growth of the saturation current. In this way, the semiconductor structure 100 provided by the present application does not affect the on-state voltage of the device during normal operation, and can control the maximum saturation current value under high current or high bias, thereby increasing the reliability of the device during short circuit. Figure 13 , the change of the saturation current of the semiconductor structure 100 provided by the present application is shown. Figure 14 The ion concentration distribution inside (eg, depth) of the semiconductor structure 100 obtained after step S500 is shown. Figures 12 to 14 It can be seen that the semiconductor structure 100 provided in the present application has practicable and relatively excellent performance.

[0130] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the various embodiments of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the various embodiments of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a first semiconductor intermediate layer on one side of the substrate, the first semiconductor intermediate layer having a trench, a gate dielectric layer and a gate structure disposed in the trench, the first semiconductor intermediate layer having a first conductivity type, and the trench extending from a surface of the first semiconductor intermediate layer, through the first semiconductor intermediate layer, and into the interior of the substrate; Performing a patterning process on the first semiconductor intermediate layer to form a first opening, wherein a portion of the first semiconductor intermediate layer remains at a bottom of the first opening, the first opening is spaced apart from the gate dielectric layer, and the first opening extends from a side of the first semiconductor layer away from the substrate to an interior of the first semiconductor layer, with the remaining first semiconductor intermediate layer forming a first semiconductor layer; Filling the first opening to form a second semiconductor layer, wherein the second semiconductor layer has a first conductivity type, the first semiconductor layer is formed between the second semiconductor layer and the gate dielectric layer, and both the first semiconductor layer and the second semiconductor layer are P-type semiconductor layers; The ion concentration of the first semiconductor layer surrounding the gate dielectric layer is lower than the ion concentration of the second semiconductor layer, and the doping concentration of the second semiconductor layer is between 1×10 16 -5×10 19 cm -3 between.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The distance between the sidewall of the first opening and the gate dielectric layer is between 0.1 μm and 1.0 μm.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The depth of the first opening is between 0.6 μm and 4.0 μm, and the width of the first opening is between 0.2 μm and 20 μm.

4. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the first semiconductor layer on one side of the substrate, the method includes: A third semiconductor layer is formed on one side of the substrate, wherein the third semiconductor layer has a second conductivity type.

5. The method for preparing a semiconductor structure according to claim 4, wherein: After forming the third semiconductor layer on one side of the substrate, the method further comprises: forming a first semiconductor initial layer on a side of the third semiconductor layer away from the substrate; Performing a patterning process on the first semiconductor initial layer to form a trench in the first semiconductor initial layer, wherein the trench extends from a side of the first semiconductor initial layer away from the substrate through the third semiconductor layer into the substrate, and the remaining first semiconductor initial layer forms the first semiconductor intermediate layer; Filling the trench to form the gate dielectric layer and the gate structure; Ion implantation is performed on the first semiconductor intermediate layer.

6. The method for preparing a semiconductor structure according to claim 1, wherein: Filling the first opening to form a second semiconductor layer includes: forming a second semiconductor initial layer in the first opening and on a side of the first semiconductor layer away from the substrate; The second semiconductor initial layer located outside the first opening is removed, and the remaining second semiconductor initial layer forms a second semiconductor layer.

7. The method for preparing a semiconductor structure according to claim 1, wherein: The second semiconductor layer has an edge region and a central region, wherein the edge region surrounds the central region; After filling the first opening to form the second semiconductor layer, the method includes: Implanting ions of the second conductivity type into the edge region to form a doped region in the edge region; A first metal layer is formed on a side of the second semiconductor layer and the doped region away from the substrate.

8. The method for preparing a semiconductor structure according to claim 7, wherein: Before forming the first metal layer on the side of the second semiconductor layer and the doped region away from the substrate, the method includes: forming a dielectric material layer on a side of the second semiconductor layer and the doped region away from the substrate; Performing a patterning process on the dielectric material layer to form a second opening in the dielectric material layer, wherein the second opening exposes the second semiconductor layer, and the remaining dielectric material layer forms a dielectric layer; The first metal layer is formed on a side of the second semiconductor layer and the doped region away from the substrate, comprising: A first metal layer is formed in the second opening and on a side of the dielectric layer away from the substrate.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The depth of the second opening is in the range of 0.3 μm to 0.5 μm, and / or the width of the second opening is in the range of 0.1 μm to 4.0 μm.

10. The method for preparing a semiconductor structure according to claim 7, wherein: After forming the first metal layer on the side of the second semiconductor layer and the doped region away from the substrate, the method includes: forming a fourth semiconductor layer on the other side of the substrate, wherein the fourth semiconductor layer has a second conductivity type; forming a fifth semiconductor layer on a side of the fourth semiconductor away from the substrate, wherein the fifth semiconductor layer has a first conductivity type; A second metal layer is formed on a side of the fifth semiconductor layer away from the substrate.

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