Transistor and method for producing such transistor

Abstract

The invention relates to a transistor comprising an upper side with V-shaped trenches, in which the internally arranged V-shaped trenches are at least partially electrically conductive, characterized in that the externally arranged V-shaped trenches are at least partially electrically non-conductive. The invention further relates to a method for producing such a transistor.

Description

Technical Field

[0001] The present invention relates to a transistor and a method for manufacturing such a transistor. Background Art

[0002] Transistors made of gallium nitride (GaN) semiconductors offer the possibility of implementing components with both low on-resistance and high breakdown voltage.

[0003] One possible structure of a GaN transistor is the so-called V-Shaped Gate High Electron Mobility Transistor (hereinafter referred to as "VHEMT") or trench current-aperture vertical electron transistor (hereinafter referred to as "Trench CAVET").

[0004] Transistors known from the prior art typically consist of a highly doped conductive current spreading layer made of gallium nitride (GaN), on which a weakly n-doped GaN drift layer is applied. Above the weakly n-doped GaN drift layer is a p-doped GaN layer, above which is an insulating aluminum gallium nitride (AlGaN) or GaN layer. The p-doped GaN layer and the insulating GaN or AlGaN layer are penetrated by V-shaped trenches, and an undoped GaN layer and an AlGaN layer extend above the trenches. In the region of the undoped GaN layer, a two-dimensional electron gas (2DEG) is formed at the interface between the undoped GaN layer and the AlGaN layer. Optionally, a p-doped GaN layer is also introduced into the V-shaped trenches to ensure normally-off operation of the component. The gate electrode contacts the p-doped GaN layer. The source contact abuts on the 2DEG. Additionally, a source contact region can be provided, which laterally contacts the 2DEG additionally. In this case, the lower part of the source contact can also be designed as a p-contact, via which the p-layer is joined.

[0005] Without applying a gate voltage, such transistors are self-blocking because the 2DEG is depleted below the p-doped GaN layer. By applying a positive voltage to the gate electrode, the entire 2DEG is filled with electrons, and the electrons flow from the source contact via the sidewalls of the trench into the bottom of the trench, and from there further downward through the GaN drift layer and the current spreading layer to the drain, which is typically arranged on the back side of the substrate.

[0006] Such or similar transistor structures are known, for example, from US10,050,138B2, US7,592,647B2, and US8,729,562B2.

[0007] The threshold voltage of a VHEMT depends to a large extent on the side angle of the V-groove, as this affects the polarization charge at the GaN-AlGaN interface.

[0008] The trenches are structured by a dry chemical process. Here, due to process reasons, the side angle of the outermost trenches of the structure field usually differs from that of the other trenches. In a transistor, this angle deviation causes a shift in the threshold voltage in the outer trench region. This leads to non-uniform current in the component, which in turn causes problems for the reliability and performance of the transistor.

[0009] The choice of the side angle is a trade-off between the highest possible charge carrier density and the highest possible threshold voltage, where a flat angle is favorable for the former and a steep angle is preferred for the latter. Here, an angle close to 45 degrees is usually used. Here, the inclined etched side is achieved by a mask layer with a bevel edge, which is partially consumed during the etching process to form an inclined structure of the GaN material. For example, the use of the following paint mask is suitable for this, the edges of which are rounded by heat flow. After structuring the paint mask by means of lithography, the edges are rounded by heat flow. Here, the shape of the edges depends on the width of the paint strip between the subsequent trenches, which is why the outer edges of the surrounding paint layer deviate from the edges within the structure field. In the dry etching step, the mask is partially consumed, thereby forming inclined edges in the GaN material. Here, the side angle of a single outer trench or multiple trenches deviates from the side angle within the structure field, i.e., the internally arranged trenches.

[0010] The object of the present invention is to overcome the above-mentioned drawbacks. Summary of the Invention

[0011] According to the present invention, this object is achieved by a transistor according to the present invention and a method according to the present invention.

[0012] According to the present invention, there is provided a transistor, the transistor comprising an upper side having a V-groove. A transistor channel that is conductive and controllable by a control electrode is at least partially constructed along an internally arranged V-groove, i.e., along a groove that is laterally surrounded by additional trenches, especially surrounded on all sides and / or on two opposite sides. Thus, the internally arranged V-groove is at least partially conductively constructed or has a conductive region. The externally arranged V-grooves, i.e., the grooves that are not adjacent to additional trenches on at least one side, are at least partially configured to be non-conductive, i.e., configured such that the grooves prevent current flow. Thus, the externally arranged V-grooves at least partially do not have a transistor channel that is conductive and controllable by a control electrode.

[0013] Thus, the core of the present invention lies in configuring a transistor with a V-shaped groove such that the externally arranged V-shaped groove or at least its external side does not contribute to current flow. That is, the transistor according to the present invention consists of a large number of identical and arranged unit cells, each of which has a V-shaped groove. Among them, at least the outermost unit cells are different from the internal unit cells in that the outermost unit cells do not contribute to current flow or only contribute to current flow in particularly internal partial regions, that is, a conductive and controllable transistor channel by a control electrode is constructed at most in the internal partial regions.

[0014] This prevents process-related deviations in the side corners of the externally arranged V-shaped groove from adversely affecting the electrical performance of the transistor. Additionally, the transistor according to the present invention enables the use of the externally arranged V-shaped groove as part of an edge termination strategy.

[0015] The conductive and controllable transistor channel by a control electrode forms a conductive region, for example.

[0016] The transistor channel is, for example, a HEMT channel.

[0017] In a preferred embodiment of the transistor according to the present invention, the internally arranged V-shaped groove is configured to be completely conductive or only non-conductive at the ends and conductive in the remaining parts.

[0018] In an exemplary embodiment of the transistor according to the present invention, the externally arranged V-shaped groove is completely non-conductive, or only the external side of each externally arranged V-shaped groove is non-conductive.

[0019] The transistor is, for example, a HEMT, especially a VHEMT.

[0020] The transistor can be a vertical transistor, that is, having a plate-like shape.

[0021] Alternatively, the transistor can be a quasi-vertical transistor, that is, a transistor that contacts the side grooves from above.

[0022] For example, the side grooves laterally adjoin the active transistor region of the transistor.

[0023] For example, the grooves are deeply etched.

[0024] In a preferred embodiment, the transistor according to the present invention includes a substrate layer, a highly doped conductive GaN current spreading layer disposed on the substrate layer, a weakly n-doped GaN drift layer disposed on the highly doped conductive GaN current spreading layer, a p-doped GaN layer disposed on the weakly n-doped GaN drift layer, and an insulating GaN layer or AlGaN layer disposed on the p-doped GaN layer.

[0025] The V-grooves can extend through, in particular interrupt, the p-doped GaN layer and the insulating GaN or AlGaN layer.

[0026] In a preferred embodiment of the transistor according to the invention, the V-grooves extend linearly or form a closed hexagonal shape, respectively.

[0027] Furthermore, the invention relates to a method for manufacturing the above-mentioned transistor, the method comprising: deeply etching the upper side of the transistor to construct V-grooves, at least partially, in particular completely, covering the end regions of the externally arranged V-grooves and / or the internally arranged V-grooves with an amorphous protective layer, and epitaxially growing over the upper side of the transistor, in particular over the internally arranged V-grooves There is a particularly low-doped or undoped GaN layer, an insulating GaN or AlGaN layer, and an optional p-doped GaN cover layer, and subsequently removing the amorphous protective layer by etching.

[0028] In a preferred embodiment of the method according to the invention, the amorphous protective layer is an oxide or nitride layer, in particular composed of silicon dioxide (SiO2) or silicon nitride (SiN).

[0029] In an exemplary embodiment of the method according to the invention, the amorphous protective layer is wet-chemically etched.

[0030] Furthermore, the invention relates to a further method for manufacturing the above-mentioned transistor, the method comprising: epitaxially growing over the upper side of the transistor, in particular over the internally arranged V-grooves, a particularly low-doped or undoped GaN layer, an insulating GaN layer or AlGaN layer, and an optional p-doped GaN cover layer, covering a partial region of the internally arranged V-grooves and / or the externally arranged V-grooves with a protective layer for preventing damage, such that at least one uncovered region is produced, removing at least the uppermost layer, in particular at least the insulating GaN or AlGaN layer, of the transistor in the uncovered region by etching, or destroying the conductivity of the transistor in the uncovered region by ion implantation, and subsequently removing the protective layer.

[0031] For example, when covering, the internally arranged V-grooves are completely covered.

[0032] Alternatively, the internally arranged V-grooves may be covered only in the central region, while the end regions of the internally arranged V-grooves adjacent to the central region remain uncovered.

[0033] When covering, the externally arranged V-grooves may be partially covered.

[0034] For example, when covering, the inner wall of the externally arranged V-grooves and / or the partial region of the externally arranged V-grooves adjacent to the internally arranged grooves are covered.

[0035] The etching may be dry chemical etching.

[0036] For example, etching is carried out by inductively coupled plasma reactive ion etching (ICP RIE), especially in the case of using a chlorine-containing process gas.

[0037] In an exemplary embodiment of a further method according to the invention, the protective layer comprises a lacquer, a metal and / or an amorphous material, especially a nitride or an oxide, especially SiO2, or is formed from these materials.

[0038] In a preferred embodiment of a further method according to the invention, nitrogen ions and / or argon ions are used during ion implantation.

[0039] Further advantages result from the description of the exemplary embodiments. Description of the Drawings

[0040] The invention is explained in more detail below using the exemplary embodiments shown in the drawings. The drawings show:

[0041] Figure 1 A schematic top view of a first transistor according to the invention, as well as a source contact, a source electrode and a gate contact;

[0042] Figure 2 Figure 1 An edge region of a cross-sectional view of the first transistor in an intermediate state during manufacture;

[0043] Figure 3 An edge region of a cross-sectional view of a second transistor according to the invention in an intermediate state during manufacture;

[0044] Figure 4 An internal region of a cross-sectional view of the second transistor according to the invention in a completed state.

[0045] Figure 5 An edge region of a cross-sectional view of a third transistor according to the invention in an intermediate state during manufacture; and

[0046] Figure 6 A top view of a fourth transistor according to the invention together with a source electrode. Detailed Description of the Invention

[0047] In Figure 1 and Figure 2 a first transistor 1 according to the invention is shown. The transistor 1 is a GaN-based VHEMT. The transistor 1 is configured in a plate-like manner.

[0048] A source electrode 31 with a planar-grown 2DEG - AlGaN - GaN layer stack is arranged on a surrounding platform. In addition, contact pads are provided for supplying the source contact 32 and the gate contact 35 (seeFigure 1 )。

[0049] As Figure 2 shown, the transistor 1 has a highly doped conductive GaN current spreading layer 11, on which a weakly n-doped GaN drift layer 12 is applied. There is a p-doped GaN layer 13 on the GaN drift layer 12, and an insulating GaN or AlGaN layer 14 is arranged on the p-doped GaN layer.

[0050] The p-doped GaN layer 13 and the insulating GaN or AlGaN layer 14 are penetrated by V-shaped trenches 33 and 34. The V-shaped trenches 33 and 34 extend parallel to each other. The internally arranged V-shaped trench 33 contributes to the current flow of the VHEMT, while the externally arranged V-shaped trench 34 blocks the current flow.

[0051] The internally arranged V-shaped trench 33, i.e., the trench laterally surrounded by the other V-shaped trenches 33 and 34, includes a conductive region 37, and a non-conductive region 36, i.e., the region that blocks the current flow, adjoins the conductive region 37 at the end of the longitudinal range of the conductive region 37.

[0052] The conductive region 37 is a conductive transistor channel constructed along the V-shaped trench 33 and can be controlled by a control electrode.

[0053] In the externally arranged V-shaped trench 34, there are no other V-shaped trenches 33 and 34 adjacent to at least one side. In particular, in a top view, the externally arranged V-shaped trench 34 is arranged in the edge region of the transistor 1.

[0054] The undoped GaN layer 15 and the AlGaN layer 16 extend in the internal region of the transistor 1 in the vertical direction, and this internal region includes the conductive region 37 of the internally arranged V-shaped trench 33. A 2DEG is formed at the interface between the undoped GaN layer 15 and the AlGaN layer 16 in the region of the undoped GaN layer 15.

[0055] In addition, in the conductive region 37 of the internal trench 33, a p-doped GaN layer can be applied to the AlGaN layer 16 to ensure normally-off operation. The gate electrode 18 can contact the p-doped GaN layer.

[0056] The configuration of the non-conductive region 36 of the internally arranged V-shaped trench 33 corresponds to the configuration of the externally arranged V-shaped trench 34.

[0057] The non-conductive regions 36 of the externally arranged V-shaped trench 34 and the internally arranged V-shaped trench 33 are covered by an amorphous protective layer 22 before the undoped GaN layer 15, the AlGaN layer 16, and an optional p-doped GaN layer are grown thereon. The amorphous protective layer 22 prevents epitaxial growth in the covered regions.

[0058] Suitable amorphous protective layers 22 are, in particular, oxide and nitride layers, preferably made of SiO2 or SiN. The use of an amorphous protective layer 22 to spatially confine epitaxial growth is known from the method of selective growth of three-dimensional GaN nanostructures (selective area growth).

[0059] The amorphous protective layer 22 inhibits the nucleation of gallium and nitrogen atoms and / or enhances the desorption of atoms adsorbed on the mask surface and their lateral diffusion. As a result, no 2DEG is formed in the non-conductive regions 36 of the externally arranged V-shaped trenches 34 and the internally arranged V-shaped trenches 33, thereby preventing the contribution to the current flow in these regions, i.e., these regions are non-conductive.

[0060] After the application of the undoped GaN layer 15, the AlGaN layer 16, and, optionally, the p-doped GaN layer, the amorphous protective layer 22 is removed by etching. Wet chemical etching is particularly suitable for this.

[0061] In Figure 3 and Figure 4 a second transistor 2 according to the invention is shown.

[0062] The second transistor 2 basically corresponds to Figure 1 and Figure 2 the first transistor 1 shown in. Therefore, only the distinguishing features will be described below. For further features, reference is made to the above description of the first transistor 1, wherein, in Figure 3 and Figure 4 the elements corresponding to the elements of the first transistor 1 are provided with the same reference numerals as those used in Figure 1 and Figure 2 .

[0063] The second transistor 2 differs from the first transistor 1 in that the non-conductive end regions 36 of the externally arranged V-shaped trenches 34 and the internally arranged V-shaped trenches 33 are also covered with the undoped GaN layer 15, the AlGaN layer 16, and, optionally, the p-doped GaN layer 17 during epitaxial overgrowth. When manufacturing the second transistor 2, no amorphous protective layer is used during epitaxial overgrowth.

[0064] After epitaxial overgrowth, the conductivity of the non-conductive end regions 36 of the external trenches 34 and the internal trenches 33 is locally disrupted by ion implantation, thereby generating a damaged region 24. No 2DEG is formed in the damaged region 24. The time point of the implantation step in the process sequence is variable. For example, the implantation occurs after the gate contact and the source contact are completed.

[0065] To limit damage to the semiconductor material caused by ion bombardment of the conductive region 37 of the internally arranged trench 33, the conductive region 37 is covered with a protective mask 23 or a protective layer, which prevents ions from penetrating into the covered area. The protective mask 23 is removed again after ion implantation.

[0066] For example, paint, metal or amorphous layers are suitable as the protective mask, especially paint, nitride or oxide, in particular SiN or SiO2.

[0067] Ions suitable for damage are, for example, nitrogen ions or argon ions.

[0068] In the conductive region 37 of the internally arranged V-shaped trench 33, a p-doped GaN layer 17 is applied to the AlGaN layer 16 to ensure normally-off operation of the component. The gate electrode 18 contacts the p-doped GaN layer 17.

[0069] The source contact 19 contacts the 2DEG from above.

[0070] Furthermore, a source contact region 20 is optionally provided, which additionally contacts the 2DEG laterally. The lower part of the source contact region 20 is implemented as a p-contact, via which the p-doped GaN layer 13 is joined.

[0071] The drain 21 is located on the back surface of the substrate 10.

[0072] Figure 5 The third transistor 3 according to the invention is shown. The third transistor 3 basically corresponds to Figure 1 and Figure 2 the first transistor 1 shown in. Therefore, only the distinguishing features will be described below. For further features, reference is made to the above description of the first transistor 1. In Figure 5 the elements of the third transistor 3 shown corresponding to the elements of the first transistor 1 have the same reference numerals.

[0073] To configure the non-conductive end regions 36 of the externally arranged V-shaped trench 34 and the internally arranged V-shaped trench 33 non-conductively, the upper semiconductor layers, in particular the (not shown) p-doped GaN layer 17, AlGaN layer 16, undoped GaN layer 15, AlGaN layer 14, p-doped GaN layer 13 and / or GaN drift layer 12 are partially removed locally in the region of the externally arranged V-shaped trench 34 and in the region of the non-conductive end regions 36 of the internally arranged V-shaped trench 33 using an etching step, but at least until the AlGaN layer 16 is completely removed, so that no 2DEG is formed in these regions.

[0074] For example, etching is preferably carried out by means of dry chemical etching, in particular by means of inductively coupled plasma reactive ion etching (ICPRIE), using a Cl-containing process gas.

[0075] In order to prevent damage to the conductive region 37 of the internal V-shaped groove 33 during the etching process, the conductive region is covered with a protective mask 25 or a protective layer before etching.

[0076] Possible materials for the protective mask include lacquer, metal or amorphous materials, in particular nitrides or oxides, especially SiO2.

[0077] The etching is preferably carried out directly after the growth of the cover or after the treatment of the source contact 19.

[0078] In Figure 6 the fourth transistor 4 according to the invention is shown.

[0079] The fourth transistor 4 basically corresponds to Figure 1 and Figure 2 the first transistor 1 shown in. Therefore, only the distinguishing features will be described below. For further features, reference is made to the above description of the first transistor 1, where Figure 6 the elements corresponding to the elements of the first transistor 1 in Figure 1 and Figure 2 are provided with the same reference numerals as those used in.

[0080] The fourth transistor 4 differs from Figure 1 the first transistor 1 shown in that the V-shaped grooves 33, 34 are not configured linearly and do not extend parallel to each other, but instead form a hexagonal shape in a top view, respectively.

[0081] The internally arranged V-groove 33 of the fourth transistor 4 is fully conductive, while the externally arranged V-groove 34 has a conductive region and a non-conductive region. The non-conductive regions are arranged in such a way that together they form a non-conductive outer region of the transistor 4.

[0082] The specific configuration of the non-conductive regions and the conductive regions can correspond to the embodiments shown in the previous figures.

[0083] The embodiments described and shown in the figures are only selected as examples. Different embodiments can be combined with each other completely or for individual features. An embodiment can also be supplemented by the features of another embodiment. In addition, the described method steps can be repeated and executed in an order different from the described order.

Claims

1. A transistor, the transistor comprising an upper side having V-shaped grooves (33, 34), wherein, A transistor channel that is conductive and controllable by a control electrode is at least partially constructed along an internally arranged V-shaped trench (33), characterized in that an externally arranged V-shaped trench (34) is at least partially non-conductive.

2. The transistor according to claim 1, characterized in that, The internally arranged V-shaped trench (33) is fully conductive or only the end regions (36) of the internally arranged V-shaped trench are non-conductive.

3. The transistor according to claim 1 or 2, characterized in that, The externally arranged V-shaped trench (34) is fully non-conductive or only the outer sides of the externally arranged V-shaped trench are non-conductive.

4. The transistor according to any one of claims 1 to 3, characterized in that A substrate layer (10), a highly doped conductive gallium nitride current spreading layer (11), a weakly n-doped gallium nitride drift layer (12), a p-doped gallium nitride layer and / or an insulating gallium nitride or aluminum gallium nitride layer (14) are provided.

5. The transistor according to claim 4, wherein, The V-shaped trenches (33, 34) extend through the p-doped gallium nitride layer (13) and / or through the insulating gallium nitride or aluminum gallium nitride layer (14).

6. The transistor according to any one of claims 1 to 5, characterized in that, The V-shaped trenches (33, 34) extend linearly respectively or form a closed hexagonal shape respectively.

7. The transistor according to any one of claims 1 to 6, characterized in that, The transistor (1, 2, 3) is a vertical gallium nitride transistor.

8. A method for manufacturing a transistor (1, 2, 3, 4) according to any one of claims 1 to 7, the method comprising the following steps: i. Deep etching the upper side of the transistor (1, 2, 3, 4) to construct V-shaped trenches (33, 34); ii. At least partially, especially completely, covering the externally arranged V-shaped trench (34) and / or the end regions (36) of the internally arranged V-shaped trench (33) with an amorphous protective layer (22); iii. Epitaxially growing a gallium nitride layer (13) and an insulating gallium nitride or aluminum gallium nitride layer (14) on the upper side of the transistor (1, 2, 3, 4); and iv. Removing the amorphous protective layer (22) by etching.

9. The method according to claim 8, characterized in that The amorphous protective layer (22) is an oxide or nitride layer, especially composed of silicon dioxide or silicon nitride.

10. The method according to claim 8 or 9, characterized in that, Wet chemical etching is performed in step iv.

11. A method for manufacturing a transistor (1, 2, 3, 4) according to any one of claims 1 to 7, the method comprising the following steps: v. Epitaxially growing a gallium nitride layer (13) and an insulating gallium nitride or aluminum gallium nitride layer (14) on the upper side of the transistor (1, 2, 3, 4); vi. At least partially, especially completely, covering partial regions, especially the inner sides, of the internally arranged V-shaped trench (33) and / or the externally arranged V-shaped trench (34) with a protective layer (23, 25), such that at least one uncovered region appears; vii. At least removing the uppermost layer (15, 16) in the uncovered region by etching, or destroying the conductivity of the transistor (1, 2, 3, 4) in the uncovered region by ion implantation; And viii. Removing the protective layer (23, 25).

12. The method according to claim 11, wherein Dry chemical etching is performed in step iii, especially using inductively coupled plasma reactive ion etching, especially in the case of using a chlorine-containing process gas.

13. The method according to claim 11 or 12, characterized in that, The protective layers (23, 25) include paint, metal and / or amorphous materials, in particular nitrides and / or oxides, in particular silicon dioxide.

14. The method according to any one of claims 11 to 13, characterized in that Nitrogen ions and / or argon ions are used in the ion implantation.

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