Semiconductor device, power module, and electronic apparatus

Abstract

The present disclosure provides a semiconductor device, a power module and an electronic device, relates to the technical field of semiconductor technology, and is used for enabling the semiconductor device to realize conduction under reverse bias under enhanced conditions; the semiconductor device comprises a substrate, a gate, a conductive electrode, a first current blocking layer, a first doped layer, a first electrode, a second current blocking layer, a second doped layer and a second electrode, a dielectric layer and a third electrode, the conductive electrode is arranged on the side of the gate close to the substrate; the first current blocking layer, the first doped layer and the first electrode are arranged in a stacked mode in the first direction and the direction away from the substrate, and are arranged on the first side of the gate; the second current blocking layer, the second doped layer and the second electrode are arranged in a stacked mode in the first direction and the direction away from the substrate; the second doped layer and the second electrode are arranged on the second side of the gate; and the second current blocking layer is arranged on the side of the conductive electrode and the second current blocking layer close to the substrate. The semiconductor device is applied to the power module.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor device, a power module and an electronic device. BACKGROUND

[0002] Ga2O3 (gallium oxide) as a new type of ultra-wide bandgap (UWBG) semiconductor material has an ultra-wide bandgap of more than 4.8eV, a theoretical breakdown field strength of 8MV / cm and a lower on-resistance, and has a broad application prospect in the field of high-power devices. However, the current enhanced gallium oxide-based metal-oxide-semiconductor field-effect transistor (MOSFET) cannot achieve conduction under reverse bias, which greatly limits the development of gallium oxide-based power devices. SUMMARY

[0003] Embodiments of the present disclosure aim to provide a semiconductor device, a power module and an electronic device for enabling a semiconductor device to achieve conduction under reverse bias in an enhanced condition.

[0004] To achieve the above-mentioned purpose, embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a semiconductor device is provided. The semiconductor device includes a substrate, a gate, a conductive electrode, a first current blocking layer, a first doped layer, a first electrode, a second current blocking layer, a second doped layer and a second electrode, a dielectric layer and a third electrode.

[0006] The gate is arranged on one side of the substrate in a first direction, which is the thickness direction of the substrate; the conductive electrode is arranged on the side of the gate close to the substrate; the first current blocking layer, the first doped layer and the first electrode are stacked in the first direction and away from the substrate, and are arranged on the first side of the gate; the second current blocking layer, the second doped layer and the second electrode are stacked in the first direction and away from the substrate; the second doped layer and the second electrode are arranged on the second side of the gate, which is the opposite side of the gate in the second direction; the second current blocking layer is arranged on the side of the conductive electrode and the second current blocking layer close to the substrate; the dielectric layer is arranged between each of the first current blocking layer, the first doped layer, the first electrode, the second doped layer, the second current blocking layer and the conductive electrode and the gate; the dielectric layer also covers the surface of the conductive electrode close to the substrate and the two opposite sides of the conductive electrode in the second direction; and the third electrode is arranged on the side of the substrate away from the gate.

[0007] In the semiconductor device, the gate is arranged on one side of the substrate in the first direction, the first current blocking layer, the first doped layer and the first electrode are arranged in a stack in the first direction and away from the substrate, and the third electrode is arranged on the side of the substrate away from the gate. When the gate voltage of the semiconductor device is less than the threshold voltage and the voltage of the third electrode is greater than the voltage of the first electrode, the semiconductor device is in an off state. When the gate voltage of the semiconductor device is greater than the threshold voltage of the semiconductor device and the voltage of the third electrode is greater than the voltage of the first electrode, the conductivity of the side of the first current blocking layer close to the gate is increased, the semiconductor device is turned on, and at this time, the current flows from the third electrode, the side of the first current blocking layer close to the gate, the first doped layer to the first electrode. Thus, the semiconductor device provided by the embodiment is an enhancement-mode semiconductor device.

[0008] On the other hand, since the conductive electrode is arranged on the side of the gate close to the substrate, the second current blocking layer, the second doped layer and the second electrode are arranged in a stack in the first direction and away from the substrate, and the second doped layer and the second electrode are arranged on the second side of the gate, the first side and the second side of the gate are respectively two opposite sides of the gate in the second direction. When the gate voltage of the semiconductor device is less than the threshold voltage and the voltage of the second electrode is greater than the voltage of the third electrode, and a voltage is also applied to the conductive electrode, the conductive electrode can be regarded as a gate, in this case, the conductivity of the side of the second current blocking layer close to the gate is increased, so that the semiconductor device can also be turned on, and at this time, the current flows from the second electrode, the side of the second current blocking layer close to the gate, the substrate to the third electrode. Thus, the enhancement-mode semiconductor device provided by the embodiment can be turned on under reverse bias without applying a voltage to the gate, thereby improving the passive freewheeling capability of the semiconductor device, that is, the working capability of the semiconductor device in the third quadrant.

[0009] In addition, the semiconductor device does not have a PN junction when turned on in the forward direction and the reverse direction, has small capacitance, fast switching speed and high current density.

[0010] In some embodiments, the third doped layer further comprises a first doped portion, the first doped portion is arranged on the side of the first current blocking layer close to the substrate, and is located on the side of the conductive electrode in the second direction.

[0011] In some embodiments, the surface of the third doped layer close to the substrate is flush with the surface of the second current blocking layer away from the substrate.

[0012] In some embodiments, the third doped layer further comprises a second doped portion, the second doped portion is arranged on the side of the first doped portion close to the substrate, and is connected with the first doped portion, and the side surface of the second doped portion is in contact with the side surface of the second current blocking layer.

[0013] In some embodiments, in a projection onto the substrate, part of the conductive electrode overlaps with part of the second current blocking layer; or, in a projection onto the substrate, the conductive electrode is located within a boundary range of the second current blocking layer.

[0014] In some embodiments, a doping concentration of the first doped layer is greater than a doping concentration of the first current blocking layer; a doping concentration of the second doped layer is greater than a doping concentration of the second current blocking layer.

[0015] In some embodiments, a doping concentration of the third doped layer is greater than a doping concentration of the first current blocking layer.

[0016] In some embodiments, the first doped layer, the second doped layer, the third doped layer and the substrate have the same doping type.

[0017] In some embodiments, the first electrode, the second electrode and the conductive electrode are electrically connected.

[0018] In some embodiments, the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer, the second sub-dielectric layer is closer to the gate than the first sub-dielectric layer; the conductive electrode is located between the first sub-dielectric layer and the second sub-dielectric layer.

[0019] In some embodiments, further comprising: a drift layer, disposed between the substrate and the first current blocking layer, and between the substrate and the second current blocking layer; the drift layer has the same doping type as the substrate, and a doping concentration of the drift layer is less than a doping concentration of the substrate.

[0020] In some embodiments, the first doped layer and the second doped layer both comprise gallium oxide, and both comprise silicon ions as doping ions; the first current blocking layer and the second current blocking layer both comprise gallium oxide, and both comprise magnesium ions as doping ions.

[0021] In some embodiments, the third doped layer comprises gallium oxide, and comprises silicon ions as doping ions.

[0022] In still another aspect, a power module is provided, comprising the semiconductor device as described in any of the above embodiments.

[0023] In still another aspect, an electronic device is provided, comprising the power module as described in any of the above embodiments.

[0024] The power module and the electronic device have the same structure and beneficial technical effects as the semiconductor device provided in some of the above embodiments, and thus repeated description is omitted here. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings in the following description are only some drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0026] Figure 1 A structural diagram of an electronic device provided by some embodiments of the present disclosure is shown in FIG. 1.

[0027] Figure 2 A structural diagram of a semiconductor device provided by some embodiments of the present disclosure is shown in FIG. 2.

[0028] Figure 3 A structural diagram of another semiconductor device provided by some embodiments of the present disclosure is shown in FIG. 3.

[0029] Figure 4 A structural diagram of another semiconductor device provided by some embodiments of the present disclosure is shown in FIG. 4.

[0030] Figure 5 A structural diagram of another semiconductor device provided by some embodiments of the present disclosure is shown in FIG. 5.

[0031] Figure 6 A structural diagram of another semiconductor device provided by some embodiments of the present disclosure is shown in FIG. 6.

[0032] Figure 7 A structural diagram of another semiconductor device provided by some embodiments of the present disclosure is shown in FIG. 7.

[0033] Figure 8 An output characteristic curve diagram of a semiconductor device provided by some embodiments of the present disclosure when forward conducting is shown in FIG. 8.

[0034] Figure 9 A transfer characteristic curve diagram of a semiconductor device provided by some embodiments of the present disclosure when forward conducting is shown in FIG. 9.

[0035] Figure 10 A conduction characteristic curve diagram of a semiconductor device provided by some embodiments of the present disclosure when reverse biased is shown in FIG. 10.

[0036] Figure 11 A flowchart of a preparation method of a semiconductor device provided by some embodiments of the present disclosure is shown in FIG. 11.

[0037] Figure 12 、 Figure 13 、Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 and Figure 23 A process schematic of a method of manufacturing a display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] The technical solutions in the some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art are within the scope of protection of the present disclosure.

[0039] Unless otherwise required by context, the term "comprises" in the specification and claims is to be construed as an open, inclusive meaning, i.e., "comprises, but is not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", or "some examples" are intended to mean that the particular feature, structure, material, or characteristic following the term is included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms do not necessarily indicate a same embodiment or example. In addition, the particular features, structures, materials, or characteristics described can be included in any suitable way in any one or more embodiments or examples.

[0040] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0041] In describing some embodiments, "connected" and its derivatives can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content herein.

[0042] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0043] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0044] The use of "applies to" or "configured as" in this article implies an open and inclusive language, which does not exclude...

[0045] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0046] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0047] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the areas shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0048] like Figure 1 As shown, this application provides an electronic device 1000. The electronic device 1000 can be a fast charger, an uninterruptible power supply (UPS), a power motor, or other electronic devices.

[0049] Continue to refer to Figure 1The electronic device 1000 includes a power module 1001 and a circuit board 1002, the power module 1001 and the circuit board 1002 are electrically connected, and the circuit board 1002 converts an external power supply into a voltage or a current required for the power module 1001 to work.

[0050] Exemplarily, the circuit board 1002 can include a printed circuit board (PCB) or the like.

[0051] Exemplarily, the circuit board 1002 can include a plurality of conductive layers. The plurality of conductive layers in the circuit board 1002 can be separated from each other by a dielectric layer.

[0052] The power module 1001 described above includes a semiconductor device.

[0053] The semiconductor device described above is described in detail below.

[0054] Reference Figure 2 The semiconductor device 100 includes a substrate 10, a gate 70, a conductive electrode 80, a first current blocking layer 41, a first doped layer 31, a first electrode 51, a second current blocking layer 42, a second doped layer 32, a second electrode 52, a dielectric layer 60, and a third electrode 53.

[0055] The gate 70 is arranged on one side of the substrate 10 in a first direction X, the first direction X being a thickness direction of the substrate 10; the conductive electrode 80 is arranged on a side of the gate 70 close to the substrate 10; the first current blocking layer 41, the first doped layer 31, and the first electrode 51 are stacked in a direction away from the substrate 10 along the first direction X, and are arranged on a first side C1 of the gate 70.

[0056] The second current blocking layer 42, the second doped layer 32, and the second electrode 52 are stacked in a direction away from the substrate 10 along the first direction X; the second doped layer 32 and the second electrode 52 are arranged on a second side C2 of the gate 70, the first side C1 and the second side C2 of the gate 70 being opposite sides of the gate 70 in a second direction Y, the second direction Y being perpendicular to the thickness direction of the substrate 10; the second current blocking layer 42 is arranged on a side of the conductive electrode 80 close to the substrate 10.

[0057] The dielectric layer 60 is arranged between each of the first current blocking layer 41, the first doped layer 31, the first electrode 51, the second doped layer 32, the second current blocking layer 42, and the conductive electrode 80 and the gate 70; the dielectric layer 60 also covers a surface of the conductive electrode 80 close to the substrate 10, and two opposite sides of the conductive electrode 80 along the second direction Y; the third electrode 53 is arranged on a side of the substrate 10 away from the gate 70.

[0058] In the semiconductor device 100, the gate 70 is arranged on one side of the substrate 10 in the first direction X, the first current blocking layer 41, the first doped layer 31 and the first electrode 51 are arranged in a stack along the first direction X and away from the substrate 10, and the third electrode 53 is arranged on the side of the substrate 10 away from the gate 70. Thus, when the voltage of the gate 70 of the semiconductor device 100 is less than the threshold voltage and the voltage of the third electrode 53 is greater than the voltage of the first electrode 51, the semiconductor device 100 is in an off state. When the voltage of the gate 70 of the semiconductor device 100 is greater than the threshold voltage of the semiconductor device 100 and the voltage of the third electrode 53 is greater than the voltage of the first electrode 51, the conductivity of the side of the first current blocking layer 41 close to the gate 70 increases, and the semiconductor device 100 is turned on. At this time, the current flows from the third electrode 53, through the substrate 10, the side of the first current blocking layer 41 close to the gate 70, the first doped layer 31 and the first electrode 51. Thus, the semiconductor device 100 provided by the embodiment is an enhancement-mode semiconductor device.

[0059] On the other hand, since the conductive electrode 80 is arranged on the side of the gate 70 close to the substrate 10, the second current blocking layer 42, the second doped layer 32 and the second electrode 52 are arranged in a stack along the first direction X and away from the substrate 10, and the second doped layer 32 and the second electrode 52 are arranged on the second side C2 of the gate 70, the first side C1 and the second side C2 of the gate 70 are opposite sides of the gate 70 in the second direction Y. Thus, when the voltage of the gate 70 of the semiconductor device 100 is less than the threshold voltage and the voltage of the second electrode 52 is greater than the voltage of the third electrode 53, and a voltage is also applied to the conductive electrode 80, the conductive electrode 80 can be regarded as a gate. In this case, the conductivity of the side of the second current blocking layer 42 close to the gate 70 increases, so that the semiconductor device 100 can also be turned on. At this time, the current flows from the second electrode 52, through the second doped layer 32, the side of the second current blocking layer 42 close to the gate 70, the substrate 10 and the third electrode 53. Thus, the enhancement-mode semiconductor device provided by the embodiment can be turned on under reverse bias without applying a voltage to the gate 70, thereby improving the passive freewheeling capability of the semiconductor device 100, that is, the working capability of the semiconductor device 100 in the third quadrant.

[0060] In addition, the semiconductor device 100 does not have a PN junction when turned on in the forward direction and the reverse direction, has small capacitance, fast switching speed and high current density.

[0061] In the semiconductor device 100, the first electrode 51 and the second electrode 52 are source electrodes, and the third electrode 53 is a drain electrode.

[0062] In some embodiments, reference is made to Figure 3In the orthographic projection onto the substrate 10, the conductive electrode 80 is located within the boundary range of the second current blocking layer 42. When the gate voltage of the semiconductor device 100 is less than the threshold voltage, and the voltage of the second electrode 52 is greater than the voltage of the third electrode 53, while a voltage is also applied to the conductive electrode 80, the conductive electrode 80 can be regarded as a gate electrode. Since the conductive electrode 80 is located within the boundary range of the second current blocking layer 42, the conductive electrode 80 has a large overlapping area with the second current blocking layer 42, so that the electric field of the conductive electrode 80 can more effectively modulate the depletion region of the second current blocking layer 42, enhance the electric field regulation ability, and also improve the stability of the threshold voltage of the semiconductor device 100 and reduce the leakage current. In addition, the control area of the conductive electrode 80 can be expanded, which is beneficial to form a more uniform conductive channel.

[0063] In some embodiments, the conductive electrode 80 is located within the boundary range of the second current blocking layer 42 in the orthographic projection onto the substrate 10. Figure 2 In some embodiments, part of the conductive electrode 80 overlaps with part of the second current blocking layer 42 in the orthographic projection onto the substrate 10. This can reduce the parasitic capacitance between the conductive electrode 80 and the second current blocking layer 42, thereby improving the switching speed of the semiconductor device 100. In addition, it is also beneficial to reduce the area of the high resistance region, so that the working current density of the semiconductor device 100 can be increased.

[0064] In some embodiments, the doping concentration of the first doped layer 31 is greater than the doping concentration of the first current blocking layer 41. The high doping concentration of the first doped layer 31 enhances the concentration and migration efficiency of the carriers, provides a low resistance channel for the carriers, and is beneficial to the efficient transmission of the carriers in the vertical direction (for example, from the source to the drain), thereby reducing the power loss of the semiconductor device 100. The low doping concentration of the first current blocking layer 41 is beneficial to form a uniformly distributed electric field, avoid local electric field concentration, and improve the breakdown voltage of the semiconductor device 100. When the semiconductor device 100 is in the on state, the low concentration of the first current blocking layer 41 has less resistance to the vertical current path, which is beneficial to charge balance in combination with the high concentration of the first doped layer 31, thereby reducing the on resistance while maintaining high voltage resistance.

[0065] For example, the doping concentration of the first doped layer 31 is 5E18cm -3 ~ 5E19cm -3 , for example 5E18cm -3 , 6E18cm -3 or 5E19cm -3 .

[0066] For example, the doping concentration of the first current blocking layer 41 is 5E14cm -3 ~ 5E15cm -3 , for example 5E14cm -3 , 6E14cm-3 , 7E14 cm -3 or 5E15 cm -3 .

[0067] In some embodiments, the doping concentration of the second doped layer 32 is greater than the doping concentration of the second current blocking layer 42. The high doping concentration of the second doped layer 32 enhances the carrier concentration and mobility, providing a low resistance path for the carriers and facilitating efficient transport of the carriers in the vertical direction (e.g., from the source to the drain), thereby reducing the power loss of the semiconductor device 100. The low doping concentration of the second current blocking layer 42 facilitates the formation of a uniform electric field and avoids local electric field concentration, improving the breakdown voltage of the semiconductor device 100. In the on-state of the semiconductor device 100, the low concentration of the second current blocking layer 42 has less resistance to the vertical current path, which, in combination with the high concentration of the second doped layer 32, facilitates charge balance, reducing the on-resistance while maintaining high voltage resistance.

[0068] In addition, due to the high doping concentration of the second doped layer 32, the current density flowing through the second doped layer 32 can be increased under a reverse bias voltage.

[0069] For example, the doping concentration of the second doped layer 32 is 5E18 cm -3 ~ 5E19 cm -3 , for example 5E18 cm -3 , 6E18 cm -3 or 5E19 cm -3 .

[0070] For example, the doping concentration of the second current blocking layer 42 is 5E14 cm -3 ~ 5E15 cm -3 , for example 5E14 cm -3 , 6E14 cm -3 , 7E14 cm -3 or 5E15 cm -3 .

[0071] In some embodiments, the materials of the first doped layer 31 and the second doped layer 32 both include gallium oxide, and the doping ions both include silicon ions. Since the band gap of gallium oxide (β-Ga2O3) is 4.8 eV, which is much higher than that of silicon carbide (3.2 eV) and gallium nitride (3.4 eV), it has a super-high breakdown field strength and higher voltage resistance capability. In addition, gallium oxide also has lower on-resistance and higher power conversion efficiency. The low on-resistance of gallium oxide can also reduce the on-state loss.

[0072] The doping ions of the first doped layer 31 and the second doped layer 32 both include silicon ions, which act as shallow donor impurities in gallium oxide and can provide high-concentration free electrons. Thus, the first doped layer 31 and the second doped layer 32 are N-type conductive, which, in combination with the wide band gap characteristics of gallium oxide, can withstand a high critical breakdown field of 8 MV / cm, making the semiconductor device 100 suitable for high-voltage application scenarios. In addition, the diffusion coefficient of silicon ions in gallium oxide is low, which is conducive to forming a steep doping interface and suppressing doping drift. Thus, the carrier distribution can be precisely controlled, and the stability is better when working at high temperatures.

[0073] In addition, since the p-type doping efficiency of gallium oxide is extremely low and the hole mobility is poor, doping silicon ions in the first doped layer 31 and the second doped layer 32 can avoid this technical difficulty.

[0074] In some embodiments, the thickness of the first doped layer 31 is 0.4 μm to 0.6 μm, for example, 0.4 μm, 0.5 μm, or 0.6 μm.

[0075] In some embodiments, the materials of the first current blocking layer 41 and the second current blocking layer 42 both include gallium oxide. Since the first current blocking layer 41 is in contact with the first doped layer 31, and the materials of the first current blocking layer 41 and the first doped layer 31 both include gallium oxide, not only can the hetero-interface defects be eliminated, the interface state density be reduced, and the carrier transport efficiency be improved, but also the epitaxial growth process can be simplified, and the lattice mismatch problem caused by hetero-epitaxy can be avoided, significantly improving the manufacturing yield of the semiconductor device.

[0076] Similarly, since the second current blocking layer 42 is in contact with the second doped layer 32, and the materials of the second current blocking layer 42 and the second doped layer 32 both include gallium oxide, the hetero-interface defects can also be eliminated, the interface state density can be reduced, the carrier transport efficiency can be improved, and the epitaxial growth process can be simplified, avoiding the lattice mismatch problem caused by hetero-epitaxy, significantly improving the manufacturing yield of the semiconductor device.

[0077] The doping ions of the first current blocking layer 41 and the second current blocking layer 42 both include magnesium ions. Since magnesium ion doping can form deep-level acceptor states in gallium oxide, effectively compensating for intrinsic carriers, the first current blocking layer 41 and the second current blocking layer 42 both exhibit high resistance characteristics, thereby suppressing leakage current and improving the voltage withstand capability of the semiconductor device 100.

[0078] In some embodiments, the thickness of the first current blocking layer 41 is 0.8 μm to 1.2 μm, for example, 0.8 μm, 1.0 μm, or 1.2 μm.

[0079] In some embodiments, the conductive electrode 80, the first electrode 51 and the second electrode 52 are made of the same material. In this way, the conductive electrode 80, the first electrode 51 and the second electrode 52 can be simultaneously prepared, i.e., formed in the same preparation step, thereby reducing the number of photolithography, deposition and other process steps, and reducing the complexity of manufacturing and production cost.

[0080] For example, the conductive electrode 80, the first electrode 51 and the second electrode 52 are made of gold or nickel. In other embodiments, the conductive electrode 80, the first electrode 51 and the second electrode 52 can also be made of other conductive metals.

[0081] In some embodiments, the third electrode 53 is made of the same material as the first electrode 51 and the second electrode 52.

[0082] For example, the third electrode 53 is made of gold or titanium. In other embodiments, the third electrode 53 can also be made of other conductive metals.

[0083] In some embodiments, the first electrode 51, the second electrode 52 and the conductive electrode 80 are electrically connected. That is, the potentials of the first electrode 51, the second electrode 52 and the conductive electrode 80 can be input by using the same input terminal, which not only reduces the complexity of the structure of the semiconductor device 100, but also improves the response speed of the semiconductor device 100.

[0084] In some embodiments, the semiconductor device 100 further comprises a connecting portion (not shown) disposed on at least one side of the gate 70 in the third direction Z, the third direction Z being perpendicular to the first direction X and the second direction Y; one end of the connecting portion is electrically connected to the conductive electrode 80, and the other end is electrically connected to the first electrode 51 and the second electrode 52; and the dielectric layer 60 is located between the gate 70 and the connecting portion. In this way, the connecting portion electrically connects the first electrode 51, the second electrode 52 and the conductive electrode 80, which reduces the complexity of the structure of the semiconductor device 100 and improves the response speed of the semiconductor device 100.

[0085] In some embodiments, the dielectric layer 60 comprises a first sub-dielectric layer 61 and a second sub-dielectric layer 62, the second sub-dielectric layer 62 being closer to the gate 70 than the first sub-dielectric layer 61; and the conductive electrode 80 is located between the first sub-dielectric layer 61 and the second sub-dielectric layer 62. The first sub-dielectric layer 61 and the second sub-dielectric layer 62 are separate film layers on the side of the gate 70 close to the substrate 10, and the first sub-dielectric layer 61 and the second sub-dielectric layer 62 are in contact with each other on the side wall of the gate 70.

[0086] In some embodiments, the material of the first sub dielectric layer 61 and the second sub dielectric layer 62 can be the same, and in other embodiments, the material of the first sub dielectric layer 61 and the second sub dielectric layer 62 can also be different.

[0087] For example, the material of the first sub dielectric layer 61 and the second sub dielectric layer 62 is both silicon dioxide (SiO2); or, the material of the first sub dielectric layer 61 and the second sub dielectric layer 62 is both aluminum oxide (Al2O3).

[0088] For example, the material of the first sub dielectric layer 61 is silicon dioxide (SiO2), and the material of the second sub dielectric layer 62 is aluminum oxide (Al2O3).

[0089] For example, the material of the first sub dielectric layer 61 is aluminum oxide (Al2O3), and the material of the second sub dielectric layer 62 is silicon dioxide (SiO2).

[0090] In some embodiments, reference can be made to Figure 2 The semiconductor device 100 further comprises a drift layer 20, which is arranged between the substrate 10 and the first current blocking layer 41, and between the substrate 10 and the second current blocking layer 42. The drift layer 20 is used to withstand high voltage of the semiconductor device 100 in an off state or reverse bias.

[0091] The drift layer 20 has the same doping type as the substrate 10, and the doping concentration of the drift layer 20 is less than that of the substrate 10. The drift layer 20 has the same doping type as the substrate 10, so that the drift layer 20 can be epitaxially grown directly on the substrate 10 without switching the doping type, which not only reduces interface defects and stress, but also avoids the occurrence of heterojunction interface electric field distortion. In addition, the substrate 10 adopts high-concentration doping (low resistance), so that it can be used as a mechanical support and a current path, and the drift layer 20 adopts low-concentration doping, so that the drift layer 20 can withstand high voltage and form a wider depletion layer, thereby dispersing the electric field intensity and avoiding breakdown, and improving the voltage withstand capability of the semiconductor device 100.

[0092] In some embodiments, the material of the substrate 10 and the drift layer 20 includes gallium oxide.

[0093] The substrate 10 and the drift layer 20 are doped with silicon ions.

[0094] For example, the doping concentration of the substrate 10 is greater than 5E18cm -3 , for example, the doping concentration of the substrate 10 is 5E18cm -3 ~5E19cm -3 .

[0095] For example, the doping concentration of the drift layer 20 is 1E16cm-3 5E17cm -3 For example, the doping concentration of the drift layer 20 is 1E16cm -3 or 5E17cm -3 .

[0096] In some embodiments, the thickness of the substrate 10 is 600μm~700μm, for example: 600μm, 650μm or 700μm.

[0097] In some embodiments, the thickness of the drift layer 20 is 6μm~8μm, for example: 6μm, 7μm or 8μm.

[0098] Referring to Figure 4 or Figure 5 , the semiconductor device 100 further comprises a third doped layer 33, the third doped layer 33 comprises a first doped part 331; the first doped part 331 is arranged on the side of the first current blocking layer 41 close to the substrate 10 and on the side of the conductive electrode 80 along the second direction Y. In this way, when the semiconductor device 100 works under positive bias voltage, the depletion of the third doped layer 33 caused by the conductive electrode 80 can be weakened, so that the channel formed by the gate 70 will not be blocked by the depletion layer formed by the conductive electrode 80, which is beneficial to improve the current density of the semiconductor device 100 under positive bias voltage.

[0099] In some embodiments, referring to Figure 4 or Figure 5 , the surface of the third doped layer 33 close to the substrate 10 is flush with the surface of the second current blocking layer 42 away from the substrate 10. In this way, the channel formed by the gate 70 will not be blocked by the depletion layer formed by the conductive electrode 80 to the greatest extent, which is beneficial to improve the current density of the semiconductor device 100 under positive bias voltage.

[0100] In some embodiments, referring to Figure 6 or Figure 7 , the third doped layer 33 further comprises a second doped part 332, the second doped part 332 is arranged on the side of the first doped part 331 close to the substrate 10 and connected with the first doped part 331; the side surface of the second doped part 332 is in contact with the side surface of the second current blocking layer 42. In this way, not only the current density of the semiconductor device 100 under positive bias voltage can be improved, but also the current density of the semiconductor device 100 under negative bias voltage can be improved.

[0101] In the case that the semiconductor device 100 includes the third doped layer 33, the doping concentration of the third doped layer 33 is greater than the doping concentration of the first current blocking layer 41. In this way, the semiconductor device 100 can ensure that the channel formed by the gate 70 is not blocked by the depletion layer formed by the conductive electrode 80 when the semiconductor device 100 is working under positive bias voltage, and can improve the current density of the semiconductor device 100 under positive bias voltage; and can also improve the current density of the semiconductor device 100 when working under reverse bias voltage.

[0102] For example, the doping concentration of the third doped layer 33 is 5E18cm -3 ~ 5E19cm -3 For example, the doping concentration of the third doped layer 33 is 5E18cm -3 , 6E18cm -3 , or 5E19cm -3 .

[0103] For example, the doping concentration of the first current blocking layer 41 is 5E14cm -3 ~ 5E15cm -3 For example, the doping concentration of the first current blocking layer 41 is 5E14cm -3 , 6E14cm -3 , 7E14cm -3 , or 5E15cm -3 .

[0104] In some embodiments, the first doped layer 31, the second doped layer 32, the third doped layer 33 and the substrate 10 have the same doping type. In this way, a continuous conduction path can be provided for electrons, the on-resistance of the semiconductor device 100 can be reduced, the epitaxial growth process can be simplified, the interface defect accumulation caused by the switching of the doping type can be reduced, and thus the reliability of the semiconductor device 100 can be improved.

[0105] In some embodiments, the material of the third doped layer 33 includes gallium oxide, and the doping ions include silicon ions. That is, the materials of the first doped layer 31 and the third doped layer 33 located on both sides of the first current blocking layer 41 are the same, and the doping ions are also the same, so that a PN junction is not formed in the semiconductor device 100, the capacitance can be reduced, the switching speed can be improved, and the working current of the semiconductor device 100 can be improved.

[0106] Similarly, under reverse bias voltage, the materials of the second doped layer 32 and the third doped layer 33 on both sides of the second current blocking layer 42 are the same, and the doping ions are also the same, so that a PN junction is not formed in the semiconductor device 100, the capacitance can be reduced, the switching speed can be improved, and the working current of the semiconductor device 100 can be improved.

[0107] Figure 8 A semiconductor device 100 provided by some embodiments of the present disclosure has an output characteristic curve when working in forward conduction,Figure 8 The horizontal axis in the figure represents the voltage V. DS The size (that is, the third electrode 53 is the drain of the semiconductor device 100, the first electrode 51 is the source of the semiconductor device 100, V) DS The vertical axis represents the voltage difference between the third electrode 53 and the first electrode 51, while the vertical axis represents the current I. DS Size (I) DS This refers to the magnitude of the current from the drain to the source, which is the magnitude of the current from the third electrode 53 to the first electrode 51. Figure 9 A transfer characteristic curve of a semiconductor device 100 in forward conduction is provided for some embodiments of this disclosure. Figure 9 The horizontal axis in the figure represents the gate voltage V. g The magnitude of the value is shown on the ordinate, where the vertical axis represents the current I. DS The size. In Figure 8 and Figure 9 From Figure 8 It can be seen from this that semiconductor device 100 exhibits a field effect, and the current I DS With gate voltage V g The increase is due to the increase in gate voltage V. g When the current is 0, there is no current in semiconductor device 100. Figure 9 In the middle, the fixed voltage V DS =20V, which shows that the threshold voltage V of semiconductor device 100 th It is approximately 3V, and semiconductor device 100 is an enhancement semiconductor device.

[0108] Figure 10 A conduction characteristic curve of a semiconductor device 100 under reverse bias is provided for some embodiments of this disclosure. Figure 10 The horizontal axis in the figure represents the voltage V. SD The size (that is, the third electrode 53 is the drain of the semiconductor device 100, the second electrode 52 is the source of the semiconductor device 100, V) SD The vertical axis represents the voltage difference between the second electrode 52 and the third electrode 53, while the vertical axis represents the current I. SD Size (I) SD This refers to the magnitude of the current from the source to the drain, that is, the magnitude of the current from the second electrode 52 to the third electrode 53. Where V... DS =-10V, that is, V SD =10V (where the second electrode 52 and the conductive electrode 80 are electrically connected, the second electrode 52 is the source, and the third electrode 53 is the drain), gate voltage V g =0V. In this case, from the IV curve of semiconductor device 100, it can be seen that semiconductor device 100 at V SD It achieved conduction at 3V, and at VSD Current I at 10V SD Density is higher.

[0109] Embodiments of the present disclosure also provide a method for manufacturing a semiconductor device, referring to Figure 11 , comprising the following steps:

[0110] Step S1: referring to Figures 12-16 , a first stack structure D1 and a second stack structure D2 are formed on one side of the substrate 10 along a first direction X, the first direction X being a thickness direction of the substrate 10; the first stack structure D1 and the second stack structure D2 are spaced apart along a second direction Y, and a first groove G1 is formed between the first stack structure D1 and the second stack structure D2, the second direction Y being perpendicular to the first direction X; the first stack structure D1 comprises a first current blocking layer 41 and a first doped layer 31 disposed on a side of the first current blocking layer 41 away from the substrate 10; the second stack structure D2 comprises a second current blocking layer 42 and a second doped layer 32 disposed on a side of the second current blocking layer 42 away from the substrate 10; and the first groove G1 exposes part of the surface of the second current blocking layer 42.

[0111] In some embodiments, step S1 comprises:

[0112] Step S11: referring to Figure 12 , an initial drift layer 200, an initial first current blocking layer 410 and an initial first doped layer 310 are sequentially formed on one side of the substrate 10.

[0113] Here, the materials of the substrate 10, the initial drift layer 200, the initial first current blocking layer 410 and the initial first doped layer 310 all comprise gallium oxide.

[0114] In some embodiments, the doping ions of the substrate 10 comprise silicon ions, and the doping concentration of the substrate 10 is greater than 5E18cm -3 .

[0115] For example, the doping concentration of the substrate 10 is 5E18cm -3 ~5E19cm -3 .

[0116] In some embodiments, the thickness of the substrate 10 is 600μm~700μm, for example: 600μm, 650μm or 700μm.

[0117] In some embodiments, the process of forming the initial drift layer 200, the initial first current blocking layer 410 and the initial first doped layer 310 comprises a metal-organic chemical vapor deposition (MOCVD) process.

[0118] In some embodiments, in forming the initial drift layer 200, a gallium source includes Trimethylgallium (TMGa), an oxygen source includes high purity oxygen, a dopant source includes silane (SiH4), a carrier gas includes argon, a growth temperature is 700°C to 800°C, e.g., 700°C, 750°C, or 800°C, and a growth pressure is 35 mbar to 45 mbar, e.g., 35 mbar, 40 mbar, or 45 mbar.

[0119] In some embodiments, the molar flow of the Trimethylgallium is 35 pmol / min to 40 pmol / min, e.g., 35 pmol / min, 38 pmol / min, or 40 pmol / min.

[0120] In some embodiments, the molar flow of the oxygen is 17,000 pmol / min to 19,000 pmol / min, e.g., 17,000 pmol / min, 18,000 pmol / min, or 19,000 pmol / min.

[0121] In some embodiments, the molar flow of the silane is 0.0004 pmol / min to 0.0006 pmol / min, e.g., 0.0004 pmol / min, 0.0005 pmol / min, or 0.0006 pmol / min.

[0122] In some embodiments, the initial drift layer 200 has a thickness of 6 pm to 8 pm, e.g., 6 pm, 7 pm, or 8 pm.

[0123] In some embodiments, in forming the initial first current blocking layer 410, a gallium source includes Trimethylgallium (TMGa), an oxygen source includes high purity oxygen, a magnesium source includes Bis(cyclopentadienyl) magnesium (Cp2Mg), a carrier gas includes argon, a growth temperature is 700°C to 800°C, e.g., 700°C, 750°C, or 800°C, and a growth pressure is 35 mbar to 45 mbar, e.g., 35 mbar, 40 mbar, or 45 mbar.

[0124] In some embodiments, the molar flow of the Trimethylgallium is 35 pmol / min to 40 pmol / min, e.g., 35 pmol / min, 38 pmol / min, or 40 pmol / min.

[0125] In some embodiments, the molar flow of the oxygen is 17,000 pmol / min to 19,000 pmol / min, e.g., 17,000 pmol / min, 18,000 pmol / min, or 19,000 pmol / min.

[0126] The molar flow of dimethyl magnesium is 2.4 pmol / min to 2.6 pmol / min, for example 2.4 pmol / min, 2.5 pmol / min or 2.6 pmol / min.

[0127] In some embodiments, the thickness of the initial first current blocking layer 410 is 0.8 pm to 1.2 pm, for example 0.8 pm, 1 pm or 1.2 pm.

[0128] In some embodiments, in the process of forming the initial first doped layer 310, the gallium source comprises Trimethylgallium (TMGa), the oxygen source is high purity oxygen, the doping source is silane (SiH4), the carrier gas used is argon, the growth temperature is 700°C to 800°C, for example 700°C, 750°C or 800°C, and the growth pressure is 35 mbar to 45 mbar, for example 35 mbar, 40 mbar or 45 mbar.

[0129] The molar flow of trimethyl gallium is 35 pmol / min to 40 pmol / min, for example 35 pmol / min, 38 pmol / min or 40 pmol / min.

[0130] The molar flow of oxygen is 17,000 pmol / min to 19,000 pmol / min, for example 17,000 pmol / min, 18,000 pmol / min or 19,000 pmol / min.

[0131] The molar flow of silane is 1.0 pmol / min to 1.2 pmol / min, for example 1.0 pmol / min, 1.1 pmol / min or 1.2 pmol / min.

[0132] In some embodiments, the thickness of the initial first doped layer 310 is 0.4 pm to 0.6 pm, for example 0.4 pm, 0.5 pm or 0.6 pm.

[0133] In some embodiments, step S11 further comprises: between forming the initial drift layer 200 and forming the initial first current blocking layer 410, further comprising: forming an initial third doped layer 330.

[0134] In some embodiments, in the process of forming the initial third doped layer 330, the gallium source used includes Trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the doping source is silane (SiH4), the carrier gas used is argon, the growth temperature is 700-800°C, for example 700°C, 750°C or 800°C, and the growth pressure is 35-45 mbar, for example 35 mbar, 40 mbar or 45 mbar.

[0135] The molar flow rate of the Trimethylgallium is 35-40 μmol / min, for example 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0136] The molar flow rate of the oxygen is 17,000-19,000 μmol / min, for example 17,000 μmol / min, 18,000 μmol / min or 19,000 μmol / min.

[0137] The molar flow rate of the silane is 1.0-1.2 μmol / min, for example 1.0 μmol / min, 1.1 μmol / min or 1.2 μmol / min.

[0138] In some embodiments, the thickness of the initial third doped layer 330 is 0.4-0.6 μm, for example 0.4 μm, 0.5 μm or 0.6 μm.

[0139] Step S12: Referring to Figure 13 , the initial drift layer 200, the initial first current blocking layer 410 and the initial first doped layer 310 located in the first target region X1 are removed to form a first opening K1; the bottom surface of the first opening K1 is lower than the bottom surface of the initial first current blocking layer 410.

[0140] Here, the step of removing the initial drift layer 200, the initial first current blocking layer 410 and the initial first doped layer 310 located in the first target region X1 includes: disposing a mask on the surface of the initial first doped layer 310 away from the substrate 10, the mask exposing the initial first doped layer 310 located in the first target region X1.

[0141] The material of the mask includes metal. For example, the material of the mask is nickel.

[0142] In some embodiments, the process of removing the initial drift layer 200, the initial first current blocking layer 410 and the initial first doped layer 310 located in the first target region X1 comprises dry etching. Inductively Coupled Plasma (ICP) can be used in particular. When etching, the radio frequency power on the inductive coupling coil is set to 300 W, the bias power is 200 W, and the pressure in the process cavity is 1 Pa. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching speed is 80 nm / min to 120 nm / min, for example 80 nm / min, 100 nm / min or 120 nm / min.

[0143] In some embodiments, the flow rate of carbon tetrafluoride (CF4) is 25 sccm to 35 sccm, for example 25 sccm, 30 sccm or 35 sccm.

[0144] In some embodiments, the flow rate of argon (Ar) is 5 sccm to 6 sccm, for example 5 sccm or 6 sccm.

[0145] In some embodiments, in the process of removing the initial drift layer 200, the initial first current blocking layer 410 and the initial first doped layer 310 located in the first target region X1, part of the thickness of the initial drift layer 200 is also removed, and then the initial drift layer 200 forms the drift layer 20.

[0146] For example, the thickness of the removed initial drift layer 200 is 450 nm to 550 nm, for example 500 nm.

[0147] In some embodiments, with reference to Figure 13 In the case of forming the initial third doped layer 330, in the process of removing the initial drift layer 200, the initial first current blocking layer 410 and the initial first doped layer 310 located in the first target region X1, and forming the first opening K1, the initial third doped layer 330 located in the first target region X1 is also removed.

[0148] Step S13: with reference to Figure 14 and Figure 15 The initial second current blocking layer 420 and the initial second doped layer 320 are formed in the first opening K1.

[0149] In some embodiments, in forming the initial second current blocking layer 420, a gallium source includes Trimethylgallium (TMGa), an oxygen source includes high purity oxygen, a magnesium source includes Bis(cyclopentadienyl) magnesium (Cp2Mg), a carrier gas includes argon, a growth temperature is 700°C to 800°C, such as 700°C, 750°C, or 800°C, and a growth pressure is 35 mbar to 45 mbar, such as 35 mbar, 40 mbar, or 45 mbar.

[0150] The molar flow rate of the Trimethylgallium is 35 pmol / min to 40 pmol / min, such as 35 pmol / min, 38 pmol / min, or 40 pmol / min.

[0151] The molar flow rate of the oxygen is 17,000 pmol / min to 19,000 pmol / min, such as 17,000 pmol / min, 18,000 pmol / min, or 19,000 pmol / min.

[0152] The molar flow rate of the Bis(cyclopentadienyl) magnesium is 2.4 pmol / min to 2.6 pmol / min, such as 2.4 pmol / min, 2.5 pmol / min, or 2.6 pmol / min.

[0153] In some embodiments, the initial second current blocking layer 420 has a thickness of 0.4 pm to 0.6 pm, such as 0.4 pm, 0.5 pm, or 0.6 pm.

[0154] In some embodiments, in forming the initial first doped layer 310, a gallium source includes Trimethylgallium (TMGa), an oxygen source includes high purity oxygen, a dopant source includes silane (SiH4), a carrier gas includes argon, a growth temperature is 700°C to 800°C, such as 700°C, 750°C, or 800°C, and a growth pressure is 35 mbar to 45 mbar, such as 35 mbar, 40 mbar, or 45 mbar.

[0155] The molar flow rate of the Trimethylgallium is 35 pmol / min to 40 pmol / min, such as 35 pmol / min, 38 pmol / min, or 40 pmol / min.

[0156] The molar flow rate of the oxygen is 17,000 pmol / min to 19,000 pmol / min, such as 17,000 pmol / min, 18,000 pmol / min, or 19,000 pmol / min.

[0157] The molar flow rate of the silane is 1.0 μmol / min to 1.2 μmol / min, for example 1.0 μmol / min, 1.1 μmol / min or 1.2 μmol / min.

[0158] In some embodiments, the thickness of the initial second doped layer 320 is 1 μm to 3 μm, for example 1 μm, 2 μm or 3 μm.

[0159] Since the initial second current blocking layer 420 and the initial second doped layer 320 are formed on the side surface of the initial first doped layer 310 away from the substrate 10 during the process of forming the initial second current blocking layer 420 and the initial second doped layer 320 in the first opening K1, the initial second current blocking layer 420 and the initial second doped layer 320 on the side surface of the initial first doped layer 310 away from the substrate 10 also need to be removed.

[0160] In some embodiments, the process of removing the initial second current blocking layer 420 and the initial second doped layer 320 on the side surface of the initial first doped layer 310 away from the substrate 10 includes dry etching. Inductively coupled plasma can be used in particular. The radio frequency power on the inductive coupling coil is set to 300 W, the bias power is set to 200 W, and the pressure in the process chamber is set to 1 Pa during etching. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching speed is 80 nm / min to 120 nm / min, for example 80 nm / min, 100 nm / min or 120 nm / min.

[0161] The flow rate of the carbon tetrafluoride (CF4) is 28 sccm to 32 sccm, for example 28 sccm, 30 sccm or 32 sccm; and the flow rate of the argon (Ar) is 4 sccm to 6 sccm, for example 4 sccm, 5 sccm or 6 sccm.

[0162] Step S14: Referring to Figure 16 , the initial first doped layer 310, the initial first current blocking layer 410 and the initial second doped layer 320 in the second target region X2 are removed to form a first groove G1.

[0163] Here, the step of removing the initial first doped layer 310, the initial first current blocking layer 410 and the initial second doped layer 320 in the second target region X2 includes: disposing a mask on the surface of the initial first doped layer 310 and the initial second doped layer 320 away from the substrate 10, the mask exposing the initial first doped layer 310 and the initial second doped layer 320 in the second target region X2.

[0164] The material of the mask includes a metal. For example, the material of the mask is nickel.

[0165] The mask is a metal prepared by a lift-off process.

[0166] In some embodiments, the process of removing the initial first doped layer 310, the initial first current blocking layer 410 and the initial second doped layer 320 located in the second target region X2 includes dry etching. Specifically, inductively coupled plasma can be used. The first groove G1 has a depth of 2 μm.

[0167] The radio frequency power on the inductive coupling coil is set to 300 W, the bias power is 200 W, and the pressure in the process cavity is 1 Pa during etching. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching speed is 80 nm / min to 120 nm / min, for example, 80 nm / min, 100 nm / min, or 120 nm / min.

[0168] The flow rate of carbon tetrafluoride (CF4) is 28 sccm to 32 sccm, for example, 28 sccm, 30 sccm, or 32 sccm; the flow rate of argon (Ar) is 4 sccm to 6 sccm, for example, 4 sccm, 5 sccm, or 6 sccm.

[0169] After step S14, in combination with reference to Figure 15 and Figure 16 , the initial first current blocking layer 410 forms the first current blocking layer 41, the initial first doped layer 310 forms the first doped layer 31, the initial third doped layer 330 forms the third doped layer 33, and the initial second doped layer 320 forms the second doped layer 32.

[0170] In the preparation method of the semiconductor device 100, the first stack structure D1 and the second stack structure D2 are spaced apart along the second direction Y, and the first groove G1 is formed between the two. Since only one trench structure needs to be formed during the preparation of the semiconductor device 100, there is no need for side slotting, and therefore the preparation process of the semiconductor device 100 is simple.

[0171] Step S2: in combination with reference to Figures 17-21 , a dielectric layer 60 and a conductive electrode 80 are formed in the first groove G1; the conductive electrode 80 is located at the bottom of the first groove G1, the dielectric layer 60 is located between the bottom surface of the first groove G1 and the conductive electrode 80, the dielectric layer 60 also covers the surface of the conductive electrode 80 away from the substrate 10, the conductive electrode 80 has two opposite sides along the second direction Y, and the sidewall of the first groove G1.

[0172] In step S2, the following steps are included:

[0173] Step S21: in combination with reference to Figure 17 andFigure 18 The first sub dielectric layer 61 is formed on the bottom surface and the sidewall of the first groove G1.

[0174] Specifically, referring to Figure 17 and Figure 18 The first sub dielectric layer 61 is formed on the sample surface with the first groove G1. The first sub dielectric layer 61 located on the side away from the substrate 10 of the first doped layer 31 and the second doped layer 32 is removed, so that the first sub dielectric layer 61 is formed on the bottom surface and the sidewall of the first groove G1.

[0175] Here, the process of forming the first sub dielectric layer 61 includes an atomic layer deposition (ALD) process.

[0176] The material of the first sub dielectric layer 61 includes hafnium dioxide (HfO2). The thickness of the first sub dielectric layer 61 is 18 nm to 22 nm, for example, 18 nm, 20 nm, or 22 nm.

[0177] The measured value of the relative dielectric constant of the first sub dielectric layer 61 is 25 under an alternating electric field frequency of 1 megahertz (1 MHz).

[0178] In the process of forming the first sub dielectric layer 61, the source used is tetra(ethylmethylamino)hafnium (TEMAHf) and H2O, the growth temperature is 200°C, the growth pressure is 1000 Pa, and the growth is performed for 400 cycles.

[0179] In some embodiments, the process of removing the first sub dielectric layer 61 located on the side away from the substrate 10 of the first doped layer 31 and the second doped layer 32 includes dry etching. Specifically, an inductively coupled plasma can be used. When etching, the radio frequency power on the inductive coupling coil is set to 300 W, the bias power is 200 W, and the pressure in the process cavity is 1 Pa. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching speed is 80 nm / min to 120 nm / min, for example, 80 nm / min, 100 nm / min, or 120 nm / min.

[0180] The flow rate of carbon tetrafluoride (CF4) is 28 sccm to 32 sccm, for example, 28 sccm, 30 sccm, or 32 sccm; and the flow rate of argon (Ar) is 4 sccm to 6 sccm, for example, 4 sccm, 5 sccm, or 6 sccm.

[0181] Step S22: referring to Figure 19 The conductive electrode 80 is formed on the bottom of the second groove G2.

[0182] Here, the lift-off technique can be used to form the conductive electrode 80 on the bottom of the second groove G2. The process of forming the conductive electrode 80 includes an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr, and the evaporation rate is 0.5 angstrom / second.

[0183] The material of the conductive electrode 80 includes a metal, such as titanium.

[0184] The thickness of the conductive electrode 80 is 18 nm to 22 nm, such as 18 nm, 20 nm, or 22 nm.

[0185] Step S23: Referring to Figure 20 The second sub-dielectric layer 62 is formed on the side of the conductive electrode 80 away from the substrate 10 and the sidewall of the second groove G2, and the first sub-dielectric layer 61 and the second sub-dielectric layer 62 form the dielectric layer 60.

[0186] Specifically, referring to Figure 19 , Figure 20 and Figure 21 , the second sub-dielectric layer 62 is formed on the sample surface with the second groove G2, the second sub-dielectric layer 62 on the side of the first doped layer 31 and the second doped layer 32 away from the substrate 10 is removed, and the first sub-dielectric layer 61 and the second sub-dielectric layer 62 form the dielectric layer 60.

[0187] Here, the process of forming the second sub-dielectric layer 62 includes a plasma enhanced chemical vapor deposition (PECVD) process or an atomic layer deposition (ALD) process.

[0188] The material of the second sub-dielectric layer 62 includes silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0189] The thickness of the second sub-dielectric layer 62 is 280 nm to 320 nm, such as 280 nm, 300 nm, or 320 nm.

[0190] When PECVD is used to deposit silicon dioxide, the sources used are SiH4 and N2O, respectively, the pressure is maintained at 100 Pa during growth, and the power is 150 W. The flow rate of SiH4 is 20 sccm, the flow rate of N2O is 1400 sccm, the flow rate of N2 is 1500 sccm, the growth temperature is 250°C, and the growth rate is 300 nm / h.

[0191] In some embodiments, the process of removing the second sub dielectric layer 62 on the side of the first doped layer 31 and the second doped layer 32 away from the substrate 10 comprises dry etching. Inductively coupled plasma can be used in particular. The radio frequency power on the inductive coupling coil is set to 300 W, the bias power is set to 200 W, and the pressure in the process chamber is set to 1 Pa during etching. The etching gas used is carbon tetrafluoride (CF4) and argon (Ar). The etching rate is 80 nm / min to 120 nm / min, for example 80 nm / min, 100 nm / min or 120 nm / min.

[0192] The flow rate of carbon tetrafluoride (CF4) is 8 sccm to 12 sccm, for example 8 sccm, 10 sccm or 12 sccm; the flow rate of argon (Ar) is 1 sccm to 3 sccm, for example 1 sccm, 2 sccm or 3 sccm.

[0193] Step S3: Referring to Figure 19 The first electrode 51 is formed on the side of the first doped layer 31 away from the first current blocking layer 41, and the second electrode 52 is formed on the side of the second doped layer 32 away from the second current blocking layer 42.

[0194] Here, the process of forming the first electrode 51 and the second electrode 52 comprises an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr and the evaporation rate is 0.5 angstrom / s.

[0195] The conductive electrode 80, the first electrode 51 and the second electrode 52 are formed in the same step, and the conductive electrode 80, the first electrode 51 and the second electrode 52 are electrically connected.

[0196] Step S4: Referring to Figure 22 The gate 70 is formed on the dielectric layer 60.

[0197] Here, the gate 70 is formed on the dielectric layer 60 by a lift-off process.

[0198] The process of forming the gate 70 comprises an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr.

[0199] The material of the gate 70 comprises a metal, for example nickel or gold. In the preparation process, the evaporation rate of nickel is 0.5 angstrom / s, and the evaporation rate of gold is 1 angstrom / s.

[0200] When the material of the gate 70 is nickel, the thickness of the gate 70 is 15 nm to 25 nm, for example 15 nm, 20 nm or 20 nm. When the material of the gate 70 is gold, the thickness of the gate 70 is 80 nm to 120 nm, for example 80 nm, 100 nm or 120 nm.

[0201] Step S5: referring to Figure 23 A third electrode 53 is formed on the side of the substrate 10 away from the gate 70.

[0202] Here, the process of forming the third electrode 53 includes an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr.

[0203] The material of the third electrode 53 includes titanium or gold. In the process of preparation, the evaporation rate of titanium is 0.5 angstrom per second, and the evaporation rate of gold is 1 angstrom per second.

[0204] The thickness of the third electrode 53 is 20 nm to 100 nm, for example, 20 nm, 50 nm, 80 nm, or 100 nm. For example, when the material of the third electrode 53 is titanium, the thickness of the third electrode 53 is 20 nm. When the material of the third electrode 53 is gold, the thickness of the third electrode 53 is 100 nm.

[0205] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who thinks of changes or replacements within the technical scope disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: forming a substrate; forming a first stack structure and a second stack structure on one side of the substrate along a first direction, the first direction being a thickness direction of the substrate; the first stack structure and the second stack structure are spaced apart along a second direction, and a first groove is formed between the first stack structure and the second stack structure, the second direction being perpendicular to the first direction; the first stack structure comprises a first current blocking layer and a first doped layer arranged on a side of the first current blocking layer away from the substrate; the second stack structure comprises a second current blocking layer and a second doped layer arranged on a side of the second current blocking layer away from the substrate; the first groove exposes part of the surface of the second current blocking layer; the first doped layer, the second doped layer and the substrate have the same doping type; forming a first sub-medium layer on the bottom surface and the sidewall of the first groove, the first sub-medium layer forming a second groove; forming a conductive electrode on the bottom of the second groove, a first electrode on a side of the first doped layer away from the first current blocking layer, and a second electrode on a side of the second doped layer away from the second current blocking layer, the conductive electrode, the first electrode and the second electrode being formed in the same step; forming a second sub-medium layer on a side of the conductive electrode away from the substrate, a sidewall of the second groove, a sidewall of the first electrode close to the second groove, and a sidewall of the second electrode close to the second groove; the first sub-medium layer and the second sub-medium layer form a medium layer; forming a gate electrode on the medium layer; the first current blocking layer, the first doped layer and the first electrode are located on a first side of the gate electrode, the second doped layer and the second electrode are located on a second side of the gate electrode, the first side and the second side of the gate electrode being opposite sides of the gate electrode in the second direction; the second current blocking layer is located on a side of the conductive electrode and the second doped layer close to the substrate; the medium layer is located between each of the first current blocking layer, the first doped layer, the first electrode, the second doped layer, the second electrode and the conductive electrode and the gate electrode; the medium layer also covers the surface of the conductive electrode close to the substrate and the two opposite sides of the conductive electrode in the second direction; forming a third electrode on a side of the substrate away from the gate electrode.

2. The method of producing a semiconductor device according to claim 1, wherein The method comprises the following steps: forming a first stack structure and a second stack structure on one side of the substrate along a first direction, comprising: forming an initial drift layer, an initial first current blocking layer and an initial first doped layer on one side of the substrate in sequence; 3. The method of producing a semiconductor device according to claim 2, wherein removing part of the initial drift layer, the initial first current blocking layer and the initial first doped layer located in a first target area to form a first opening, the bottom surface of the first opening being lower than the bottom surface of the initial first current blocking layer; the initial drift layer forms a drift layer. The method comprises the following steps: forming an initial drift layer, an initial first current blocking layer and an initial first doped layer on one side of the substrate in sequence, comprising: The material of the substrate, the initial drift layer, the initial first current blocking layer and the initial first doped layer comprises gallium oxide.

4. The method of producing a semiconductor device according to claim 2, wherein The removing of the part of the initial drift layer, the initial first current blocking layer and the initial first doped layer in the first target region to form the first opening comprises: A mask is arranged on the surface of the initial first doped layer away from the substrate, and the mask exposes the initial first doped layer in the first target region; The part of the initial drift layer, the initial first current blocking layer and the initial first doped layer in the exposed region are removed by using a dry etching process.

5. The method of producing a semiconductor device according to claim 2, wherein The first and second stack structures are formed on one side of the substrate along a first direction, and the method further comprises: The initial second current blocking layer and the initial second doped layer are formed in the first opening. The initial first doped layer, the initial first current blocking layer and the initial second doped layer in the second target region are removed to form a first groove, the initial first current blocking layer forms the first current blocking layer, the initial first doped layer forms the first doped layer, the initial second current blocking layer forms the second current blocking layer, and the initial second doped layer forms the second doped layer.

6. The method of producing a semiconductor device according to claim 5, wherein The initial second current blocking layer and the initial second doped layer are formed in the first opening, and the method further comprises: The initial second current blocking layer and the initial second doped layer are formed on the surface of the sample with the first opening. The initial second current blocking layer and the initial second doped layer on the surface of the initial first doped layer away from the substrate are removed by using a dry etching process.

7. The method of producing a semiconductor device according to claim 5, wherein The initial first doped layer, the initial first current blocking layer and the initial second doped layer in the second target region are removed to form a first groove, and the method further comprises: A mask is arranged on the surface of the initial first doped layer and the initial second doped layer away from the substrate, and the mask exposes the initial first doped layer and the initial second doped layer in the second target region; The initial first doped layer, the initial first current blocking layer and the initial second doped layer in the exposed region are removed by using a dry etching process.

8. The method of manufacturing a semiconductor device according to any one of claims 5 to 7, wherein The method further comprises: The initial third doped layer is formed; In the process of removing the part of the initial drift layer, the initial first current blocking layer and the initial first doped layer in the first target region to form the first opening, the initial third doped layer in the first target region is also removed; In the process of removing the initial first doped layer, the initial first current blocking layer and the initial second doped layer in the second target region to form the first groove, the initial third doped layer in the second target region is also removed to form the third doped layer.

9. The method of producing a semiconductor device according to any one of claims 1 to 7, wherein The first sub-medium layer is formed on the bottom surface and the sidewall of the first groove, and the first sub-medium layer forms a second groove, and the method further comprises: The first sub-medium layer is formed on the surface of the sample with the first groove, and the first sub-medium layer on the side away from the substrate of the first doped layer and the second doped layer is removed.

10. The method of producing a semiconductor device according to any one of claims 1 to 7, wherein A second sub dielectric layer is formed on the side of the conductive electrode away from the substrate, and the side wall of the second recess, the side wall of the first electrode close to the side of the second recess, and the side wall of the second electrode close to the side of the second recess, comprising: A second sub dielectric layer is formed on the sample surface with the second recess, and the second sub dielectric layer on the side of the first doped layer and the second doped layer away from the substrate is removed.

11. A semiconductor device, characterized by comprising: The semiconductor device is prepared according to the preparation method of the semiconductor device in any one of claims 1-10.

12. A power module, characterized by Comprising: The semiconductor device of claim 11.

13. An electronic device, comprising: Comprising: The power module of claim 12.

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