Double-groove type silicon carbide field effect transistor device and preparation method thereof

Abstract

The invention provides a double-groove type silicon carbide field effect transistor device and a preparation method thereof, the double-groove type silicon carbide field effect transistor device comprises an N-type drain electrode and drain electrode metal located on the lower surface of the N-type drain electrode, an N-type epitaxial layer is arranged on the upper surface of the N-type drain electrode to serve as a drift region of a JFET, an N-type source region is arranged on the upper surface of the N-type epitaxial layer, and a Silicide layer and source electrode metal are sequentially arranged on the upper surface of the N-type source region. A source region groove and a longitudinal groove are formed in the surface of one end, far away from the N-type drain electrode, of the N-type epitaxial layer, an oxide layer is arranged in the source region groove, the side wall of the source region groove is surrounded by an N-type source region, a second oxide layer is arranged in the longitudinal groove, the periphery of the longitudinal groove is wrapped by a P-type doped region, and a Silicide layer is further arranged between the P-type doped region and the second oxide layer. According to the invention, a gate trench and a Silicide layer structure are formed by adopting a self-alignment process, so that the production cost is reduced, and meanwhile, the gate resistance is reduced, so that the switching instantaneous current of the device is more uniform.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a double-groove type silicon carbide field effect transistor device and a manufacturing method thereof. Background Art

[0002] As one of the representatives of the third-generation wide bandgap semiconductor materials, silicon carbide (SiC) material has the advantages of wide bandgap, high critical breakdown electric field, high thermal conductivity, high saturation drift velocity, etc. compared with the existing silicon materials. The MOSFET device prepared with SiC material has the advantages of low on-resistance, small size, fast switching speed, etc. compared with the silicon-based MOSFET with the same breakdown voltage level, making it have broad application prospects in the fields of high-power, high-temperature and high-frequency power electronics. Compared with the traditional SiC MOSFET, the SiC JFET adopts a fully junction structure, eliminating the threshold drift problem caused by the gate oxide interface traps. The on-resistance is reduced by more than 30% compared with the MOSFET of the same specification, and the output capacitance Coss is reduced by more than 50%, with ultra-low loss. Currently, most SiC JFETs are normally-on types, requiring negative voltage to turn off, greatly increasing the complexity of the drive circuit, being sensitive to the gate voltage fluctuation, and vulnerable to noise interference; when switching at high speed, due to the existence of parasitic capacitance, the current will be uneven, which may cause mis-turn-on; the gate leakage current increases at high temperature, affecting the turn-off reliability. Summary of the Invention

[0003] The object of the present invention is to overcome the deficiencies existing in the prior art and provide a double-groove type silicon carbide field effect transistor device and a manufacturing method thereof. The present invention eliminates the lithography alignment error through a self-alignment process, improving the device consistency. At the same time, the Silicide layer formed by the self-alignment process reduces the parasitic capacitance and greatly reduces the gate distributed resistance RG, making the cell switching consistency in different regions of the device better during the switching instant and the current inside the device more uniform. In addition, the JFET of this invention can be used in the cascode structure and co-packaged with a low-voltage MOSFET device, greatly reducing the system cost while optimizing the dynamic performance of the overall structure, greatly improving the switching speed, reducing the overshoot voltage of the drain of the low-voltage MOS during the switching instant of the Cascode co-packaged device, and reducing the risk of high-frequency oscillation.

[0004] To achieve the above technical objectives, the technical solution adopted in the embodiment of the present invention is:

[0005] In a first aspect, an embodiment of the present invention provides a double-groove type silicon carbide field effect transistor device, which includes an N-type drain and a drain metal on its lower surface. An N-type epitaxial layer is provided on the upper surface of the N-type drain as the drift region of the JFET. An N-type source region is provided on the upper surface of the N-type epitaxial layer. A Silicide layer and a source metal are sequentially provided on the upper surface of the N-type source region. A source region trench and a longitudinal trench are provided on the surface of one end of the N-type epitaxial layer away from the N-type drain. An oxide layer is provided inside the source region trench, and the sidewall of the source region trench is surrounded by the N-type source region. A second oxide layer is provided inside the longitudinal trench, and the periphery of the longitudinal trench is wrapped by a P-type doped region, and a Silicide layer is further provided between the P-type doped region and the second oxide layer.

[0006] Further, the source region trench is etched after uniformly implanting N-type impurities in the cell region to form the N-type source region, and the depth of the source region trench is not less than the depth of the N-type source region.

[0007] Further, the longitudinal trench is formed by a self-alignment process after etching the source region trench and depositing a first oxide layer, and the Silicide layer is formed by a self-alignment process.

[0008] Further, the doping element of the P-type doped region is a trivalent element including aluminum element and boron element, which is formed by one-time or multiple implantations on the sidewall, and the doping concentration is 1×10 10 ~1×10 16 cm -3 , and the implantation angle is 1 to 30°.

[0009] Further, the N-type epitaxial layer is single-layer or multi-layer. When the N-type epitaxial layer is multi-layer, the concentration of the second epitaxy is different from that of the first epitaxy.

[0010] Further, the sidewall of the longitudinal trench is implanted with N-type impurities one or more times at a certain angle to form an N-type modulation region for modulating the on-resistance of the JFET region.

[0011] Further, the source metal serves as the source of the device, and the gate metal serves as the gate of the device, and is arranged outside the cell region of the device.

[0012] In a second aspect, the present embodiment provides a preparation method of the double-groove type silicon carbide field effect transistor device described in the first aspect. The formation of the source region trench and the longitudinal trench is realized by a self-alignment process method, and includes the following steps:

[0013] Step 1: Select an N-type substrate material as the N-type drain of the device, and epitaxially grow an N-type epitaxial layer on the upper surface of the N-type drain;

[0014] Step 2: Using a mask for the N-type source region, implant donor ions on the surface of the N-type epitaxial layer to form an N-type source region;

[0015] Step 3: Using a mask for the source region trench, etch downward to form a source region trench in the N-type source region, and remove the mask;

[0016] Step 4: Deposit a first oxide layer above the N-type epitaxial layer, and the first oxide layer covers the upper surface of the N-type source region, the bottom and side walls of the source region trench;

[0017] Step 5: Etch the first oxide layer downward, and retain the first oxide layer on the side walls of the source region trench;

[0018] Step 6: Using a mask for the vertical trench, etch the N-type epitaxial layer downward by using the first oxide layer in Step 5 with a self-alignment process to form a vertical trench;

[0019] Step 7: Implant acceptor ions on the side walls and bottom of the vertical trench to form a P-type doped region, and remove the mask;

[0020] Step 8: Deposit a metal nickel layer on the upper surface of the N-type epitaxial layer, and the metal nickel layer covers the upper surfaces of the P-type doped region, the first oxide layer, and the N-type source region;

[0021] Step 9: Perform high-temperature annealing on the device, remove the metal nickel layer, and form a Silicide layer on the upper surface of the N-type source region and the surface of the P-type doped region;

[0022] Step 10: Deposit a second oxide layer on the upper surface of the N-type epitaxial layer, and the second oxide layer fills the interiors of the source region trench and the vertical trench, and forms a flat surface on the upper surface of the N-type epitaxial layer;

[0023] Step 11: Etch the excess second oxide layer on the upper surface of the N-type epitaxial layer and deposit metal, deposit metal on the lower surface of the N-type drain, and anneal to form source electrode metal and drain electrode metal respectively.

[0024] In a third aspect, the present embodiment provides a method for manufacturing the double-trench type silicon carbide field effect transistor device described in the first aspect, where the P-type doped region is formed before etching the vertical trench, and the method includes the following steps:

[0025] Step S1: Select an N-type substrate material as the N-type drain of the device, and epitaxially grow an N-type epitaxial layer on the upper surface of the N-type drain;

[0026] Step S2: Using a mask for the N-type source region, implant donor ions on the surface of the N-type epitaxial layer to form an N-type source region;

[0027] Step S3: Using the mask of the source region trench, etch downwards to form a source region trench in the N-type source region;

[0028] Step S4: Using the mask of the source region trench, implant acceptor ions with high energy on the N-type epitaxial layer to form a P-type doped region, and remove the mask;

[0029] Step S5: Deposit a first oxide layer above the N-type epitaxial layer, and the first oxide layer covers the upper surface of the N-type source region, the bottom and side walls of the source region trench;

[0030] Step S6: Etch the first oxide layer downwards, and retain the first oxide layer on the side walls of the source region trench;

[0031] Step S7: Using the mask of the longitudinal trench, etch the P-type doped region downwards, and form a longitudinal trench by using the self-alignment process with the first oxide layer;

[0032] Step S8: Deposit a metal nickel layer on the upper surface of the N-type epitaxial layer, and the metal nickel layer covers the upper surfaces of the P-type doped region, the first oxide layer and the N-type source region;

[0033] Step S9: Anneal the device at high temperature, remove the metal nickel layer, and form a Silicide layer on the upper surface of the N-type source region and the surface of the P-type doped region;

[0034] Step S10: Deposit a second oxide layer on the upper surface of the N-type epitaxial layer, and the second oxide layer fills the interiors of the source region trench and the longitudinal trench, and forms a flat surface on the upper surface of the N-type epitaxial layer; Step S11: Etch the excess second oxide layer on the upper surface of the N-type epitaxial layer, deposit metal, deposit metal on the lower surface of the N-type drain, and anneal to form a source metal and a drain metal respectively.

[0035] Fourthly, the embodiment of the present invention provides a preparation method of the device terminal of the double-trench type silicon carbide field effect transistor described in the first aspect, and the gate metal is arranged as the gate of the device on the periphery of the terminal, including the following steps:

[0036] Step St1: Select an N-type substrate material as the N-type drain of the device, and epitaxially grow an N-type epitaxial layer on the upper surface of the N-type drain;

[0037] Step St2: Using the mask of the source region trench, etch downwards to form a source region trench in the N-type source region of the cell and form a source region trench in the peripheral region of the terminal;

[0038] Step St3: Deposit a first oxide layer above the N-type epitaxial layer, and the first oxide layer covers the N-type source region and the source region trench, and then etch the first oxide layer downwards to retain the first oxide layer for the self-alignment process in the source region trench;

[0039] Step St4: Using a mask for the vertical trench, etch the N-type epitaxial layer downward to form a vertical trench and form a gate trench in the peripheral region of the terminal.

[0040] Step St5: Inject acceptor ions into the sidewalls and bottoms of the vertical trench and the gate trench to form a P-type doped region, and remove the mask.

[0041] Step St6: Deposit a nickel metal layer on the upper surface of the N-type epitaxial layer, and the nickel metal layer covers the upper surfaces of the P-type doped region, the first oxide layer, and the N-type source region.

[0042] Step St7: Perform high-temperature annealing on the device, remove the nickel metal layer, and form a Silicide layer on the surfaces of the vertical trench and the gate trench.

[0043] Step St8: Deposit a second oxide layer on the upper surface of the N-type epitaxial layer. The second oxide layer fills the interiors of the source region trench and the vertical trench, and forms a flat surface on the upper surface of the N-type epitaxial layer.

[0044] Step St9: Using a gate metal mask, etch the excess second oxide layer on the upper surface of the N-type epitaxial layer, then deposit metal, and deposit metal on the lower surface of the N-type drain, and anneal to form gate metal and drain metal respectively.

[0045] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0046] (1) Eliminate the lithography alignment error through the self-alignment process, improve the device consistency, reduce the cost. At the same time, the Silicide layer formed by the self-alignment process reduces the parasitic capacitance, greatly reduces the RG of the device, and makes the current more uniform when the device is conducting.

[0047] (2) The JFET of the present invention can be used in a cascode structure, co-packaged with a low-voltage MOSFET device, greatly reducing the cost of the system while optimizing the dynamic performance of the overall structure, greatly improving the switching speed, and reducing the risk of high-frequency oscillation. Description of the Drawings

[0048] Figure 1 It is a schematic cross-sectional structure diagram of the double-trench type silicon carbide field effect transistor device in Embodiment 1.

[0049] Figure 2 It is a schematic cross-sectional structure diagram after forming the N-type epitaxial layer in Embodiment 2 of the present invention.

[0050] Figure 3 It is a schematic cross-sectional structure diagram after forming the N-type source region in Embodiment 2 of the present invention.

[0051] Figure 4 It is a schematic cross-sectional structure diagram after forming the source region trench in Embodiment 2 of the present invention.

[0052] Figure 5 It is a schematic cross-sectional structure diagram after forming the first oxide layer in Embodiment 2 of the present invention.

[0053] Figure 6 It is a schematic cross-sectional structure diagram after forming the self-aligned oxide layer in Embodiment 2 of the present invention.

[0054] Figure 7 It is a schematic cross-sectional structure diagram after forming the vertical trench in Embodiment 2 of the present invention.

[0055] Figure 8 It is a schematic cross-sectional structure diagram after forming the P-type doped region in Embodiment 2 of the present invention.

[0056] Figure 9 It is a schematic cross-sectional structure diagram after depositing the metal nickel layer in Embodiment 2 of the present invention.

[0057] Figure 10 It is a schematic cross-sectional structure diagram after forming the Silicide layer in Embodiment 2 of the present invention.

[0058] Figure 11 It is a schematic cross-sectional structure diagram after depositing the second oxide layer in Embodiment 2 of the present invention.

[0059] Figure 12 It is a schematic cross-sectional structure diagram after forming the N-type modulation region in Embodiment 3 of the present invention.

[0060] Figure 13 It is a schematic cross-sectional structure diagram after depositing the metal nickel layer in Embodiment 3 of the present invention.

[0061] Figure 14 It is a schematic cross-sectional structure diagram after forming the Silicide layer in Embodiment 3 of the present invention.

[0062] Figure 15 It is a schematic cross-sectional structure diagram after depositing the second oxide layer in Embodiment 3 of the present invention.

[0063] Figure 16 It is a schematic cross-sectional structure diagram of forming the metal electrode in Embodiment 3 of the present invention.

[0064] Figure 17 It is a schematic cross-sectional structure diagram after forming the P-type doped region in Embodiment 4 of the present invention.

[0065] Figure 18 It is a schematic cross-sectional structure diagram after forming the first oxide layer in Embodiment 4 of the present invention.

[0066] Figure 19Schematic cross-sectional structure diagram after forming the self-aligned oxide layer in Embodiment 4 of the present invention.

[0067] Figure 20 Schematic cross-sectional structure diagram after forming the source region trench in Embodiment 5 of the present invention.

[0068] Figure 21 Schematic cross-sectional structure diagram after forming the self-aligned oxide layer in Embodiment 5 of the present invention.

[0069] Figure 22 Schematic cross-sectional structure diagram after forming the vertical trench and the gate trench in Embodiment 5 of the present invention.

[0070] Figure 23 Schematic cross-sectional structure diagram after forming the P-type doped region in Embodiment 5 of the present invention.

[0071] Figure 24 Schematic cross-sectional structure diagram after depositing the metal nickel layer in Embodiment 5 of the present invention.

[0072] Figure 25 Schematic cross-sectional structure diagram after forming the Silicide layer in Embodiment 5 of the present invention.

[0073] Figure 26 Schematic cross-sectional structure diagram after forming the second oxide layer in Embodiment 5 of the present invention.

[0074] Figure 27 Schematic cross-sectional structure diagram of forming the metal electrode in Embodiment 5 of the present invention.

[0075] Explanation of reference numerals: 1 - source metal; 2 - first oxide layer; 3 - N-type source region; 4 - P-type doped region; 5 - N-type epitaxial layer; 6 - N-type drain; 7 - drain metal; 8 - source region trench; 9 - vertical trench; 10 - metal nickel layer; 11 - Silicide layer; 12 - second oxide layer; 13 - gate trench; 14 - gate metal; 15 - N-type modulation region. Detailed implementation manners

[0076] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0077] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0078] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0079] Embodiment 1

[0080] As shown in Figure 1 Figure, a double-groove type silicon carbide field effect transistor device includes an N-type drain 6 and a drain metal 7 located on its lower surface. An N-type epitaxial layer 5 is provided on the upper surface of the N-type drain 6 as the drift region of the JFET. An N-type source region 3 is provided on the upper surface of the N-type epitaxial layer 5. A Silicide layer 11 and a source metal 1 are sequentially provided on the upper surface of the N-type source region 3. A source region trench 8 and a longitudinal trench 9 are provided on the surface of the N-type epitaxial layer 5 away from the N-type drain 6. A second oxide layer 12 is provided inside the source region trench 8. The side wall of the source region trench 8 is surrounded by the N-type source region 3. A second oxide layer 12 is provided inside the longitudinal trench 9. The periphery of the longitudinal trench 9 is wrapped by a P-type doped region 4. And a Silicide layer 11 is also provided between the P-type doped region 4 and the second oxide layer 12.

[0081] The longitudinal trench 9 is located below the source region trench 8. The source region trench 8 and the longitudinal trench 9 are connected and arranged, and the center lines of the source region trench 8 and the longitudinal trench 9 coincide. The width of the source region trench 8 is greater than the width of the longitudinal trench 9.

[0082] As an implementation manner, the source region trench 8 is etched after the N-type impurity is implanted in the cell region to form the N-type source region 3. There is no general implantation in the terminal region. The depth of the source region trench 8 is the same as or slightly greater than the depth of the N-type source region 3. The depth of the source region trench 8 is 0.5 - 2.5 μm.

[0083] As an implementation manner, the longitudinal trench 9 is formed by a self-alignment process after etching the source region trench 8 and depositing the first oxide layer 2. At the same time, the Silicide layer 11 is also formed by a self-alignment process.

[0084] The doping element of the P-type doped region 4 is a trivalent element including aluminum element and boron element, which is formed by one-time or multiple implantations on the side wall. The doping concentration is 1×10 10 ~1×10 16 cm-3 , the injection angle is 1 to 30°.

[0085] As an embodiment, the doping element of the P-type doping region 4 is aluminum, which is formed by multiple sidewall injections, and the impurity injection concentration is 1×10 13 ~8×10 14 cm -3 , and the injection angle is 15°.

[0086] The source metal 1 serves as the source of the device, and the gate metal 14 serves as the gate of the device, which are arranged on the periphery of the device cell region.

[0087] The N-type epitaxial layer 5 is single-layer or multi-layer. When the N-type epitaxial layer 5 is multi-layer, the concentration of the second epitaxy is different from that of the first epitaxy.

[0088] As an embodiment, the sidewalls of the vertical trench 9 are injected with N-type impurities once or multiple times at a certain angle to modulate the on-resistance of the JFET region.

[0089] Embodiment 2

[0090] A preparation method of a double-groove type silicon carbide field effect transistor device includes the following steps:

[0091] Step 1: Select an N-type substrate material as the N-type drain 6 of the device, epitaxially grow an N-type epitaxial layer 5 on the upper surface of the N-type drain 6 once, and then clean the epitaxial wafer to obtain a device structure as shown in Figure 2 :

[0092] The N-type substrate material is 4H-SiC, 6H-SiC or 3C-SiC, preferably 4H-SiC;

[0093] Step 2: The cell region adopts a general injection form. Using the mask plate of the N-type source region 3, donor ions are injected on the surface of the N-type epitaxial layer 5 to form the N-type source region 3, and a device structure as shown in Figure 3 is obtained. The concentration range of the injected donor ions is 1e 14 cm -3 ~2e 15 cm -3 ;

[0094] Step 3: Using the mask plate of the source region trench 8, the region in the N-type source region 3 that needs to form the source region trench 8 is exposed through lithography, and then SiC is etched downward to form the source region trench 8 in the N-type source region 3, and the mask plate is removed to obtain a device structure as shown in Figure 4 ;

[0095] Step 4: Deposit a first oxide layer 2 above the N-type epitaxial layer 5. The first oxide layer 2 covers the upper surface of the N-type source region 3, the bottom and sidewalls of the source region trench 8, and a device structure as shown inFigure 5 The device structure shown;

[0096] Step Five: Wet-etch the first oxide layer 2 downward, and retain the first oxide layer 2 in the source region trench 8 for self-alignment process, obtaining the device structure as shown in Figure 6 The device structure shown;

[0097] Step Six: Using the mask of the vertical trench 9, etch the N-type epitaxial layer 5 downward through the self-alignment effect of the first oxide layer 2 to form the vertical trench 9, obtaining the device structure as shown in Figure 7 The device structure shown;

[0098] Step Seven: Implant acceptor ions into the sidewalls and bottom of the vertical trench 9 and anneal to form a P-type doped region 4. Implant multiple times with different energies, and the implanted impurity concentration is 1×10 13 ~8×10 14 cm -3 , and the implantation angle is 1 - 30°, obtaining the device structure as shown in Figure 8 The device structure shown;

[0099] Step Eight: Deposit a metal nickel layer 10 on the upper surface of the N-type epitaxial layer 5 by sputtering. The metal nickel layer 10 covers the surfaces of the P-type doped region 4, the first oxide layer 2, and the N-type source region 3, obtaining the device structure as shown in Figure 9 The device structure shown;

[0100] Step Nine: Perform rapid thermal annealing on the device to remove the metal nickel layer 10, and form a Silicide layer 11 on the surfaces of the N-type source region 3 and the P-type doped region 4 (the region where the metal nickel layer 10 contacts SiC), obtaining the device structure as shown in Figure 10 The device structure shown;

[0101] Step Ten: Deposit a second oxide layer 12 on the upper surface of the N-type epitaxial layer 5. The second oxide layer 12 fills the interiors of the source region trench 8 and the vertical trench 9, and forms a flat surface on the upper surface of the N-type epitaxial layer 5, obtaining the device structure as shown in Figure 11 The device structure shown;

[0102] Among them, the second oxide layer 12 has the same material as the first oxide layer 2;

[0103] Step Eleven: Etch the excess second oxide layer 12 on the upper surface of the N-type epitaxial layer 5 and deposit metal. Deposit metal on the lower surface of the N-type drain 6, anneal, form a source metal 1 on the upper surface of the N-type epitaxial layer 5, and form a drain metal 7 on the lower surface of the N-type drain 6, obtaining the device structure as shown in Figure 1 The device structure shown.

[0104] Among them, the lower surface of the source metal 1 is connected to the upper surface of the Silicide layer 11 and the second oxide layer 12 in the source region trench 8.

[0105] The process method provided by the present invention etches longitudinal grooves through a self-alignment process, improving the process precision. At the same time, the self-alignment region is used for the process of the P-type doped region, reducing the use of photomasks and lowering the production cost of the device.

[0106] Example 3

[0107] A preparation method of a double-groove type silicon carbide field effect transistor device includes the following steps:

[0108] Step 1: Select an N-type substrate material as the N-type drain 6 of the device. Epitaxially grow an N-type epitaxial layer 5 on the upper surface of the N-type drain 6 once, and then clean the epitaxial wafer to obtain the device structure as Figure 2 shown:

[0109] Among them, the N-type substrate material is 4H-SiC, 6H-SiC or 3C-SiC, preferably 4H-SiC;

[0110] Step 2: In the cell region, in a universal implantation form, using the mask of the N-type source region 3, implant donor ions on the surface of the N-type epitaxial layer 5 to form the N-type source region 3, and obtain the device structure as Figure 3 shown. The concentration range of the implanted donor ions is 1e 14 cm -3 ~2e 15 cm -3 ;

[0111] Step 3: Using the mask of the source region trench 8, expose the region in the N-type source region 3 that needs to form the source region trench 8 through photolithography, and then etch SiC downward to form the source region trench 8 in the N-type source region 3, and remove the mask to obtain the device structure as Figure 4 shown;

[0112] Step 4: Deposit a first oxide layer 2 above the N-type epitaxial layer 5. The first oxide layer 2 covers the upper surface of the N-type source region 3 and the bottom and side walls of the source region trench 8 to obtain the device structure as Figure 5 shown;

[0113] Step 5: Etch the first oxide layer 2 downward by wet etching, and retain the first oxide layer 2 for the self-alignment process in the source region trench 8 to obtain the device structure as Figure 6 shown;

[0114] Step 6: Using the mask of the longitudinal trench 9, etch the N-type epitaxial layer 5 downward through the self-alignment effect of the retained first oxide layer 2 to form the longitudinal trench 9, and obtain the device structure as Figure 7 shown;

[0115] Step Seven: Inject acceptor ions into the sidewalls and bottom of the vertical trench 9 and anneal to form a P-type doped region 4. Inject multiple times with different energies, and the implanted impurity concentration is 1×10 13 ~8×10 14 cm -3 . The injection angle is 1 to 30°, and the device structure as shown in Figure 8 is obtained;

[0116] Step Eight: Inject acceptor ions into the sidewalls and bottom of the vertical trench 9 and anneal to form an N-type modulation region 15. Inject multiple times with different energies and different angles, and the device structure as shown in Figure 12 is obtained;

[0117] Step Nine: Deposit a metal nickel layer 10 on the upper surface of the N-type epitaxial layer 5 by sputtering. The metal nickel layer 10 covers the surfaces of the P-type doped region 4, the first oxide layer 2, and the N-type source region 3, and the device structure as shown in Figure 13 is obtained;

[0118] Step Ten: Perform rapid thermal annealing on the device to remove the metal nickel layer 10 and form a Silicide layer 11 on the surfaces of the N-type source region 3 and the vertical trench 9 (the region where the metal nickel layer 10 contacts SiC), and the device structure as shown in Figure 14 is obtained;

[0119] Step Eleven: Deposit a second oxide layer 12 on the upper surface of the N-type epitaxial layer 5. The second oxide layer 12 fills the interiors of the source region trench 8 and the vertical trench 9 and forms a flat surface on the upper surface of the N-type epitaxial layer 5, and the device structure as shown in Figure 15 is obtained;

[0120] Step Twelve: Etch the excess second oxide layer 12 on the upper surface of the N-type epitaxial layer 5 and deposit metal. Deposit metal on the lower surface of the N-type drain 6, anneal, form a source metal 1 on the upper surface of the N-type epitaxial layer 5, and form a drain metal 7 on the lower surface of the N-type drain 6, and the device structure as shown in Figure 16 is obtained.

[0121] In this embodiment, an N-type modulation region 15 is formed by angled sidewall injection to modulate the resistance of the JFET region, and the on-resistance of the overall device can be reduced.

[0122] Embodiment 4

[0123] A preparation method of a double-trench type silicon carbide field effect transistor device, in which the P-type doped region is formed before etching the vertical trench, and includes the following steps:

[0124] Step S1: Select an N-type substrate material as the N-type drain 6 of the device, epitaxially grow an N-type epitaxial layer 5 on the upper surface of the N-type drain 6 once, and then clean the epitaxial wafer to obtain the structure as shown in Figure 2The device structure shown:

[0125] Among them, the N-type substrate material is 4H-SiC, 6H-SiC or 3C-SiC, preferably 4H-SiC;

[0126] Step S2: The cell region adopts a general implantation form. Using the mask of the N-type source region 3, donor ions are implanted on the surface of the N-type epitaxial layer 5 to form the N-type source region 3, obtaining the device structure as shown in Figure 3 The concentration range of the implanted donor ions is 1e 14 cm -3 ~2e 15 cm -3 ;

[0127] Step S3: Using the mask of the source region trench 8, the region in the N-type source region 3 that needs to form the source region trench 8 is exposed by photolithography, and then SiC is etched downward to form the source region trench 8 in the N-type source region 3, obtaining the device structure as shown in Figure 4 The device structure shown;

[0128] Step S4: Using the mask of the source region trench 8, acceptor ions are implanted at high energy on the N-type epitaxial layer 5 to form the P-type doped region 4, and the mask is removed, obtaining the device structure as shown in Figure 17 The device structure shown;

[0129] Step S5: Deposit the first oxide layer 2 above the N-type epitaxial layer 5. The first oxide layer 2 covers the upper surface of the N-type source region 3, the bottom and side walls of the source region trench 8, obtaining the device structure as shown in Figure 18 The device structure shown;

[0130] Step S6: Etch the first oxide layer 2 downward wetly, and retain the first oxide layer 2 in the source region trench 8 for self-alignment process, obtaining the device structure as shown in Figure 19 The device structure shown;

[0131] Step S7: Using the mask of the vertical trench 9, etch the P-type doped region 4 downward by self-alignment process to form the vertical trench 9, and remove the mask, obtaining the device structure as shown in Figure 8 The device structure shown;

[0132] Step S8: Deposit a metal nickel layer 10 on the upper surface of the N-type epitaxial layer 5 by sputtering. The metal nickel layer 10 covers the upper surface of the P-type doped region 4, the first oxide layer 2 and the N-type source region 3, obtaining the device structure as shown in Figure 9 The device structure shown;

[0133] Step S9: Perform rapid thermal annealing on the device, remove the metal nickel layer 10, and form a Silicide layer 11 on the surfaces of the N-type source region 3 and the vertical trench 9 (the region where the metal nickel contacts SiC), obtaining the device structure as shown in Figure 10 The device structure shown;

[0134] Step S10: Deposit a second oxide layer 12 on the upper surface of the N-type epitaxial layer 5. The second oxide layer 12 fills the interiors of the source trenches 8 and the vertical trenches 9 and forms a flat surface on the upper surface of the N-type epitaxial layer 5, obtaining the device structure as shown in Figure 11 the figure;

[0135] Step S11: Etch the excess second oxide layer 12 on the upper surface of the N-type epitaxial layer 5 and deposit metal. Deposit metal on the lower surface of the N-type drain 6 and anneal. Form a source metal 1 on the upper surface of the N-type epitaxial layer 5 and form a drain metal 7 on the lower surface of the N-type drain 6, obtaining the device structure as shown in Figure 1 the figure.

[0136] In this embodiment, the P-type doping region is formed before etching the vertical trenches, and no angled sidewall implantation is required, which has lower requirements for equipment and can reduce the production cost of the device.

[0137] Embodiment 5

[0138] A method for preparing the terminal of a double-trench type silicon carbide field effect transistor device, in which a gate metal 14 is arranged as the gate of the device around the terminal, includes the following steps:

[0139] Step St1: Select an N-type substrate material as the N-type drain 6 of the device. Epitaxially grow an N-type epitaxial layer 5 on the upper surface of the N-type drain 6 once, and then clean the epitaxial wafer, which is consistent with the cell region process:

[0140] wherein the N-type substrate material is 4H-SiC, 6H-SiC or 3C-SiC, preferably 4H-SiC;

[0141] Step St2: Use the mask plate of the source trench 8 to etch SiC downward, form source trenches 8 in the N-type source region 3 of the cell, and form long source trenches 8 in the peripheral region of the terminal, obtaining the device structure as shown in Figure 20 the figure;

[0142] Step St3: Deposit a first oxide layer 2 above the N-type epitaxial layer 5 to cover the N-type source region 3 and the source trenches 8, and then etch the first oxide layer 2 downward to retain the first oxide layer 2 for self-alignment process in the source trenches 8, obtaining the device structure as shown in Figure 21 the figure;

[0143] Step St4: Use the mask plate of the vertical trench 9 to etch the N-type epitaxial layer 5 downward to form vertical trenches 9 and form gate trenches 13 in the peripheral region of the terminal, obtaining the device structure as shown in Figure 22 the figure;

[0144] Step St5: Using the mask of the vertical trench 9, implant acceptor ions into the sidewalls and bottom of the vertical trench 9 and anneal to form the P-type doped region 4. The doping element is aluminum, boron or other trivalent elements, which is formed by implanting at an angle on the sidewalls once or multiple times. The doping concentration is 1×10 10 ~1×10 16 cm -3 , the implantation angle is 1-30°, and the device structure shown in Figure 23 is obtained;

[0145] Step St6: Deposit a metal nickel layer 10 on the upper surface of the N-type epitaxial layer 5 by sputtering. The metal nickel layer 10 covers the upper surfaces of the P-type doped region 4, the first oxide layer 2 and the N-type source region 3, and the device structure shown in Figure 24 is obtained;

[0146] Step St7: Perform rapid thermal annealing on the device to remove the metal nickel layer 10 and form a Silicide layer 11 on the surface of the vertical trench 9 (the area where the metal nickel layer 10 contacts SiC), and the device structure shown in Figure 25 is obtained;

[0147] Step St8: Deposit a second oxide layer 12 on the upper surface of the N-type epitaxial layer 5. The second oxide layer 12 fills the interiors of the source trench 8 and the vertical trench 9 and forms a flat surface on the upper surface of the N-type epitaxial layer 5, and the device structure shown in Figure 26 is obtained;

[0148] Step St9: Using the gate metal mask, etch the excess second oxide layer 12 on the upper surface of the N-type epitaxial layer 5 and then deposit metal, deposit metal on the lower surface of the N-type drain 6, and anneal to form a source metal 1 on the upper surface of the N-type epitaxial layer 5 and a drain metal 7 on the lower surface of the N-type drain 6, and the device structure shown in Figure 27 is obtained.

[0149] In this embodiment, a terminal structure matching the cell structure is provided, and this structure can significantly reduce Rg and improve current uniformity.

[0150] The present invention eliminates lithography alignment errors through a self-alignment process, improves device consistency, and reduces costs. At the same time, the self-alignment process uniformly forms a Silicide layer on the sidewalls and bottom of the trench gate. Since the resistance of the Silicide layer is very low, the gate current of the device mainly flows through the Silicide layer to the gate bus and gate pad, and further flows to the external circuit. The present invention increases the conductive area of the Silicide layer of the JFET device, greatly reduces the gate distributed resistance RG of the JFET device, making the cell switching consistency in different regions better during the switching instant of the device, and the current inside the device more uniform. In addition, the JFET device of the present invention can be used in a cascode structure and co-packaged with a low-voltage MOSFET device, greatly reducing the cost of the system while optimizing the dynamic performance of the overall structure, greatly improving the switching speed, reducing the overshoot voltage of the low-voltage MOS drain at the switching instant of the Cascode co-packaged device, and reducing the risk of high-frequency oscillation.

[0151] The above describes the present invention and its implementation manners. This description is not restrictive. Only two implementation manners of the present invention are shown in the drawings, and the actual structure is not limited thereto. In general, if those of ordinary skill in the art are inspired by it and design similar structural manners and embodiments to this technical solution without creative efforts without departing from the purpose of the present invention, they should fall within the protection scope of the present invention.

Claims

1. A double-groove type silicon carbide field effect transistor device, comprising an N-type drain (6) and a drain metal (7) located on its lower surface. An N-type epitaxial layer (5) is provided on the upper surface of the N-type drain (6) as a drift region of the JFET. An N-type source region (3) is provided on the upper surface of the N-type epitaxial layer (5), characterized in that, On the upper surface of the N-type source region (3), a Silicide layer (11) and a source metal (1) are sequentially provided. On the surface of the N-type epitaxial layer (5) at one end far from the N-type drain (6), a source region trench (8) and a longitudinal trench (9) are provided. An oxide layer is provided inside the source region trench (8), and the side wall of the source region trench (8) is surrounded by the N-type source region (3). A second oxide layer (12) is provided inside the longitudinal trench (9), and the periphery of the longitudinal trench (9) is wrapped by a P-type doped region (4), and a Silicide layer (11) is further provided between the P-type doped region (4) and the second oxide layer (12).

2. The double-groove type silicon carbide field effect transistor device according to claim 1, wherein The source region trench (8) is etched and formed after the N-type impurity is generally implanted in the cell region to form the N-type source region (3), and the depth of the source region trench (8) is not less than the depth of the N-type source region (3).

3. The double-groove type silicon carbide field effect transistor device according to claim 1, characterized in that, The longitudinal trench (9) is formed by a self-alignment process after etching the source region trench (8) and depositing the first oxide layer (2), and the Silicide layer (11) is formed by a self-alignment process.

4. The dual-groove type silicon carbide field effect transistor device according to claim 1, characterized in that The doping elements of the P-type doping region (4) are trivalent elements including aluminum and boron, which are formed by one or more injections into the sidewall, with a doping concentration of 1×10 10 ~1×10 16 cm -3 , the injection angle is 1~30°.

5. The double-groove type silicon carbide field effect transistor device according to claim 1, wherein The N-type epitaxial layer (5) is single-layer or multi-layer. When the N-type epitaxial layer (5) is multi-layer, the concentration of the second epitaxy is different from that of the first epitaxy.

6. The double-groove type silicon carbide field effect transistor device according to claim 1, wherein The side wall of the longitudinal trench (9) is implanted with N-type impurities once or multiple times at a certain angle to form an N-type modulation region (15) for modulating the on-resistance of the JFET region.

7. The double-groove type silicon carbide field effect transistor device according to claim 1, characterized in that The source metal (1) serves as the source of the device, and the gate metal (14) serves as the gate of the device, and is arranged on the periphery of the device cell region.

8. The manufacturing method of the double-groove type silicon carbide field effect transistor device according to any one of claims 1-5, characterized in that, The formation of the source region trench (8) and the longitudinal trench (9) is realized by a self-alignment process method, including the following steps: Step 1: Select an N-type substrate material as the N-type drain (6) of the device, and epitaxially grow an N-type epitaxial layer (5) on the upper surface of the N-type drain (6); Step 2: Using the mask of the N-type source region (3), implant donor ions on the surface of the N-type epitaxial layer (5) to form the N-type source region (3); Step 3: Using the mask of the source region trench (8), etch downward to form the source region trench (8) in the N-type source region (3), and remove the mask; Step 4: Deposit a first oxide layer (2) above the N-type epitaxial layer (5), and the first oxide layer (2) covers the upper surface of the N-type source region (3), the bottom and side walls of the source region trench (8); Step 5: Etch the first oxide layer (2) downward, and retain the first oxide layer (2) on the side wall of the source region trench (8); Step 6: Using the mask of the longitudinal trench (9), use the first oxide layer (2) retained in Step 5 to etch the N-type epitaxial layer (5) downward by a self-alignment process to form the longitudinal trench (9); Step 7: Inject acceptor ions into the side wall and bottom of the longitudinal trench (9) to form a P-type doped region (4), and remove the mask; Step 8: Deposit a metal nickel layer (10) on the upper surface of the N-type epitaxial layer (5), and the metal nickel layer (10) covers the upper surfaces of the P-type doped region (4), the first oxide layer (2) and the N-type source region (3); Step Nine: Anneal the device at high temperature to remove the nickel metal layer (10), and form a Silicide layer (11) on the upper surface of the N-type source region (3) and the surface of the P-type doped region (4); Step Ten: Deposit a second oxide layer (12) on the upper surface of the N-type epitaxial layer (5). The second oxide layer (12) fills the interiors of the source region trench (8) and the longitudinal trench (9), and forms a flat surface on the upper surface of the N-type epitaxial layer (5); Step Eleven: Etch the excess second oxide layer (12) on the upper surface of the N-type epitaxial layer (5) and deposit metal. Deposit metal on the lower surface of the N-type drain (6), and anneal to form the source metal (1) and the drain metal (7) respectively; 9. The preparation method of the double-groove type silicon carbide field effect transistor device according to any one of claims 1-5, characterized in that, The P-type doped region (4) is formed before etching the longitudinal trench (9), and includes the following steps: Step S1: Select an N-type substrate material as the N-type drain (6) of the device, and epitaxially grow an N-type epitaxial layer (5) on the upper surface of the N-type drain (6); Step S2: Using the N-type source region (3) mask plate, implant donor ions on the surface of the N-type epitaxial layer (5) to form the N-type source region (3); Step S3: Using the mask plate of the source region trench (8), etch downward to form a source region trench (8) in the N-type source region (3); Step S4: Using the mask plate of the source region trench (8), implant acceptor ions at high energy on the N-type epitaxial layer (5) to form the P-type doped region (4), and remove the mask plate; Step S5: Deposit a first oxide layer (2) above the N-type epitaxial layer (5). The first oxide layer (2) covers the upper surface of the N-type source region (3), the bottom and sidewalls of the source region trench (8); Step S6: Etch the first oxide layer (2) downward, and retain the first oxide layer (2) on the sidewalls of the source region trench (8); Step S7: Using the longitudinal trench (9) mask plate, etch the P-type doped region (4) downward, and use the first oxide layer (2) retained in Step S6 to form the longitudinal trench (9) by self-alignment process; Step S8: Deposit a nickel metal layer (10) on the upper surface of the N-type epitaxial layer (5). The nickel metal layer (10) covers the upper surfaces of the P-type doped region (4), the first oxide layer (2), and the N-type source region (3); Step S9: Anneal the device at high temperature to remove the nickel metal layer (10), and form a Silicide layer (11) on the upper surface of the N-type source region (3) and the surface of the P-type doped region (4); Step S10: Deposit a second oxide layer (12) on the upper surface of the N-type epitaxial layer (5). The second oxide layer (12) fills the interiors of the source region trench (8) and the longitudinal trench (9), and forms a flat surface on the upper surface of the N-type epitaxial layer (5); Step S11: Etch the excess second oxide layer (12) on the upper surface of the N-type epitaxial layer (5), and deposit metal. Deposit metal on the lower surface of the N-type drain (6), and anneal to form the source metal (1) and the drain metal (7) respectively; 10. The double-groove type silicon carbide field effect transistor device according to claim 7, characterized in that, The gate metal (14) is arranged at the periphery of the terminal as the gate of the device. The method for preparing the terminal of the double-groove type silicon carbide field effect transistor device includes the following steps: Step St1: Select an N-type substrate material as the N-type drain (6) of the device, and epitaxially grow an N-type epitaxial layer (5) on the upper surface of the N-type drain (6); Step St2: Using the mask plate of the source region trench (8), etch downward to form the source region trench (8) in the N-type source region (3) of the cell and the source region trench (8) in the peripheral region of the terminal; Step St3: Deposit a first oxide layer (2) above the N-type epitaxial layer (5). The first oxide layer (2) covers the N-type source region (3) and the source region trench (8), and then etch the first oxide layer (2) downward to retain the first oxide layer (2) for self-alignment process in the source region trench (8); Step St4: Using the mask plate of the longitudinal trench (9), etch the N-type epitaxial layer (5) downward to form the longitudinal trench (9) and form the gate trench (13) in the peripheral region of the terminal; Step St5: Inject acceptor ions into the side walls and bottoms of the longitudinal trench (9) and the gate trench (13) to form a P-type doped region (4), and remove the mask plate; Step St6: Deposit a metal nickel layer (10) on the upper surface of the N-type epitaxial layer (5). The metal nickel layer (10) covers the upper surfaces of the P-type doped region (4), the first oxide layer (2), and the N-type source region (3); Step St7: Anneal the device at a high temperature to remove the metal nickel layer (10) and form a Silicide layer (11) on the surfaces of the longitudinal trench (9) and the gate trench (13); Step St8: Deposit a second oxide layer (12) on the upper surface of the N-type epitaxial layer (5). The second oxide layer (12) fills the interiors of the source region trench (8) and the longitudinal trench (9) and forms a flat surface on the upper surface of the N-type epitaxial layer (5); Step St9: Using the gate metal mask template, etch the excess second oxide layer (12) on the upper surface of the N-type epitaxial layer (5) and then deposit metal, and deposit metal on the lower surface of the N-type drain (6), and anneal to form the gate metal (14) and the drain metal (7) respectively.

Images