Semiconductor structures and semiconductor devices

Abstract

The present application provides a semiconductor structure and a semiconductor device, the semiconductor structure comprising: a substrate; an epitaxial layer located on a surface of the substrate, the epitaxial layer comprising an epitaxial layer body and a trench, the trench being located in the epitaxial layer body; a gate structure located at least in the trench, the sidewalls of the gate structure contacting a portion of the sidewalls of the trench; a first metal layer located at least in the trench, the sidewalls of the first metal layer contacting a portion of the sidewalls of the trench, the first metal layer being located on one side of the gate structure in a first direction perpendicular to the thickness of the substrate; a first doped region located in the epitaxial layer body, the first doped region being located on a side of the first metal layer away from the gate structure, the first doped region contacting the first metal layer, the doping type of the first doped region being different from the doping type of the epitaxial layer. The present application solves the problem in the prior art of trench-gate MOSFETs that it is difficult to ensure a small cell size while ensuring a strong trench bottom.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a semiconductor device. Background Art

[0002] Silicon carbide (SiC), as a wide bandgap semiconductor material, has broad application prospects in high voltage, high power, high temperature and high frequency applications due to its advantages such as wide bandgap, high critical electric field strength, high thermal conductivity and high saturation drift velocity.

[0003] Compared with planar-gate MOSFETs, trench-gate MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have higher trench mobility and smaller cell width pitch size, resulting in better conduction characteristics and smaller chip size. Combined with their faster switching speed, they have significant advantages in high-voltage, high-frequency, and high-power density applications.

[0004] However, the robustness of trench-gate MOSFETs requires solving the gate oxide electric field problem on the one hand and the latch-up problem of parasitic thyristors on the other. This requires clever structural design to avoid eroding the conduction characteristics and improve the compromise between robustness and conductivity.

[0005] Rohm's double trench MOS structure (DT-MOS) adds an additional source trench etch and then performs ion implantation on the source trench to obtain a P-well region of sufficient depth. The purpose is to improve the electric field at the gate oxide position at the bottom of the trench gate, thereby improving robustness. However, this structure separates the source and gate trenches, limiting the reduction of the cell width Pitch.

[0006] It is difficult for trench-gate MOSFETs in the prior art to ensure the robustness of the trench bottom while keeping the cell size small. Summary of the Invention

[0007] The main purpose of the present application is to provide a semiconductor structure and a semiconductor device to solve the problem in the prior art that it is difficult to ensure the robustness of the trench bottom while ensuring a small cell size.

[0008] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer located on the surface of the substrate, the epitaxial layer comprising an epitaxial layer body and a trench, the trench being located in the epitaxial layer body; a gate structure located at least in the trench, the sidewalls of the gate structure being in contact with part of the sidewalls of the trench; a first metal layer located at least in the trench, the sidewalls of the first metal layer being in contact with part of the sidewalls of the trench, and in a first direction, the first metal layer being located on one side of the gate structure, the first direction being perpendicular to the direction of the substrate thickness; a first doped region located in the epitaxial layer body, the first doped region being located on a side of the first metal layer away from the gate structure, and the first doped region being in contact with the first metal layer, and the doping type of the first doped region being different from the doping type of the epitaxial layer.

[0009] Optionally, the semiconductor structure further includes: an isolation dielectric layer, located at least in the trench and between the gate structure and the first metal layer.

[0010] Optionally, the semiconductor structure also includes: a second doping region, located in the epitaxial layer body and on the side of the trench close to the substrate, the doping type of the second doping region is the same as the doping type of the first doping region; a third doping region, located in the epitaxial layer body and at least on a portion of the surface of the second doping region away from the substrate, the third doping region is in contact with the trench, the doping type of the third doping region is the same as the doping type of the first doping region, and the doping concentration of the third doping region is greater than the doping concentration of the first doping region.

[0011] Optionally, the semiconductor structure further includes: a fourth doping region located in the epitaxial layer body and on the side of the first doping region away from the first metal layer, the first doping region in contact with the fourth doping region, the doping type of the fourth doping region being the same as the doping type of the first doping region, and the doping concentration of the fourth doping region being less than the doping concentration of the first doping region; a fifth doping region located in the epitaxial layer body and at least on a portion of the surface of the first doping region away from the substrate and a surface of the fourth doping region away from the substrate, the doping type of the fifth doping region being the same as the doping type of the epitaxial layer, and the doping concentration of the fifth doping region being greater than the doping concentration of the epitaxial layer, wherein the isolation dielectric layer is located in the trench, on the surface of the gate structure away from the substrate, and on a portion of the surface of the fifth doping region away from the substrate.

[0012] Optionally, the semiconductor structure also includes: a sixth doping region, located in the epitaxial layer body, and at least located on the surface of the first doping region close to the substrate and on a portion of the surface of the fourth doping region close to the substrate, the doping type of the sixth doping region being the same as the doping type of the epitaxial layer.

[0013] Optionally, the sixth doping region is located on a surface of the first doping region close to the substrate and on a surface of the fourth doping region close to the substrate.

[0014] Optionally, the sixth doping region is located on the surface of the first doping region close to the substrate and on a portion of the surface of the fourth doping region close to the substrate, and the sixth doping region is not in contact with the first metal layer, wherein the portion of the side wall of the first metal layer in contact with the epitaxial layer body forms a Schottky contact.

[0015] Optionally, the gate structure is located in the trench, and the gate structure includes: a gate oxide layer located in the trench, the thickness of the isolation dielectric layer is greater than the thickness of the gate oxide layer; and a gate located on a surface of the gate oxide layer away from the substrate.

[0016] Optionally, the gate structure is located in the trench and on a portion of the surface of the fifth doping region away from the substrate, and the gate structure includes: a gate oxide layer, located in the trench and on a portion of the surface of the fifth doping region away from the substrate, the thickness of the isolation dielectric layer is greater than the thickness of the gate oxide layer; and a gate, located on a surface of the gate oxide layer away from the substrate.

[0017] Optionally, the fifth doping region is located on a surface of the first doping region away from the substrate and on a surface of the fourth doping region away from the substrate, and the first metal layer is located in the groove and on a portion of the surface of the fifth doping region away from the substrate.

[0018] Optionally, the fifth doping region is located on a portion of the surface of the first doping region away from the substrate, on a portion of the side wall of the first doping region away from the first metal layer, and on a surface of the fourth doping region away from the substrate, and the first metal layer is located in the groove, on a portion of the surface of the fifth doping region away from the substrate, and on a portion of the surface of the first doping region away from the substrate.

[0019] Optionally, the fifth doping region is located on a portion of the surface of the first doping region away from the substrate, on a portion of the side wall of the first doping region away from the first metal layer, and on a portion of the surface of the fourth doping region away from the substrate, and the first metal layer is located in the groove, on a portion of the surface of the fifth doping region away from the substrate, on a portion of the side wall of the fifth doping region close to the first metal layer, and on a portion of the surface of the first doping region away from the substrate.

[0020] Optionally, a portion of the surface of the first metal layer close to the substrate contacts the epitaxial layer body, and a portion of the portion of the surface of the first metal layer close to the substrate in contact with the epitaxial layer body forms a Schottky contact.

[0021] Optionally, the sixth doped region contacts the first metal layer, and a portion of the sixth doped region contacting the first metal layer forms a Schottky contact.

[0022] Optionally, the third doping region is located at least on a portion of the surface of the second doping region away from the substrate and on a sidewall of the sixth doping region close to the first metal layer.

[0023] Optionally, there are differences in the projection patterns of the third doping region on the substrate.

[0024] Optionally, the semiconductor structure further includes: a second metal layer located on a surface of the substrate away from the epitaxial layer.

[0025] According to another aspect of the present application, a semiconductor device is provided, comprising any one of the semiconductor structures described above.

[0026] Applying the technical solution of the present application, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a gate structure, a first metal layer and a first doped region, wherein the epitaxial layer includes an epitaxial layer body and a groove, the groove is located in the epitaxial layer body, the gate structure and the first metal layer are respectively located at least in the groove, in a first direction, the first metal layer is located on one side of the gate structure, the first direction is perpendicular to the direction of the substrate thickness, the first doped region is located in the epitaxial layer body, the first doped region is located on the side of the first metal layer away from the gate structure, and the first doped region is in contact with the first metal layer, and the doping type of the first doped region is different from the doping type of the epitaxial layer. Compared with the problem in the prior art that it is difficult to ensure the robustness of the trench bottom while ensuring a small cell size, the first metal layer and the gate structure in the present application are arranged in the same trench, which is conducive to decoupling the limitations of the trench digging process capability on the width of small-sized cells (which can reduce the gate width and source width), and thus helps to reduce the size of the overall cell; the first metal layer is located in the trench, contacts part of the side wall of the trench, and is located on one side of the gate structure in the first direction. Such a layout helps to form a stable electrical connection, and can provide an additional conductive path on one side of the gate structure, which helps to disperse the current density, reduce current concentration, and reduce parasitic capacitance, thereby improving the robustness of the device. In addition, the doping type of the first doping region is different from the doping type of the epitaxial layer, which helps to form a good PN junction and improve the electrical stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0028] Figures 1 to 13 Schematic diagrams of cross-sectional structures of different semiconductor structures provided according to embodiments of the present application are respectively shown.

[0029] The above drawings include the following reference numerals:

[0030] 10. Substrate; 11. Epitaxial layer; 111. Epitaxial layer body; 112. Trench; 12. Gate structure; 13. First metal layer; 14. First doped region; 15. Isolation dielectric layer; 16. Second doped region; 17. Third doped region; 18. Fourth doped region; 19. Fifth doped region; 20. Sixth doped region; 121. Gate oxide layer; 122. Gate; 21. Second metal layer. DETAILED DESCRIPTION

[0031] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0032] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0033] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being “on” another element, the element may be directly on the other element or intervening elements may be present. Furthermore, in the specification and claims, when it is described that an element is “connected to” another element, the element may be “directly connected to” the other element or “connected to” the other element through a third element.

[0034] As introduced in the background art, it is difficult for trench-gate MOSFETs in the prior art to ensure the robustness of the trench bottom while keeping the cell size small. To solve the above problems, embodiments of the present application provide a semiconductor structure and a semiconductor device.

[0035] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0036] The present application embodiment provides a semiconductor structure, such as Figures 1 to 13 As shown, including:

[0037] substrate 10;

[0038] An epitaxial layer 11 is located on the surface of the substrate 10 . The epitaxial layer 11 includes an epitaxial layer body 111 and a trench 112 . The trench 112 is located in the epitaxial layer body 111 .

[0039] a gate structure 12 located at least in the trench 112 , with a sidewall of the gate structure 12 contacting a portion of the sidewall of the trench 112 ;

[0040] A first metal layer 13 is located at least in the trench 112, with a sidewall of the first metal layer 13 contacting a portion of the sidewall of the trench 112. In a first direction, the first metal layer 13 is located on one side of the gate structure 12, and the first direction is perpendicular to the thickness direction of the substrate 10;

[0041] The first doped region 14 is located in the epitaxial layer body 111. The first doped region 14 is located on the side of the first metal layer 13 away from the gate structure 12, and the first doped region 14 is in contact with the first metal layer 13. The doping type of the first doped region 14 is different from the doping type of the epitaxial layer 11.

[0042] Through the above embodiments, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a gate structure, a first metal layer and a first doped region, wherein the epitaxial layer includes an epitaxial layer body and a groove, the groove is located in the epitaxial layer body, the gate structure and the first metal layer are respectively located at least in the groove, in a first direction, the first metal layer is located on one side of the gate structure, the first direction is perpendicular to the direction of the substrate thickness, the first doped region is located in the epitaxial layer body, the first doped region is located on the side of the first metal layer away from the gate structure, and the first doped region is in contact with the first metal layer, and the doping type of the first doped region is different from the doping type of the epitaxial layer. Compared with the problem in the prior art that it is difficult to ensure the robustness of the trench bottom while ensuring a small cell size, the first metal layer and the gate structure in the present application are arranged in the same trench, which is conducive to decoupling the limitations of the trench digging process capability on the width of small-sized cells (which can reduce the gate width and source width), and thus helps to reduce the size of the overall cell; the first metal layer is located in the trench, contacts part of the side wall of the trench, and is located on one side of the gate structure in the first direction. Such a layout helps to form a stable electrical connection, and can provide an additional conductive path on one side of the gate structure, which helps to disperse the current density, reduce current concentration, and reduce parasitic capacitance, thereby improving the robustness of the device. In addition, the doping type of the first doping region is different from the doping type of the epitaxial layer, which helps to form a good PN junction and improve the electrical stability of the device.

[0043] Specifically, the provision of the first metal layer is conducive to heat dissipation and improves high temperature resistance.

[0044] Specifically, the semiconductor structure in this application is a trench gate MOSFET, the first metal layer serves as the source metal,

[0045] In the embodiment of the present application, the doping type of the above-mentioned substrate and the above-mentioned epitaxial layer are both N-type, the doping concentration of the above-mentioned substrate is greater than the doping concentration of the above-mentioned epitaxial layer, the above-mentioned substrate is 4H-SiC, and the doping concentration of the above-mentioned substrate is 5E18cm -3 ~1E21cm -3 The thickness of the substrate is 50 μm to 500 μm; the doping type of the first doping region is P type, and the doping concentration of the first doping region is 2E17 cm -3 ~8E19cm -3The thickness of the above-mentioned first doped region is 0~5μm; the width of the above-mentioned groove (that is, the length in the above-mentioned first direction) is 0.5μm~5μm, and the depth of the above-mentioned groove (that is, the length in the direction parallel to the thickness of the above-mentioned substrate) is 0.5μm~5μm.

[0046] Specifically, the material of the first metal layer includes but is not limited to nickel and titanium.

[0047] In other embodiments, the epitaxial layer body includes a first sub-epitaxial layer and a second sub-epitaxial layer, the first sub-epitaxial layer is located on the surface of the substrate, the second sub-epitaxial layer is located on the surface of the first sub-epitaxial layer away from the substrate, the doping concentration of the first sub-epitaxial layer is greater than the doping concentration of the second sub-epitaxial layer, wherein the trench is located in the second sub-epitaxial layer.

[0048] Specifically, the thickness of the first sub-epitaxial layer is smaller than the thickness of the second sub-epitaxial layer.

[0049] In the embodiment of the present application, the doping concentration of the first epitaxial layer is 5E15cm -3 ~1E19cm -3 The thickness of the first epitaxial layer is 5 μm to 50 μm; the doping concentration of the second epitaxial layer is 1E14 cm -3 ~5E17cm -3 The thickness of the second sub-epitaxial layer is 5 μm to 150 μm.

[0050] In one option, Figure 1 As shown, the semiconductor structure further includes an isolation dielectric layer 15, which is located at least in the trench 112 and between the gate structure 12 and the first metal layer 13. In this embodiment, the isolation dielectric layer is introduced into the trench and located between the gate structure and the first metal layer. This can reduce direct electrical contact between the gate structure and the first metal layer, thereby reducing the risk of electrical breakdown and further enhancing the electrical robustness of the device.

[0051] In the embodiment of the present application, the materials of the isolation dielectric layer are not limited to BPSG, SiO2 and Si x O y N z .

[0052] In other embodiments, Figures 1 to 13As shown, the semiconductor structure further includes: a second doping region 16 located in the epitaxial layer body 111 and on a side of the trench 112 close to the substrate 10. The doping type of the second doping region 16 is the same as the doping type of the first doping region 14; and a third doping region 17 located in the epitaxial layer body 111 and at least on a portion of the surface of the second doping region 16 away from the substrate 10. The third doping region 17 contacts the trench 112. The doping type of the third doping region 17 is the same as the doping type of the first doping region 14, and the doping concentration of the third doping region 17 is greater than the doping concentration of the first doping region 14. In this embodiment, the second doping region is provided below the trench, that is, below the gate structure, which helps reduce CGD and improve switching characteristics. In addition, the introduction of the second and third doping regions helps improve the electric field distribution at the bottom of the trench and reduces electric field concentration, thereby reducing the risk of device breakdown under high voltage and further improving the robustness of the device.

[0053] In the embodiment of the present application, the doping type of the second doping region is P type, the doping concentration of the second doping region is, and the thickness of the second doping region is 8E16cm -3 ~5E19cm -3 The thickness of the second doping region is 0.5 μm to 3 μm; the doping type of the third doping region is N-type, and the doping concentration of the third doping region is 4E17 cm -3 ~1E20cm -3 The thickness of the third doping region is 0.2 μm to 2 μm, and the length of the third doping region in the first direction is 0.5 μm to 20 μm.

[0054] In the embodiment of the present application, the doping elements of the P-type doping region include but are not limited to aluminum ions, and the doping elements of the N-type doping region include but are not limited to nitrogen ions.

[0055] According to some exemplary embodiments of the present application, Figures 1 to 13As shown, the semiconductor structure further includes: a fourth doping region 18 located in the epitaxial layer body 111 and located on a side of the first doping region 14 away from the first metal layer 13, the first doping region 14 is in contact with the fourth doping region 18, the doping type of the fourth doping region 18 is the same as the doping type of the first doping region 14, and the doping concentration of the fourth doping region 18 is less than the doping concentration of the first doping region 14; a fifth doping region 19 located in the epitaxial layer body 111 and at least located on a portion of the surface of the first doping region 14 away from the substrate 10 and a surface of the fourth doping region 18 away from the substrate 10, the doping type of the fifth doping region 19 is the same as the doping type of the epitaxial layer 11, and the doping concentration of the fifth doping region 19 is greater than the doping concentration of the epitaxial layer 11, wherein the isolation dielectric layer 15 is located in the trench 112, on a surface of the gate structure 12 away from the substrate 10, and on a portion of the surface of the fifth doping region 19 away from the substrate 10. In this embodiment, by introducing the fourth doping region and the fifth doping region into the semiconductor structure and precisely controlling their doping types and concentrations, the electrical characteristics of the semiconductor device can be further optimized, such as increasing the carrier mobility and reducing the resistivity, thereby further improving the overall performance of the device. The doping concentration of the fifth doping region is greater than the doping concentration of the epitaxial layer, which helps to distribute the electric field more evenly when the device is working and reduce the electric field concentration, thereby improving the voltage resistance and reliability of the device. The existence of the fourth doping region and its doping concentration is less than that of the first doping region, which helps to enhance the gate's control over the channel, which is very critical for improving the switching speed of the device and reducing leakage current; the design of the isolation dielectric layer helps to reduce leakage current and improve the insulation performance of the device, thereby further improving the overall electrical reliability.

[0056] In the embodiment of the present application, the doping type of the fourth doping region is P type, and the doping concentration of the fourth doping region is 5E15cm -3 ~2E18cm -3 The thickness of the fourth doping region is 0.2 μm to 3 μm; the doping type of the fifth doping region is N-type, and the doping concentration of the fifth doping region is 1E18 cm -3 ~5E21cm -3 The thickness of the fifth doping region is 0.1 μm to 3 μm.

[0057] In other embodiments, Figures 1 to 13As shown, the semiconductor structure further includes a sixth doped region 20 located in the epitaxial layer body 111 and located at least on the surface of the first doped region 14 proximal to the substrate 10 and on a portion of the surface of the fourth doped region 18 proximal to the substrate 10. The doping type of the sixth doped region 20 is the same as the doping type of the epitaxial layer 11. In this embodiment, the introduction of the sixth doped region can further adjust and optimize the electrical characteristics of the semiconductor structure. Since the doping type of the sixth doped region is the same as that of the epitaxial layer, it can affect the distribution and mobility of carriers to a certain extent, thereby improving the conductive performance and switching speed of the device.

[0058] In the embodiment of the present application, the doping type of the sixth doping region is N-type, and the doping concentration of the sixth doping region is 5E15cm -3 ~1E19cm -3 The thickness of the sixth doping region is 0.5 μm to 5 μm.

[0059] Specifically, the third doping region can have various variations, such as Figures 1 to 8 Various deformations of the third doped region.

[0060] According to other exemplary embodiments of the present application, Figures 1 to 11 As shown, the sixth doping region 20 is located on a surface of the first doping region 14 close to the substrate 10 and on a surface of the fourth doping region 18 close to the substrate 10 .

[0061] Some of the options in this application, such as Figure 12 and Figure 13 As shown, the sixth doped region 20 is located on the surface of the first doped region 14 near the substrate (not shown) and on a portion of the surface of the fourth doped region 18 near the substrate. The sixth doped region 20 does not contact the first metal layer 13. The portion where the sidewall of the first metal layer 13 contacts the epitaxial layer body (not shown) forms a Schottky contact. In this embodiment, the formation of a Schottky contact can reduce contact resistance and further improve the device's conductivity. The provision of the sixth doped region can also reduce the current density near the SBD (Schottky Barrier Diode) region, thereby reducing the peak temperature in the SBD region and improving the device's robustness.

[0062] Specifically, localized configuration of the nJFET region (i.e., the sixth doped region) in certain areas (local configuration refers to configuration on the channel side, not on the source contact side) can reduce the current density near the SBD region, thereby lowering the peak temperature in the SBD region and improving device robustness. The source contact side refers to the side close to the source metal (i.e., the first metal layer); the channel side refers to the side close to the channel formed between the fourth doped region and the gate oxide layer.

[0063] Specifically, if Figure 12 and Figure 13 As shown, the portion where the sidewall of the first metal layer 13 forms Schottky contact with the epitaxial layer body is a vertical Schottky contact region (not marked).

[0064] In other embodiments, Figure 13 As shown, the gate structure 12 is located in the trench 112. The gate structure 12 includes a gate oxide layer 121 located in the trench 112. The isolation dielectric layer 15 has a thickness greater than that of the gate oxide layer 121. A gate 122 is located on a surface of the gate oxide layer 121 that is away from the substrate (not shown). In this embodiment, the gate oxide layer effectively isolates the electric field between the gate and other parts of the semiconductor, improving the gate's insulation performance. In addition, the isolation dielectric layer having a thickness greater than that of the gate oxide layer provides a stronger electric field shielding effect, thereby further improving the reliability and stability of the device.

[0065] Specifically, within the same trench, an isolation dielectric layer is configured between the first metal layer and the gate structure, replacing the original gate oxide layer. This increases the thickness and area of ​​the dielectric layer, which is beneficial to reducing CGS (Capacitance between Gate and Source) and thus improving switching characteristics.

[0066] In some alternative solutions of this application, such as Figures 1 to 12 As shown, the gate structure 12 is located in the trench 112 and on the portion of the surface of the fifth doping region 19 away from the substrate 10. The gate structure 12 includes a gate oxide layer 121 located in the trench 112 and on the portion of the surface of the fifth doping region 19 away from the substrate 10. The thickness of the isolation dielectric layer 15 is greater than the thickness of the gate oxide layer 121; and a gate 122 located on the surface of the gate oxide layer 121 away from the substrate 10. In this embodiment, by providing a gate oxide layer in the trench and on the portion of the surface of the fifth doping region away from the substrate, and ensuring that the thickness of the isolation dielectric layer is greater than the thickness of the gate oxide layer, the gate and trench can be effectively isolated, leakage current can be reduced, and the electrical performance of the device can be further improved.

[0067] Specifically, the gate oxide layer is located on part of the sidewalls of the trench, part of the surface (i.e., the bottom surface), and part of the fifth doped region, wherein the thickness of the gate oxide layer located on part of the sidewalls of the trench and part of the fifth doped region is greater than the thickness of the gate oxide layer located on part of the sidewalls of the trench. This can reduce the migration of carriers in the gate oxide layer to the gate oxide position, thereby improving the threshold stability.

[0068] Specifically, the ILD (InterLayer Dielectric) dielectric layer (i.e., the isolation dielectric layer) can be further extended into the upper surface of the epitaxial layer to increase the thickness of the dielectric layer between the P field stop region (i.e., the second doped region) and the gate, which is beneficial to threshold stability.

[0069] In some further optional solutions of this application, such as Figure 10 As shown, the fifth doping region 19 is located on the surface of the first doping region 14 away from the substrate (not shown) and on the surface of the fourth doping region 18 away from the substrate. The first metal layer 13 is located in the trench 112 and on a portion of the surface of the fifth doping region 19 away from the substrate. In this embodiment, by precisely controlling the position of the fifth doping region, the electric field distribution in the semiconductor structure can be optimized, especially near the trench region, which helps further improve the withstand voltage performance of the device.

[0070] In other embodiments, Figure 9 As shown, the fifth doping region 19 is located on a portion of the surface of the first doping region 14 away from the substrate (not shown), on a portion of the sidewall of the first doping region 14 away from the first metal layer 13, and on a surface of the fourth doping region 18 away from the substrate. The first metal layer 13 is located in the trench 112, on a portion of the surface of the fifth doping region 19 away from the substrate, and on a portion of the surface of the first doping region 14 away from the substrate. In this embodiment, by precisely controlling the positions of the first doping region, the fifth doping region, and the first metal layer, the electrical characteristics of the semiconductor device can be further optimized, such as reducing resistance and improving carrier mobility.

[0071] According to other exemplary embodiments of the present application, Figure 11As shown, the fifth doping region 19 is located on a portion of the surface of the first doping region 14 away from the substrate (not shown), on a portion of the sidewall of the first doping region 14 away from the first metal layer 13, and on a portion of the surface of the fourth doping region 18 away from the substrate. The first metal layer 13 is located in the trench 112, on a portion of the surface of the fifth doping region 19 away from the substrate, on a portion of the sidewall of the fifth doping region 19 close to the first metal layer 13, and on a portion of the surface of the first doping region 14 away from the substrate. In this embodiment, by increasing the ohmic contact area between the fifth doping region and the first doping region and the first metal layer, the contact resistance can be reduced, thereby improving the short-circuit characteristics.

[0072] Specifically, a portion of the first doping region that contacts the first metal layer forms an ohmic contact, and a portion of the fifth doping region that contacts the first metal layer forms an ohmic contact.

[0073] In other embodiments, Figure 2 、 Figure 4 and Figure 6 A portion of the surface of the first metal layer 13 near the substrate 10 contacts the epitaxial layer body 111, and a Schottky contact is formed in the portion of the surface of the first metal layer 13 near the substrate 10 that contacts the epitaxial layer body 111. In this embodiment, the formation of the Schottky contact can improve the stability and reliability of the device under high voltage and high current conditions because the Schottky contact has lower reverse leakage current and higher breakdown voltage.

[0074] Specifically, a portion of the surface of the first metal layer close to the substrate that forms Schottky contact with the epitaxial layer body is a horizontal Schottky contact region, and a length of the horizontal Schottky contact region in the first direction is 0.1 μm to 3 μm.

[0075] According to some further exemplary embodiments of the present application, Figures 1 to 6 ,like Figures 9 to 11 As shown, the sixth doped region 20 contacts the first metal layer 13, and the portion of the sixth doped region 20 in contact with the first metal layer 13 forms a Schottky contact. In this embodiment, the portion of the sixth doped region in contact with the first metal layer forms a Schottky contact, which can further improve the switching speed of the device.

[0076] Specifically, configuring a Schottky at the source metal contact position is beneficial to reducing the reverse leakage current of the device.

[0077] Specifically, the portion where the sixth doped region forms Schottky contact with the first metal layer is a vertical Schottky contact region.

[0078] Specifically, the vertical Schottky contact region and the horizontal Schottky contact region may have the same or different barrier heights, which is not specifically limited in this application. Specifically, the vertical Schottky contact region and the horizontal Schottky contact region provide the possibility of realizing two barrier heights.

[0079] Specifically, the P field stop region and the P++ doped region (ie, the third doped region) are configured in separate panels, which provides the possibility for configuring a horizontal Schottky contact.

[0080] Specifically, the local sidewall SBD region (i.e., the vertical Schottky contact region) combined with the source ohmic contact region (i.e., the portion where the first metal layer contacts the first doped region and the fifth doped region, respectively) can change the blocking state and the flow path of the avalanche hole current, which is beneficial to improving the misconduction of the BJT transistor.

[0081] Specifically, the local sidewall SBD region is divided into small segments, and the surrounding areas are all configured with P-type doped regions, which is beneficial to improving the high-temperature leakage of the SBD region and at the same time, can improve the surge resistance of the reverse freewheeling diode.

[0082] According to some further exemplary embodiments of the present application, Figure 7 and Figure 8 As shown, the third doped region 17 is located on at least a portion of the surface of the second doped region 16 away from the substrate (not shown) and on a sidewall of the sixth doped region 20 adjacent to the first metal layer 13. In this embodiment, providing the third doped region on the sidewall of the sixth doped region adjacent to the first metal layer helps reduce parasitic effects, such as parasitic transistor effects, thereby further improving the switching speed and efficiency of the device.

[0083] In other embodiments, Figure 7 As shown, the third doping region 17 is located on the surface of the second doping region 16 away from the substrate and on the sidewall of the sixth doping region 20 close to the first metal layer 13 .

[0084] In other embodiments, Figure 1 、 Figures 9 to 13 As shown, the third doping region 17 is located on a surface of the second doping region 16 away from the substrate 10 .

[0085] Specifically, the third doping region may be provided to the entire bottom of the trench, or to a portion of the bottom of the trench.

[0086] Specifically, the change in the injection position of the P field stop region can further increase the width of the JFET region and improve the conduction characteristics.

[0087] In other embodiments, the projection pattern of the third doped region on the substrate varies. Specifically, the projection pattern of the third doped region on the substrate varies at different positions in a second direction, where the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the substrate.

[0088] Specifically, the third doped region may have different patterns in the second direction. When the semiconductor structure is cut at two different positions in the second direction, the third doped region may be different in the two cross-sectional views obtained. For example, Figure 5 and Figure 6 .

[0089] Specifically, the first doped region may have different patterns in the second direction. When the semiconductor structure is cut at two different positions in the second direction, the first doped region may be different in the two cross-sectional views obtained, for example: Figure 9 and Figure 10 .

[0090] In other embodiments, Figures 1 to 13 As shown, there are two grooves 112 , and the two grooves 112 are spaced apart in the first direction.

[0091] Specifically, if Figures 1 to 13 As shown, the sixth doping region 20 may be entirely or partially disposed between the two trenches 112 .

[0092] Specifically, there are also two corresponding third doped regions. The specific locations of the first third doped region (i.e., the third doped region below the first trench) and the second third doped region (i.e., the third doped region below the second trench) can be different or the same, and this application does not impose any specific restrictions on this. For example, the first third doped region is located below the isolation dielectric layer in the first trench, and the second doped region is located below the first metal layer in the second trench.

[0093] In other embodiments, Figure 1 and Figure 2 As shown, the semiconductor structure further includes: a second metal layer 21 located on a surface of the substrate 10 away from the epitaxial layer 11 .

[0094] Specifically, the semiconductor structure in the present application is a trench-gate MOSFET, the first metal layer serves as a source, and the second metal layer serves as a drain.

[0095] Specifically, in an embodiment of the present application, the first metal layer serves as the source metal, the second metal layer serves as the drain metal, the first doped region serves as the P+ doped region, the second doped region serves as the P field stop region, the third doped region serves as the source P++ doped region, the fourth doped region serves as the P well region, the fifth doped region serves as the source N+ doped region, and the sixth doped region serves as the nJFET region.

[0096] The embodiment of the present application also provides a method for preparing a semiconductor structure, which specifically includes the following steps: step 1, epitaxially growing an nBuffer epitaxial layer (i.e., a first sub-epitaxial layer) and an ndrift epitaxial layer (i.e., a second sub-epitaxial layer) on an n+ silicon carbide substrate; step 2, implanting an nJFET region (i.e., a sixth doping region) on the ndrift epitaxial layer; step 3, implanting a P-well region (i.e., a fourth doping region) in the nJFET region; step 4, implanting a patterned P+ doping region (i.e., a first doping region) and an N+ doping region (i.e., a fifth doping region) in the P-well region; step 5, forming a gate-source common trench by an etching process; step 6: implanting a P-field stop region (i.e., a second doping region) at the bottom of the trench; ), forming a patterned P++ doping region (i.e., the third doping region) at the bottom of the trench and part of the trench sidewall; Step 7: coating with a carbon film, and annealing at a high temperature of 1600°C to 1800°C to activate the doping; Step 8: sacrificially oxidizing the implanted damaged layer and removing the sacrificial oxide layer by wet etching; Step 9: growing a gate oxide layer by thermally oxidizing SiC to form SiO2, or directly depositing SiO2 or depositing Si to oxidize Si; Step 10: depositing polysilicon on the gate oxide layer to form a gate electrode (i.e., the gate), wherein the polysilicon needs to be doped to control the threshold voltage and gate resistance; Step 11: etching away excess gate polysilicon and the gate oxide layer underneath; Step 12: depositing an isolation dielectric layer;

[0097] Step 13: Opening holes in the isolation oxide layer in part of the N+ doped area and part of the P+ doped area, depositing a metal or alloy such as Ni, and after high-temperature annealing, forming an ohmic contact with the P+ doped area and part of the N+ doped area in contact with the metal, and then removing the unreacted metal;

[0098] Step 14: depositing a metal or alloy such as Ti (i.e., a first metal layer) by sputtering or evaporation, and forming a Schottky contact with the ndrift epitaxial layer in contact with the metal after high-temperature annealing;

[0099] In step 16, the wafer is flipped over, the substrate is thinned, and metal is deposited to form a backside ohmic contact (i.e., a second metal layer) to serve as the drain electrode of the device.

[0100] An embodiment of the present application also provides a semiconductor device comprising any of the above-mentioned semiconductor structures.

[0101] In the above embodiment, the semiconductor device includes a semiconductor structure, wherein the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a gate structure, a first metal layer and a first doped region, wherein the epitaxial layer includes an epitaxial layer body and a groove, the groove is located in the epitaxial layer body, the gate structure and the first metal layer are respectively located at least in the groove, in a first direction, the first metal layer is located on one side of the gate structure, the first direction is perpendicular to the direction of the substrate thickness, the first doped region is located in the epitaxial layer body, the first doped region is located on the side of the first metal layer away from the gate structure, and the first doped region is in contact with the first metal layer, and the doping type of the first doped region is different from the doping type of the epitaxial layer. Compared with the problem in the prior art that it is difficult to ensure the robustness of the trench bottom while ensuring a small cell size, the first metal layer and the gate structure in the present application are arranged in the same trench, which is conducive to decoupling the limitations of the trench digging process capability on the width of small-sized cells (which can reduce the gate width and source width), and thus helps to reduce the size of the overall cell; the first metal layer is located in the trench, contacts part of the side wall of the trench, and is located on one side of the gate structure in the first direction. Such a layout helps to form a stable electrical connection, and can provide an additional conductive path on one side of the gate structure, which helps to disperse the current density, reduce current concentration, and reduce parasitic capacitance, thereby improving the robustness of the device. In addition, the doping type of the first doping region is different from the doping type of the epitaxial layer, which helps to form a good PN junction and improve the electrical stability of the device.

[0102] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0103] 1) In the semiconductor structure of the present application, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a gate structure, a first metal layer and a first doped region, wherein the epitaxial layer includes an epitaxial layer body and a groove, the groove is located in the epitaxial layer body, the gate structure and the first metal layer are respectively located at least in the groove, in a first direction, the first metal layer is located on one side of the gate structure, the first direction is perpendicular to the direction of the substrate thickness, the first doped region is located in the epitaxial layer body, the first doped region is located on the side of the first metal layer away from the gate structure, and the first doped region is in contact with the first metal layer, and the doping type of the first doped region is different from the doping type of the epitaxial layer. Compared with the problem in the prior art that it is difficult to ensure the robustness of the trench bottom while ensuring a small cell size, the first metal layer and the gate structure in the present application are arranged in the same trench, which is conducive to decoupling the limitations of the trench digging process capability on the width of small-sized cells (which can reduce the gate width and source width), and thus helps to reduce the size of the overall cell; the first metal layer is located in the trench, contacts part of the side wall of the trench, and is located on one side of the gate structure in the first direction. Such a layout helps to form a stable electrical connection, and can provide an additional conductive path on one side of the gate structure, which helps to disperse the current density, reduce current concentration, and reduce parasitic capacitance, thereby improving the robustness of the device. In addition, the doping type of the first doping region is different from the doping type of the epitaxial layer, which helps to form a good PN junction and improve the electrical stability of the device.

[0104] 2) In the semiconductor device of the present application, the semiconductor device includes a semiconductor structure, wherein the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a gate structure, a first metal layer and a first doped region, wherein the epitaxial layer includes an epitaxial layer body and a groove, the groove is located in the epitaxial layer body, the gate structure and the first metal layer are respectively located at least in the groove, in a first direction, the first metal layer is located on one side of the gate structure, the first direction is perpendicular to the direction of the substrate thickness, the first doped region is located in the epitaxial layer body, the first doped region is located on the side of the first metal layer away from the gate structure, and the first doped region is in contact with the first metal layer, and the doping type of the first doped region is different from the doping type of the epitaxial layer. Compared with the problem in the prior art that it is difficult to ensure the robustness of the trench bottom while ensuring a small cell size, the first metal layer and the gate structure in the present application are arranged in the same trench, which is conducive to decoupling the limitations of the trench digging process capability on the width of small-sized cells (which can reduce the gate width and source width), and thus helps to reduce the size of the overall cell; the first metal layer is located in the trench, contacts part of the side wall of the trench, and is located on one side of the gate structure in the first direction. Such a layout helps to form a stable electrical connection, and can provide an additional conductive path on one side of the gate structure, which helps to disperse the current density, reduce current concentration, and reduce parasitic capacitance, thereby improving the robustness of the device. In addition, the doping type of the first doping region is different from the doping type of the epitaxial layer, which helps to form a good PN junction and improve the electrical stability of the device.

[0105] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A semiconductor structure, characterized in that include: substrate; an epitaxial layer located on the surface of the substrate, the epitaxial layer comprising an epitaxial layer body and a trench, wherein the trench is located in the epitaxial layer body; a gate structure, located at least in the trench, wherein a sidewall of the gate structure contacts a portion of a sidewall of the trench; a first metal layer, located at least in the trench, with a sidewall of the first metal layer contacting a portion of the sidewall of the trench, and the first metal layer located on one side of the gate structure in a first direction, the first direction being perpendicular to a thickness direction of the substrate; a first doped region located in the epitaxial layer body, the first doped region being located on a side of the first metal layer away from the gate structure, the first doped region being in contact with the first metal layer, and the doping type of the first doped region being different from the doping type of the epitaxial layer; a fourth doping region, located in the epitaxial layer body and on a side of the first doping region away from the first metal layer, the first doping region being in contact with the fourth doping region, the fourth doping region having the same doping type as the first doping region, and a doping concentration of the fourth doping region being less than a doping concentration of the first doping region; A fifth doping region is located in the epitaxial layer body and is located at least on a portion of the surface of the first doping region away from the substrate and on a surface of the fourth doping region away from the substrate. The doping type of the fifth doping region is the same as the doping type of the epitaxial layer, and the doping concentration of the fifth doping region is greater than the doping concentration of the epitaxial layer.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: An isolation dielectric layer is located between the gate structure and the first metal layer, and is located in the trench, on a surface of the gate structure away from the substrate, and on a portion of a surface of the fifth doping region away from the substrate.

3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further comprises: a second doping region, located in the epitaxial layer body and on a side of the trench close to the substrate, wherein the doping type of the second doping region is the same as the doping type of the first doping region; A third doping region is located in the epitaxial layer body and at least on a portion of the surface of the second doping region away from the substrate. The third doping region is in contact with the groove. The doping type of the third doping region is the same as the doping type of the first doping region, and the doping concentration of the third doping region is greater than the doping concentration of the first doping region.

4. The semiconductor structure according to claim 3, wherein: The semiconductor structure further comprises: A sixth doping region is located in the epitaxial layer body and is at least located on the surface of the first doping region close to the substrate and on a portion of the surface of the fourth doping region close to the substrate. The doping type of the sixth doping region is the same as the doping type of the epitaxial layer.

5. The semiconductor structure according to claim 4, wherein: The sixth doped region is not in contact with the first metal layer, wherein a portion of the sidewall of the first metal layer in contact with the epitaxial layer body forms a Schottky contact.

6. The semiconductor structure according to claim 2, wherein: The gate structure is located in the trench, and the gate structure includes: a gate oxide layer located in the trench, wherein the thickness of the isolation dielectric layer is greater than the thickness of the gate oxide layer; The gate is located on a surface of the gate oxide layer away from the substrate.

7. The semiconductor structure according to claim 2, wherein: The gate structure is located in the trench and on a portion of the surface of the fifth doping region away from the substrate, and the gate structure includes: a gate oxide layer located in the trench and on a portion of the surface of the fifth doping region away from the substrate, wherein the thickness of the isolation dielectric layer is greater than the thickness of the gate oxide layer; The gate is located on a surface of the gate oxide layer away from the substrate.

8. The semiconductor structure according to claim 1, wherein: The fifth doping region is located on a surface of the first doping region away from the substrate and a surface of the fourth doping region away from the substrate. The first metal layer is located in the trench and on a portion of the surface of the fifth doping region away from the substrate.

9. The semiconductor structure according to claim 1, wherein: The fifth doping region is located on a portion of the surface of the first doping region away from the substrate, on a portion of the side wall of the first doping region away from the first metal layer, and on a surface of the fourth doping region away from the substrate, and the first metal layer is located in the groove, on a portion of the surface of the fifth doping region away from the substrate, and on a portion of the surface of the first doping region away from the substrate.

10. The semiconductor structure according to claim 1, wherein: The fifth doping region is located on a portion of the surface of the first doping region away from the substrate, on a portion of the side wall of the first doping region away from the first metal layer, and on a portion of the surface of the fourth doping region away from the substrate, and the first metal layer is located in the groove, on a portion of the surface of the fifth doping region away from the substrate, on a portion of the side wall of the fifth doping region close to the first metal layer, and on a portion of the surface of the first doping region away from the substrate.

11. The semiconductor structure according to claim 1, wherein: A portion of the surface of the first metal layer close to the substrate contacts the epitaxial layer body, and a portion of the portion of the surface of the first metal layer close to the substrate contacting the epitaxial layer body forms a Schottky contact.

12. The semiconductor structure according to claim 4, wherein: The sixth doping region contacts the first metal layer, and a portion of the sixth doping region contacting the first metal layer forms a Schottky contact.

13. The semiconductor structure according to claim 4, wherein: The third doping region is located at least on a portion of the surface of the second doping region away from the substrate and on a sidewall of the sixth doping region close to the first metal layer.

14. The semiconductor structure according to claim 3, wherein: The third doping region has different cross-sectional shapes at a plurality of different positions in a second direction, the second direction intersects the first direction, and the second direction is perpendicular to the direction of the substrate thickness.

15. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: The second metal layer is located on a surface of the substrate away from the epitaxial layer.

16. A semiconductor device, characterized in that: A semiconductor structure comprising any one of claims 1 to 15.

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