Integrated passive device structure and manufacturing method thereof

Abstract

The invention provides an integrated passive device structure and a manufacturing method thereof, and the method comprises the steps: forming a barrier layer on a thin-film resistor, and employing the barrier layer as an etching barrier layer through the high etching selection ratio of the barrier layer and a dielectric layer in the etching process of a contact through hole, the first contact through hole connected with the MIM capacitor and the second contact through hole connected with the thin-film resistor are synchronously formed, so that synchronous etching of the contact through holes of the MIM capacitor and the thin-film resistor at different heights is realized, a layer of photomask is reduced, the process is simplified, the process window is improved, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and particularly to an integrated passive device structure and a manufacturing method thereof. Background Art

[0002] As the functions of mobile and handheld devices become increasingly rich, it is necessary to accommodate more frequency bands and meet the requirements of small size. Integrated passive devices (IPDs, Integrated Passive Component) are an increasingly popular technology, providing small size and high performance advantages for radio frequency solutions. IPDs are composed of passive components such as resistors, inductors, and capacitors, playing a key role in system-level packaging solutions and being used for many different functions in the semiconductor industry.

[0003] Figure 1 is a process schematic diagram of an integrated passive device structure. As Figure 1 shown, in the IPD platform, customers have a need to use titanium nitride (TiN) as a resistor (Thin film resistor). Because of the high requirements for radio frequency (RF) performance, it is necessary to isolate the TiN from M1. It is impossible to use the TiN on the upper plate of the MIM, and only a new layer of TiN layer (TFR) can be added. Since there is a large height difference between the TFR and the MIM, it is necessary to perform the etching of the upper contact via (VIA) step by step. The process flow is relatively complex, and a total of six photomasks are used. Moreover, there is a risk of contact via photoresist residue (VIA PR residue) and misalignment of overlay (OVL). Summary of the Invention

[0004] The present invention provides an integrated passive device structure and a manufacturing method thereof, which realizes the synchronous etching of the contact vias of the MIM capacitor and the thin film resistor at different heights, reduces one photomask, and simplifies the process.

[0005] To achieve the above object, the present invention provides an integrated passive device structure, including:

[0006] Providing a substrate, and forming a metal-insulator-metal capacitor on the substrate;

[0007] Forming a first dielectric layer, the first dielectric layer at least covering the metal-insulator-metal capacitor;

[0008] Forming a thin film resistor on the surface of the first dielectric layer that is horizontally different from the position where the metal-insulator-metal capacitor is located and a barrier layer on the thin film resistor;

[0009] Forming a second dielectric layer on the surface of the first dielectric layer, the second dielectric layer covering the thin film resistor and the barrier layer;

[0010] Using the high etching selectivity between the materials of the first dielectric layer and the second dielectric layer and the material of the barrier layer, with the barrier layer as an etching stop layer, etch the first dielectric layer and the second dielectric layer to simultaneously form a first contact via connecting the metal-insulator-metal capacitor and a second contact via connecting the thin film resistor.

[0011] Optionally, the barrier layer includes a silicon nitride layer.

[0012] Optionally, the formation of the metal-insulator-metal capacitor includes:

[0013] A first capacitor metal layer, a capacitor insulating layer, and a second capacitor metal layer stacked from bottom to top;

[0014] Etch the second capacitor metal layer and the capacitor insulating layer to expose part of the first capacitor insulating layer.

[0015] Optionally, the formation of the thin film resistor and the barrier layer includes:

[0016] Form a thin film resistor material layer and a barrier material layer on the surface of the first dielectric layer from bottom to top in sequence;

[0017] Perform patterning on the thin film resistor material layer and the barrier material layer to form a thin film resistor and a barrier layer that are horizontally different from the position of the metal-insulator-metal capacitor.

[0018] Optionally, it further includes:

[0019] Form a top metal layer on the second dielectric layer, and the top metal layer connects the first contact via and the second contact via;

[0020] Form an insulating layer that covers the top and side walls of the top metal layer;

[0021] Form a passivation layer that covers the top and side walls of the insulating layer and the second dielectric layer between the intervals of the top metal layer.

[0022] Optionally, the thickness of the thin film resistor is 800 Å to 1200 Å.

[0023] Optionally, the height from the first capacitor metal layer to the thin film resistor is 8300 Å to 8700 Å.

[0024] ]Optionally, the substrate includes a high resistivity silicon substrate.

[0025] The present invention also provides an integrated passive device structure, including:

[0026] A substrate and a metal-insulator-metal capacitor located on the substrate;

[0027] A first dielectric layer, located on the substrate, covering the metal-insulator-metal capacitor;

[0028] A thin film resistor and a barrier layer located on the thin film resistor, the thin film resistor being located on the first dielectric layer and horizontally different from the position of the metal-insulator-metal capacitor;

[0029] A second dielectric layer, located on the first dielectric layer, covering the thin film resistor and the barrier layer;

[0030] A first contact via, connecting the metal-insulator-metal capacitor;

[0031] A second contact via, connecting the thin film resistor.

[0032] Optionally, the barrier layer includes a silicon nitride layer.

[0033] Optionally, the metal-insulator-metal capacitor includes: a first capacitive metal layer, a capacitive insulating layer, and a second capacitive metal layer stacked from bottom to top. Among them, there is an uncovered part of the first capacitive metal layer not covered by the second capacitive metal layer and the capacitive insulating layer, and the first contact via connects the second capacitive metal layer and the uncovered part of the first capacitive metal layer.

[0034] Optionally, the integrated passive device structure further includes:

[0035] A top metal layer, spaced apart and distributed on the second dielectric layer, connecting the first contact via and the second contact via;

[0036] An insulating layer, covering the top and side walls of the top metal layer;

[0037] A passivation layer, covering the top and side walls of the insulating layer and the second dielectric layer between the intervals of the top metal layer.

[0038] In summary, the present invention provides an integrated passive device structure and a manufacturing method thereof. A barrier layer is formed on the thin film resistor. During the etching process of the contact via, using the high etching selectivity of the barrier layer and the dielectric layer, the barrier layer is used as an etching barrier layer to simultaneously form the first contact via connecting the MIM capacitor and the second contact via connecting the thin film resistor, thereby realizing the synchronous etching of the contact vias of the MIM capacitor and the thin film resistor at different heights, reducing one photomask, simplifying the process, improving the process window, and reducing the production cost. Description of the Drawings

[0039] Figure 1It is a process schematic diagram of an integrated passive device structure;

[0040] Figure 2 It is a schematic flow chart of an integrated passive device structure and a manufacturing method thereof provided by an embodiment of the present invention;

[0041] Figures 3A to 3E It is a schematic structural diagram formed by the steps corresponding to the integrated passive device structure and its manufacturing method in an embodiment of the present invention;

[0042] Among them, the reference numerals are explained as follows:

[0043] 100 - Substrate; 110 - Bottom dielectric layer; 120 - First dielectric layer; 130 - Second dielectric layer; 140 - First contact via; 150 - Second contact via;

[0044] 101 - First capacitor metal layer; 102 - Capacitor insulating layer; 103 - Second capacitor metal layer; 104 - Thin film resistor; 105 - Barrier layer; 104a - Thin film resistor material layer; 105a - Barrier material layer; 106 - Top metal layer; 107 - Insulating layer; 108 - Passivation layer. Specific embodiments

[0045] To make the content of the present invention clearer and easier to understand, the following further describes the content of the present invention in conjunction with the accompanying drawings of the specification. Of course, the present invention is not limited to this specific embodiment, and general substitutions well known to those skilled in the art are also covered by the protection scope of the present invention.

[0046] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the sake of convenience of description, the schematic diagrams are enlarged locally not in accordance with the general ratio, and this should not be regarded as a limitation of the present invention.

[0047] For the sake of convenience of description, some embodiments of the present invention may use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or some other) element or component as shown in the accompanying drawings of the embodiments. It should be understood that in addition to the orientations described in the accompanying drawings, the spatial relative terms are also intended to include different orientations during the use or operation of the device. For example, if the device in the accompanying drawings is flipped, the element or component described as "below" or "beneath" other elements or components will subsequently be positioned "above" or "on top of" other elements or components. The terms "first", "second", etc. in the following are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence.

[0048] Such as Figure 1As shown, the thin-film resistor TIN is isolated from M1, and the TIN on the upper electrode plate of the MIM capacitor cannot be utilized. A new TIN layer needs to be added as the thin-film resistor (TFR). Due to the large height difference between the TFR and the MIM, the etching of the contact vias above needs to be carried out step by step. After the etching of the contact via (MVTF) above the thin-film resistor, the etching of the contact via (MV1) on the MIM capacitor is carried out, and finally the deposition of the via filling is carried out together, followed by the subsequent chemical mechanical polishing (CMP).

[0049] However, during the etching process of the contact via (MV1) on the MIM capacitor, the photoresist will cover the previously formed MVTF. Since the size of the MVTF (0.5um) is large, the photoresist may drill into the MVTF and it is difficult to clean it up completely. In addition, during the photolithography etching process, MV1 OVL is aligned with M1, MVTF OVL is aligned with TFR, and MT OVL is aligned with MV1. There is a risk that the OVL between MT and MVTF may deviate greatly.

[0050] In view of this, the present invention provides an integrated passive device structure and a manufacturing method thereof. A barrier layer is formed on the thin-film resistor. During the etching process of the contact via, by using the high etching selectivity ratio between the barrier layer and the dielectric layer, the barrier layer is used as the etching barrier layer to simultaneously form the first contact via connecting the MIM capacitor and the second contact via connecting the thin-film resistor, thereby realizing the synchronous etching of the contact vias of the MIM capacitor and the thin-film resistor at different heights, reducing one photomask, simplifying the process, improving the process window, and reducing the production cost.

[0051] Figure 2 It is a schematic flow chart of a manufacturing method of an integrated passive device structure provided by an embodiment of the present invention. As Figure 2 shown, the manufacturing method of the integrated passive device structure provided by this embodiment includes the following steps:

[0052] Step S01: Provide a substrate and form a metal-insulator-metal capacitor on the substrate;

[0053] Step S02: Form a first dielectric layer that at least covers the metal-insulator-metal capacitor;

[0054] Step S03: Form a thin-film resistor on the surface of the first dielectric layer that is horizontally different from the position of the metal-insulator-metal capacitor and a barrier layer on the thin-film resistor;

[0055] Step S04: Form a second dielectric layer on the surface of the first dielectric layer, and the second dielectric layer covers the thin-film resistor and the barrier layer; and,

[0056] Step S05: Using the high etching selectivity between the materials of the first dielectric layer and the second dielectric layer and the material of the barrier layer, with the barrier layer as the etching barrier layer, etch the first dielectric layer and the second dielectric layer to simultaneously form a first contact via connecting the metal-insulator-metal capacitor and a second contact via connecting the thin film resistor.

[0057] Figures 3A to 3E FIG. is a schematic structural diagram formed by the steps corresponding to the manufacturing method of the integrated passive device structure in an embodiment of the present invention. Please refer to Figure 2 as shown, and in combination with Figures 3A to 3E , the manufacturing method of the integrated passive device structure provided by the present invention will be described in detail.

[0058] First, referring to Figure 3A as shown, perform step S01 to provide a substrate 100, and form a metal-insulator-metal (MIM) capacitor on the substrate 100.

[0059] The substrate 100 includes a high-resistivity silicon substrate (High-R Silicon Substrate), and a bottom dielectric layer (Pre-Metal Dielectric, PMD) 110 is formed on the substrate 100. The formation of the metal-insulator-metal capacitor includes: a first capacitive metal layer 101, a capacitive insulating layer 102, and a second capacitive metal layer 103 stacked from bottom to top on the bottom dielectric layer 110. Then, etch the second capacitive metal layer 103 and the capacitive insulating layer 102 to expose a part of the first capacitive insulating layer 101. Among them, the materials of the first capacitive metal layer 101 and the second capacitive metal layer 103 can be titanium (Ti), titanium nitride (TiN), aluminum (Al), tantalum nitride (TaN), etc., and the material of the capacitive insulating layer 102 includes a silicon nitride (SiN) layer and / or a silicon oxynitride (SiON).

[0060] Next, continue to refer to Figure 3A as shown, perform step S02 to form a first dielectric layer 120, and the first dielectric layer 120 at least covers the metal-insulator-metal capacitor.

[0061] The material of the first dielectric layer 120 includes silicon oxide, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, such as undoped silicon glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). The material of the first dielectric layer 120 may also include spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane doped with phosphorus (PTEOS), or tetraethoxysilane doped with boron (BTEOS).

[0062] After the first dielectric layer 120 is deposited as an inter-layer dielectric (ILD), it further includes a chemical mechanical polishing (CMP) process for the deposited first dielectric layer 120.

[0063] Next, referring to Figures 3B to 3C As shown, step S03 is performed to form a thin film resistor 104 on the surface of the first dielectric layer 120 that is horizontally different from the position of the metal-insulator-metal capacitor and a barrier layer 105 on the thin film resistor 104.

[0064] Specifically, the formation of the thin film resistor 104 and the barrier layer 105 includes:

[0065] A thin film resistor material layer 104a and a barrier material layer 105a are sequentially formed from bottom to top on the surface of the first dielectric layer 120;

[0066] The thin film resistor material layer 104a and the barrier material layer 105a are patterned to form a thin film resistor 104 and a barrier layer 105 that are horizontally different from the position of the metal-insulator-metal capacitor.

[0067] The thin film resistor 104 is made of any one of TiN, TiW, TaN, polysilicon material, or a combination thereof. The material of the barrier layer 105 can be silicon nitride (SIN) or other composite material layers based on nitrides / carbides. The thickness of the thin film resistor 104 is 800 Å to 1200 Å, for example, 1000 Å. The thickness of the barrier layer 105 is 900 Å to 1000 Å, for example, 960 Å. The height from the first capacitor metal layer 101 to the thin film resistor 104 is 8300 Å to 8700 Å, for example, 8500 Å.

[0068] Next, referring to Figure 3DAs shown, step S04 is performed to form a second dielectric layer 130 on the surface of the first dielectric layer 110, and the second dielectric layer 130 covers the thin film resistor 104 and the barrier layer 105.

[0069] After the second dielectric layer 130, which serves as an Inter-Metal Dielectric (IMD), is deposited, chemical mechanical polishing is carried out. After polishing, the thickness of the second dielectric layer 130 on the barrier layer 105 is 9000 angstroms to 13000 angstroms, for example, 11000 angstroms. The material of the second dielectric layer 130 can be the same as that of the first dielectric layer 120, such as silicon oxide, or other low-k (low dielectric constant) materials can also be selected.

[0070] Next, continue to refer to Figure 3D As shown, step S05 is performed to etch the first dielectric layer 120 and the second dielectric layer 130 to simultaneously form a first contact via 140 and a second contact via 150.

[0071] Specifically, by using the high etching selectivity between the materials of the first dielectric layer 120 and the second dielectric layer 130 and the material of the barrier layer 105, with the barrier layer 105 as the etching stop layer, the first dielectric layer 120 and the second dielectric layer 130 are etched to simultaneously form a first contact via 140 connecting the metal-insulator-metal capacitor and a second contact via 150 connecting the thin film resistor, thereby realizing the simultaneous etching of contact vias at different heights on the MIM capacitor and the thin film resistor.

[0072] Since the contact vias on the MIM capacitor and the thin film resistor at different heights are formed by simultaneous etching, compared with etching the MIM capacitor and the thin film resistor with different height distributions separately, one photomask layer is reduced, the process is simplified, and the production cost is reduced.

[0073] In addition, since the contact vias on the MIM capacitor and the thin film resistor are formed by simultaneous etching and are not etched separately due to the different height differences between them, the photoresist residue on the previously formed metal via is avoided. Moreover, the simultaneous formation of the contact vias on the MIM capacitor and the thin film resistor means that during the subsequent formation of the top metal layer, the OVL can only be aligned with one layer of contact vias, increasing the OVL window of the top metal layer for the contact vias and reducing the deviation risk of the OVL between the top metal and the contact vias on the thin film resistor.

[0074] Furthermore, referring to Figure 3E As shown, the manufacturing method of the integrated passive device structure provided in this embodiment further includes:

[0075] A top metal layer 106 is formed on the second dielectric layer 130, and the top metal layer 106 connects the first contact via 140 and the second contact via 150;

[0076] An insulating layer 107 is formed, and the insulating layer 107 covers the top and sidewalls of the top metal layer 106;

[0077] A passivation layer 108 is formed, and the passivation layer 108 covers the top and sidewalls of the insulating layer 107 and the second dielectric layer 130 between the intervals of the top metal layer 106.

[0078] The manufacturing method of the integrated passive device structure provided in this embodiment further includes integrating the integrated passive device structure in a radio frequency (RF) filter.

[0079] In this embodiment, a barrier layer is deposited on the thin film resistor. During the etching process of the contact via, by using the high etching selectivity between the barrier layer and the dielectric layer, with the barrier layer as the etching barrier layer, the first contact via connecting the MIM capacitor and the second contact via connecting the thin film resistor are synchronously formed, so as to realize the synchronous etching of the contact vias of the MIM capacitor and the thin film resistor at different heights, reduce one mask layer, simplify the process, improve the process window, and reduce the production cost.

[0080] The present invention also provides an integrated passive device structure, as Figure 3E shown, including:

[0081] A substrate 100 and a metal-insulator-metal capacitor;

[0082] A first dielectric layer 120, located on the substrate 100, covering the metal-insulator-metal capacitor;

[0083] A thin film resistor 104 and a barrier layer 105 located on the thin film resistor 104, the thin film resistor 104 is located on the first dielectric layer 120 and is horizontally different from the position where the metal-insulator-metal capacitor is located;

[0084] A second dielectric layer 130, located on the first dielectric layer 120, covering the thin film resistor 104 and the barrier layer 105;

[0085] A first contact via 140, connecting the metal-insulator-metal capacitor;

[0086] A second contact via 150, connecting the thin film resistor 104.

[0087] Specifically, the thin film resistor 104 is made of any one of TiN, TiW, TaN, polysilicon material, or a combination thereof. The material of the barrier layer 105 may be silicon nitride (SIN) or other composite material layers based on nitrides / carbides.

[0088] The metal-insulator-metal capacitor includes: a first capacitive metal layer 101, a capacitive insulating layer 102, and a second capacitive metal layer 103 stacked from bottom to top. Among them, there is an uncovered part of the first capacitive metal layer 101 that is not covered by the second capacitive metal layer and the capacitive insulating layer. The first contact via connects the second capacitive metal layer and the uncovered part of the first capacitive metal layer.

[0089] Furthermore, the integrated passive device structure provided in this embodiment further includes:

[0090] A top metal layer 106, spaced apart and distributed on the second dielectric layer 130, connecting the first contact via 140 and the second contact via 150;

[0091] An insulating layer 107, covering the top and sidewalls of the top metal layer 106;

[0092] A passivation layer 108, covering the top and sidewalls of the insulating layer 107 and the second dielectric layer 130 between the intervals of the top metal layer 106.

[0093] The integrated passive device structure provided in this embodiment is integrated in a radio frequency (RF) filter.

[0094] In summary, the present invention provides an integrated passive device structure and a manufacturing method thereof. A barrier layer is formed on the thin film resistor. During the etching process of the contact via, by using the high etching selectivity between the barrier layer and the dielectric layer, the barrier layer is used as an etching barrier layer to simultaneously form the first contact via connecting the MIM capacitor and the second contact via connecting the thin film resistor, thereby realizing the synchronous etching of the contact vias of the MIM capacitor and the thin film resistor at different heights, reducing one photomask, simplifying the process, improving the process window, and reducing the production cost.

[0095] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A manufacturing method of an integrated passive device structure, characterized in that Comprising: Providing a substrate, and forming a metal-insulator-metal capacitor on the substrate; Forming a first dielectric layer, the first dielectric layer at least covering the metal-insulator-metal capacitor; Forming a thin film resistor on the surface of the first dielectric layer, which is horizontally different from the position where the metal-insulator-metal capacitor is located, and a barrier layer on the thin film resistor; Forming a second dielectric layer on the surface of the first dielectric layer, the second dielectric layer covering the thin film resistor and the barrier layer; Utilizing the high etching selectivity between the materials of the first dielectric layer and the second dielectric layer and the material of the barrier layer, using the barrier layer as an etching barrier layer, etching the first dielectric layer and the second dielectric layer, and simultaneously forming a first contact via connecting the metal-insulator-metal capacitor and a second contact via connecting the thin film resistor.

2. The manufacturing method of the integrated passive device structure according to claim 1, wherein The barrier layer includes a silicon nitride layer.

3. The manufacturing method of the integrated passive device structure according to claim 1, wherein, The formation of the metal-insulator-metal capacitor includes: A first capacitive metal layer, a capacitive insulating layer, and a second capacitive metal layer stacked from bottom to top; Etching the second capacitive metal layer and the capacitive insulating layer to expose a part of the first capacitive insulating layer.

4. The manufacturing method of the integrated passive device structure according to claim 1, wherein The formation of the thin film resistor and the barrier layer includes: Sequentially forming a thin film resistor material layer and a barrier material layer from bottom to top on the surface of the first dielectric layer; Performing patterning on the thin film resistor material layer and the barrier material layer to form a thin film resistor and a barrier layer that are horizontally different from the position where the metal-insulator-metal capacitor is located.

5. The manufacturing method of the integrated passive device structure according to claim 1, wherein Further comprising: Forming a top metal layer on the second dielectric layer, the top metal layer connecting the first contact via and the second contact via; Forming an insulating layer, the insulating layer covering the top and side walls of the top metal layer; Forming a passivation layer, the passivation layer covering the top and side walls of the insulating layer and the second dielectric layer between the intervals of the top metal layer.

6. The manufacturing method of the integrated passive device structure according to claim 1, wherein The thickness of the thin film resistor is 800 angstroms to 1200 angstroms.

7. The manufacturing method of the integrated passive device structure according to claim 1, wherein The height from the first capacitive metal layer to the thin film resistor is 8300 angstroms to 8700 angstroms.

8. The manufacturing method of the integrated passive device structure according to claim 1, characterized in that The substrate includes a high-resistivity silicon substrate.

9. An integrated passive device structure, characterized in that, Comprising: A substrate and a metal-insulator-metal capacitor located on the substrate; A first dielectric layer, located on the substrate, covering the metal-insulator-metal capacitor; A thin film resistor and a barrier layer located on the thin film resistor, the thin film resistor being located on the first dielectric layer and being horizontally different from the position where the metal-insulator-metal capacitor is located; A second dielectric layer, located on the first dielectric layer, covering the thin film resistor and the barrier layer; A first contact via connecting the metal-insulator-metal capacitor; A second contact via connecting the thin film resistor.

10. The integrated passive device structure according to claim 9, wherein, The barrier layer includes a silicon nitride layer.

11. The integrated passive device structure according to claim 9, characterized in that, The metal-insulator-metal capacitor includes: a first capacitive metal layer, a capacitive insulating layer, and a second capacitive metal layer stacked from bottom to top. Among them, there is an uncovered part of the first capacitive metal layer not covered by the second capacitive metal layer and the capacitive insulating layer, and the first contact via connects the second capacitive metal layer and the uncovered part of the first capacitive metal layer.

12. The integrated passive device structure according to claim 9, wherein, It further includes: A top metal layer, which is distributed at intervals on the second dielectric layer and connects the first contact via and the second contact via; An insulating layer, which covers the top and side walls of the top metal layer; A passivation layer, which covers the top and side walls of the insulating layer and the second dielectric layer between the intervals of the top metal layer.

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