Semiconductor structure and forming method thereof, semiconductor device and electronic device

Abstract

The present disclosure provides a semiconductor structure and a method for forming the same, a semiconductor device, and an electronic device, wherein the method for forming the semiconductor structure includes: forming a drift region, the drift region being adjacent to a first region in a first direction, the first direction being parallel to the top surface of the drift region; forming a first gate, a second gate, and a first field dielectric layer, the first field dielectric layer covering the first region and the drift region, the first gate covering the first field dielectric layer above the first region, the second gate covering the first field dielectric layer above the drift region, the first gate being spaced apart from the second gate along the first direction; and forming a field plate, the field plate covering the first field dielectric layer, the field plate being spaced apart from the second gate, and being located on the side of the second gate away from the first gate in the first direction. The above technical solution can improve the reliability of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same, a semiconductor device, and an electronic device. Background Art

[0002] Compared with current-controlled power devices, voltage-controlled power devices control the operating current of the device by controlling the gate voltage. At the same time, as majority-carrier devices, they are not affected by the minority-carrier storage effect and have a switching speed much faster than that of current-controlled devices. They can be used in high-frequency environments.

[0003] However, existing voltage-controlled power devices have poor electrical performance.

[0004] Therefore, how to provide a technical solution to improve the electrical performance of voltage-controlled power devices has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, a semiconductor device, and an electronic device, which can improve the reliability of the semiconductor structure.

[0006] To solve the above technical problems, the present disclosure provides a method for forming a semiconductor structure, comprising:

[0007] forming a drift region, wherein the drift region is disposed adjacent to the first region in a first direction, and the first direction is parallel to a top surface of the drift region;

[0008] forming a first gate, a second gate, and a first field dielectric layer, wherein the first field dielectric layer covers the first region and the drift region, the first gate covers the first field dielectric layer above the first region, the second gate covers the first field dielectric layer above the drift region, and the first gate is spaced apart from the second gate along the first direction;

[0009] A field plate is formed, wherein the field plate covers the first field dielectric layer, is spaced apart from the second gate, and is located on a side of the second gate away from the first gate in the first direction.

[0010] Optionally, the semiconductor structure satisfies one or more of the following conditions:

[0011] The second gate includes a gate body and a plurality of gate extensions, the gate body extending along a second direction, the gate extensions being spaced apart in the second direction, one end of each gate extension being connected to the gate body, and the other end of each gate extension being extended along the first direction, the second direction being parallel to the top surface of the drift region and perpendicular to the first direction;

[0012] The field plate includes a field plate body and a plurality of field plate extensions, wherein the field plate body extends along the second direction, the field plate extensions are arranged at intervals in the second direction, and one end of each field plate extension is connected to the field plate body, and the other end extends along the first direction;

[0013] The gate extension is located between the gate body and the field plate body;

[0014] The field plate extension is located between the gate body and the field plate body;

[0015] The field plate extensions are alternately arranged with each other in the second direction.

[0016] Optionally, adjacent gate extensions have different lengths in the first direction;

[0017] The lengths of adjacent field plate extensions in the first direction are different.

[0018] Optionally, before forming the field plate, the method further comprises the following steps:

[0019] forming a second field dielectric layer, wherein the second field dielectric layer covers a top surface of the first field dielectric layer between the first gate and the second gate, a surface of the second gate, and a top surface of the first field dielectric layer located on a side of the second gate away from the first gate in the first direction;

[0020] The field plate covering the first field dielectric layer includes the field plate covering the second field dielectric layer above the first field dielectric layer.

[0021] Optionally, the first field dielectric layer is formed by a thermal oxidation process;

[0022] The second field dielectric layer is formed by a low temperature deposition process.

[0023] Optionally, before forming the second field dielectric layer, the method further comprises the following steps:

[0024] forming a body region, wherein a doping type of the body region is different from a doping type of the drift region, and the body region is disposed adjacent to the first region in the first direction and located on a side of the first region away from the drift region;

[0025] Annealing is performed on the semiconductor structure to allow the body region to diffuse into the first region until it adjoins the drift region.

[0026] Optionally, before forming the second field dielectric layer, the method further comprises the following steps:

[0027] forming a source region and a drain region, wherein the source region is located in the body region and has a doping type different from that of the body region, and the drain region is located in the drift region and has a doping type consistent with that of the drift region;

[0028] An extraction region is formed, wherein the extraction region is located in the source region and adjacent to the body region, the doping type of the extraction region is consistent with the doping type of the body region, and the doping concentration of the extraction region is greater than the doping concentration of the body region.

[0029] The present disclosure also provides a semiconductor structure, including:

[0030] drift zone;

[0031] a body region, wherein the drift region is disposed adjacent to the body region in a first direction, a doping type of the drift region is different from a doping type of the body region, and the first direction is parallel to a top surface of the drift region;

[0032] a first field dielectric layer, wherein the first field dielectric layer covers the body region and the drift region;

[0033] a first gate, wherein the first gate covers the first field dielectric layer above a portion of the body region adjacent to the drift region in a first direction;

[0034] a second gate, wherein the second gate covers the first field dielectric layer above the drift region, and the second gate is spaced apart from the first gate along the first direction;

[0035] A field plate, wherein the field plate covers the first field dielectric layer, is spaced apart from the second gate, and is located on a side of the second gate away from the first gate in the first direction.

[0036] Optionally, the semiconductor structure satisfies one or more of the following conditions:

[0037] The second gate includes a gate body and a plurality of gate extensions, the gate body extending along a second direction, the gate extensions being spaced apart in the second direction, one end of each gate extension being connected to the gate body, and the other end of each gate extension being extended along the first direction, the second direction being parallel to the top surface of the drift region and perpendicular to the first direction;

[0038] The field plate includes a field plate body and a plurality of field plate extensions, wherein the field plate body extends along the second direction, the field plate extensions are arranged at intervals in the second direction, and one end of each field plate extension is connected to the field plate body, and the other end extends along the first direction;

[0039] The gate extension is located between the gate body and the field plate body;

[0040] The field plate extension is located between the gate body and the field plate body;

[0041] The field plate extensions are alternately arranged with each other in the second direction.

[0042] Optionally, the lengths of adjacent field plate extensions in the first direction are different;

[0043] The lengths of adjacent field plate extensions in the first direction are different.

[0044] Optionally, the semiconductor structure further includes:

[0045] a source region, wherein the source region is located within the body region, and a doping type of the source region is different from a doping type of the body region;

[0046] a drain region, wherein the drain region is located in the drift region, and a doping type of the drain region is consistent with a doping type of the drift region;

[0047] an extraction region, wherein the extraction region is located within the source region and adjacent to the body region, a doping type of the extraction region is consistent with a doping type of the body region, and a doping concentration of the extraction region is greater than a doping concentration of the body region;

[0048] a second field dielectric layer, wherein the second field dielectric layer covers a top surface of the first field dielectric layer between the first gate and the second gate and a surface of the second gate, and further covers a top surface of the first field dielectric layer located on a side of the second gate away from the first gate in the first direction;

[0049] The field plate covering the first field dielectric layer includes the field plate covering the second field dielectric layer above the first field dielectric layer.

[0050] Optionally, the first field dielectric layer is formed by a thermal oxidation process;

[0051] The second field dielectric layer is formed by a low-temperature deposition process.

[0052] An embodiment of the present disclosure also provides a semiconductor device, comprising the semiconductor structure described in any of the aforementioned examples.

[0053] An embodiment of the present disclosure also provides an electronic device, comprising the semiconductor device described in any of the aforementioned examples.

[0054] Compared with the prior art, the technical solution of the embodiment of the present disclosure has the following beneficial effects:

[0055] On the first aspect, compared with the semiconductor structure in which only the first gate is set, the first gate and the second gate in this solution are arranged at intervals along the first direction, which can increase the total length of the gate along the first direction, thereby increasing the proportion of the area modulated by the gate in the semiconductor structure, and further improving the voltage resistance performance of LDMOS.

[0056] On the second aspect, compared to the capacitance formed between the first gate and its covering area and the capacitance formed between the second gate and its covering area when the first gate and the second gate are connected along the first direction, in this solution, the first gate and the second gate are spaced apart along the first direction, and the capacitance formed between the first gate and its covering area and the capacitance formed between the second gate and its covering area are independent of each other. The switching frequency of the semiconductor structure of this solution depends on the minimum value of the frequency of the charge discharge of the capacitor corresponding to the first gate and the frequency of the charge discharge of the capacitor corresponding to the second gate. In this solution, the frequency of the charge discharge of the capacitor corresponding to the first gate and the frequency of the charge discharge of the capacitor corresponding to the second gate are both higher than the frequency of the charge discharge of the corresponding capacitor when the first gate and the second gate are connected, which means that the switching frequency of the semiconductor structure of this solution is greater than the switching frequency of the semiconductor structure in which the first gate and the second gate are connected along the first direction. Therefore, the above technical solution can improve the switching frequency of the semiconductor structure.

[0057] In summary, the technical solution of the embodiment of the present disclosure can take into account both the voltage resistance performance and the switching frequency of LDMOS, and improve the reliability of LDMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the following briefly introduces the drawings required for use in the embodiments of this specification or the description of the prior art. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0059] Figure 1 A flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure is shown;

[0060] Figures 2 to 5 A schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present disclosure is shown;

[0061] Figure 6 A top view of a semiconductor structure in an embodiment of the present disclosure is shown.

[0062] Description of reference numerals:

[0063] Substrate 100, drift region 110, body region 120, source region 130, drain region 140, extraction region 150;

[0064] A first field dielectric material layer 200 and a first field dielectric layer 210 .

[0065] Gate material layer 300 , first gate 310 , second gate 320 , gate body 321 , gate extension 322 ;

[0066] Second field dielectric layer 400;

[0067] Field plate 500, field plate body 510, field plate extension 520;

[0068] First direction F1, second direction F2. DETAILED DESCRIPTION

[0069] As mentioned above, in the structural design of voltage-controlled power devices, it is necessary to improve the reliability of the devices.

[0070] Taking a laterally diffused metal-oxide-semiconductor (LDMOS) device as an example, the LDMOS has a body region, a drift region, and a gate, wherein the gate covers part of the body region and the drift region.

[0071] The gate length is related to the voltage withstand performance of the LDMOS. For example, the gate modulates the electric field distribution on the surface of its footprint. Increasing the gate length increases the gate footprint, increasing the modulated area within the drift region and improving the voltage withstand performance of the LDMOS.

[0072] Gate length is associated with a reduction in LDMOS switching frequency. For example, capacitance is formed between the gate and the underlying body and drift regions. Increasing the gate length increases the amount of charge stored in this capacitance, increasing the period it takes to discharge the charge, reducing the LDMOS switching frequency and ultimately decreasing its reliability.

[0073] How to balance the voltage resistance and switching frequency of LDMOS and improve the reliability of LDMOS is an urgent problem to be solved.

[0074] In order to solve the above technical problems, an embodiment of the present disclosure provides a method for forming a semiconductor structure, including: forming a drift region, wherein the drift region is arranged adjacent to the first region in a first direction, and the first direction is parallel to the top surface of the drift region; forming a first gate, a second gate and a first field dielectric layer, wherein the first field dielectric layer covers the body region and the drift region, the first gate covers the first field dielectric layer above the first region, the second gate covers the first field dielectric layer above the drift region, and the first gate is spaced apart from the second gate along the first direction; forming a field plate, wherein the field plate covers the first field dielectric layer, the field plate is spaced apart from the second gate, and is located on the side of the second gate away from the first gate in the first direction.

[0075] The technical solution of the embodiment of the present disclosure has the following beneficial effects:

[0076] On the first aspect, compared with the semiconductor structure in which only the first gate is set, the first gate and the second gate in this solution are arranged at intervals along the first direction, which can increase the total length of the gate along the first direction, thereby increasing the proportion of the area modulated by the gate in the semiconductor structure, and further improving the voltage resistance performance of LDMOS.

[0077] On the second aspect, compared to the capacitance formed between the first gate and its covering area and the capacitance formed between the second gate and its covering area when the first gate and the second gate are connected along the first direction, in this solution, the first gate and the second gate are spaced apart along the first direction, and the capacitance formed between the first gate and its covering area and the capacitance formed between the second gate and its covering area are independent of each other. The switching frequency of the semiconductor structure of this solution depends on the minimum value of the frequency of the charge discharge of the capacitor corresponding to the first gate and the frequency of the charge discharge of the capacitor corresponding to the second gate. In this solution, the frequency of the charge discharge of the capacitor corresponding to the first gate and the frequency of the charge discharge of the capacitor corresponding to the second gate are both higher than the frequency of the charge discharge of the corresponding capacitor when the first gate and the second gate are connected, which means that the switching frequency of the semiconductor structure of this solution is greater than the switching frequency of the semiconductor structure in which the first gate and the second gate are connected along the first direction. Therefore, the above technical solution can improve the switching frequency of the semiconductor structure.

[0078] In summary, the technical solution of the embodiment of the present disclosure can take into account both the voltage resistance performance and the switching frequency of LDMOS, and improve the reliability of LDMOS.

[0079] In order to make the above-mentioned objectives, features and beneficial effects of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0080] Reference Figure 1 , Figure 1Flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. The method for forming a semiconductor structure may include steps S11 to S13:

[0081] Step S11: forming a drift region and a first region, wherein the drift region is disposed adjacent to the first region in a first direction, and the first direction is parallel to a top surface of the drift region;

[0082] Step S12: forming a first gate, a second gate, and a first field dielectric layer, wherein the first field dielectric layer covers the body region and the drift region, the first gate covers the first field dielectric layer above the first region, the second gate covers the first field dielectric layer above the drift region, and the first gate is spaced apart from the second gate along the first direction;

[0083] Step S13: forming a field plate, wherein the field plate covers the first field dielectric layer, is spaced apart from the second gate, and is located on a side of the second gate away from the first gate in the first direction.

[0084] The following combination Figures 2 to 6 The above-mentioned formation method will be explained.

[0085] Figures 2 to 5 It is a schematic diagram of the cross-sectional structure corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0086] Reference Figure 2 , providing a substrate 100.

[0087] The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.

[0088] The substrate 100 may be a silicon substrate, or the material of the substrate 100 may also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate on which an epitaxial layer (Epitaxylayer, Epilayer) is grown.

[0089] In some embodiments, the substrate 100 may have a first region (not shown in the figures), wherein the first region is used as a diffusion region for the body region 120 and the drift region 110 in subsequent processes.

[0090] In some embodiments, an isolation ring is formed on the substrate 100 .

[0091] Specifically, the step of forming the isolation ring may include: etching the surface of the substrate 100 to form an isolation ring groove; and filling the isolation ring groove to form the isolation ring. The isolation ring is a ring-shaped structure that can achieve electrical isolation between the inner structure and the outer structure of the ring.

[0092] In some embodiments, the material of the isolation ring may be silicon dioxide.

[0093] A drift region 110 is formed in the substrate 100 .

[0094] The drift region 110 may be disposed adjacent to the first area in a first direction F1 , and the first direction F1 is parallel to the surface of the substrate 100 , for example, the first direction F1 is parallel to the top surface of the drift region 110 .

[0095] In some embodiments, the drift region 110 may be formed in the isolation ring by an ion implantation process.

[0096] In some embodiments, the doping type of the drift region 110 may be N-type doping or P-type doping.

[0097] It should be noted that, in the following description, N-type doping may be used as an example for illustration, but this does not constitute a limitation on the specific doping type used in the drift region 110 .

[0098] Continue to refer to Figure 2 , a first field dielectric material layer 200 is formed on the substrate 100 .

[0099] The process for forming the first field dielectric material layer 200 includes a thermal oxidation process. The process temperature of the thermal oxidation process is much higher than that of the low-temperature deposition process. Compared with the low-temperature deposition process, the interface between the first field dielectric material layer 200 and the substrate 100 formed by the thermal oxidation process has advantages such as lower interface state, lower interface defect density, and higher interface quality.

[0100] In some embodiments, the first field dielectric material layer 200 may be a silicon dioxide layer.

[0101] Continue to refer to Figure 2 , forming a gate material layer 300 . The gate material layer 300 covers the first field dielectric material layer 200 .

[0102] In some embodiments, the gate material layer 300 may be formed using a low-temperature deposition process, such as plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). Compared to thermal oxidation, the redistribution of doping concentration within the drift region 110 during the formation of the gate material layer 300 using a low-temperature deposition process is negligible.

[0103] In some embodiments, the gate material layer 300 may be a polysilicon layer, a metal layer, or a metal-silicide layer.

[0104] Reference Figure 2 and Figure 3 , forming a first gate 310 , a second gate 320 and a first field dielectric layer 210 .

[0105] The first field dielectric layer 210 covers the first region and the drift region 110 , the first gate 310 covers the first field dielectric layer 210 above the first region, the second gate 320 covers the first field dielectric layer 210 above the drift region 110 , and the first gate 310 is spaced apart from the second gate 320 along the first direction F1 .

[0106] In some embodiments, forming the first gate 310, the second gate 320 and the first field dielectric layer 210 may include the following steps: forming a patterned first mask layer, the first mask layer covering a partial surface area of ​​the gate dielectric material layer; using the first mask layer as a mask, removing other gate material layers 300 outside the area covered by the first mask layer to obtain the first gate 310 and the second gate 320; forming a patterned second mask layer, the second mask layer covering a partial surface area of ​​the first field dielectric material layer 200, the surface of the first gate 310 and the surface of the second gate 320; using the second mask layer as a mask, removing other first field dielectric material layers 200 outside the area covered by the second mask layer to obtain the first field dielectric layer 210.

[0107] It is understood that the thickness of the first gate 310 and the thickness of the second gate 320 formed by etching the gate material layer 300 are both consistent with the thickness of the gate material layer 300. The thickness of the first field dielectric layer 210 formed by etching the first field dielectric material layer 200 is consistent with the thickness of the first field dielectric material layer 200.

[0108] It should be noted that the first field dielectric layer 210 covered by the first gate 310 serves as the gate dielectric layer of the first gate 310. The first gate 310, the first field dielectric layer 210 covered by the first gate 310, the body region 120 covered by the first gate 310, and the drift region 110 form a capacitor structure corresponding to the first gate 310. The first field dielectric layer 210 covered by the second gate 320 serves as the gate dielectric layer of the second gate 320. The second gate 320, the first field dielectric layer 210 covered by the second gate 320, and the drift region 110 covered by the second gate 320 form a capacitor structure corresponding to the second gate 320.

[0109] It can be understood that the gate dielectric layer used as the first gate 310 and the first field dielectric layer 210 used as the gate dielectric layer of the second gate 320 and the remaining first field dielectric layers 210 are continuous structures formed in the same process, and the electrical characteristics on both sides of the adjacent interfaces are continuously distributed, so the adjacent interfaces will not cause electric field spikes at the corresponding positions of the substrate 100.

[0110] Figure 6 A top view of a semiconductor structure in an embodiment of the present disclosure is shown.

[0111] In some embodiments, reference Figure 6 The first gate 310 may extend along a second direction F2, wherein the second direction F2 is parallel to the top surface of the drift region 110 and perpendicular to the first direction F1.

[0112] It should be noted that the number of first gates 310 is not limited to one. In other examples, the number of first gates 310 can be multiple, for example two, and the first gates 310 are arranged at intervals along the first direction F1 and are all located on the same side of the second gate 320 in the first direction F1.

[0113] In some embodiments, continue to refer to Figure 6 The second gate 320 (the area surrounded by the dotted line in the figure) can include a gate body 321 and multiple gate extensions 322. The gate body 321 can be connected to an external electrode. Each gate extension 322 has one end connected to the gate body 321 and the other end extending along the first direction F1. In this way, the potential of each gate extension 322 is consistent with that of the gate body 321.

[0114] In some embodiments, continue to refer to Figure 6 The gate body 321 extends along the second direction F2, and the gate extensions 322 are arranged at intervals in the second direction F2. First, the edges of the gate extensions 322 in the second direction F2 can introduce more electric field peaks spaced along the second direction F2 on the surface of the drift region 110, thereby optimizing the lateral electric field distribution on the surface of the drift region 110 in the second direction F2 and improving the voltage resistance of the semiconductor structure. Second, compared to a plurality of gate extensions 322 connected in the second direction F2, the second gate 320 formed by the gate body 321 and the plurality of gate extensions 322 in this solution is a comb-like structure, which can reduce the coverage area of ​​the second gate 320, thereby reducing the amount of charge stored in the corresponding capacitor, reducing the time it takes for the capacitor to discharge the charge, and improving the switching frequency of the semiconductor structure. Third, it can disperse the conduction channel and the carrier transport path, thereby improving the thermal reliability of the semiconductor structure.

[0115] In some embodiments, continue to refer to Figure 6 Adjacent gate extensions 322 have different lengths along the first direction F1. This can increase the distance between the edges of adjacent gate extensions 322 in the first direction F1, thereby reducing the superimposed electric field strength of adjacent gate extensions 322 at the edges of the gate extensions 322 along the first direction F1, thereby further optimizing the lateral electric field distribution on the surface of the drift region 110 and improving the withstand voltage performance of the semiconductor structure.

[0116] In other examples, the lengths of the gate extensions 322 along the first direction F1 may also be the same.

[0117] Reference Figure 3 and Figure 4 , forming the body region 120.

[0118] The doping type of the body region 120 is different from that of the drift region 110 . The body region 120 is adjacent to the first region in the first direction F1 and is located on a side of the first region away from the drift region 110 .

[0119] In some embodiments, forming the body region 120 may include the steps of: forming a patterned third mask layer, the third mask layer exposing a portion of the substrate 100 adjacent to the first region, and the portion of the substrate 100 is located on the side of the first region away from the drift region 110; using the third mask layer as a mask, doping the portion of the substrate 100 exposed by the third mask layer to obtain the body region 120.

[0120] In some embodiments, after forming the body region 120 , the step of annealing the semiconductor structure may be further included to diffuse both the body region 120 and the drift region 110 toward the first region until the diffused body region 120 is adjacent to the drift region 110 .

[0121] It should be pointed out that if Figure 4 As shown, after annealing, the interface between the body region 120 and the drift region 110 is located between the two side edges of the first gate 310 in the first direction F1. This can improve the problem of premature breakdown or hot carrier effect caused by excessive local electric field in the semiconductor structure due to the overlap of the electric field spike introduced by the interface between the body region 120 and the drift region 110 and the electric field spike introduced by the edge of the first gate 310 on the surface of the drift region 110.

[0122] Continue to refer to Figure 4 , forming a source region 130 and a drain region 140.

[0123] The source region 130 is located in the body region 120 , and the doping type of the source region 130 is different from that of the body region 120 . The drain region 140 is located in the drift region 110 , and the doping type of the drain region 140 is consistent with that of the drift region 110 .

[0124] Continue to refer to Figure 4 , forming an extraction area 150.

[0125] The extraction region 150 is located within the source region 130 and adjacent to the body region 120. The doping type of the extraction region 150 is consistent with the doping type of the body region 120, and the doping concentration of the extraction region 150 is greater than the doping concentration of the body region 120. The extraction region 150 extracts the charge accumulated in the body region 120 by applying an external potential, thereby stabilizing the potential of the body region 120.

[0126] Reference Figure 5 , forming a second field dielectric layer 400.

[0127] The second field dielectric layer 400 conformally covers the top surface of the first field dielectric layer 210 between the first gate 310 and the second gate 320, the surface of the second gate 320, and the top surface of the first field dielectric layer 210 on the side of the second gate 320 away from the first gate 310 in the first direction F1.

[0128] In some embodiments, forming the second field dielectric layer 400 may include the steps of: forming a patterned fourth mask layer, the fourth mask layer exposing the top surface of the first field dielectric layer 210 between the first gate 310 and the second gate 320, the surface of the second gate 320, and the top surface of the first field dielectric layer 210 located on the side of the second gate 320 away from the first gate 310 in the first direction F1; using the fourth mask layer as a mask, depositing the area exposed by the fourth mask layer to obtain the second field dielectric layer 400.

[0129] In some embodiments, a low temperature deposition process can be used to form the second field dielectric layer 400. Compared to a thermal oxidation process, the low temperature deposition process has a negligible effect on the redistribution of doping concentrations in the doped regions within the substrate 100.

[0130] In some embodiments, the thickness of the second field dielectric layer 400 is greater than the thickness of the first field dielectric layer 210 .

[0131] In some embodiments, the second field dielectric layer 400 may be a silicon dioxide layer.

[0132] It should be pointed out that the first field dielectric layer 210 and the second field dielectric layer 400 are both used to form the final field dielectric layer. Compared with directly forming the final dielectric layer by a thermal oxidation process or directly forming the final dielectric layer by a low-temperature deposition process, in the embodiment of the present disclosure, a thermal oxidation process is first used to obtain the first field dielectric layer 210, and then a low-temperature deposition process is used to obtain the second field dielectric layer 400 to form the final field dielectric layer. In this way, a balance can be achieved between reducing the "interface defect density between the field dielectric layer and the drift region 110" and reducing the "redistribution effect of the doping concentration in each doping region in the substrate 100 during the formation of the field dielectric layer."

[0133] It should be noted that the first field dielectric layer 210 and the second field dielectric layer 400 are formed successively using different processes. The different process temperature differences lead to a large number of defects at the interface between the first field dielectric layer 210 and the second field dielectric layer 400. These defects will capture and accumulate carriers, causing the threshold voltage to drift.

[0134] In some embodiments, after forming the second field dielectric layer 400 , the process may further include annealing the semiconductor structure.

[0135] This can promote atomic diffusion at the interface between the first field dielectric layer 210 and the second field dielectric layer 400, thereby reducing the amount of defects at the interface, thereby reducing the amount of carriers captured and accumulated at the interface between the first field dielectric layer 210 and the second field dielectric layer 400, and further reducing the drift of the threshold voltage.

[0136] It should be noted that in order to simplify the process steps, in other examples, the annealing step after forming the body region 120 and before forming the source region 130 and the drain region 140 can be omitted. Through the annealing step after forming the second field dielectric layer 400, the body region 120 and the drift region 110 are both diffused into the first region until the diffused body region 120 is adjacent to the drift region 110.

[0137] Continue to refer to Figure 5 , forming a field plate 500 .

[0138] The field plate covers the first field dielectric layer 210, is spaced apart from the second gate 320, and is located on a side of the second gate 320 away from the first gate 310 in the first direction F1. It should be noted that the field plate covering the first field dielectric layer 210 means that the field plate covers the second field dielectric layer 400 above the first field dielectric layer 210.

[0139] The field plate 500 can be connected to an external electrode. By connecting to the external electrode, the field plate 500 can form an electric field perpendicular to the top surface of the substrate 100. This electric field can disperse the carriers captured and accumulated at the interface between the first field dielectric layer 210 and the second field dielectric layer 400, thereby reducing the drift of the threshold voltage.

[0140] In addition, the field plate 500 can also introduce a fixed potential by connecting to an external electrode, thereby preventing the first field dielectric layer 210 and the second field dielectric layer 400 from introducing a random potential due to a floating effect, ensuring that the first field dielectric layer 210 and the second field dielectric layer 400 are at a fixed potential, thereby stabilizing the lateral electric field distribution in the drift region 110.

[0141] In some embodiments, forming the field plate 500 may include the steps of: forming a patterned fifth mask layer, the fifth mask layer covering a partial surface area of ​​the second field dielectric layer 400; using the fifth mask layer as a mask, depositing the area exposed by the fifth mask layer to obtain the field plate 500.

[0142] In some embodiments, reference Figure 5 and Figure 6The field plate 500 may include: a field plate body 510 and a plurality of field plate extensions 520, wherein the field plate body 510 may be connected to an external electrode, one end of each field plate extension 520 is respectively connected to the field plate body 510, and the other end thereof extends along the first direction F1. In this way, the potential of each field plate extension 520 is consistent with that of the field plate body 510. The field plate body 510 extends along the second direction F2, and the field plate extensions 520 are arranged at intervals in the second direction F2. In this way, the edges of each field plate extension 520 in the second direction F2 can introduce more electric field spikes spaced along the second direction F2 on the surface of the drift region 110, thereby optimizing the lateral electric field distribution on the surface of the drift region 110 in the second direction F2 and improving the withstand voltage performance of the semiconductor structure.

[0143] In some embodiments, continue to refer to Figure 6 Adjacent field plate extensions 520 have different lengths along the first direction F1. This can increase the distance between the edges of adjacent field plate extensions 520 in the first direction F1, thereby reducing the superimposed electric field strength of adjacent field plate extensions 520 at the edges of the field plate extensions 520 along the first direction F1. This can further optimize the lateral electric field distribution on the surface of the drift region 110 and enhance the withstand voltage performance of the semiconductor structure.

[0144] In other examples, the lengths of the field plate extensions 520 along the first direction F1 may also be the same.

[0145] In some embodiments, continue to refer to Figure 6 , each gate extension 322 is located between the gate body 321 and the field plate body 510, and each field plate extension 520 is located between the gate body 321 and the field plate body 510; each field plate extension 520 and each field plate extension 520 are alternately arranged in the second direction F2.

[0146] Compared with the situation where the projections of the field plate and the second gate 320 on the projection plane perpendicular to the second direction F2 have no overlapping area, the projections of the field plate extension 520 and the gate extension 322 have an overlapping area. Therefore, the field plate extension 520 located between the two field plate extensions 520 along the second direction F2 can modulate the electric field distribution on the surface of the drift region 110 between the two field plate extensions 520. On the one hand, this can enhance the independence of the conduction channel between the two gate extensions 322 in the second direction F2 and further disperse the carrier transport path; on the other hand, it can reduce the on-resistance of the drift region 110 between the two gate extensions 322.

[0147] In some embodiments, the semiconductor structure may be an LDMOS device, which includes a semiconductor unit, wherein the semiconductor unit may include a drift region 110, a body region 120, a source region 130, a drain region 140, an extraction region 150, a first gate 310, a second gate 320, a first field dielectric layer 210, a second field dielectric layer 400, and a field plate.

[0148] Furthermore, the semiconductor structure may be a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The two symmetrical semiconductor units share the same body region 120 , source region 130 , and extraction region 150 .

[0149] Specifically, sharing the same body region 120 , source region 130 , and extraction region 150 can improve the current driving capability of the LDMOS device, while also simplifying the layout and improving the integration of the device.

[0150] It should be noted that, in addition to the shared body region 120, source region 130, and extraction region 150, each semiconductor unit in the symmetric LDMOS device may have its own drift region 110, drain region 140, first gate 310, second gate 320, first field dielectric layer 210, second field dielectric layer 400, and field plate, and the above-mentioned parts may be completely consistent or not completely consistent.

[0151] In the embodiment of the present disclosure, a semiconductor structure is further provided, referring to Figure 5 and Figure 6 The semiconductor structure may include: a drift region 110, a body region 120, a first field dielectric layer 210, a first gate 310, a second gate 320, and a field plate 500; wherein the drift region 110 is adjacent to the body region 120 in a first direction F1, the doping type of the drift region 110 is different from the doping type of the body region 120, and the first direction F1 is parallel to the top surface of the drift region 110; the first field dielectric layer 210 covers the body region 120 and the drift region 110; the first gate 310 covers the first field dielectric layer 210 above a portion of the body region 120 adjacent to the drift region 110 in the first direction F1; the second gate 320 covers the first field dielectric layer 210 above the drift region 110, and is spaced apart from the first gate 310 along the first direction F1; the field plate 500 covers the first field dielectric layer 210, is spaced apart from the second gate 320, and is located on a side of the second gate 320 away from the first gate 310 in the first direction F1.

[0152] In some embodiments, the first gate 310 extends along a second direction F2 , wherein the second direction F2 is parallel to the top surface of the drift region 110 and perpendicular to the first direction F1 .

[0153] In some embodiments, the second gate 320 includes a gate body 321 and a plurality of gate extensions 322. The gate body 321 extends along the second direction F2, and the gate extensions 322 are arranged at intervals along the second direction F2. One end of each gate extension 322 is connected to the gate body 321, and the other end extends along the first direction F1.

[0154] In some embodiments, the field plate 500 includes a field plate body 510 and multiple field plate extensions 520. The field plate body 510 extends along the second direction F2, and the field plate extensions 520 are arranged at intervals in the second direction F2. One end of each field plate extension 520 is respectively connected to the field plate body 510, and the other end extends along the first direction F1.

[0155] In some embodiments, the gate extension 322 is located between the gate body 321 and the field plate body 510; the field plate extension 520 is located between the gate body 321 and the field plate body 510; and each field plate extension 520 is alternately arranged in the second direction F2.

[0156] In some embodiments, the lengths of adjacent field plate extensions 520 in the first direction F1 are different; the lengths of adjacent field plate extensions 520 in the first direction F1 are different.

[0157] In some embodiments, the semiconductor structure further includes: a source region 130, a drain region 140, an extraction region 150 and a second field dielectric layer 400, wherein the source region 130 is located in the body region 120, and the doping type of the source region 130 is different from the doping type of the body region 120; the drain region 140 is located in the drift region 110, and the doping type of the drain region 140 is consistent with the doping type of the drift region 110; the extraction region 150 is located in the source region 130 and adjacent to the body region 120, the doping type of the extraction region 150 is consistent with the doping type of the body region 120, and the doping concentration of the extraction region 150 is greater than the doping concentration of the body region 120; the second field dielectric layer 400 covers the top surface of the first field dielectric layer 210 between the first gate 310 and the second gate 320 and the surface of the second gate 320, and also covers the top surface of the first field dielectric layer 210 located on the side of the second gate 320 away from the first gate 310 in the first direction F1.

[0158] It should be noted that the field plate 500 covering the first field dielectric layer 210 includes the field plate 500 covering the second field dielectric layer 400 above the first field dielectric layer 210 .

[0159] In some embodiments, the first field dielectric layer 210 is formed by a thermal oxidation process, and the second field dielectric layer 400 is formed by a low-temperature deposition process.

[0160] In some embodiments, the semiconductor structure may be an LDMOS device, which includes a semiconductor unit, wherein the semiconductor unit may include a drift region 110, a body region 120, a source region 130, a drain region 140, an extraction region 150, a first gate 310, a second gate 320, a first field dielectric layer 210, a second field dielectric layer 400, and a field plate.

[0161] Furthermore, the semiconductor structure may be a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The two symmetrical semiconductor units share the same body region 120 , source region 130 , and extraction region 150 .

[0162] Specifically, sharing the same body region 120 , source region 130 , and extraction region 150 can improve the current driving capability of the LDMOS device, while also simplifying the layout and improving the integration of the device.

[0163] It should be noted that, in addition to the shared body region 120, source region 130, and extraction region 150, each semiconductor unit in the symmetric LDMOS device may have its own drift region 110, drain region 140, first gate 310, second gate 320, first field dielectric layer 210, second field dielectric layer 400, and field plate, and the above-mentioned parts may be completely consistent or not completely consistent.

[0164] It should be noted that for the principle, specific implementation and beneficial effects of the semiconductor structure, please refer to the previous article and Figures 2 to 6 The description of the method for forming the semiconductor structure is not repeated here.

[0165] In an embodiment of the present disclosure, a semiconductor device is further provided, comprising the semiconductor structure in any of the aforementioned examples.

[0166] In an embodiment of the present disclosure, an electronic device is also provided, comprising the semiconductor device in any of the aforementioned examples.

[0167] It should be understood that the term "and / or" in this document simply describes an association relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, the character " / " in this document indicates that the related objects are in an "or" relationship.

[0168] It is understood that the term "multiple" as used herein refers to two or more. The terms "first," "second," and so on, appearing in the embodiments of this application are for illustrative purposes only and are intended to distinguish the objects being described. They are not in any particular order and do not represent a specific limit on the number of devices in the embodiments of this application. They do not constitute any limitation on the embodiments of this application.

[0169] It can be understood that the above describes multiple embodiment schemes provided by the embodiments of the present disclosure. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and disclosed by the present disclosure.

[0170] Although the embodiments of the present disclosure are disclosed above, the present disclosure is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming a drift region, wherein the drift region is disposed adjacent to the first region in a first direction, and the first direction is parallel to a top surface of the drift region; forming a first gate, a second gate, and a first field dielectric layer, wherein the first field dielectric layer covers the first region and the drift region, the first gate covers the first field dielectric layer above the first region, the second gate covers the first field dielectric layer above the drift region, and the first gate is spaced apart from the second gate along the first direction; forming a field plate, wherein the field plate covers the first field dielectric layer, the field plate is spaced apart from the second gate, and is located on a side of the second gate away from the first gate in the first direction; The second gate includes a gate body and a plurality of gate extensions, the gate body extends along a second direction, the gate extensions are spaced apart in the second direction, one end of each gate extension is connected to the gate body, and the other end extends along the first direction, the second direction is parallel to the top surface of the drift region and perpendicular to the first direction; The field plate includes a field plate body and a plurality of field plate extensions, wherein the field plate body extends along the second direction, the field plate extensions are arranged at intervals in the second direction, and one end of each field plate extension is connected to the field plate body, and the other end extends along the first direction; The gate extension is located between the gate body and the field plate body; The field plate extension is located between the gate body and the field plate body; The field plate extensions are alternately arranged with each other in the second direction.

2. The forming method according to claim 1, wherein: Adjacent gate extensions have different lengths in the first direction; The lengths of adjacent field plate extensions in the first direction are different.

3. The forming method according to claim 1, wherein: Before forming the field plate, the method further includes the following steps: forming a second field dielectric layer, wherein the second field dielectric layer covers a top surface of the first field dielectric layer between the first gate and the second gate, a surface of the second gate, and a top surface of the first field dielectric layer located on a side of the second gate away from the first gate in the first direction; The field plate covering the first field dielectric layer includes the field plate covering the second field dielectric layer above the first field dielectric layer.

4. The forming method according to claim 3, wherein: forming the first field dielectric layer by a thermal oxidation process; The second field dielectric layer is formed by a low temperature deposition process.

5. The forming method according to claim 3, wherein: Before forming the second field dielectric layer, the method further comprises the following steps: forming a body region, wherein a doping type of the body region is different from a doping type of the drift region, and the body region is disposed adjacent to the first region in the first direction and located on a side of the first region away from the drift region; Annealing is performed on the semiconductor structure to allow the body region to diffuse into the first region until it adjoins the drift region.

6. The forming method according to claim 5, wherein: Before forming the second field dielectric layer, the method further comprises the following steps: forming a source region and a drain region, wherein the source region is located in the body region and has a doping type different from that of the body region, and the drain region is located in the drift region and has a doping type consistent with that of the drift region; An extraction region is formed, wherein the extraction region is located in the source region and adjacent to the body region, the doping type of the extraction region is consistent with the doping type of the body region, and the doping concentration of the extraction region is greater than the doping concentration of the body region.

7. A semiconductor structure, characterized in that include: drift zone; a body region, wherein the drift region is disposed adjacent to the body region in a first direction, a doping type of the drift region is different from a doping type of the body region, and the first direction is parallel to a top surface of the drift region; a first field dielectric layer, wherein the first field dielectric layer covers the body region and the drift region; a first gate, wherein the first gate covers the first field dielectric layer above a portion of the body region adjacent to the drift region in a first direction; a second gate, wherein the second gate covers the first field dielectric layer above the drift region, and the second gate is spaced apart from the first gate along the first direction; a field plate, wherein the field plate covers the first field dielectric layer, the field plate is spaced apart from the second gate, and is located on a side of the second gate away from the first gate in the first direction; The second gate includes a gate body and a plurality of gate extensions, the gate body extends along a second direction, the gate extensions are spaced apart in the second direction, one end of each gate extension is connected to the gate body, and the other end extends along the first direction, the second direction is parallel to the top surface of the drift region and perpendicular to the first direction; The field plate includes a field plate body and a plurality of field plate extensions, wherein the field plate body extends along the second direction, the field plate extensions are arranged at intervals in the second direction, and one end of each field plate extension is connected to the field plate body, and the other end extends along the first direction; The gate extension is located between the gate body and the field plate body; The field plate extension is located between the gate body and the field plate body; The field plate extensions are alternately arranged with each other in the second direction.

8. The semiconductor structure according to claim 7, wherein: The lengths of adjacent field plate extensions in the first direction are different; The lengths of adjacent field plate extensions in the first direction are different.

9. The semiconductor structure according to claim 7, wherein: Also includes: a source region, wherein the source region is located within the body region, and a doping type of the source region is different from a doping type of the body region; a drain region, wherein the drain region is located in the drift region, and a doping type of the drain region is consistent with a doping type of the drift region; an extraction region, wherein the extraction region is located within the source region and adjacent to the body region, a doping type of the extraction region is consistent with a doping type of the body region, and a doping concentration of the extraction region is greater than a doping concentration of the body region; a second field dielectric layer, wherein the second field dielectric layer covers a top surface of the first field dielectric layer between the first gate and the second gate and a surface of the second gate, and further covers a top surface of the first field dielectric layer located on a side of the second gate away from the first gate in the first direction; The field plate covering the first field dielectric layer includes the field plate covering the second field dielectric layer above the first field dielectric layer.

10. The semiconductor structure according to claim 9, wherein: The first field dielectric layer is formed by a thermal oxidation process; The second field dielectric layer is formed by a low-temperature deposition process.

11. A semiconductor device, characterized in that: A semiconductor structure comprising any one of claims 7 to 10.

12. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to claim 11.

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