A back contact battery without etching an opening semiconductor and a preparation method thereof

Abstract

The present invention belongs to the technical field of back-contact battery preparation, and specifically relates to a back-contact battery and a preparation method thereof that does not require etching of an opening semiconductor, including: S103, polishing or texturing the back of the silicon wafer obtained in S102; S104, depositing an intrinsic crystalline silicon layer on the back of the silicon wafer; S105, masking the non-target deposition area with a hard mask plate, and depositing alternatingly arranged N-type crystalline silicon layers on the back; then replacing the hard mask plate mask to form a P-type crystalline silicon layer and an overlapping area; S106, depositing a conductive film layer on the back of the silicon wafer; S107, opening an isolation groove on the conductive film layer, and controlling the width W4 of the isolation groove to be 0.03-0.15mm; S108, forming a metal electrode on the back. The present invention can achieve the goal of not etching an opening for the back semiconductor, greatly simplifying the process flow, and at the same time, will not cause etching damage, thereby improving the battery conversion efficiency, battery stability, and production yield.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact battery preparation, and in particular relates to a back contact battery without etching an opening semiconductor and a preparation method thereof. Background Art

[0002] At present, the back contact battery process is generally as follows:

[0003] S1, double-sided polishing of silicon wafer;

[0004] S2. Coating a first mask layer on the back of the silicon wafer for protection, wherein the first mask layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide;

[0005] S3, cleaning the silicon wafer texture to form a pyramid texture surface opposite the first mask layer, and then removing the first mask layer to form a silicon wafer with a single-side texture and single-side polishing structure;

[0006] S4, sequentially coating the back side of the silicon wafer with a first semiconductor layer and a second mask layer, wherein the second mask layer is generally silicon nitride;

[0007] S5. Laser or etch an opening on the back side of the silicon wafer to remove the second mask layer and a portion of the first semiconductor layer to form a second semiconductor opening region;

[0008] S6, cleaning the silicon wafer to remove the first semiconductor layer in the second semiconductor opening area;

[0009] S7, forming an amorphous layer, a passivation layer, and an anti-reflection layer in sequence on the front side of the silicon wafer, and forming a second semiconductor layer on the back side;

[0010] S8. Laser or etching the second semiconductor layer on the back side of the silicon wafer to form first semiconductor opening regions alternately arranged with the second semiconductor opening regions;

[0011] S9, cleaning the silicon wafer to remove the second mask layer in the first semiconductor opening area;

[0012] S10, depositing a conductive film layer on the back side of the silicon wafer;

[0013] S11, forming an isolation trench between the first semiconductor opening region and the second semiconductor opening region by laser or etching;

[0014] S12, forming metal electrodes on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer.

[0015] However, in the above-mentioned existing preparation method, the first semiconductor and the second semiconductor need to undergo two etching openings and cleanings before they can be formed, and the process flow is cumbersome; and after S5 laser or etches an opening on the back of the silicon wafer, removes the second mask layer and part of the first semiconductor layer to form the second semiconductor opening area, passivation defects are easily generated at the edge of the first semiconductor layer, thereby affecting the battery conversion efficiency.

[0016] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or public known technology. Summary of the Invention

[0017] The purpose of the present invention is to overcome the defects of the prior art in that the preparation of back-contact batteries requires two etching openings to form, which leads to a cumbersome process flow and easily produces passivation defects at the edge of the first semiconductor layer, thereby affecting the battery conversion efficiency. A back-contact battery that does not require etching openings for the semiconductor and a preparation method thereof are provided. The back-contact battery can achieve the goal of not requiring etching openings for the back semiconductor, greatly simplifying the process flow, and at the same time will not cause etching damage, thereby improving the battery passivation effect, reducing leakage current, and thereby improving the battery conversion efficiency, battery stability, and production yield.

[0018] To achieve the above objectives, in a first aspect, the present invention provides a method for preparing a back-contact cell without etching an opening semiconductor, comprising the following steps:

[0019] S101, provide double-sided textured silicon wafers;

[0020] S102, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer;

[0021] S103, polishing or texturing the back side of the silicon wafer obtained in S102 to form a polished surface or a texturing surface, and then cleaning;

[0022] S104, depositing an intrinsic crystalline silicon layer on the back side of the silicon wafer;

[0023] S105, masking the non-target deposition area through a hard mask plate, and depositing alternatingly arranged N-type crystalline silicon layers outside the back intrinsic crystalline silicon layer;

[0024] Then, a hard mask plate is replaced to mask a portion of the N-type crystalline silicon layer, forming a P-type crystalline silicon layer alternately arranged with the N-type crystalline silicon layer, and the ends of the P-type crystalline silicon layer are respectively extended outward to cover the outside of the back surface of the adjacent N-type crystalline silicon layer, and the covered area is an overlapping area; the crystalline silicon layers corresponding to the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer each independently include amorphous silicon and / or microcrystalline silicon;

[0025] S106, depositing a conductive film layer on the back side of the silicon wafer;

[0026] S107. An isolation trench is formed on the conductive film layer outside the boundary region between the longitudinal edge of the N-type crystalline silicon layer and the P-type crystalline silicon layer. The width W4 of the isolation trench is controlled to be 0.03-0.15 mm, and the width W5 of the isolation trench above the N-type crystalline silicon layer is 5%-95% of the width W4 of the isolation trench. The ratio of the width W2 of the overlapping region to the width W4 of the isolation trench is 1:(0.1-1).

[0027] S108, forming a metal electrode on the back side.

[0028] In some preferred embodiments of the present invention, the width W2 of the overlapping region is 0.05-0.30 mm.

[0029] In some preferred embodiments of the present invention, the width of the N-type crystalline silicon layer is 0.2-0.8 mm, and / or the width W1 of the P-type crystalline silicon layer between adjacent N-type crystalline silicon layers is 0.3-1 mm.

[0030] In some preferred embodiments of the present invention, the thickness ratio of the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer is 1:(0.5-5):(0.5-5).

[0031] Preferably, in the present invention, the thickness of the intrinsic crystalline silicon layer is 5-20 nm, the thickness of the N-type crystalline silicon layer is 5-40 nm, and the thickness of the P-type crystalline silicon layer is 5-40 nm.

[0032] In some preferred embodiments of the present invention, after the P-type crystalline silicon layer is formed in S105, a first semiconductor opening region that does not cover the P-type crystalline silicon layer is naturally formed in the mask area on the back side of the N-type crystalline silicon layer, and a second semiconductor opening region is formed between adjacent N-type crystalline silicon layers. The width W3 of the first semiconductor opening region is 0.1-0.7 mm.

[0033] In some preferred embodiments of the present invention, the thickness of the conductive film layer in S106 is 20-500 nm.

[0034] In some preferred embodiments of the present invention, in S102, the passivation layer is a silicon dielectric film layer and / or aluminum oxide, the anti-reflection layer is a silicon dielectric film layer, and the silicon dielectric film layer is selected from at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0035] In some preferred embodiments of the present invention, in S102 , the passivation layer and the anti-reflection layer are formed by one-time continuous coating using tubular PECVD.

[0036] In some preferred embodiments of the present invention, the passivation layer is a stack of a tunneling silicon oxide layer and a crystalline silicon layer arranged in sequence, or a stack of a tunneling silicon oxide layer and an aluminum oxide layer arranged in sequence, wherein the thickness of the tunneling silicon oxide layer is 0.3-2nm, the thickness of the crystalline silicon layer is 2-10nm, and the thickness of the aluminum oxide layer is 2-10nm.

[0037] In some preferred embodiments of the present invention, the thickness ratio of the tunneling silicon oxide layer to the intrinsic crystalline silicon layer is 1:(1-20).

[0038] In some preferred embodiments of the present invention, the antireflection layer comprises a stack of silicon nitride, silicon oxynitride, and silicon oxide arranged in sequence, with the thickness of silicon nitride being 50-90 nm, the thickness of silicon oxynitride being 10-60 nm, and the thickness of silicon oxide being 30-100 nm.

[0039] In a second aspect, the present invention provides a back-contact battery without etching an opening semiconductor, which is manufactured by the method for preparing a back-contact battery without etching an opening semiconductor described in the first aspect.

[0040] Beneficial effects:

[0041] The present invention uses the above-mentioned technical solution, especially the use of S102-S107, to achieve the back semiconductor without etching an opening, which greatly simplifies the process flow and does not cause etching damage, thereby improving the passivation effect of the battery and further improving the battery conversion efficiency; at the same time, utilizing the characteristic that the acid and alkali resistance of the P-type crystalline silicon layer is significantly better than that of the N-type crystalline silicon layer, the P-type crystalline silicon layer is extended and superimposed on the N-type crystalline silicon layer, and after the conductive film layer is opened to form an isolation groove, the P-type crystalline silicon layer in the isolation groove area is exposed to the outside, which is beneficial to improving the stability of the battery, and the isolation groove is arranged outside the junction area between the edge of the N-type crystalline silicon layer and the P-type crystalline silicon layer, and the proportion of the width W5 of the isolation groove located above the N-type crystalline silicon layer and the ratio of the width W2 of the overlapping area to the width W4 of the isolation groove are controlled, which is beneficial to reducing the leakage current of the battery and improving the insulation effect of the two semiconductor layers; the P-type crystalline silicon layer is directly deposited outside the N-type crystalline silicon layer and does not need to be deposited on the surface of the silicon nitride mask layer, which greatly improves the adhesion of the second semiconductor layer and improves the product yield and stability.

[0042] The present invention utilizes the very poor conductivity of the overlapping region formed by the superposition of the N-type crystalline silicon layer and the P-type crystalline silicon layer to provide a good insulation effect. This, combined with the structure of the intrinsic crystalline silicon layer, forms a good insulation structure. Furthermore, the use of an appropriately wide isolation trench and its appropriate ratio to the width of the overlapping region can achieve a good insulation effect without the need for vertical isolation. At the same time, the insulation structure enhances the back passivation effect and improves the etching resistance of S107, thereby improving the conversion efficiency and reliability of the battery. Furthermore, the back semiconductor passivation structure uses amorphous silicon and / or microcrystalline silicon, allowing the entire process to be formed using a low-temperature process, simplifying the process. However, if the back semiconductor passivation structure uses polycrystalline silicon, even if an isolation trench is formed, it will not meet the insulation requirements. Polycrystalline silicon has higher conductivity and severe leakage current, and neither can form good insulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 A schematic structural diagram of an N-type single-crystal silicon wafer after double-sided texturing is provided for an embodiment of the present invention;

[0045] Figure 2 Schematic diagram of the structure of forming a passivation layer and an anti-reflection layer on the front side of a silicon wafer according to an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the structure of forming a polished surface on the back side of a silicon wafer according to an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of the structure of depositing an intrinsic amorphous silicon layer on the back side of a silicon wafer according to an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of the structure of depositing an N-type crystalline silicon layer on the back side of a silicon wafer according to an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of the structure of depositing a P-type crystalline silicon layer on the back side of a silicon wafer according to an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of the structure of depositing a conductive film layer on the back side of a silicon wafer according to an embodiment of the present invention;

[0051] Figure 8 This is a schematic diagram of a structure in which an isolation trench is formed on the back side of a silicon wafer according to an embodiment of the present invention;

[0052] Figure 9Schematic diagram of the structure of forming a metal electrode on the back side of a silicon wafer according to an embodiment of the present invention.

[0053] Description of Reference Numerals

[0054] Silicon wafer 10 , passivation layer 11 , anti-reflection layer 12 , intrinsic amorphous silicon layer 13 , N-type amorphous silicon layer 14 , P-type amorphous silicon layer 15 , conductive film layer 16 , metal electrode 17 . DETAILED DESCRIPTION

[0055] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0056] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0057] The endpoints of the ranges and any values ​​disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values ​​can be combined to form one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed herein. The terms "optional" and "optional" both mean that a range may or may not be included (or may or may not be present).

[0058] In the present invention, the area close to the silicon wafer is considered as the inside, and the area far from the silicon wafer is considered as the outside.

[0059] In a first aspect, the present invention provides a method for preparing a back-contact cell without etching an opening semiconductor, comprising the following steps:

[0060] S101, provide double-sided textured silicon wafers;

[0061] S102, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer;

[0062] S103, polishing or texturing the back side of the silicon wafer obtained in S102 to form a polished surface or a texturing surface, and then cleaning;

[0063] S104, depositing an intrinsic crystalline silicon layer on the back side of the silicon wafer;

[0064] S105, masking the non-target deposition area through a hard mask plate, and depositing alternatingly arranged N-type crystalline silicon layers outside the back intrinsic crystalline silicon layer;

[0065] Then, a hard mask plate is replaced to mask a portion of the N-type crystalline silicon layer, forming a P-type crystalline silicon layer alternately arranged with the N-type crystalline silicon layer, and the ends of the P-type crystalline silicon layer are respectively extended outward to cover the outside of the back surface of the adjacent N-type crystalline silicon layer, and the covered area is an overlapping area; the crystalline silicon layers corresponding to the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer each independently include amorphous silicon and / or microcrystalline silicon;

[0066] S106, depositing a conductive film layer on the back side of the silicon wafer;

[0067] S107, forming an isolation trench on the conductive film layer outside the boundary region between the longitudinal edge of the N-type crystalline silicon layer and the P-type crystalline silicon layer;

[0068] S108, forming a metal electrode on the back side.

[0069] In the present invention, the width W4 of the isolation groove is controlled to be 0.03-0.15 mm, for example, it can be 0.03 mm, 0.04 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.10 mm, 0.11 mm, 0.12 mm, 0.13 mm, 0.14 mm, 0.15 mm and the range between any two point values.

[0070] The width W5 of the isolation groove above the N-type crystalline silicon layer is 5%-95% of the width W4 of the isolation groove, for example, it can be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95% and the range between any two point values, for example, 35%-95% can be preferred.

[0071] Preferably, the present invention controls the ratio of the width W2 of the overlapping region to the width W4 of the isolation trench to be 1:(0.1-1), preferably 1:(0.30-1.00), which is beneficial for ensuring excellent insulation effect without etching the opening semiconductor and without the need for vertical isolation means, thereby improving the passivation level.

[0072] The texturing solution in S101 of the present invention can refer to the prior art. For example, a solution containing a base with a mass concentration of 0.5%-5% and a texturing additive with a mass concentration of 0.05%-1% can be used, wherein the base can be potassium hydroxide or sodium hydroxide. In addition, the temperature of the texturing solution is 70-90°C. The present invention can also perform conventional cleaning after texturing. The texturing additive is commercially available and will not be described in detail here.

[0073] In some preferred embodiments of the present invention, the width W2 of the overlap region is 0.05-0.30 mm, for example, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.10 mm, 0.11 mm, 0.12 mm, 0.13 mm, 0.14 mm, 0.15 mm, 0.16 mm, 0.17 mm, 0.18 mm, 0.19 mm, 0.20 mm, 0.21 mm, 0.22 mm, 0.23 mm, 0.24 mm, 0.25 mm, 0.26 mm, 0.27 mm, 0.28 mm, 0.29 mm, 0.30 mm, and any range between any two values. Using an overlap region of appropriate width is more conducive to improving the process window, thereby improving battery efficiency and production yield.

[0074] In some preferred embodiments of the present invention, the width of the N-type crystalline silicon layer is 0.2-0.8 mm.

[0075] In some preferred embodiments of the present invention, the width W1 of the P-type crystalline silicon layer between adjacent N-type crystalline silicon layers is 0.3-1 mm.

[0076] In some preferred embodiments of the present invention, the thickness ratio of the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer is 1:(0.5-5):(0.5-5). This preferred solution is more conducive to improving battery efficiency.

[0077] In some preferred embodiments of the present invention, the thickness of the intrinsic crystalline silicon layer is 5-20 nm.

[0078] In some preferred embodiments of the present invention, the thickness of the N-type crystalline silicon layer is 5-40 nm.

[0079] In some preferred embodiments of the present invention, the thickness of the P-type crystalline silicon layer is 5-40 nm.

[0080] In some preferred embodiments of the present invention, after the P-type crystalline silicon layer is formed in S105, a first semiconductor opening region that does not cover the P-type crystalline silicon layer is naturally formed in the mask area on the back side of the N-type crystalline silicon layer, and a second semiconductor opening region is formed between adjacent N-type crystalline silicon layers.

[0081] Further preferably, the width W3 of the first semiconductor opening region is 0.1-0.7 mm.

[0082] In the present invention, the intrinsic crystalline silicon layer, N-type crystalline silicon layer, and P-type crystalline silicon layer can be formed by referring to the prior art, for example, by PECVD, hot-wire CVD, etc., preferably using PECVD technology.

[0083] It is understood that in the present invention, the hard mask plate masking in S105 refers to covering and attaching the hard mask plate to the silicon wafer, and the covered area is the non-target deposition area.

[0084] In some preferred embodiments of the present invention, the thickness of the conductive film layer in S106 is 20-500 nm. The conductive film layer is preferably a transparent conductive film layer, which can be conventional conductive film layers in the art such as ITO, and can be used in the present invention, which will not be described in detail here.

[0085] The isolation trench of the present invention may be formed by laser or chemical etching technology.

[0086] In some preferred embodiments of the present invention, in S102 , the passivation layer is a silicon dielectric film layer and / or aluminum oxide, and the anti-reflection layer is a silicon dielectric film layer.

[0087] Further preferably, the silicon dielectric film layer is selected from at least one of silicon nitride, silicon oxynitride, and silicon oxide. It is understood that the silicon dielectric film layers of the passivation layer and the anti-reflection layer can be the same or different.

[0088] In S102, the passivation layer and anti-reflection layer can be formed using equipment such as ALD, PECVD, or LPCVD. In some preferred embodiments of the present invention, in S102, the passivation layer and anti-reflection layer are formed using a one-time continuous coating process using tubular PECVD, which further simplifies the process flow while simultaneously improving passivation quality. Furthermore, preferably, the deposition temperature of the passivation layer and the anti-reflection layer can each independently be 400-500°C.

[0089] In some preferred embodiments of the present invention, the passivation layer is a stack of a tunneling silicon oxide layer and a crystalline silicon layer, or a stack of a tunneling silicon oxide layer and an aluminum oxide layer. This preferred embodiment, combined with the specific preparation method of the present invention, further reduces UV attenuation, thereby improving battery reliability. The crystalline silicon layer includes amorphous silicon and / or microcrystalline silicon.

[0090] In the passivation layer, preferably, the thickness of the tunneling silicon oxide layer is 0.3-2 nm, the thickness of the crystalline silicon layer is 2-10 nm, and the thickness of the aluminum oxide layer is 2-10 nm.

[0091] In some preferred embodiments of the present invention, the thickness ratio of the tunneling silicon oxide layer to the intrinsic crystalline silicon layer is 1:(1-20), which is more conducive to improving passivation and thus improving battery efficiency.

[0092] In some preferred embodiments of the present invention, the anti-reflection layer comprises a stack of silicon nitride, silicon oxynitride, and silicon oxide arranged in sequence. Using this specific combination of anti-reflection layers is more conducive to reducing reflection and improving battery efficiency.

[0093] Further preferably, in the anti-reflection layer, the thickness of silicon nitride is 50-90 nm, the thickness of silicon oxynitride is 10-60 nm, and the thickness of silicon oxide is 30-100 nm.

[0094] The polishing solution used in the polishing process of step S103 of the present invention can refer to existing technologies. For example, a solution containing a base at a mass concentration of 2% to 10% and a polishing additive at a mass concentration of 0% to 1% can be used, where the base can be potassium hydroxide or sodium hydroxide. Furthermore, the temperature of the polishing solution is illustratively 70°C to 90°C. The polishing additive is commercially available and will not be described in detail here.

[0095] In a second aspect, the present invention provides a back-contact cell that does not require etching of an opening semiconductor, produced using the method for preparing a back-contact cell that does not require etching of an opening semiconductor described in the first aspect. The back-contact cell of the present invention is free of etching defects, improves cell passivation, reduces leakage current, and thereby increases cell conversion efficiency, cell stability, and production yield.

[0096] The embodiments of the present invention are described in detail below, which are exemplary and only used to explain the present invention, and are not to be construed as limiting the present invention.

[0097] Example 1

[0098] A back contact battery is prepared by the following preparation method:

[0099] S101、 Figure 1 As shown, a double-sided textured silicon wafer 10 (N-type single crystal silicon) is provided;

[0100] The texturing solution is an aqueous solution of sodium hydroxide with a mass concentration of 1% and a texturing additive with a mass concentration of 0.25% at a temperature of 80° C. After texturing, the surface of the silicon wafer 10 is cleaned.

[0101] S102, such as Figure 2As shown, a passivation layer 11 and an anti-reflection layer 12 are sequentially formed on the front surface of the silicon wafer 10. The passivation layer 11 and the anti-reflection layer 12 are formed by one-time continuous coating using tubular PECVD at a deposition temperature of 450° C. A 1 nm thick tunneling silicon oxide layer and a 5 nm thick amorphous silicon layer are sequentially formed on the front surface of the silicon wafer 10 as the passivation layer 11. Subsequently, a 60 nm thick silicon nitride layer, a 10 nm thick silicon oxynitride layer, and an 80 nm thick silicon oxide layer are sequentially formed as the anti-reflection layer 12.

[0102] S103, such as Figure 3 As shown, the back side of the silicon wafer 10 is polished to form a polished surface, and then the surface of the silicon wafer 10 is cleaned; the polishing process uses an aqueous solution of sodium hydroxide with a mass concentration of 3% and a polishing additive with a mass concentration of 0.5% at a temperature of 70°C;

[0103] S104, such as Figure 4 As shown, an intrinsic amorphous silicon layer 13 with a thickness of 10 nm is deposited on the back of the silicon wafer 10 by PECVD technology; according to calculation, the ratio of the thickness of the tunneling silicon oxide layer to the intrinsic amorphous silicon layer 13 is 1:10.

[0104] S105, such as Figure 5 、 Figure 6 As shown, a 15nm thick N-type amorphous silicon layer 14 is deposited on the back of a silicon wafer 10 using chemical vapor deposition (CVD) technology through a hard mask. The hard mask is then replaced to form 15nm thick P-type amorphous silicon layers 15, alternating with the N-type amorphous silicon layers 14. The ends of the P-type amorphous silicon layers 15 extend outward to overlap the back of adjacent N-type amorphous silicon layers 14. A first semiconductor opening region, not covering the P-type amorphous silicon layer 15, is naturally formed in the masked region on the back of the N-type amorphous silicon layer 14. The width W3 of the first semiconductor opening region is 0.3mm. The width W2 of the overlapping region is 0.1mm. The width of the N-type amorphous silicon layer 14 is 0.5mm. The width W1 of the P-type amorphous silicon layer 15 between adjacent N-type amorphous silicon layers 14 is 0.5mm. According to calculation, the thickness ratio of the intrinsic amorphous silicon layer 13 , the N-type amorphous silicon layer 14 , and the P-type amorphous silicon layer 15 is 1:1.5:1.5.

[0105] S106, such as Figure 7 As shown, a 60nm conductive film layer 16 (ITO) is deposited on the back of the silicon wafer 10;

[0106] S107, such as Figure 8As shown, laser etching technology is used to form an isolation groove in the conductive film layer 16 at the junction area between the edge of the N-type amorphous silicon layer 14 and the P-type amorphous silicon layer 15. The width W4 of the isolation groove is 0.05 mm, and the width W5 of the isolation groove above the N-type amorphous silicon layer 14 accounts for 50% of the width W4 of the isolation groove; after calculation, the ratio of the width W2 of the overlapping area to the width W4 of the isolation groove is 1:0.5.

[0107] S108, such as Figure 9 As shown, a metal electrode 17 is formed on the back side of the silicon wafer 10 .

[0108] Example 2

[0109] The same method is carried out as in Example 1, except that the amorphous silicon layer in the front passivation layer is replaced by an aluminum oxide layer of the same thickness.

[0110] Example 3

[0111] The process is carried out in accordance with Example 1, except that in S105 , the width W2 of the overlapping region is controlled to be 0.2 mm, so that the ratio of the width W2 of the overlapping region to the width W4 of the isolation trench is 1:0.25.

[0112] Example 4

[0113] The process is carried out with reference to Example 1, except that in S107 , the width W5 of the isolation trench located above the N-type crystalline silicon layer is controlled to be 0.018 mm, so that W5 is 30% of the width W4 of the isolation trench.

[0114] Example 5

[0115] The process is carried out in accordance with Example 1, except that, in S103, the back side of the silicon wafer is subjected to texturing treatment to form a texturing surface, which is then cleaned.

[0116] Comparative Example 1

[0117] The process is carried out in accordance with Example 1, except that no overlapping region is provided. Specifically, in S105 , the hard mask plate is adjusted and replaced to mask a portion of the N-type amorphous silicon layer, so that the N-type amorphous silicon layer and the P-type amorphous silicon layer are only alternately arranged without overlapping.

[0118] Comparative Example 2

[0119] The process is carried out in accordance with Example 1, except that in S107 , the width W5 of the isolation trench located above the N-type amorphous silicon layer is controlled to be 0 mm.

[0120] Comparative Example 3

[0121] The process is carried out in accordance with Example 1, except that in S105 , the width W2 of the overlapping region is controlled to be 0.04 mm, so that the ratio of the width W2 of the overlapping region to the width W4 of the isolation trench is 1:1.5.

[0122] Comparative Example 4

[0123] The process is carried out in accordance with Example 1, except that the NP types of the two amorphous silicon layer semiconductors are swapped in S105, while the other structures, film thickness, and width remain unchanged. That is, in S105, the non-target deposition area is masked by a hard mask plate, and alternating P-type amorphous silicon layers are deposited outside the intrinsic amorphous silicon layer on the back side.

[0124] Then, the hard mask plate is replaced to mask part of the P-type amorphous silicon layer to form an N-type amorphous silicon layer arranged alternately with the P-type amorphous silicon layer, and the two ends of the N-type amorphous silicon layer are respectively extended outward to cover the outside of the back side of the adjacent P-type amorphous silicon layer, and the covered area is the overlapping area.

[0125] Test Case

[0126] The back-contact batteries obtained in Examples 1-5 and Comparative Examples 1-4 were subjected to performance tests, and the results are shown in Table 1. The battery efficiency, open circuit voltage, and leakage current were all obtained through IEC60904 standard testing. The test method for battery production yield is as follows: 1,000 pieces are produced as a batch, and yield data is collected according to the same qualification standard. The test method for DH attenuation is as follows: refer to the IEC61215 standard test for DH test attenuation data for 1,000 hours under an environment of 85% humidity and 85°C, which is used to characterize battery stability. The smaller the value, the better the battery stability.

[0127] Table 1

[0128]

[0129] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can achieve the goal of not etching an opening for the back semiconductor, which greatly simplifies the process flow and does not cause etching damage, thereby improving the battery passivation effect, reducing leakage current, and further improving battery conversion efficiency, battery stability, and production yield.

[0130] Furthermore, according to Example 1 and Examples 2-4, it can be seen that the preferred solution of the present invention is more conducive to improving both battery conversion efficiency and battery stability and production yield.

[0131] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, various simple variations of the technical solution of the present invention may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed in the present invention and fall within the scope of protection of the present invention.

Claims

1. A method for preparing a back contact battery without etching an opening semiconductor, characterized in that: The steps include: S101, provide double-sided textured silicon wafers; S102, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer; S103, polishing or texturing the back side of the silicon wafer obtained in S102 to form a polished surface or a texturing surface, and then cleaning; S104, depositing an intrinsic crystalline silicon layer on the back side of the silicon wafer; S105, masking the non-target deposition area through a hard mask plate, and depositing alternatingly arranged N-type crystalline silicon layers outside the back intrinsic crystalline silicon layer; Then, a hard mask plate is replaced to mask a portion of the N-type crystalline silicon layer to form a P-type crystalline silicon layer alternately arranged with the N-type crystalline silicon layer, and both ends of the P-type crystalline silicon layer are respectively extended outward to cover the outside of the back surface of the adjacent N-type crystalline silicon layer, and the covering area is an overlapping area, and the width W2 of the overlapping area is 0.05-0.30mm; the crystalline silicon layers corresponding to the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer each independently include amorphous silicon and / or microcrystalline silicon; S106, depositing a conductive film layer on the back side of the silicon wafer; S107. An isolation trench is formed on the conductive film layer outside the boundary region between the longitudinal edge of the N-type crystalline silicon layer and the P-type crystalline silicon layer. The width W4 of the isolation trench is controlled to be 0.03-0.15 mm, and the width W5 of the isolation trench above the N-type crystalline silicon layer is 5%-95% of the width W4 of the isolation trench. The ratio of the width W2 of the overlapping region to the width W4 of the isolation trench is 1:(0.1-1). S108, forming a metal electrode on the back side.

2. The method for preparing a back contact battery without etching an opening semiconductor according to claim 1, characterized in that: The width of the N-type crystalline silicon layer is 0.2-0.8 mm, and / or the width W1 of the P-type crystalline silicon layer between adjacent N-type crystalline silicon layers is 0.3-1 mm.

3. The method for preparing a back contact battery without etching an opening semiconductor according to claim 1, wherein: The thickness ratio of the intrinsic crystalline silicon layer, the N-type crystalline silicon layer, and the P-type crystalline silicon layer is 1:(0.5-5):(0.5-5).

4. The method for preparing a back contact battery without etching an opening semiconductor according to claim 1, wherein: The thickness of the intrinsic crystalline silicon layer is 5-20 nm, the thickness of the N-type crystalline silicon layer is 5-40 nm, and the thickness of the P-type crystalline silicon layer is 5-40 nm.

5. The method for preparing a back contact battery without etching an opening semiconductor according to claim 1, wherein: After the P-type crystalline silicon layer is formed in S105, a first semiconductor opening region that does not cover the P-type crystalline silicon layer is naturally formed in the mask area on the back side of the N-type crystalline silicon layer, and a second semiconductor opening region is formed between adjacent N-type crystalline silicon layers. The width W3 of the first semiconductor opening region is 0.1-0.7 mm. and / or, The thickness of the conductive film layer in S106 is 20-500 nm.

6. The method for preparing a back contact battery without etching an opening semiconductor according to claim 1, wherein: In S102, the passivation layer is a silicon dielectric film layer and / or aluminum oxide, the anti-reflection layer is a silicon dielectric film layer, and the silicon dielectric film layer is selected from at least one of silicon nitride, silicon oxynitride, and silicon oxide; and / or, In S102, the passivation layer and the anti-reflection layer are formed by one-time continuous coating using tubular PECVD.

7. The method for preparing a back contact battery without etching an opening semiconductor according to claim 6, characterized in that: The passivation layer is a stack of a tunneling silicon oxide layer and a crystalline silicon layer arranged in sequence, or a stack of a tunneling silicon oxide layer and an aluminum oxide layer arranged in sequence, wherein the thickness of the tunneling silicon oxide layer is 0.3-2nm, the thickness of the crystalline silicon layer is 2-10nm, and the thickness of the aluminum oxide layer is 2-10nm.

8. The method for preparing a back contact battery without etching an opening semiconductor according to claim 7, characterized in that: The thickness ratio of the tunneling silicon oxide layer to the intrinsic crystalline silicon layer is 1:(1 - 20).

9. The method for preparing a back contact battery without etching an opening semiconductor according to claim 6 or 7, characterized in that: The anti-reflection layer comprises a stack of silicon nitride, silicon oxynitride and silicon oxide arranged in sequence, the thickness of the silicon nitride is 50-90nm, the thickness of the silicon oxynitride is 10-60nm, and the thickness of the silicon oxide is 30-100nm.

10. A back contact battery without etching an opening semiconductor, characterized in that: The battery is prepared by the method for preparing a back-contact battery without etching an opening semiconductor as described in any one of claims 1 to 9.

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