Solar cell and method of manufacturing the same, stacked cell, photovoltaic module

Abstract

The application relates to a solar cell and a manufacturing method thereof, a laminated cell and a photovoltaic module, and relates to the technical field of solar cells. The solar cell adopts a substrate doped with an antimony element to improve the majority carrier concentration, optimize the carrier transport efficiency of the cell, and improve the fill factor of the cell. Meanwhile, by controlling the concentration of the antimony element in the first semiconductor layer to be greater than the concentration of the antimony element in the second semiconductor layer, the electrical properties of the first semiconductor layer and the second semiconductor layer are optimized, the carrier recombination rate of the cell can be optimized, the passivation effect of the second semiconductor layer is improved, and the overall passivation effect of the solar cell is further improved.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a solar cell and its manufacturing method, a tandem cell, and a photovoltaic module. Background Technology

[0002] The positive and negative electrodes of the back-contact solar cell are both located on the back of the cell, and there are no grid lines blocking the front of the cell, which reduces the light loss from the front of the cell and maximizes the utilization of the incident light from the front of the cell, thereby improving the cell conversion efficiency.

[0003] However, back-contact solar cells still have many shortcomings, which affect the yield rate and industrialization of back-contact solar cells. Summary of the Invention

[0004] Therefore, it is necessary to provide a solar cell and its manufacturing method, a tandem cell, and a photovoltaic module to address the problems in the existing technology.

[0005] In a first aspect, this application provides a solar cell, comprising:

[0006] A substrate having a first conductivity type, the substrate being doped with antimony;

[0007] A first semiconductor layer is disposed on the back side of the substrate, and the first semiconductor layer has the same conductivity type as the substrate;

[0008] A second semiconductor layer is disposed on the back side of the substrate, and the second semiconductor layer and the first semiconductor layer are alternately disposed on the back side of the substrate, wherein the conductivity type of the second semiconductor layer is opposite to that of the substrate;

[0009] The concentration of antimony in the first semiconductor layer is greater than the concentration of antimony in the second semiconductor layer.

[0010] Optionally, the diffusion depth of antimony in the first semiconductor layer is greater than the diffusion depth of antimony in the second semiconductor layer.

[0011] Optionally, the solar cell further includes:

[0012] An isolation region is located between the first semiconductor layer and the second semiconductor layer;

[0013] A passivation layer that covers the back side of the substrate of the first semiconductor layer, the second semiconductor layer, and the isolation region.

[0014] Optionally, the solar cell further includes:

[0015] A first metal electrode is disposed on the side of the first semiconductor layer away from the substrate, and the first metal electrode is electrically connected to the first semiconductor layer.

[0016] A second metal electrode is disposed on the side of the second semiconductor layer away from the substrate, and the second metal electrode is electrically connected to the second semiconductor layer.

[0017] Optionally, the antimony doping concentration in the first semiconductor layer is 1×10⁻⁶. 9 cm -3 -1×10 14 cm -3 The antimony doping concentration in the second semiconductor layer is 1×10⁻⁶. 8 cm -3 -1×10 13 cm -3 .

[0018] Optionally, the antimony doping concentration in the substrate is 1×10⁻⁶. 14 cm -3 -1×10 18 cm -3 .

[0019] Optionally, the first semiconductor layer is doped with a first element having a first conductivity type, and the doping concentration of the first element in the first semiconductor layer is 1×10⁻⁶. 20 cm -3 -5×10 20 cm -3 ;

[0020] The second semiconductor layer has a second element of a second conductivity type, and the doping concentration of the second element in the second semiconductor layer is 2 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 .

[0021] Optionally, the total amount of antimony in the first semiconductor layer is greater than the total amount of antimony in the second semiconductor layer.

[0022] Optionally, the average concentration of antimony in the first semiconductor layer is greater than the average concentration of antimony in the second semiconductor layer.

[0023] Optionally, at the same distance from the substrate, the concentration of antimony in the first semiconductor layer is greater than the concentration of antimony in the second semiconductor layer.

[0024] Secondly, this application provides a method for manufacturing a solar cell, wherein the solar cell is the solar cell described in the first aspect, and the manufacturing method includes:

[0025] A substrate is provided, the back side of which includes a first region and a second region;

[0026] A first semiconductor layer is formed in the first region, and a first element having a first conductivity type is doped into the first semiconductor layer;

[0027] A second semiconductor layer is formed in the second region, and a second element having a second conductivity type is doped into the second semiconductor layer.

[0028] Optionally, the first element includes elements of Group VA; the second element includes elements of Group IIIA.

[0029] Thirdly, this application provides a stacked battery, including a bottom battery and a top battery stacked on the bottom battery;

[0030] The bottom cell includes a solar cell as described in the first aspect, or a solar cell manufactured by the method described in the second aspect; the top cell includes a perovskite cell.

[0031] Fourthly, this application provides a photovoltaic module, including a solar cell as described in the first aspect, or a solar cell manufactured by the method described in the second aspect, or a tandem cell as described in the third aspect.

[0032] The solar cell, its fabrication method, tandem cell, and photovoltaic module of this application employ an antimony-doped substrate, which can increase the majority carrier concentration of the substrate, optimize the carrier transport efficiency of the cell, and improve the fill factor of the cell. At the same time, antimony doping of the substrate can reduce the interface state density at the contact between the substrate and the first and second tunneling layers, which is beneficial to improving the passivation effect of the cell, thereby improving the stability of the cell and improving the yield and industrialization of the cell. By controlling the concentration of antimony in the first semiconductor layer to be greater than that in the second semiconductor layer, the electrical performance of the first and second semiconductor layers is optimized, which can optimize the carrier recombination rate of the cell and improve the passivation effect of the second semiconductor layer, further improving the overall passivation effect of the solar cell. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1This is a schematic diagram of the structure of a solar cell provided in one embodiment;

[0035] Figure 2 This is a doping concentration curve of the first semiconductor layer and the antimony element in the substrate below it, provided in one embodiment;

[0036] Figure 3 This is a doping concentration curve of the second semiconductor layer and the antimony element in the substrate below it, provided in one embodiment;

[0037] Figure 4 This is a process flow diagram of a method for manufacturing a solar cell provided in one embodiment;

[0038] Figure 5 This is a schematic diagram of the structure after forming a first tunneling layer, a first amorphous silicon layer and a phosphosilicate glass layer on the back side of a substrate, as provided in one embodiment.

[0039] Figure 6 This is a schematic diagram of the structure after doping a first element into a first amorphous silicon layer according to one embodiment;

[0040] Figure 7 This is a schematic diagram of the structure after removing the first semiconductor layer and the first tunneling layer other than the first region, as provided in one embodiment;

[0041] Figure 8 This is a schematic diagram of the structure after forming a second tunneling layer, a second amorphous silicon layer and a borosilicate glass layer on the back side of a substrate, as provided in one embodiment.

[0042] Figure 9 This is a schematic diagram of the structure after doping a second element into a second amorphous silicon layer according to one embodiment;

[0043] Figure 10 This is a schematic diagram of the structure after removing the second semiconductor layer and the second tunneling layer other than the second region in one embodiment;

[0044] Figure 11 This is a schematic diagram of the structure after texturing the isolation area in one embodiment;

[0045] Figure 12 This is a schematic diagram of the structure after the passivation layer is formed, as provided in one embodiment.

[0046] Figure 13 This is a schematic diagram showing the connection between the top and bottom cells of a stacked battery provided in one embodiment;

[0047] Figure 14 This is a schematic diagram showing the connection between the top and bottom cells of a stacked battery provided in another embodiment;

[0048] Figure 15This is a schematic diagram showing the connection between the top and bottom cells of a stacked battery provided in another embodiment.

[0049] Explanation of reference numerals in the attached figures:

[0050] 21. Substrate; 21a. Back side; 21b. Front side; 22. First tunneling layer; 23. First semiconductor layer; 23a. First amorphous silicon layer; 25. Phosphosilicate glass layer; 26. Second tunneling layer; 27. Second semiconductor layer; 27a. Second amorphous silicon layer; 29. ​​Borosilicate glass layer; 30. Passivation layer; 31. Alumina layer; 32. Silicon nitride layer; 41. First metal electrode; 42. Second metal electrode; A1. First region; A2. Second region; A3. Isolation region; 20. Bottom cell; 50. Top cell; 1. Stacked cell. Detailed Implementation

[0051] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0053] As described in the background section, back-contact solar cells still have many shortcomings, affecting their yield and industrialization. The efficiency of back-contact solar cells still needs to be improved, and the passivation limitation of back-contact solar cells is determined by the passivation effect of the p-region doped layer. The passivation effect of the p-region doped layer directly affects the yield and industrialization of back-contact solar cells.

[0054] According to an exemplary embodiment, this embodiment provides a solar cell, such as Figure 1As shown, the solar cell includes a substrate 21, a first semiconductor layer 23, and a second semiconductor layer 27. The substrate 21 has a first conductivity type and has a front side 21b and a back side 21a disposed opposite to each other. Antimony is doped into the substrate 21. The first semiconductor layer 23 is disposed on the back side 21a of the substrate 21, and has the same conductivity type as the substrate 21. A first tunneling layer 22, which can be a silicon oxide layer, is disposed between the first semiconductor layer 23 and the substrate 21. The second semiconductor layer 27 is disposed on the back side 21a of the substrate 21, and the second semiconductor layer 27 and the first semiconductor layer 23 are alternately disposed on the back side 21a of the substrate 21. The second semiconductor layer 27 has the opposite conductivity type to the substrate 21. A second tunneling layer 26, which can also be a silicon oxide layer, is disposed between the second semiconductor layer 27 and the substrate 21. The concentration of antimony in the first semiconductor layer 23 is greater than the concentration of antimony in the second semiconductor layer 27.

[0055] In this embodiment, the first conductivity type is n-type, and the substrate 21 is doped with phosphorus and antimony. The first semiconductor layer 23 is n-type, and the second semiconductor layer 27 is p-type. The solar cell of this embodiment is obtained by sequentially forming an n-type first semiconductor layer 23 and a p-type second semiconductor layer 27 on an antimony-doped n-type substrate 21. The first semiconductor layer 23 is formed earlier, and the first semiconductor layer 23 is subjected to high-temperature treatment more times than the second semiconductor layer 27, so that the concentration of antimony in the first semiconductor layer 23 is greater than the concentration of antimony in the second semiconductor layer 27.

[0056] The antimony doping concentration in the first semiconductor layer 23 and the substrate 21 below it, as well as the antimony doping concentration in the second semiconductor layer 27 and the substrate 21 below it, were detected using electrochemical voltage (ECV) in this embodiment. The results were obtained respectively. Figure 2 , Figure 3 .

[0057] Reference Figure 2 , Figure 2 The doping concentration curves of antimony in the first semiconductor layer 23 and the substrate 21 below it are obtained by detecting the antimony element from the surface of the first semiconductor layer 23 away from the substrate 21 towards the substrate 21. Figure 2 The horizontal axis represents the detection depth, and the vertical axis represents the antimony doping concentration. Figure 2 To the left of the mid-inflection point P1 is the antimony doping concentration in the first semiconductor layer 23. Figure 2To the right of the inflection point P1 is the antimony doping concentration in the substrate 21 below the first semiconductor layer 23. From the surface of the first semiconductor layer 23 away from the substrate 21 towards the substrate 21, the antimony doping concentration in the first semiconductor layer 23 gradually increases. Antimony is detected at a detection depth of approximately 0.11 μm in the first semiconductor layer 23, and the slope of the antimony curve for the first semiconductor layer 23 is relatively large. This indicates that the closer the first semiconductor layer 23 is to the substrate 21, the higher the antimony concentration in the first semiconductor layer 23.

[0058] Reference Figure 3 , Figure 3 The doping concentration curves of antimony in the second semiconductor layer 27 and the substrate 21 below it are obtained by detecting the antimony element from the surface of the second semiconductor layer 27 away from the substrate 21 towards the substrate 21. Figure 3 The horizontal axis represents the detection depth, and the vertical axis represents the antimony doping concentration. Figure 3 To the left of the mid-inflection point P2 is the antimony doping concentration in the second semiconductor layer 27. Figure 3 The doping concentration of antimony in the substrate 21 beneath the second semiconductor layer 27 is to the right of the inflection point P2. From the surface of the second semiconductor layer 27 away from the substrate 21 towards the substrate 21, the doping concentration of antimony in the second semiconductor layer 27 gradually increases. Antimony is detected at a detection depth of approximately 0.13 μm in the second semiconductor layer 27, and the slope of the antimony doping curve in the second semiconductor layer 27 is smaller than that in the first semiconductor layer 23, indicating that the rate of increase of antimony in the second semiconductor layer 27 is less than that in the first semiconductor layer 23.

[0059] Reference Figure 2 , Figure 3 The antimony doping concentration in the first semiconductor layer 23 is 1×10⁻⁶. 9 cm -3 -1×10 14 cm -3 The antimony doping concentration in the second semiconductor layer 27 is 1×10⁻⁶. 8 cm -3 -1×10 13 cm -3 The antimony doping concentration in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0060] Reference Figure 2 , Figure 3 As shown, the antimony doping concentration in the substrate 21 below the first semiconductor layer 23 is the same as the antimony doping concentration in the substrate 21 below the second semiconductor layer 27; the antimony doping concentration in the substrate 21 is 1×10⁻⁶. 14 cm -3 -1×10 18 cm -3 .

[0061] In this embodiment, the solar cell uses an antimony-doped substrate 21, which increases the majority carrier concentration in the substrate 21, optimizes the carrier transport efficiency of the cell, and improves the fill factor. Simultaneously, antimony doping of the substrate 21 reduces the interface state density at the contact points between the substrate 21 and the first tunneling layer 22 and the second tunneling layer 26, which is beneficial for improving the passivation effect of the cell, thereby enhancing cell stability and improving yield and industrialization. By controlling the antimony concentration in the first semiconductor layer 23 to be greater than that in the second semiconductor layer 27, the electrical performance of the first semiconductor layer 23 and the second semiconductor layer 27 is optimized, which optimizes the carrier recombination rate of the cell and improves the passivation effect of the second semiconductor layer 27, further enhancing the overall passivation effect of the solar cell.

[0062] In some embodiments, refer to Figure 1 The diffusion depth of antimony in the first semiconductor layer 23 is greater than that of antimony in the second semiconductor layer 27.

[0063] Reference Figure 2 , Figure 3 As shown, antimony is detected at a detection depth of approximately 0.11 μm from the surface of the first semiconductor layer 23 away from the substrate 21 towards the substrate 21, and at a detection depth of approximately 0.13 μm from the surface of the second semiconductor layer 27 away from the substrate 21 towards the substrate 21. Therefore, it can be concluded that the diffusion depth of antimony in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0064] In some embodiments, refer to Figure 2 , Figure 3 The total amount of antimony in the first semiconductor layer 23 is greater than the total amount of antimony in the second semiconductor layer 27.

[0065] In some embodiments, the average concentration of antimony in the first semiconductor layer 23 is greater than the average concentration of antimony in the second semiconductor layer 27.

[0066] In some embodiments, at the same distance from the substrate 21, the concentration of antimony in the first semiconductor layer 23 is greater than the concentration of antimony in the second semiconductor layer 27.

[0067] In some embodiments, refer to Figure 2 The first semiconductor layer 23 is doped with a first element having a first conductivity type, and the doping concentration of the first element in the first semiconductor layer 23 is 1×10⁻⁶. 20 cm -3 -5×10 20 cm -3 .

[0068] Reference Figure 3 The second semiconductor layer 27 is doped with a second element having a second conductivity type, and the doping concentration of the second element in the second semiconductor layer 27 is 2 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 .

[0069] In this embodiment, the first element includes a Group VA element; for example, the first element can be at least one of phosphorus and arsenic; the second element includes a Group IIIA element; for example, the second element can be at least one of boron and aluminum.

[0070] In some embodiments, refer to Figure 1 As shown, the solar cell also includes an isolation region A3, which is located between the first semiconductor layer 23 and the second semiconductor layer 27. Thus, the first semiconductor layer 23 and the second semiconductor layer 27 are isolated by the isolation region A3 to prevent them from contacting each other, thereby achieving electrical isolation between the first semiconductor layer 23 and the second semiconductor layer 27 and preventing majority and minority carrier recombination at the interface, which would reduce cell efficiency.

[0071] In some embodiments, refer to Figure 1 As shown, isolation zone A3 has a pyramid structure.

[0072] In some embodiments, refer to Figure 1 As shown, the solar cell also includes a passivation layer 30, which covers the back surface 21a of the substrate 21 of the first semiconductor layer 23, the second semiconductor layer 27, and the isolation region A3.

[0073] Reference Figure 1 As shown, the passivation layer 30 may include at least one layer selected from aluminum oxide, silicon oxide, and silicon nitride, or the passivation layer 30 may include multiple layers stacked together. The passivation layer 30 covers the first semiconductor layer 23, the second semiconductor layer 27, and the substrate 21 of the isolation region A3.

[0074] For example, refer to Figure 1 As shown, the passivation layer 30 may include an aluminum oxide layer 31 and a silicon nitride layer 32 stacked sequentially. The aluminum oxide layer 31 can effectively block impurities and moisture from the external environment from corroding the inside of the battery. At the same time, aluminum oxide can also reduce the number of dangling bonds on the surface of the substrate 21, thereby reducing the surface recombination rate and improving the open-circuit voltage and short-circuit current of the battery. The silicon nitride layer 32 has good insulation properties and corrosion resistance, which can further reduce recombination losses on the surface of the substrate 21.

[0075] In some embodiments, refer to Figure 1As shown, the solar cell also includes a first metal electrode 41 and a second metal electrode 42. The first metal electrode 41 is disposed on the side of the first semiconductor layer 23 away from the substrate 21, and the first metal electrode 41 is electrically connected to the first semiconductor layer 23; the second metal electrode 42 is disposed on the side of the second semiconductor layer 27 away from the substrate 21, and the second metal electrode 42 is electrically connected to the second semiconductor layer 27.

[0076] Reference Figure 1 As shown, the passivation layer 30 covers the surface of the first semiconductor layer 23 and the second semiconductor layer 27 away from the substrate 21. The first metal electrode 41 passes through the passivation layer 30 and is electrically connected to the first semiconductor layer 23, and the second metal electrode 42 passes through the passivation layer 30 and is electrically connected to the second semiconductor layer 27.

[0077] According to an exemplary embodiment, this embodiment provides a method for manufacturing a solar cell, wherein the solar cell is the solar cell described in the above embodiment. (Refer to...) Figure 4 As shown, the method for manufacturing a solar cell includes the following steps:

[0078] Step S101: Provide a substrate, the back side of which includes a first region and a second region. In this embodiment, the substrate is doped with antimony.

[0079] Step S102: Form a first semiconductor layer in the first region and dope the first semiconductor layer with a first element having a first conductivity type.

[0080] Step S103: Form a second semiconductor layer in the second region and dope the second semiconductor layer with a second element having a second conductivity type.

[0081] The solar cell fabrication method of this embodiment uses an antimony-doped substrate 21, which can increase the majority carrier concentration in the substrate 21, optimize the carrier transport efficiency of the cell, and improve the fill factor of the cell. By optimizing the process flow, a first semiconductor layer 23 doped with the first element is first formed on the back side of the substrate 21, and then a second semiconductor layer 27 doped with the first element is formed on the back side of the substrate 21. This reduces the number of times and the duration of high-temperature treatment of the second semiconductor layer 27, thereby reducing the diffusion of antimony from the substrate 21 to the second semiconductor layer 27. As a result, the antimony content in the second semiconductor layer 27 is lower than the antimony content in the first semiconductor layer 23, which reduces the impact of antimony on the performance of the second semiconductor layer 27. This is beneficial to improving the encapsulation effect of the second semiconductor layer 27, thereby improving the encapsulation effect of the solar cell, improving the efficiency, reliability, and stability of the cell, and facilitating the improvement of cell yield and industrialization.

[0082] In some embodiments, the substrate 21 is n-type. The first semiconductor layer 23 is n-type, and the second semiconductor layer 27 is p-type.

[0083] The first element includes elements of Group VA; for example, the first element can be at least one of phosphorus and arsenic; the second element includes elements of Group IIIA; for example, the second element can be at least one of boron and aluminum.

[0084] Thus, the first semiconductor layer 23, doped with more antimony, can improve its conductivity and reduce the contact resistance between the first semiconductor layer 23 and the first metal electrode 41. The second semiconductor layer 27, doped with less antimony, can reduce the number of minority carriers in the second semiconductor layer 27 that combine with antimony, thereby increasing the number of minority carriers in the second semiconductor layer 27. This is beneficial for improving the conductivity of the second semiconductor layer 27, enhancing its passivation effect, and ultimately improving the passivation effect of the battery, thus contributing to higher battery yield and industrialization.

[0085] In step S101, refer to Figure 5 As shown, the substrate 21 used in this embodiment is a silicon substrate. In other embodiments, substrates made of semiconductor materials such as germanium-silicon substrates or germanium substrates can also be selected to fabricate the battery. The back side of substrate 21 includes alternating first regions A1 and second regions A2.

[0086] In this embodiment, the substrate 21 has an n-type conductivity and is doped with antimony. The concentration of antimony in the substrate 21 is 1 × 10⁻⁶. 14 cm -3 -1×10 18 cm -3 The resistivity of substrate 21 is 10Ω-50Ω. In this embodiment, antimony is doped into substrate 21, which significantly increases the majority carrier concentration in substrate 21, thereby improving the short-circuit current and open-circuit voltage of the battery, which is beneficial to improving the long-term stability and lifespan of the battery. In this embodiment, phosphorus is also doped into substrate 21, and the phosphorus concentration is greater than 1×10⁻⁶. 14 cm -3 -1×10 18 cm -3 .

[0087] In some embodiments, after providing the substrate 21, the front side 21b and the back side 21a of the substrate 21 are alkaline polished. After polishing, the surface reflectivity of the substrate 21 is 35%-45%.

[0088] In step S102, in this embodiment, refer to Figure 5 As shown, a first tunneling layer 22 and a first amorphous silicon layer 23a can be sequentially formed on the back side 21a of the substrate 21 using low-pressure chemical vapor deposition (LPCVD).

[0089] For example, the temperature at which the first amorphous silicon layer 23a is deposited is 500°C-650°C, such as 500°C, 510°C, 520°C, 535°C, 545°C, 550°C, 560°C, 570°C, 580°C, 590°C, 610°C, 630°C or 650°C.

[0090] For example, the thickness of the first tunneling layer 22 is 0.5nm-3nm, and the thickness of the first amorphous silicon layer 23a is 50nm-350nm.

[0091] Then, a first element is doped into the first amorphous silicon layer 23a to form a first semiconductor layer 23. This embodiment can be implemented using the following method: Refer to... Figure 5 As shown, an atomic layer deposition method is used to deposit a phosphorus silicate glass layer 25 on the side of the first amorphous silicon layer 23a away from the substrate 21. (Refer to...) Figure 6 As shown, the substrate 21 is subjected to thermal annealing at a temperature of 800℃-1000℃ to diffuse phosphorus from the phosphorus-silicon phosphate glass layer 25 into the first amorphous silicon layer 23a to form the first semiconductor layer 23, which has an n-type conductivity. The thermal annealing causes some antimony from the substrate 21 to diffuse through the first tunneling layer 22 into the first semiconductor layer 23, thereby doping the first semiconductor layer 23 with antimony.

[0092] The first semiconductor layer 23 is doped with a first element having a first conductivity type, and the doping concentration of the first element in the first semiconductor layer 23 is 1×10⁻⁶. 20 cm -3 -5×10 20 cm -3 In this embodiment, the first element is phosphorus.

[0093] like Figure 2 The diagram shows the antimony doping concentration curves in the first semiconductor layer 23 and the underlying substrate 21. The antimony doping concentration in the first semiconductor layer 23 is 1 × 10⁻⁶. 9 cm -3 -1×10 14 cm -3 .

[0094] In this embodiment, after doping the first amorphous silicon layer 23a with a first element to form a first semiconductor layer 23, a mask layer (not shown in the figure) is formed on the side of the phosphorus silicon glass layer 25 away from the substrate 21. The mask layer covers the phosphorus silicon glass layer 25 of the first region A1. (Refer to...) Figure 7 As shown, the phosphorus silicate glass layer 25, the first semiconductor layer 23 and the first tunneling layer 22 other than the first region A1 are removed by mask etching, exposing the back surface 21a of the substrate 21 of the second region A2. The first region A1 and the second region A2 are alternately arranged on the back surface 21a of the substrate 21.

[0095] For example, the phosphorus silicon glass layer 25, the first semiconductor layer 23, and the first tunneling layer 22 can be etched using a dry process or a wet process.

[0096] In step S103, refer to Figure 8 As shown, a second tunneling layer 26 and a second amorphous silicon layer 27a can be sequentially formed on the back side 21a of the substrate 21 using low-pressure chemical vapor deposition (LPCVD). The second tunneling layer 26 and the second amorphous silicon layer 27a cover the exposed back side 21a of the substrate 21. The second tunneling layer 26 and the second amorphous silicon layer 27a also cover the first tunneling layer 22, the first semiconductor layer 23, and the phosphosilicate glass layer 25 in the first region A1. The second tunneling layer 26 is a silicon oxide layer.

[0097] For example, the temperature at which the second amorphous silicon layer 27a is deposited is 500°C-650°C. For instance, it can be 500°C, 510°C, 520°C, 530°C, 550°C, 565°C, 575°C, 585°C, 595°C, 605°C, 615°C, 625°C, 635°C, 645°C, or 650°C.

[0098] For example, the thickness of the second tunneling layer 26 is 0.5nm-3nm, and the thickness of the second amorphous silicon layer 27a is 50nm-350nm.

[0099] Then, a second element is doped into the second amorphous silicon layer 27a to form a second semiconductor layer 27. (Refer to...) Figure 8 As shown, an atomic layer deposition method can be used to deposit a borosilicate glass layer 29 on the side of the second amorphous silicon layer 27a away from the substrate 21. (Refer to...) Figure 9 As shown, the substrate 21 is subjected to thermal annealing at a temperature of 900℃-1100℃ to diffuse boron from the borosilicate glass layer 29 into the second amorphous silicon layer 27a to form the second semiconductor layer 27. In this embodiment, the second element is boron.

[0100] During the thermal annealing process, some antimony elements in the substrate 21 further diffuse into the first semiconductor layer 23, so that the concentration of antimony elements in the first semiconductor layer 23 is higher and the distribution of antimony elements in the first semiconductor layer 23 is more uniform, so that the number of majority carriers in the first semiconductor layer 23 is greater and the conductivity of the first semiconductor layer 23 is better.

[0101] Reference Figure 3 The diagram shows the antimony concentration curves in the second semiconductor layer 27 and the underlying substrate 21 after doping. The antimony concentration in the second semiconductor layer 27 after doping is 1 × 10⁻⁶. 8 cm -3 -1×10 13cm -3 .

[0102] In some embodiments, during the process of doping the second element into the second semiconductor layer 27, some of the antimony element in the substrate 21 also diffuses into the second semiconductor layer 27, and the concentration of antimony element in the first semiconductor layer 23 is greater than the concentration of antimony element in the second semiconductor layer 27.

[0103] It is understandable that the first semiconductor layer 23 is subjected to high-temperature treatment many times and for a longer duration. Antimony element is present in the first semiconductor layer 23 along its thickness direction, and the antimony element is uniformly distributed in the first semiconductor layer 23. The first semiconductor layer 23 has high uniformity and lower resistance, which can improve the electrical performance of the first semiconductor layer 23.

[0104] The second semiconductor layer 27 undergoes fewer high-temperature treatments and shorter treatment times, resulting in less antimony doping. Furthermore, the antimony content on the side of the second semiconductor layer 27 furthest from the substrate 21 is lower than that on the side closer to the substrate 21. This reduces the adverse effects of antimony on the passivation effect of the second semiconductor layer 27, thus improving its passivation performance. It is understood that the passivation effect of the second semiconductor layer 27 represents the lowest point of passivation in the solar cell. This embodiment improves the passivation effect of the second semiconductor layer 27, which is equivalent to improving the passivation effect of the solar cell, thereby contributing to higher cell yield and industrialization.

[0105] In some embodiments, refer to Figure 2 , Figure 3 The total amount of antimony in the first semiconductor layer 23 is greater than the total amount of antimony in the second semiconductor layer 27.

[0106] In some embodiments, the average concentration of antimony in the first semiconductor layer 23 is greater than the average concentration of antimony in the second semiconductor layer 27.

[0107] In some embodiments, at the same distance from the substrate 21, the concentration of antimony in the first semiconductor layer 23 is greater than the concentration of antimony in the second semiconductor layer 27.

[0108] In some embodiments, this embodiment provides a method for manufacturing a solar cell, and after step S103, the following steps are also performed:

[0109] Step S104: Pattern the second semiconductor layer 27 and the second tunneling layer 26, and remove the second semiconductor layer 27 and the second tunneling layer 26 located outside the second region A2.

[0110] In this embodiment, refer to Figure 10As shown, a mask layer (not shown) is formed on the side of the borosilicate glass layer 29 away from the substrate 21. The mask layer covers the borosilicate glass layer 29 of the second region A2. The borosilicate glass layer 29, the second semiconductor layer 27, and the second tunneling layer 26 outside the second region A2 are removed by etching according to the mask layer.

[0111] Step S105: After patterning the second semiconductor layer 27 and the second tunneling layer 26, the back surface 21a of the substrate 21 of the isolation region A3 is exposed. (Refer to...) Figure 10 As shown, isolation region A3 is used to isolate the first semiconductor layer 23 and the second semiconductor layer 27 to prevent majority and minority carriers from recombining at the interface between the first semiconductor layer 23 and the second semiconductor layer 27, thereby reducing battery efficiency.

[0112] Then, the film layer deposited around the side and front sides 21b of the substrate 21 is etched away to expose the side and front sides 21b of the substrate 21 for processing of the substrate 21.

[0113] Step S106: Refer to Figure 11 The isolation area A3 of the front side 21b and back side 21a of the substrate 21 is texturized to form a pyramid structure. This increases the light-receiving area of ​​the substrate 21 and improves the photoelectric conversion efficiency of the cell. The width of the pyramid base is 5μm-30μm.

[0114] Step S107: Refer to Figure 11 The phosphosilicate glass layer 25 and the borosilicate glass layer 29 are removed. In this embodiment, a wet etching process can be used to remove the phosphosilicate glass layer 25 and the borosilicate glass layer 29.

[0115] Step S108: Form a passivation layer 30, which covers the back surface 21a of the substrate 21 of the first semiconductor layer 23, the second semiconductor layer 27, and the isolation region A3. (Refer to...) Figure 12 As shown, in this embodiment, passivation layers 30 are deposited on both the front side 21b and the back side 21a of the substrate 21. The passivation layers 30 are used to protect the first semiconductor layer 23, the second semiconductor layer 27, and the substrate 21, which is beneficial to improving the photoelectric conversion efficiency and stability of the solar cell.

[0116] In this embodiment, refer to Figure 12 As shown, the passivation layer 30 may include an aluminum oxide layer 31 and a silicon nitride layer 32 stacked sequentially.

[0117] For example, an aluminum oxide layer 31 can be formed by atomic layer deposition. The aluminum oxide layer 31 covers the first tunneling layer 22 and the first semiconductor layer 23 in the first region A1. The aluminum oxide layer 31 also covers the second tunneling layer 26 and the second semiconductor layer 27 in the second region A2. The aluminum oxide layer 31 also covers the isolation region A3 on the back side 21a of the substrate 21 and the front side 21b of the substrate 21. The aluminum oxide layer 31 can effectively block impurities and moisture from the external environment from corroding the inside of the battery. At the same time, aluminum oxide can reduce the number of dangling bonds on the surface of the substrate 21, thereby reducing the surface recombination rate and improving the open-circuit voltage and short-circuit current of the battery.

[0118] For example, an atomic layer deposition method can be used to form a silicon nitride layer 32, which covers an aluminum oxide layer 31. The silicon nitride layer 32 has good insulation properties and corrosion resistance, and can further reduce recombination losses on the surface of the substrate 21.

[0119] Both the aluminum oxide layer 31 and the silicon nitride layer 32 have good light transmittance, which is beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0120] Step S109: A first metal electrode 41 is formed on the side of the first semiconductor layer 23 away from the substrate 21, and the first metal electrode 41 is electrically connected to the first semiconductor layer 23; a second metal electrode 42 is formed on the side of the second semiconductor layer 27 away from the substrate 21, and the second metal electrode 42 is electrically connected to the second semiconductor layer 27.

[0121] Reference Figure 1 As shown, the first metal electrode 41 passes through the passivation layer 30 and is electrically connected to the first semiconductor layer 23. Since the first semiconductor layer 23 is doped with a large amount of antimony, the number of majority carriers in the first semiconductor layer 23 is greater, and the first metal electrode 41 and the first semiconductor layer 23 form a good ohmic contact, which is beneficial to reducing the contact resistance between the first metal electrode 41 and the first semiconductor layer 23.

[0122] Reference Figure 1 As shown, the second metal electrode 42 passes through the passivation layer 30 and is electrically connected to the second semiconductor layer 27. Because the second semiconductor layer 27 is doped with less antimony, it has a higher number of minority carriers, resulting in a good ohmic contact between the second metal electrode 42 and the second semiconductor layer 27. This helps reduce the contact resistance between the two layers. Consequently, this reduces the overall resistance of the solar cell, decreases electrical losses caused by resistance, and further improves the photoelectric conversion efficiency of the solar cell.

[0123] For example, the first metal electrode 41 and the second metal electrode 42 can be formed by screen printing.

[0124] According to an exemplary embodiment, this embodiment provides a stacked battery 1, referring to... Figure 13 , Figure 14 , Figure 15 As shown, the tandem solar cell 1 includes a bottom cell 20 and a top cell 50 stacked on the bottom cell 20. The bottom cell 20 includes a solar cell from the above embodiments or a solar cell fabricated using the method described in the above embodiments. The top cell 50 includes a perovskite cell. The perovskite cell comprises a transparent electrode layer, an electron transport layer, a perovskite light absorption layer, and a hole transport layer sequentially stacked on the solar cell. The tandem solar cell 1 in this embodiment can be a two-terminal, three-terminal, or four-terminal tandem solar cell. The tandem solar cell 1 of this embodiment is compatible with both solar and perovskite cells, offering advantages such as high current compatibility, high process tolerance, and wider applicability in outdoor scenarios, thus possessing greater development and application potential.

[0125] In one example, such as Figure 13 As shown, the tandem solar cell 1 is a two-terminal tandem solar cell. The perovskite cell is disposed on one side of the back of the solar cell, and the perovskite cell and the solar cell are connected in series. The positive electrode of the solar cell is connected to the negative electrode of the perovskite cell, with the positive electrode of the perovskite cell serving as the positive electrode of the tandem solar cell 1, and the negative electrode of the solar cell serving as the negative electrode of the tandem solar cell 1. An intermediate connecting layer can also be provided between the perovskite cell and the solar cell, with the negative electrode of the perovskite cell connected to the positive electrode of the solar cell through the intermediate connecting layer. The intermediate connecting layer can be a transparent conductive oxide layer or a composite layer.

[0126] In another example, such as Figure 14 As shown, the tandem solar cell 1 is a three-terminal tandem solar cell. The tandem solar cell 1 includes a solar cell, a perovskite cell, and a common electrode layer. The perovskite cell is stacked on top of the solar cell, and the common electrode layer is located between the perovskite cells. The first metal electrode of the solar cell is the positive electrode, and the second metal electrode is the negative electrode. The negative electrode of the perovskite cell and the positive electrode of the solar cell are connected to the common electrode layer. The common electrode layer is a transparent conductive material or a composite material layer with specific optical properties, used to optimize the transmission and distribution of photogenerated charge. The positive electrode of the perovskite cell is connected to its transparent electrode layer. Thus, the top cell 50 and the bottom cell 20 of the tandem solar cell 1 each have independent output electrodes, and both share some charge with the common electrode layer through optical coupling or electrical connection; the photogenerated current of the top cell 50 and the bottom cell 20 can be output partially independently, or integrated through the current of the common electrode layer.

[0127] In yet another example, such as Figure 15As shown, the tandem solar cell 1 is a four-terminal tandem solar cell. Tandem solar cell 1 includes a solar cell and a perovskite cell stacked on top of the solar cell. The solar cell and the perovskite cell achieve efficient utilization of light energy through optical coupling, but are completely independent electrically. The perovskite cell and the solar cell each have independent positive and negative electrodes, used to collect and transfer photogenerated charges, respectively; the electrodes of the perovskite cell and the solar cell are independently connected to external circuits to achieve their respective photogenerated current outputs; there is no direct electrical connection between the perovskite cell and the solar cell, and spectral segmentation and light energy distribution are achieved only through optical design.

[0128] According to an exemplary embodiment, this embodiment provides a photovoltaic module, including a solar cell as described in the above embodiments, or a solar cell manufactured by the method for manufacturing a solar cell as described in the above embodiments, or a tandem cell as described in the above embodiments.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A solar cell, characterized in that, include: A substrate having a first conductivity type, the substrate being doped with antimony; A first semiconductor layer is disposed on the back side of the substrate, and the first semiconductor layer has the same conductivity type as the substrate; A second semiconductor layer is disposed on the back side of the substrate, and the second semiconductor layer and the first semiconductor layer are alternately disposed on the back side of the substrate, wherein the conductivity type of the second semiconductor layer is opposite to that of the substrate; The concentration of antimony in the first semiconductor layer is greater than the concentration of antimony in the second semiconductor layer; The antimony doping concentration in the first semiconductor layer is 1×10⁻⁶. 9 cm -3 -1×10 14 cm -3 The antimony doping concentration in the second semiconductor layer is 1×10⁻⁶. 8 cm -3 -1×10 13 cm -3 ; The first semiconductor layer is doped with a first element having a first conductivity type, and the doping concentration of the first element in the first semiconductor layer is 1×10⁻⁶. 20 cm -3 -5×10 20 cm -3 ; The second semiconductor layer has a second element of a second conductivity type, and the doping concentration of the second element in the second semiconductor layer is 2 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 .

2. The solar cell according to claim 1, characterized in that, The diffusion depth of antimony in the first semiconductor layer is greater than that of antimony in the second semiconductor layer.

3. The solar cell according to claim 1, characterized in that, The solar cell also includes: An isolation region is located between the first semiconductor layer and the second semiconductor layer; A passivation layer that covers the back side of the substrate of the first semiconductor layer, the second semiconductor layer, and the isolation region.

4. The solar cell according to claim 3, characterized in that, The solar cell also includes: A first metal electrode is disposed on the side of the first semiconductor layer away from the substrate, and the first metal electrode is electrically connected to the first semiconductor layer. A second metal electrode is disposed on the side of the second semiconductor layer away from the substrate, and the second metal electrode is electrically connected to the second semiconductor layer.

5. The solar cell according to claim 4, characterized in that, The antimony doping concentration in the substrate is 1×10⁻⁶. 14 cm -3 -1×10 18 cm -3 .

6. The solar cell according to claim 1, characterized in that, The total amount of antimony in the first semiconductor layer is greater than the total amount of antimony in the second semiconductor layer.

7. The solar cell according to claim 1, characterized in that, The average concentration of antimony in the first semiconductor layer is greater than the average concentration of antimony in the second semiconductor layer.

8. The solar cell according to claim 1, characterized in that, At the same distance from the substrate, the concentration of antimony in the first semiconductor layer is greater than the concentration of antimony in the second semiconductor layer.

9. A method for manufacturing a solar cell, wherein the solar cell is the solar cell according to any one of claims 1-8, characterized in that, The manufacturing method includes: A substrate is provided, the back side of which includes a first region and a second region; A first semiconductor layer is formed in the first region, and a first element having a first conductivity type is doped into the first semiconductor layer; the doping concentration of the first element in the first semiconductor layer is 1×10⁻⁶. 20 cm -3 -5×10 20 cm -3 ; A second semiconductor layer is formed in the second region, and a second element having a second conductivity type is doped into the second semiconductor layer; the doping concentration of the second element in the second semiconductor layer is 2 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 ; The formation of the first semiconductor layer includes at least two thermal annealing processes; the formation of the second semiconductor layer includes one thermal annealing process; the antimony doping concentration in the first semiconductor layer is 1 × 10⁻⁶. 9 cm -3 -1×10 14 cm -3 The antimony doping concentration in the second semiconductor layer is 1×10⁻⁶. 8 cm -3 -1×10 13 cm -3 .

10. The method for manufacturing a solar cell according to claim 9, characterized in that, The first element includes elements of Group VA; the second element includes elements of Group IIIA.

11. A stacked battery, characterized in that, Includes a bottom battery and a top battery stacked on the bottom battery; The bottom cell includes a solar cell as described in any one of claims 1-8, or a solar cell manufactured by the method described in claim 9 or 10; the top cell includes a perovskite cell.

12. A photovoltaic module, characterized in that, The solar cell includes any one of claims 1-8, or a solar cell manufactured by the method of manufacturing a solar cell as described in claim 9 or 10, or a tandem cell as described in claim 11.

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