Passivation contact structure and preparation method thereof, solar cell and photovoltaic module

Abstract

The invention discloses a passivation contact structure and a preparation method thereof, a solar cell and a photovoltaic module. The passivation contact structure is used for the surface of a silicon wafer, the passivation contact structure comprises a silicon oxide layer stacked on the surface of the silicon wafer and a doped polycrystalline silicon layer stacked on the silicon oxide layer, the silicon oxide layer comprises a first silicon oxide sub-layer and a second silicon oxide sub-layer, the first silicon oxide sub-layer is arranged close to the silicon wafer, the thickness of the first silicon oxide sub-layer is 0.2-0.5 nm, the refractive index of the first silicon oxide sub-layer is 1.48-1.53, and the thickness of the second silicon oxide sub-layer is 0.2-0.5 nm. The second silicon dioxide layer is arranged close to the doped polycrystalline silicon layer, the thickness of the second silicon dioxide layer is 1-2 nm, and the refractive index of the second silicon dioxide layer is 1.40-1.45. The mode that the first silicon oxide sub-layer is matched with the second silicon oxide sub-layer is adopted, and the overall passivation effect of the passivation contact structure and shortening of the beat time are achieved at the same time.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to a passivation contact structure and a preparation method thereof, a solar cell, and a photovoltaic module. Background Art

[0002] In solar cells, the passivation contact structure on the surface of the silicon wafer is a silicon oxide layer superimposed on a polysilicon layer (poly layer). This passivation contact structure allows majority electrons to pass through the silicon oxide layer into the polysilicon layer while blocking the recombination of minority holes. As a result, electrons are laterally transmitted in the polysilicon layer and collected by the metal, reducing the metal contact recombination current and improving the open circuit voltage and short circuit current of the battery.

[0003] To achieve higher solar cell efficiency, silicon oxide layers are generally required to be dense and uniform. However, this also increases the time and cost of preparing the silicon oxide layer, making it difficult to meet the production line's takt time requirements. To meet this takt time requirement, the silicon oxide layer's growth rate is increased, resulting in poor density and uniformity, severe Auger recombination, and poor passivation performance. Summary of the Invention

[0004] The embodiments of the present invention disclose a passivation contact structure and a preparation method thereof, a solar cell, and a photovoltaic module. The passivation contact structure has both excellent passivation effect and short cycle time.

[0005] In a first aspect, embodiments of the present application provide a passivation contact structure.

[0006] The passivation contact structure is used for the surface of a silicon wafer. The passivation contact structure includes a silicon oxide layer stacked on the surface of the silicon wafer and a doped polysilicon layer stacked on the silicon oxide layer. The silicon oxide layer includes a first silicon oxide sublayer and a second silicon oxide sublayer. The first silicon oxide sublayer is arranged close to the silicon wafer, has a thickness of 0.2nm to 0.5nm, and a refractive index of 1.48 to 1.53. The second silicon oxide sublayer is arranged close to the doped polysilicon layer, has a thickness of 1nm to 2nm, and a refractive index of 1.40 to 1.45.

[0007] As an optional implementation, in an embodiment of the present invention, the non-uniformity of the thickness of the first silicon oxide sub-layer is 10% to 20%, and the non-uniformity of the thickness of the second silicon oxide sub-layer is 25% to 35%.

[0008] As an optional implementation, in an embodiment of the present invention, the material of the silicon oxide layer is silicon oxide; and / or the silicon wafer is a normal wafer or a reworked wafer, and the surface of the reworked wafer does not include a wet oxide layer.

[0009] Second aspect, an embodiment of the present application provides a method for preparing a passivated contact structure.

[0010] The passivated contact structure is prepared on the surface of a silicon wafer by chemical vapor deposition. The method for preparing the passivated contact structure includes the following steps:

[0011] Prepare a silicon oxide layer:

[0012] Prepare a first silicon oxide sub-layer: Deposit the first silicon oxide sub-layer on the surface of the silicon wafer, control the deposition rate of the first silicon oxide sub-layer to be 0.005 Å / s to 0.01 Å / s, and the deposition time to be 200 s to obtain the first silicon oxide sub-layer;

[0013] Prepare a second silicon oxide sub-layer: Deposit the second silicon oxide sub-layer on the surface of the first silicon oxide sub-layer, control the deposition rate of the second silicon oxide sub-layer to be 0.2 Å / s to 0.4 Å / s, and the deposition time to be 50 s to obtain the second silicon oxide sub-layer;

[0014] Prepare an intrinsic amorphous silicon layer and a doped amorphous silicon layer: Sequentially prepare the intrinsic amorphous silicon layer and the doped amorphous silicon layer on the surface of the second silicon oxide sub-layer;

[0015] Annealing: After the annealing treatment, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are crystallized and transformed into a doped polycrystalline silicon layer to obtain the passivated contact structure mentioned in the first aspect.

[0016] As an optional implementation manner, in the embodiment of the present invention, in the step of preparing the silicon oxide layer, the deposition temperature is 400 °C to 500 °C, the process pressure is 1000 mT to 3000 mT, and the gas flow rate of the oxygen-containing gas is 5000 sccm to 10000 sccm, where the oxygen-containing gas is one or more of N2O, CO2, CO, O2, and NO;

[0017] When preparing the first silicon oxide sub-layer, control the power to be 0.5 kW to 6 kW, the duty cycle to be 0.5% to 2%, the frequency to be pure low frequency or a combination of low frequency and high frequency, and the time ratio of low frequency to high frequency to be greater than or equal to 10%;

[0018] When preparing the second silicon oxide sub-layer, control the power to be 0.5 kW to 6 kW, the duty cycle to be 3% to 10%, the frequency to be pure low frequency or a combination of low frequency and high frequency, and the time ratio of low frequency to high frequency to be greater than or equal to 1%.

[0019] As an alternative embodiment, in the embodiments of the present invention, in the step of preparing the intrinsic amorphous silicon layer, the deposition temperature is 400°C to 500°C, the process pressure is 2000 mT to 5000 mT, and the power is 5.0 kW to 8.0 kW. In the step of preparing the doped amorphous silicon layer, the deposition temperature is 400°C to 500°C, the process pressure is 3000 mT to 5000 mT, the power is 6.0 kW to 10 kW, and the doping mass concentration of the doping element is 1% to 10%; and / or,

[0020] The annealing is annealing treatment at 800°C to 1000°C for 20 min to 60 min.

[0021] In a third aspect, the present application provides a solar cell.

[0022] The solar cell includes a passivation contact structure as mentioned in the first aspect or a passivation contact structure prepared by the preparation method as mentioned in the second aspect.

[0023] As an alternative embodiment, in the embodiments of the present invention, the solar cell is a passivation contact solar cell or a perovskite-passivation contact tandem solar cell.

[0024] As an alternative embodiment, in the embodiments of the present invention, the passivation contact solar cell includes:

[0025] A silicon wafer having a first conductivity type;

[0026] A doped layer and a first functional layer sequentially disposed on the light-receiving surface of the silicon wafer; the doped layer has a second conductivity type, and one of the first conductivity type and the second conductivity type is N-type and the other is P-type;

[0027] The passivation contact structure and a second functional layer sequentially disposed on the backlight surface of the silicon wafer;

[0028] A first electrode and a second electrode, the first electrode forms an ohmic contact with the doped layer, and the second electrode forms an ohmic contact with the passivation contact structure.

[0029] As an alternative embodiment, in the embodiments of the present invention, the perovskite-passivation contact tandem solar cell is composed of a perovskite top cell and a passivation contact bottom cell. A carrier transport layer is provided on the surface of the passivation contact bottom cell to connect the perovskite top cell and the passivation contact bottom cell. The passivation contact bottom cell includes:

[0030] A silicon wafer, the silicon wafer having a first conductivity type;

[0031] A doping layer and a first functional layer sequentially disposed on one surface of the silicon wafer; the doping layer has a second conductivity type, and one of the first conductivity type and the second conductivity type is N-type and the other is P-type;

[0032] A passivated contact structure disposed on the other surface of the silicon wafer;

[0033] It further includes a first electrode, and the first electrode forms an ohmic contact with the doping layer;

[0034] The carrier transport layer is disposed on the surface of the passivated contact structure.

[0035] As an optional implementation manner, in the embodiment of the present invention, the junction depth of the doping layer is 50 nm to 300 nm; and / or,

[0036] The first functional layer includes a passivation layer and an antireflection layer, the thickness of the passivation layer is 3 nm to 10 nm, and the thickness of the antireflection layer is 70 nm to 100 nm; and / or,

[0037] The thickness of the carrier transport layer is 10 nm to 40 nm; and / or,

[0038] The perovskite top cell includes a hole transport layer, a perovskite layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, an antireflection layer, and a second electrode sequentially stacked on the carrier transport layer. The fine grid height of the second electrode is 5 μm to 50 μm, the width is 10 μm to 100 μm, the main grid height is 5 μm to 50 μm, and the width is 50 μm to 150 μm.

[0039] In a fourth aspect, the present application provides a photovoltaic module.

[0040] A photovoltaic module includes the solar cell described in the third aspect.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0042] It is found in this application that the silicon oxide layer is divided into a first silicon oxide sub-layer close to the surface of the silicon wafer and a second silicon oxide sub-layer close to the doped polysilicon layer. The first silicon oxide sub-layer has a higher density, while the second silicon oxide sub-layer is relatively loose and has a lower density. The combination of the first silicon oxide sub-layer and the second silicon oxide sub-layer with specific thicknesses has excellent synergistic effects. It can not only effectively reduce the cycle time of the silicon oxide layer and improve industrial production, but also enhance the passivation effect of the overall passivated contact structure, effectively ensuring the efficiency of the solar cell. This is because the first silicon oxide sub-layer has a high density, which can effectively prevent the doping elements in the doped polysilicon layer from passing through the first silicon oxide layer to reach the surface of the silicon wafer, reducing Auger recombination on the silicon wafer surface and increasing the minority carrier lifetime. The second silicon oxide sub-layer is relatively loose, which is beneficial to the diffusion of the doping elements in the doped polysilicon layer to the second silicon oxide sub-layer, enhancing the field passivation effect of the doped polysilicon layer. Therefore, by combining a first silicon oxide layer with a relatively thin thickness and a second silicon oxide sub-layer with a relatively thick thickness, the field passivation effect of the doped polysilicon layer can be ensured, and Auger recombination on the silicon wafer can be minimized to the greatest extent.

[0043] Moreover, the thickness of the first silicon oxide sub-layer is 0.2 nm to 0.5 nm, and the refractive index is 1.48 to 1.53. Its preparation can be completed within 200 s. In addition, due to the high density of the first silicon oxide sub-layer close to the silicon wafer, the required production rate is relatively slow, which can effectively reduce the interface damage of the silicon wafer and reduce the interface defects of the silicon wafer. The thickness of the second silicon oxide sub-layer is 1 nm to 2 nm, and the refractive index is 1.40 to 1.45. Its preparation can be completed within 50 s. The total deposition time of the silicon oxide layer is 250 s, which is close to the time for producing the silicon oxide layer in the current production line, effectively ensuring the cycle time of the production line. Therefore, the overall production time of the silicon oxide layer is short, effectively improving the cycle time of the passivated contact structure production. Moreover, the prepared passivated contact structure has an excellent passivation effect, and the silicon wafer interface is not easily damaged, making it suitable for industrial production and showing significant progress.

[0044] When the density of the first silicon oxide sub-layer or the second silicon oxide sub-layer is too high, the overall density of the silicon oxide layer increases, and the impurity source of the doped crystalline silicon layer has a greater obstacle to entering the silicon oxide layer, resulting in a decrease in the field passivation effect of the polysilicon layer. When the density of the first silicon oxide sub-layer decreases, the overall quality of the silicon oxide layer drops significantly, the passivation effect decreases very obviously, and it is easy to cause more impurity sources of the polysilicon layer to diffuse through the first silicon oxide layer to reach the surface of the silicon wafer or even enter the silicon wafer, leading to an increase in Auger recombination and a worse passivation effect. Description of the Drawings

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0046] Figure 1 is a schematic structural diagram of a front-passivated contact bottom cell disclosed in an embodiment of the present invention;

[0047] Figure 2 is a schematic structural diagram of a perovskite-passivated contact tandem solar cell disclosed in an embodiment of the present invention;

[0048] Figure 3 is a schematic structural diagram of a perovskite-passivated contact tandem solar cell disclosed in Comparative Example 1 of the present invention;

[0049] Figure 4 is a comparison diagram of the simulated minority carrier lifetime test structures of Embodiment 1 and Comparative Example 4 of the present invention.

[0050] Reference numerals: 100, passivated contact bottom cell; 11, silicon wafer; 12, passivated contact structure; 121, silicon oxide layer; 1211, first silicon oxide sub-layer; 1212, second silicon oxide sub-layer; 122, doped polysilicon layer; 13, carrier exchange layer; 14, doped layer; 15, first functional layer; 151, passivation layer; 152, antireflection layer; 16, first electrode; 200, perovskite top cell; 21, second electrode. Detailed embodiments

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0052] In addition, the terms "installed", "set", "provided with", "connected", "connected to" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there is internal communication between two devices, components or parts. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] In addition, terms such as "first", "second", etc. are mainly used to distinguish different devices, components or parts (the specific types and structures may be the same or different), and are not used to indicate or imply the relative importance and quantity of the indicated devices, components or parts. Unless otherwise specified, the meaning of "a plurality" is two or more.

[0054] Currently, the thickness of the silicon oxide layer in the passivation contact structure is 1 nm to 2 nm. The silicon oxide layer with a higher film density (refractive index of about 1.48) has high quality and few defects. The time required to produce the silicon oxide layer with the above thickness is relatively long, generally more than 1000 s, which seriously affects the production cycle time during the production process and is generally not used. The silicon oxide layer with poor film density (refractive index of about 1.44) has a faster production rate and can complete the production of the silicon oxide layer within 100 to 200 s. Currently, the second solution is usually adopted on the production line.

[0055] In order to simultaneously achieve the passivation effect of the overall passivation contact structure and shorten the cycle time, the present application provides a passivation contact structure, a preparation method thereof, a solar cell, and a photovoltaic module.

[0056] The technical solutions of the present invention will be further described below with reference to embodiments and drawings.

[0057] In a first aspect, an embodiment of the present application provides a passivation contact structure 12.

[0058] See Figure 1 , the passivation contact structure 12 is used on the surface of the silicon wafer 11. The passivation contact structure 12 includes a silicon oxide layer 121 stacked on the surface of the silicon wafer 11 and a doped polysilicon layer 122 stacked on the silicon oxide layer 121. The silicon oxide layer 121 includes a first silicon oxide sub-layer 1211 and a second silicon oxide sub-layer 1212. The first silicon oxide sub-layer 1211 is disposed close to the silicon wafer 11, the thickness of the first silicon oxide sub-layer 1211 is 0.2 nm to 0.5 nm, and the refractive index is 1.48 to 1.53. The second silicon oxide sub-layer 1212 is disposed close to the doped polysilicon layer 122, and the thickness of the second silicon oxide sub-layer 1212 is 1 nm to 2 nm, and the refractive index is 1.40 to 1.45.

[0059] It is found in this application that the silicon oxide layer 121 is divided into a first silicon oxide sub-layer 1211 and a second silicon oxide sub-layer 1212. The first silicon oxide sub-layer 1211 has a higher density, while the second silicon oxide sub-layer 1212 is relatively loose and has a lower density. The combination of the first silicon oxide sub-layer 1211 and the second silicon oxide sub-layer 1212 with specific thicknesses has excellent synergistic effects. It can not only effectively reduce the cycle time of the silicon oxide layer 121 and improve industrial output, but also enhance the passivation effect of the entire passivation contact structure 12, effectively ensuring the efficiency of the solar cell. This is because the first silicon oxide sub-layer 1211 has a high density, which can effectively prevent the doping elements of the doped polysilicon layer 122 from passing through the first silicon oxide sub-layer 1211 and reaching the surface of the silicon wafer 11, reducing the occurrence of Auger recombination on the surface of the silicon wafer 11 and improving the minority carrier lifetime. The second silicon oxide sub-layer 1212 is relatively loose, which is conducive to the diffusion of the doping elements of the doped polysilicon layer 122 into the second silicon oxide sub-layer 1212, improving the field passivation effect of the doped polysilicon layer 122. Therefore, by combining the first silicon oxide sub-layer 1211 with a relatively thin thickness and the second silicon oxide sub-layer 1212 with a relatively thick thickness, the field passivation effect of the doped polysilicon layer 122 can be ensured, and the Auger recombination of the silicon wafer 11 can be minimized to the greatest extent.

[0060] Moreover, the thickness of the first silicon oxide sub-layer 1211 is 0.2 nm to 0.5 nm, and the refractive index is 1.48 to 1.53. The preparation can be completed within 200 s. In addition, due to the high density of the first silicon oxide sub-layer 1211 close to the silicon wafer 11, the required production rate is relatively slow, which can effectively reduce the interface damage of the silicon wafer 11 and reduce the interface defects of the silicon wafer 11. The thickness of the second silicon oxide sub-layer 1212 is 1 nm to 2 nm, and the refractive index is 1.40 to 1.45. The preparation can be completed within 50 s. The total deposition time of the silicon oxide layer 121 is 250 s, which is close to the time for producing the silicon oxide layer 121 in the current production line, effectively ensuring the cycle of the production line. Therefore, the overall production time of the silicon oxide layer 121 is short, effectively improving the cycle time of the passivation contact structure 12. The passivation contact structure 12 prepared has an excellent passivation effect, and the interface of the silicon wafer 11 is not easily damaged, which is suitable for industrial production and has significant progress.

[0061] When the density of the first silicon oxide sub-layer 1211 or the second silicon oxide sub-layer 1212 is too high, the overall density of the silicon oxide layer 121 increases, and the hindrance for the impurity source of the doped crystalline silicon layer to enter the silicon oxide layer 121 is large, resulting in a decrease in the field passivation effect of the polysilicon layer. When the density of the first silicon oxide sub-layer 1211 decreases, the overall quality of the silicon oxide layer 121 drops significantly, the passivation effect decreases very obviously, and it is easy to cause more impurity sources of the polysilicon layer to diffuse through the first silicon oxide sub-layer 1211 and reach the surface of the silicon wafer 11 or even enter the silicon wafer 11, resulting in an aggravation of Auger recombination and a deterioration of the passivation effect.

[0062] It should be noted that the material of the above-mentioned silicon oxide layer is silicon oxide. The silicon oxide layer has excellent passivation performance, which can minimize the recombination loss of minority carriers on the surface of the silicon wafer, and has excellent durability for subsequent high-temperature processes.

[0063] In some embodiments, the film thickness non-uniformity of the first silicon oxide sub-layer 1211 is 10% - 20%, and the film thickness non-uniformity of the second silicon oxide sub-layer 1212 is 25% - 35%.

[0064] The film thickness non-uniformity of the first silicon oxide sub-layer 1211 is relatively low and the uniformity is relatively high. Combined with the setting of the relatively high density of the first silicon oxide sub-layer 1211, the quality of the first silicon oxide sub-layer 1211 is improved, which can further reduce the diffusion of doping elements in the doped polysilicon layer 122 through the first silicon oxide sub-layer 1211 and into the surface of the silicon wafer 11, thereby reducing the Auger recombination of the silicon wafer 11 and improving the minority carrier lifetime. The second silicon oxide sub-layer 1212 is relatively loose and the requirement for film thickness non-uniformity is relatively low. By controlling the density and film thickness uniformity, the passivation effect of the passivation contact structure 12 is better after the first silicon oxide sub-layer 1211 and the second silicon oxide sub-layer 1212 are combined.

[0065] In some embodiments, the silicon wafer 11 is a normal wafer or a reworked wafer, and the surface of the reworked wafer does not include a wet oxide layer.

[0066] The silicon wafer 11 is an important material in the manufacture of solar cells. A large amount of waste and reworked wafers will be generated during its manufacturing process. The reworked wafer is the silicon wafer 11 after rework treatment after being put into use. The normal wafer is the silicon wafer 11 that has not undergone rework treatment.

[0067] After the silicon wafer 11 completes the boron diffusion treatment, a wet oxide layer will be deposited on the surface of the boron-doped layer 14. During the deposition process on the front side, the wet oxide layer will also be deposited by plating around to the back side of the silicon wafer 11 opposite to the boron-doped layer 14. The wet oxide layer itself has a certain passivation effect and can cooperate with the silicon oxide layer 121 and the doped polysilicon layer 122 to jointly improve the passivation effect on the surface of the silicon wafer 11. For the reworked wafers that need to be reworked, the thickness is generally thinned. Due to the relatively high viscosity of the wet oxide layer, the reworked wafers are prone to sticking to each other during the production process, which is not conducive to the normal progress of production on the production line. During the production process on the production line, in order to reduce the adverse effects caused by the sticking of reworked wafers, HF (hydrofluoric acid) is used to remove the wet oxide layer on the surface of the silicon wafer 11. At present, the silicon oxide layer 121 prepared in the production line has a relatively low density and poor quality to meet the production rhythm requirements, resulting in a significant reduction in the efficiency of reworked wafers compared to normal wafers. Therefore, the quality of the silicon oxide layer 121 has also become the main factor restricting the improvement of the efficiency of reworked wafers.

[0068] This application uses the method of combining the first silicon oxide sub-layer 1211 and the second silicon oxide sub-layer 1212 to obtain a silicon oxide layer 121 with excellent quality, which can effectively improve the passivation effect of the passivation contact structure 12 on the back of the rework wafer, reduce the adverse effects brought by the lack of wet oxide film to the rework wafer, and promote the efficiency improvement of the rework wafer.

[0069] Secondly, an embodiment of this application provides a method for preparing a passivation contact structure 12.

[0070] The passivation contact structure 12 is prepared on the surface of the silicon wafer 11 by chemical vapor deposition. The preparation method of the passivation contact structure 12 includes the following steps:

[0071] Prepare the silicon oxide layer 121:

[0072] Prepare the first silicon oxide sub-layer 1211: Deposit the first silicon oxide sub-layer 1211 on the surface of the silicon wafer 11, control the deposition rate of the first silicon oxide sub-layer 1211 to be 0.005 Å / s to 0.01 Å / s, and the deposition time to be 150 s to 250 s to obtain the first silicon oxide sub-layer 1211;

[0073] Prepare the second silicon oxide sub-layer 1212: Deposit the second silicon oxide sub-layer 1212 on the surface of the first silicon oxide sub-layer 1211, control the deposition rate of the second silicon oxide sub-layer 1212 to be 0.2 Å / s to 0.4 Å / s, and the deposition time to be 40 s to 60 s to obtain the second silicon oxide sub-layer 1212;

[0074] Prepare the intrinsic amorphous silicon layer and the doped amorphous silicon layer: Sequentially prepare the intrinsic amorphous silicon layer and the doped amorphous silicon layer on the surface of the second silicon oxide sub-layer 1212;

[0075] Annealing: After annealing treatment, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are crystallized and transformed into the doped polycrystalline silicon layer 122 to obtain the passivation contact structure 12 mentioned in the first aspect.

[0076] By controlling the deposition rate of the first silicon oxide sub-layer 1211 to be 0.005 Å / s to 0.01 Å / s and controlling the deposition time to 200 s, the first silicon oxide sub-layer 1211 prepared at this deposition rate has a high density. Characterized by the refractive index, the refractive index of the first silicon oxide sub-layer 1211 can be increased to 1.48 to 1.53, and the thickness of the first silicon oxide sub-layer 1211 is set to 0.2 nm to 0.5 nm, and the deposition can be completed within 200 s.

[0077] By increasing the deposition rate of the second silicon oxide sub-layer 1212 to 0.2 Å / s to 0.4 Å / s and controlling the deposition time to 50 s, the second silicon oxide sub-layer 1212 prepared at this deposition rate has a relatively low density. Characterized by the refractive index, the refractive index of the second silicon oxide sub-layer 1212 is 1.40 to 1.45, and the thickness of the second silicon oxide sub-layer 1212 is set to 1 nm to 2 nm, and the deposition can be completed within 50 s.

[0078] An intrinsic amorphous silicon layer and a doped amorphous silicon layer are sequentially prepared on the surface of the second silicon oxide sub-layer 1212. After annealing treatment, the crystallization performance of the intrinsic amorphous silicon layer and the doped amorphous silicon layer is improved, and the doping elements in the doped amorphous silicon layer diffuse toward the intrinsic amorphous silicon layer that does not contain doping elements. Therefore, after annealing, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are transformed into a doped polycrystalline silicon layer 122. Moreover, during the annealing process, the doping elements further diffuse toward the relatively porous second silicon oxide sub-layer 1212 and the first silicon oxide sub-layer 1211 with a higher density. Blocked by the first silicon oxide sub-layer 1211 with a higher density, it is difficult to penetrate through the first silicon oxide sub-layer 1211 and enter the surface of the silicon wafer 11. Thus, while improving the field passivation effect of the doped polycrystalline silicon layer 122, the Auger recombination on the surface of the silicon wafer 11 is reduced, and the overall passivation effect of the passivation contact structure 12 is improved, thereby improving the conversion efficiency of the battery.

[0079] In some embodiments, in the step of preparing the silicon oxide layer 121, the deposition temperature is 400 °C to 500 °C, the process pressure is 1000 mT to 3000 mT, and the gas flow rate of the oxygen-containing gas is 5000 sccm to 10000 sccm, where the oxygen-containing gas is one or more of N2O, CO2, CO, O2, and NO;

[0080] When preparing the first silicon oxide sub-layer 1211, the power is controlled to be 0.5 kW to 6 kW, the duty cycle is 0.5% to 2%, the frequency is pure low frequency or a combination of low frequency and high frequency, and the time ratio of low frequency to high frequency is greater than or equal to 10%;

[0081] When preparing the second silicon oxide sub-layer 1212, the power is controlled to be 0.5 kW to 6 kW, the duty cycle is 3% to 10%, the frequency is pure low frequency or a combination of low frequency and high frequency, and the time ratio of low frequency to high frequency is greater than or equal to 1%.

[0082] The duty cycle refers to the proportion of the energized time relative to the total time within a pulse cycle. It can also be understood as the time ratio of shortening the effective power pulse within a period.

[0083] It should be noted that the low frequency refers to the lower range of frequencies from 30 kHz to 500 kHz, such as a frequency of 380 kHz, and the high frequency refers to the higher range of frequencies from 3 MHz to 100 MHz, such as a frequency of 40 MHz.

[0084] By controlling the power, duty cycle, and high-low frequency time ratio of the silicon oxide layer 121, the deposition rate of the first silicon oxide sub-layer 1211 can be effectively controlled respectively, making the deposition rate of the first silicon oxide sub-layer 1211 lower and the deposition rate of the second silicon oxide sub-layer 1212 higher. At the same time, the temperature can be kept stable as much as possible, avoiding controlling the deposition rate of the silicon oxide layer 121 by switching the temperature. This can reduce the impact of the production of the silicon oxide layer 121 on the silicon wafer 11, prevent the silicon wafer 11 from deforming due to temperature switching, resulting in problems such as film layer peeling or reduced covering effect on the surface of the silicon wafer 11, causing local failure of the solar cell. It can also prevent the mesoporous density of the silicon oxide layer from increasing extremely at high temperatures, preventing a large amount of doping source from entering the surface of the silicon wafer 11 through the mesopores, exacerbating Auger recombination, and making the passivation effect worse. It can also prevent the high temperature brought by annealing from activating the defects and impurities in the silicon wafer 11 to the interface between the silicon wafer 11 and the silicon oxide layer 121, resulting in an increase in the defects at the interface of the silicon wafer 11 and serious carrier recombination loss.

[0085] In some embodiments, in the step of preparing the intrinsic amorphous silicon layer, the deposition temperature is 400 °C to 500 °C, the process pressure is 2000 mT to 5000 mT, and the power is 5.0 kW to 8.0 kW. In the step of preparing the doped amorphous silicon layer, the deposition temperature is 400 °C to 500 °C, the process pressure is 3000 mT to 5000 mT, the power is 6.0 kW to 10 kW, and the doping mass concentration of the doping element is 1% to 10%; and / or,

[0086] The annealing is an annealing treatment at 800 °C to 1000 °C for 20 min to 60 min.

[0087] By controlling the above deposition conditions, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are prepared. At the above annealing temperature, the crystallization performance transformation effect of the intrinsic amorphous silicon layer and the doped amorphous silicon layer is better. Moreover, the doping element of the doped amorphous silicon layer can not only diffuse towards the intrinsic amorphous silicon layer without doping elements, but also further diffuse towards the relatively loose second silicon oxide sub-layer 1212 and the first silicon oxide sub-layer 1211 with a higher density. Blocked by the first silicon oxide sub-layer 1211 with a higher density at the above annealing temperature, it is difficult for the doping element to penetrate through the first silicon oxide sub-layer 1211 into the surface of the silicon wafer 11, thereby effectively improving the field passivation effect of the doped polycrystalline silicon layer 122, reducing the Auger recombination of the silicon wafer 11, enhancing the overall passivation effect of the passivation contact structure 12, and thus improving the conversion efficiency of the battery.

[0088] In a third aspect, the present application provides a solar cell.

[0089] The solar cell includes the passivation contact structure 12 as mentioned in the first aspect or the passivation contact structure 12 prepared by the preparation method as mentioned in the second aspect.

[0090] In some embodiments, the solar cell is a passivation contact solar cell or a perovskite-passivation contact tandem solar cell.

[0091] In some embodiments, the passivation contact solar cell includes:

[0092] A silicon wafer 11 having a first conductivity type;

[0093] A doped layer 14 and a first functional layer 15 sequentially disposed on one surface side of the silicon wafer 11; the doped layer 14 has a second conductivity type, and one of the first conductivity type and the second conductivity type is N-type and the other is P-type;

[0094] A passivation contact structure 12 and a second functional layer sequentially disposed on the other surface side of the silicon wafer 11;

[0095] A first electrode 16 and a second electrode 21, the first electrode 16 forms an ohmic contact with the doped layer 14, and the second electrode 21 forms an ohmic contact with the passivation contact structure 12.

[0096] It should be noted that the first functional layer 15 includes a first passivation layer 151 and a first antireflection layer 152. Specifically, the passivation layer 151 can be selected as an alumina layer, and the antireflection layer 152 can be selected as a silicon nitride layer. The second functional layer includes a second antireflection layer 152, and the second antireflection layer 152 can be selected as a silicon nitride layer.

[0097] When the selected conductivity type of the silicon wafer 11 is N-type, the doped layer 14 is P-type, that is, when the silicon wafer 11 is an N-type silicon wafer 11, the doped layer 14 is a boron-doped layer 14. When the selected conductivity type of the silicon wafer 11 is P-type, the doped layer 14 is N-type, that is, when the silicon wafer 11 is a P-type silicon wafer 11, the doped layer 14 is a phosphorus diffusion layer.

[0098] In some embodiments, referring to Figure 2 , the perovskite-passivation contact tandem solar cell is composed of a perovskite top cell 200 and a passivation contact bottom cell 100. A carrier transport layer is disposed on the surface of the passivation contact bottom cell 100 to connect the perovskite top cell 200 and the passivation contact bottom cell 100. The passivation contact bottom cell 100 includes:

[0099] A silicon wafer 11 having a first conductivity type;

[0100] A doping layer 14 and a first functional layer 15 are sequentially disposed on one side surface of the silicon wafer 11; the doping layer 14 has a second conductivity type, and one of the first conductivity type and the second conductivity type is N-type and the other is P-type;

[0101] A passivation contact structure 12 is disposed on the other side surface of the silicon wafer 11;

[0102] It further includes a first electrode 16, and the first electrode 16 forms an ohmic contact with the doping layer 14;

[0103] A carrier transport layer is disposed on the surface of the passivation contact structure 12.

[0104] It should be noted that the first functional layer 15 includes a first passivation layer 151 and a first antireflection layer 152. Specifically, the passivation layer 151 can be an alumina layer, and the antireflection layer 152 can be a silicon nitride layer.

[0105] When the selected conductivity type of the silicon wafer 11 is N-type, the doping layer 14 is P-type, that is, when the silicon wafer 11 is an N-type silicon wafer, the doping layer 14 is a boron-doped layer. When the selected conductivity type of the silicon wafer 11 is P-type, the doping layer 14 is N-type, that is, when the silicon wafer 11 is a P-type silicon wafer, the doping layer 14 is a phosphorus diffusion layer.

[0106] In some embodiments, the junction depth of the doping layer 14 is 50 nm to 300 nm; and / or

[0107] The first functional layer 15 includes a passivation layer 151 and an antireflection layer 152. The thickness of the passivation layer 151 is 3 nm to 10 nm, and the thickness of the antireflection layer 152 is 70 nm to 100 nm; and / or

[0108] The thickness of the carrier transport layer is 10 nm to 40 nm; and / or

[0109] The perovskite top cell 200 includes a hole transport layer, a perovskite layer, a passivation layer 151, an electron transport layer, a buffer layer, a transparent conductive layer, an antireflection layer, and a second electrode 21 that are sequentially stacked on the carrier transport layer. The fine grid height of the second electrode 21 is 5 μm to 50 μm, the width is 10 μm to 100 μm, the main grid height is 5 μm to 50 μm, and the width is 50 μm to 150 μm.

[0110] The material of the hole transport layer is nickel oxide, and the thickness is 10 nm to 30 nm.

[0111] The thickness of the perovskite layer is 400 nm to 1000 nm;

[0112] The material of the passivation layer is LiF, and the thickness is 0.5 nm to 2 nm;

[0113] The material of the electron transport layer is C 60, with a thickness of 10 nm to 30 nm,

[0114] The material of the buffer layer is SnO2, with a thickness of 10 nm to 30 nm;

[0115] The material of the transparent conductive layer is indium zinc oxide, with a thickness of 30 nm to 130 nm;

[0116] The material of the antireflection layer is MgF, with a thickness of 100 nm to 200 nm;

[0117] The material of the second electrode is Ag, with a thickness of 0.3 μm to 10 μm.

[0118] Fourthly, the present application provides a photovoltaic module.

[0119] A photovoltaic module includes the solar cell of the third aspect.

[0120] In some embodiments, the preparation of the passivated contact bottom cell 100 includes the following steps:

[0121] Provide a silicon wafer 11 with a textured surface;

[0122] Perform doping diffusion treatment on the front side of the silicon wafer 11 to prepare a doped layer 14;

[0123] Etch and polish the back side of the silicon wafer 11 after the doped layer 14 is processed, and then prepare a passivated contact structure 12 on the back side of the silicon wafer 11;

[0124] Etch the side of the doped layer 14 away from the silicon wafer 11, and then prepare a first functional film layer on the side of the doped layer 14 away from the silicon wafer 11;

[0125] Prepare a first electrode 16 on the first functional film layer, so that the first electrode 16 passes through the first functional film layer to form an ohmic contact with the boron-doped layer 14.

[0126] Next, the technical solutions of the present invention will be further described in conjunction with the embodiments and the drawings.

[0127] Example 1

[0128] The embodiment of the present application provides a perovskite-passivated contact tandem solar cell. The perovskite-passivated contact tandem solar cell is composed of a perovskite top cell and a passivated contact bottom cell. A carrier transport layer is provided on the surface of the passivated contact bottom cell to connect the perovskite top cell and the passivated contact bottom cell. The passivated contact bottom cell includes:

[0129] An N-type monocrystalline silicon wafer with a thickness of 200 μm;

[0130] A doping layer, a passivation layer, and an antireflection layer are sequentially disposed on the backlight side of the silicon wafer. The doping layer is a boron-doped layer with a P-type conductivity type and a junction depth of 100 nm. The passivation layer is an alumina layer with a thickness of 5 nm. The antireflection layer is a silicon nitride layer with a thickness of 85 nm;

[0131] A passivated contact structure is disposed on the light-receiving side of the silicon wafer. The passivated contact structure includes a silicon oxide layer stacked on the light-receiving side of the silicon wafer and a doped polysilicon layer stacked on the silicon oxide layer. The silicon oxide layer includes a first silicon oxide sub-layer and a second silicon oxide sub-layer. The first silicon oxide sub-layer is disposed close to the silicon wafer, with a thickness of 0.35 nm, a refractive index of 1.50, and a film thickness non-uniformity of 15%. The second silicon oxide sub-layer is disposed close to the doped polysilicon layer, with a thickness of 1.5 nm, a refractive index of 1.43, and a film thickness non-uniformity of 30%. The doping mass concentration of phosphorus element in the doped polysilicon layer is 5%;

[0132] A first electrode, the first electrode forms an ohmic contact with the boron-doped layer. The height of the fine grid of the first electrode is 25 μm, the width is 50 μm, the height of the main grid is 25 μm, and the width is 50 μm;

[0133] A carrier transport layer is disposed on the surface of the doped polysilicon layer, with a thickness of 20 nm;

[0134] The perovskite top cell includes:

[0135] A hole transport layer stacked on the carrier transport layer, the material is nickel oxide, and the thickness is 10 - 30 nm,

[0136] A perovskite layer stacked on the hole transport layer, with a thickness of 600 nm,

[0137] A passivation layer stacked on the perovskite layer, the material is LiF, and the thickness is 1 nm;

[0138] An electron transport layer stacked on the passivation layer, the material is C 60 with a thickness of 20 nm,

[0139] A buffer layer stacked on the electron transport layer, the material is SnO2, and the thickness is 15 nm;

[0140] A transparent conductive layer stacked on the buffer layer, the material is indium zinc oxide, and the thickness is 150 nm;

[0141] An antireflection layer stacked on the transparent conductive layer, the material is MgF, and the thickness is 150 nm;

[0142] A second electrode disposed on the transparent conductive layer and forming an ohmic contact with the transparent conductive layer, the material is Ag, and the thickness is 5 μm.

[0143] The embodiment of the present application also provides a preparation method of a perovskite-passivated contact stacked solar cell. Among them, the preparation method of the passivated contact bottom cell includes the following steps:

[0144] Provide an N-type monocrystalline silicon wafer: After pre-cleaning the N-type monocrystalline silicon wafer, perform double-sided chemical polishing to remove the oil stains on the wafer surface and the cutting damage layer, and form a pyramid light-trapping structure;

[0145] Front diffusion: Diffuse a boron-doped layer on the light-receiving surface of the silicon wafer. The pushing temperature is 1000 °C, the pushing pressure is 750 Pa, and the diffusion source is BBr3;

[0146] Back etching and polishing: Adopt the chain floating-on-water method to remove the boron-doped silicon dioxide diffused to the edges and back of the N-type monocrystalline silicon wafer with hydrofluoric acid, and adopt the tank-type alkali polishing method to remove the boron-doped layer diffused to the edges and back of the N-type monocrystalline silicon wafer, and polish off the back pyramid light-trapping structure to form a fully polished surface;

[0147] Prepare a passivated contact structure: Deposit a silicon oxide layer, an intrinsic amorphous silicon layer, and a doped amorphous silicon layer in sequence by plasma-enhanced chemical vapor deposition. The specific steps include:

[0148] Prepare a silicon oxide layer, including:

[0149] Prepare the first silicon oxide sub-layer: Deposit the first silicon oxide sub-layer on the surface of the silicon wafer. Control the deposition temperature to be 450 °C, the process pressure to be 2000 mT, the gas flow rate of N2O to be 8000 sccm, the power to be 1000 W, the duty cycle to be 1%, and use a low frequency of 380 kHz to control the deposition rate of the first silicon oxide sub-layer to be 0.008 Å / s, and the deposition time to be 200 s to obtain the first silicon oxide sub-layer;

[0150] Prepare the second silicon oxide sub-layer: Deposit the second silicon oxide sub-layer on the surface of the first silicon oxide sub-layer. Control the deposition temperature to be 450 °C, the process pressure to be 2000 mT, the gas flow rate of N2O to be 8000 sccm, the power to be 6 kW, the duty cycle to be 3%, and use a combination of low frequency and high frequency. Specifically, the time ratio of 380 kHz:40 MHz is 2:1 to control the deposition rate of the second silicon oxide sub-layer to be 0.3 Å / s, and the deposition time to be 50 s to obtain the second silicon oxide sub-layer;

[0151] Prepare the intrinsic amorphous silicon layer and the doped amorphous silicon layer: Prepare the intrinsic amorphous silicon layer on the surface of the second silicon oxide sub-layer, with a deposition temperature of 450 °C, a process pressure of 3000 mT, and a power of 6.5 kW. Prepare the doped amorphous silicon layer on the surface of the intrinsic amorphous silicon, with a deposition temperature of 450 °C, a process pressure of 4000 mT, and a power of 8.5 kW;

[0152] Annealing: After annealing at 900 °C, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are crystallized and transformed into a doped polycrystalline silicon layer to obtain a passivated contact structure;

[0153] Front etching: The phosphorus-doped silicon oxide layer deposited on the edge and front of the N-type monocrystalline silicon wafer is removed by the chain floating method on water, and the doped amorphous silicon layer deposited on the edge and front of the N-type monocrystalline silicon wafer is removed by the tank-type alkali cleaning method;

[0154] Preparation of the first functional layer: An aluminum oxide layer is deposited on the boron-doped layer by atomic layer deposition at a deposition temperature of 200 °C and a process pressure of less than 1 mbar. Then, a silicon nitride layer is deposited on the aluminum oxide layer by chemical vapor deposition at a deposition temperature of 500 °C, a pressure of 1500 mT, and a power of 7.5 kW;

[0155] Preparation of the second electrode: The second electrode is prepared on the silicon nitride layer by evaporation;

[0156] Preparation of the carrier transport layer: The carrier transport layer is prepared on the doped polycrystalline silicon layer by physical vapor deposition.

[0157] The preparation of the perovskite top cell includes the following steps:

[0158] Invert the passivated contact bottom cell, and sequentially deposit a hole transport layer, a perovskite layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, an anti-reflection layer, and a front grid electrode on the carrier transport layer to obtain a perovskite top cell.

[0159] Example 2

[0160] The embodiment of the present application provides a perovskite-passivated contact tandem solar cell, which is different from Example 1 in that: the refractive index of the first silicon oxide sub-layer is 1.48, the film thickness non-uniformity is 20%, the deposition rate is 0.01 Å / s, the refractive index of the second silicon oxide sub-layer is 1.45, the film thickness non-uniformity is 25%, the deposition rate is 0.2 Å / s, and the rest is the same as in Example 1.

[0161] Example 3

[0162] The embodiment of the present application provides a perovskite-passivated contact tandem solar cell, which is different from Example 1 in that: the refractive index of the first silicon oxide sub-layer is 1.53, the film thickness non-uniformity is 10%, the deposition rate is 0.005 Å / s, the refractive index of the second silicon oxide sub-layer is 1.4, the film thickness non-uniformity is 35%, the deposition rate is 0.4 Å / s, and the rest is the same as in Example 1.

[0163] Example 4

[0164] An embodiment of the present application provides a perovskite-passivated contact tandem solar cell, which is different from Embodiment 1 in that: the thickness of the first silicon oxide sub-layer is 0.5 nm, the thickness of the second silicon oxide sub-layer is 1 nm, and the rest is the same as that of Embodiment 1.

[0165] Embodiment 5

[0166] An embodiment of the present application provides a perovskite-passivated contact tandem solar cell, which is different from Embodiment 1 in that: the thickness of the first silicon oxide sub-layer is 0.2 nm, the thickness of the second silicon oxide sub-layer is 2 nm, and the rest is the same as that of Embodiment 1.

[0167] Embodiment 6

[0168] An embodiment of the present application provides a perovskite-passivated contact tandem solar cell, which is different from Embodiment 1 in that: a reworked wafer is used to replace the N-type monocrystalline silicon wafer, and the reworked wafer is treated by removing the wet oxide film on the silicon wafer surface with hydrofluoric acid, and the rest is the same as that of Embodiment 1.

[0169] Comparative Example 1

[0170] This comparative example provides a perovskite-passivated contact tandem solar cell, which is different from Embodiment 1 in that: as Figure 3 shown in the perovskite-passivated contact tandem solar cell, the silicon oxide layer is a single layer, the refractive index of the silicon oxide layer is 1.44, the film thickness non-uniformity is 30%, the deposition rate is 0.15 Å / s, the deposition time is 200 s, and the preparation of the passivated contact structure is as follows:

[0171] Deposit a silicon oxide layer on the silicon wafer surface, control the deposition temperature at 450 °C, the process pressure at 2000 mT, the gas flow rate of N2O introduced at 8000 sccm, the power at 1000 W, the duty cycle at 1%, and the high-low frequency time ratio at 15 times to control the deposition rate at 0.15 Å / s and the deposition time at 200 s to obtain the silicon oxide layer;

[0172] Prepare an intrinsic amorphous silicon layer and a doped amorphous silicon layer: Prepare an intrinsic amorphous silicon layer on the silicon oxide layer surface, with the deposition temperature at 450 °C, the process pressure at 3000 mT, and the power at 6.5 kW. Prepare a doped amorphous silicon layer on the intrinsic amorphous silicon surface, with the deposition temperature at 450 °C, the process pressure at 4000 mT, and the power at 8.5 kW;

[0173] Annealing: After annealing treatment at 900 °C, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are crystallized and transformed into a doped polycrystalline silicon layer to obtain the passivated contact structure.

[0174] The rest is the same as that of Embodiment 1.

[0175] Comparative Example 2

[0176] The comparative example of this application provides a perovskite-passivated contact tandem solar cell, which is different from Example 1 in that: the silicon oxide layer is a single layer, the refractive index of the silicon oxide layer is 1.48, the film thickness non-uniformity is 20%, the deposition rate of the silicon oxide layer is 0.015 Å / s, the deposition time is 1000 s, and the preparation of the passivated contact structure is specifically as follows:

[0177] Deposit a silicon oxide layer on the surface of the silicon wafer, control the deposition temperature at 450 °C, the process pressure at 2000 mT, the gas flow rate of N2O introduced at 8000 sccm, the power at 1000 W, the duty cycle at 1%, and the high-low frequency time ratio at 15 times to control the deposition rate at 0.015 Å / s and the deposition time at 1000 s to obtain the silicon oxide layer;

[0178] Prepare an intrinsic amorphous silicon layer and a doped amorphous silicon layer: Prepare an intrinsic amorphous silicon layer on the surface of the silicon oxide layer, with the deposition temperature at 450 °C, the process pressure at 3000 mT, and the power at 6.5 kW. Prepare a doped amorphous silicon layer on the surface of the intrinsic amorphous silicon, with the deposition temperature at 450 °C, the process pressure at 4000 mT, and the power at 8.5 kW;

[0179] Annealing: After annealing at 900 °C, crystallize the intrinsic amorphous silicon layer and the doped amorphous silicon layer to transform into a doped polycrystalline silicon layer to obtain the passivated contact structure.

[0180] The rest is the same as that of Example 1.

[0181] Comparative Example 3

[0182] The comparative example of this application provides a perovskite-passivated contact tandem solar cell, which is different from Comparative Example 1 in that: a reworked wafer is used to replace the N-type monocrystalline silicon wafer, and the reworked wafer is treated by removing the wet oxide film on the light-receiving surface of the silicon wafer with hydrofluoric acid, and the rest is the same as that of Comparative Example 1.

[0183] Comparative Example 4

[0184] The comparative example of this application provides a perovskite-passivated contact tandem solar cell, which is different from Example 1 in that: the positions of the first silicon oxide sub-layer and the second silicon oxide sub-layer are swapped, so that the second silicon oxide sub-layer is close to the silicon wafer and the first silicon oxide sub-layer is close to the doped polycrystalline silicon layer; specifically, the preparation of the passivated contact structure includes the following steps:

[0185] Prepare a silicon oxide layer, including:

[0186] Preparation of the second silicon dioxide sub-layer: Deposit the second silicon dioxide sub-layer on the surface of the silicon wafer, control the deposition temperature at 400°C - 500°C, the process pressure at 1000 mT - 3000 mT, the gas flow rate of N2O introduced at 5000 sccm - 10000 sccm, the power at 6 kW, the duty cycle at 3%, and adopt a combination of low frequency and high frequency. Specifically, the time ratio of 380 kHz:40 MHz is 2:1 to control the deposition rate of the second silicon dioxide sub-layer at 0.3 Å / s and the deposition time at 50 s to obtain the second silicon dioxide sub-layer;

[0187] Preparation of the first silicon dioxide sub-layer: Deposit the first silicon dioxide sub-layer on the surface of the second silicon dioxide sub-layer, control the deposition temperature at 450°C, the process pressure at 2000 mT, the gas flow rate of N2O introduced at 8000 sccm, the power at 1000 W, the duty cycle at 1%, and adopt a low frequency of 380 kHz to control the deposition rate of the first silicon dioxide sub-layer at 0.008 Å / s and the deposition time at 200 s to obtain the first silicon dioxide sub-layer; Preparation of the intrinsic amorphous silicon layer and the doped amorphous silicon layer: Prepare the intrinsic amorphous silicon layer on the surface of the first silicon dioxide sub-layer with a deposition temperature of 450°C, a process pressure of 3000 mT, and a power of 6.5 kW. Prepare the doped amorphous silicon layer on the surface of the intrinsic amorphous silicon with a deposition temperature of 450°C, a process pressure of 4000 mT, and a power of 8.5 kW;

[0188] Annealing: Perform annealing treatment at 900°C to crystallize the intrinsic amorphous silicon layer and the doped amorphous silicon layer and transform them into a doped polycrystalline silicon layer to obtain a passivated contact structure; the rest is the same as in Example 1.

[0189] Comparative Example 5

[0190] The comparative example of this application provides a perovskite-passivated contact stacked solar cell, which is different from Example 1 in that: the thickness of the first silicon dioxide sub-layer is 0.7 nm, and the rest is the same as in Example 1.

[0191] Comparative Example 6

[0192] The comparative example of this application provides a perovskite-passivated contact stacked solar cell, which is different from Example 1 in that: the refractive index of the second silicon dioxide sub-layer is 1.47. In the step of preparing the second silicon dioxide sub-layer, control the deposition temperature at 450°C, the process pressure at 2000 mT, the gas flow rate of N2O introduced at 8000 sccm, the power at 1.8 kW, the duty cycle at 2%, and adopt a low frequency of 380 kHz to control the deposition rate of the second silicon dioxide sub-layer at 0.013 Å / s, and the rest is the same as in Example 1.

[0193] Experiment 1

[0194] The performance of the perovskite solar cell was tested using a Wavelabs solar simulator. The test conditions were: AM1.5, 1000 W / m 2 , and the test ambient temperature was 25 °C. Before the test, a standard silicon cell was used to calibrate the sunlight intensity simulated by the light source. The performance tests included energy conversion efficiency, open-circuit voltage, short-circuit current, and fill factor. Among them, PCE represents the energy conversion efficiency, with the unit of %, Voc represents the open-circuit voltage, with the unit of V, Jsc represents the short-circuit current density, with the unit of mA / cm 2 , and FF represents the fill factor, with the unit of %.

[0195] The test results of the perovskite-passivated contact stacked solar cells in the above examples and comparative examples are shown in Table 1.

[0196] Table 1

[0197]

[0198] By comparing the data of Example 1 with Comparative Example 1 and Comparative Example 2, it can be obtained that compared with Comparative Example 1, the energy conversion efficiency of Example 1 increased by 0.66%, the open-circuit voltage increased by 0.0124 V, the short-circuit current increased by 0.07 mA / cm 2 , and the fill factor increased by 1.06%. Compared with Comparative Example 2, the energy conversion efficiency of Example 1 only decreased by 0.02%, the open-circuit voltage decreased by 0.0028 V, the short-circuit current increased by 0.04 mA / cm 2 , and the fill factor decreased by 0.07%. It is proved that compared with Comparative Example 1 that prepares the silicon oxide layer at a deposition rate of 0.15 A / s or Comparative Example 2 that prepares the silicon oxide layer at a deposition rate of 0.015 A / s, Example 1 adopts a scheme of first preparing a relatively thin first silicon oxide sub-layer at a deposition rate of 0.008 A / s, and then preparing a relatively thick second silicon oxide sub-layer at a deposition rate of 0.3 A / s on the first silicon oxide sub-layer. Through the coordinated cooperation of the first silicon oxide sub-layer and the second silicon oxide sub-layer, the total time for depositing the silicon oxide layer in Example 1 is close to that of Comparative Example 1, and the passivation performance is greatly improved compared with that of Comparative Example 1, thereby significantly improving the energy conversion efficiency of the solar cell. Compared with the significantly shortened time for depositing the silicon oxide layer in Comparative Example 2 and the performance being close to that of Comparative Example 2, it can be seen that the silicon oxide layer prepared in this application has both excellent passivation performance and short growth time, and has significant progress compared with both Comparative Example 1 and Comparative Example 2.

[0199] Comparative Example 3 used a reworked wafer. From the comparison of the data of Comparative Example 1 and Comparative Example 3, it can be known that compared with Comparative Example 1, the energy conversion efficiency of Comparative Example 3 decreased by 1.96%, the open-circuit voltage decreased by 0.0417 V, and the short-circuit current decreased by 0.12 mA / cm 2, the fill factor decreased by 3.36%, indicating that the efficiency of the solar cells made from the reworked wafers after rework treatment is significantly lower than that of the normal wafers. In Example 6, reworked wafers were also used, but the efficiency of the solar cells in Example 6 is close to that in Example 1, with the energy conversion only decreasing by 0.09%, the open-circuit voltage decreasing by 0.0022 V, and the short-circuit current increasing by 0.13 mA / cm 2 , the fill factor decreased by 0.12%, indicating that the efficiency gap between the solar cells made from reworked wafers and normal wafers has significantly decreased, proving that the quality of the silicon oxide layer in Example 1 is excellent, which can effectively improve the passivation performance of the reworked wafers and promote the performance improvement of the solar cells made from the reworked wafers. And compared with Comparative Example 3, the energy conversion increased by 2.53%, the open-circuit voltage increased by 0.0563 V, and the short-circuit current increased by 0.06 mA / cm 2 , the fill factor increased by 4.54%, indicating that using the above silicon oxide layer on the surface of the reworked wafers is very beneficial for passivating the surface defects of the reworked wafers and improving the performance of the solar cells.

[0200] From the data comparison between Example 1 and Comparative Example 4, it can be obtained that compared with Comparative Example 4, the energy conversion efficiency of Example 1 increased by 0.23%, the open-circuit voltage increased by 0.0049 V, and the short-circuit current increased by 0.015 mA / cm 2 , the fill factor decreased by 0.11%, proving that in Example 1, the first silicon oxide sub-layer is close to the silicon wafer, and the second silicon oxide sub-layer is close to the doped polysilicon layer. The combination of the first silicon oxide sub-layer and the second silicon oxide sub-layer can play a synergistic effect, promoting the significant improvement of the performance of the solar cells. In Comparative Example 4, the positions of the first silicon oxide sub-layer and the second silicon oxide sub-layer were swapped, making the second silicon oxide sub-layer close to the silicon wafer and the first silicon oxide sub-layer close to the doped polysilicon layer. The energy conversion efficiency of the resulting solar cells is significantly lower than that of Example 1.

[0201] From the data comparison between Example 1 and Comparative Example 5, it can be obtained that compared with Comparative Example 5, the energy conversion efficiency of Example 1 increased by 0.22%, the open-circuit voltage increased by 0.0055 V, and the short-circuit current increased by 0.07 mA / cm 2 , the fill factor increased by 0.13%, proving that if the thickness of the first silicon oxide sub-layer is too high, it is easy to reduce the field passivation effect of the polysilicon layer, resulting in a decrease in the passivation effect of the passivation contact structure and a decrease in the open-circuit voltage, fill factor, and energy conversion efficiency of the solar cells.

[0202] From the data comparison between Example 1 and Comparative Example 6, it can be obtained that compared with Comparative Example 6, the energy conversion efficiency of Example 1 increased by 0.29%, the open-circuit voltage increased by 0.0059 V, and the short-circuit current increased by 0.1 mA / cm 2, the fill factor is increased by 0.18%, which proves that the density of the second silicon oxide sub-layer is too high, increasing the refractive index to 1.47. This not only leads to a decrease in the deposition rate of the second silicon oxide sub-layer with a corresponding thickness, significantly prolonging the deposition time, but also is not conducive to the diffusion of the doping elements in the doped polysilicon layer in the second silicon oxide layer, resulting in a decrease in the field passivation effect of the doped polysilicon layer and a reduction in the energy conversion efficiency of the solar cell.

[0203] Experiment 2

[0204] By simulating the minority carrier lifetime test and comparing the passivation effects of the passivation contact structures of Example 1 and Comparative Example 4, Example 1 and Comparative Example 4 were each tested three times, and the experimental results are shown in Figure 4 , the upper figure corresponds to the test result of Example 1, the lower figure corresponds to the test result of Comparative Example 4, and the minority carrier lifetime values are recorded in Table 2.

[0205] Table 2

[0206] Example 1 Comparative Example 4 The 1st time 2120 1820 The 2nd time 2187 1760 The 3rd time 2035 1710 Average value 2114 1763

[0207] From Figure 4 Combining the data in Table 2, it can be seen that the minority carrier lifetime of Example 1 is significantly higher than that of Comparative Example 4, which proves that in Example 1, the first silicon oxide sub-layer is close to the silicon wafer, and the second silicon oxide sub-layer is close to the doped polysilicon layer. The combination of the first silicon oxide sub-layer and the second silicon oxide sub-layer can achieve a synergistic effect. In Comparative Example 4, the first silicon oxide sub-layer is close to the doped polysilicon layer, and the second silicon oxide sub-layer is close to the silicon wafer. The combination effect of the first silicon oxide sub-layer and the second silicon oxide sub-layer is poor. Therefore, the passivation effect of the passivation contact structure on the back surface of the silicon wafer in Example 1 is significantly higher than that of Comparative Example 4, and the minority carrier lifetime of Example 1 is significantly improved compared to that of Comparative Example 4.

[0208] The passivation contact structure, its preparation method, solar cell, and photovoltaic module disclosed in the embodiments of the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation methods of the present invention. The descriptions of the above embodiments are only used to help understand the passivation contact structure, its preparation method, solar cell, photovoltaic module, and its core idea of the present invention: At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A passivated contact structure, characterized in that, The passivation contact structure is used on the surface of a silicon wafer. The passivation contact structure includes a silicon oxide layer stacked on the surface of the silicon wafer and a doped polysilicon layer stacked on the silicon oxide layer. The silicon oxide layer includes a first silicon oxide sub-layer and a second silicon oxide sub-layer. The first silicon oxide sub-layer is disposed close to the silicon wafer, and the thickness of the first silicon oxide sub-layer is 0.2 nm to 0.5 nm, and the refractive index is 1.48 to 1.

53. The second silicon oxide sub-layer is disposed close to the doped polysilicon layer, and the thickness of the second silicon oxide sub-layer is 1 nm to 2 nm, and the refractive index is 1.40 to 1.

45.

2. The passivation contact structure according to claim 1, wherein, The film thickness non-uniformity of the first silicon oxide sub-layer is 10% to 20%, and the film thickness non-uniformity of the second silicon oxide sub-layer is 25% to 35%.

3. The passivation contact structure according to claim 1, characterized in that, The material of the silicon oxide layer is silicon oxide; and / or, the silicon wafer is a normal wafer or a reworked wafer, and the surface of the reworked wafer does not include a wet oxide layer.

4. A method for preparing a passivated contact structure, characterized in that, The passivation contact structure is prepared on the surface of the silicon wafer by chemical vapor deposition. The preparation method of the passivation contact structure includes the following steps: Preparing a silicon oxide layer: Preparing the first silicon oxide sub-layer: Depositing the first silicon oxide sub-layer on the surface of the silicon wafer, controlling the deposition rate of the first silicon oxide sub-layer to be 0.005 Å / s to 0.01 Å / s, and the deposition time to be 150 s to 250 s, to obtain the first silicon oxide sub-layer; Preparing the second silicon oxide sub-layer: Depositing the second silicon oxide sub-layer on the surface of the first silicon oxide sub-layer, controlling the deposition rate of the second silicon oxide sub-layer to be 0.2 Å / s to 0.4 Å / s, and the deposition time to be 40 s to 60 s, to obtain the second silicon oxide sub-layer; Preparing an intrinsic amorphous silicon layer and a doped amorphous silicon layer: Sequentially preparing the intrinsic amorphous silicon layer and the doped amorphous silicon layer on the surface of the second silicon oxide sub-layer; Annealing: After the annealing treatment, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are crystallized and transformed into a doped polysilicon layer, to obtain the passivation contact structure as described in any one of claims 1-3.

5. The method for preparing the passivated contact structure according to claim 4, wherein, In the step of preparing the silicon oxide layer, the deposition temperature is 400 °C to 500 °C, the process pressure is 1000 mT to 3000 mT, and the gas flow rate of the oxygen-containing gas is 5000 sccm to 10000 sccm, where the oxygen-containing gas is one or more of N2O, CO2, CO, O2, and NO; When preparing the first silicon oxide sub-layer, control the power to be 0.5 kW to 6 kW, the duty cycle to be 0.5% to 2%, the frequency to be pure low frequency or a combination of low frequency and high frequency, and the time ratio of low frequency to high frequency to be greater than or equal to 10%; When preparing the second silicon oxide sub-layer, control the power to be 0.5 kW to 6 kW, the duty cycle to be 3% to 10%, the frequency to be pure low frequency or a combination of low frequency and high frequency, and the time ratio of low frequency to high frequency to be greater than or equal to 1%.

6. The manufacturing method of the passivated contact structure according to claim 4, characterized in that, In the step of preparing the intrinsic amorphous silicon layer, the deposition temperature is 400°C to 500°C, the process pressure is 2000 mT to 5000 mT, and the power is 5.0 kW to 8.0 kW. In the step of preparing the doped amorphous silicon layer, the deposition temperature is 400°C to 500°C, the process pressure is 3000 mT to 5000 mT, the power is 6.0 kW to 10 kW, and the doping mass concentration of the doping element is 1% to 10%; and / or, In the step of preparing the doped amorphous silicon layer, the reaction gases include phosphine and silane, and the gas flow ratio of the phosphine to the silane is 3% to 30%; and / or, The annealing is annealing treatment at 800°C to 1000°C for 20 min to 60 min.

7. A solar cell, characterized in that, It includes the passivation contact structure as described in any one of claims 1 - 3 or the passivation contact structure prepared by the preparation method as described in any one of claims 4 - 6.

8. The solar cell according to claim 7, wherein The solar cell is a passivation contact solar cell or a perovskite - passivation contact tandem solar cell.

9. The solar cell according to claim 8, wherein, The passivation contact solar cell includes: A silicon wafer having a first conductivity type; A doped layer and a first functional layer sequentially disposed on one surface of the silicon wafer; the doped layer has a second conductivity type, and one of the first conductivity type and the second conductivity type is N - type and the other is P - type; The passivation contact structure and a second functional layer sequentially disposed on the other surface of the silicon wafer; A first electrode and a second electrode, the first electrode forms an ohmic contact with the doped layer, and the second electrode forms an ohmic contact with the passivation contact structure.

10. The solar cell according to claim 8, wherein The perovskite - passivation contact tandem solar cell is composed of a perovskite top cell and a passivation contact bottom cell. A carrier transport layer is disposed on the surface of the passivation contact bottom cell to connect the perovskite top cell and the passivation contact bottom cell. The passivation contact bottom cell includes: A silicon wafer having a first conductivity type; A doped layer and a first functional layer sequentially disposed on one surface of the silicon wafer; the doped layer has a second conductivity type, and one of the first conductivity type and the second conductivity type is N - type and the other is P - type; The passivation contact structure disposed on the other surface of the silicon wafer; It further includes a first electrode, and the first electrode forms an ohmic contact with the doped layer; The carrier transport layer is disposed on the surface of the passivation contact structure.

11. The solar cell according to claim 9 or 10, characterized in that, The junction depth of the doped layer is 50 nm to 300 nm; and / or, The first functional layer includes a passivation layer and an antireflection layer. The thickness of the passivation layer is 3 nm to 10 nm, and the thickness of the antireflection layer is 70 nm to 100 nm; and / or, The thickness of the carrier transport layer is 10 nm to 40 nm; and / or, The perovskite top cell includes a hole transport layer, a perovskite layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, an antireflection layer, and a second electrode sequentially stacked on the carrier transport layer. The fine grid height of the second electrode is 5 μm to 50 μm, the width is 10 μm to 100 μm, the main grid height is 5 μm to 50 μm, and the width is 50 μm to 150 μm.

12. A photovoltaic module, characterized in that, It includes the solar cell as described in any one of claims 7 - 11.

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