Photoelectric device packaging structure and manufacturing method thereof

Abstract

The present invention provides a photoelectric device packaging structure and a method for manufacturing the same, which are applied to the field of semiconductor technology. In the present invention, the thermal management structure includes multiple semiconductor layers, wherein the second semiconductor layer is provided with a plurality of mutually spaced rectangular grooves. A plurality of through-silicon vias (TSVs) are provided in the first semiconductor layer below each of the rectangular grooves. The plurality of rectangular grooves are surrounded by a hollow cavity (vacuum cavity). By disposing different radiation detection components of the photoelectric device in different rectangular grooves, the structure isolates the photoelectric device from thermal disturbances caused by an external alternating thermal field environment and from radiation crosstalk between different radiation detection components. The TSVs are also used to promptly remove heat from the radiation detection components. This structure isolates the photoelectric device from thermal disturbances caused by an external alternating thermal field environment while maintaining a stable internal temperature, ultimately improving the efficiency and reliability of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a photoelectric device packaging structure and a manufacturing method thereof. Background Art

[0002] Most photoelectric sensors currently on the market use packages such as TO packages (using stainless steel or Kovar alloy tubes) or vacuum packages. In TO packages, a heat sink is often integrated within the package structure to improve heat dissipation efficiency, accelerating heat dissipation to maintain a stable reference temperature and reducing output drift caused by device heat accumulation. Vacuum packages, on the other hand, often use metal tubes or vacuum metal packages, forming a sealed cavity through a high-temperature welding process. Getters are often integrated within the package to adsorb residual gas molecules and maintain a long-term vacuum to isolate air heat conduction and convection. Surface mount (SMD) packaging is also used for pyroelectric devices, employing epoxy resin molded packages combined with a metal shielding layer to suppress electromagnetic interference while simultaneously improving transient thermal response speed through thin-film heat sinks.

[0003] However, both TO packaging and vacuum packaging are difficult to effectively isolate external heat conduction, which causes sensitive elements in photoelectric sensors, such as the cold end (reference end) of the thermopile, to be affected by ambient temperature fluctuations. This destroys the temperature difference between the hot end and the cold end, causing the Seebeck voltage to drift. For example, sensitive elements in photoelectric sensors, such as pyroelectrics, will experience increased heat exchange due to air convection in non-vacuum packaging. External thermal interference is transmitted to the sensitive film through the package body, forming background noise, reducing the signal-to-noise ratio, and interfering with the stability of the pyroelectric material. Summary of the Invention

[0004] The purpose of the present invention is to provide a photovoltaic device packaging structure and a manufacturing method thereof, and specifically to provide a thermal management structure for packaging photovoltaic devices and serving as a heat sink. By combining a central control cavity (vacuum cavity) and a non-vacuum rectangular groove, the thermal disturbance of the photovoltaic device in an external alternating thermal field environment is isolated, the internal temperature of the photovoltaic device is kept stable, and the efficiency and reliability of the photovoltaic device are improved.

[0005] In a first aspect, an embodiment of the present invention provides an optoelectronic device packaging structure, comprising:

[0006] substrate.

[0007] At least one thermal management structure is located on the substrate, the thermal management structure comprising:

[0008] a first semiconductor layer.

[0009] The second semiconductor layer is located on the first semiconductor layer and includes a plurality of rectangular grooves spaced apart from each other along a first direction and respectively passing through the second semiconductor layer, and a hollow cavity surrounding the outside of the plurality of rectangular grooves along the first and second directions and located within the second semiconductor layer.

[0010] The third semiconductor layer is located on the second semiconductor layer, and in a third direction, a projection of the third semiconductor layer overlaps with a projection of the second semiconductor layer.

[0011] The second semiconductor layer and the first semiconductor layer are integrally formed, the first direction and the second direction are perpendicular to each other, and the third direction is perpendicular to the plane where the first direction and the second direction are located.

[0012] Optionally, the portion of the hollow cavity surrounding the outside of the rectangular groove may be in the shape of a rectangular frame or an annular frame.

[0013] Furthermore, the top surface of the hollow cavity may be flush with the top surface of the second semiconductor layer.

[0014] Furthermore, the width of the portion of the hollow cavity located between adjacent rectangular grooves in the first direction may be a first width, the height of the second semiconductor layer in the third direction may be a first height, and the value of the first height may be 2 to 4 times the value of the first width.

[0015] Furthermore, the thermal management structure may further include:

[0016] A plurality of through silicon vias are arranged in the first semiconductor layer below the rectangular groove and spaced apart from each other along the first direction and / or the second direction.

[0017] Furthermore, the materials of the first semiconductor layer and the second semiconductor layer may be the same, and the materials of the second semiconductor layer and the third semiconductor layer may be different.

[0018] Furthermore, the thermal management structure may further include:

[0019] A fourth semiconductor layer is located on the second semiconductor layer, with its top flush with the top of the third semiconductor layer, its sidewall in contact with the third semiconductor layer, and in the third direction, the sum of the projections of the fourth semiconductor layer and the third semiconductor layer completely overlaps with the projection of the second semiconductor layer.

[0020] Furthermore, the optoelectronic device packaging structure may further include:

[0021] The pyroelectric sensor includes a plurality of radiation detection components, wherein one of the radiation detection components is located in one of the rectangular grooves in the thermal management structure.

[0022] Furthermore, the bottom of the radiation detection component is in direct contact with the top of the through silicon via.

[0023] Furthermore, the optoelectronic device packaging structure may further include:

[0024] An adhesive layer is located between the substrate and the first semiconductor layer, and / or between the radiation detection component and the first semiconductor layer.

[0025] Furthermore, the adhesive layer may include a conductive adhesive.

[0026] Furthermore, the thermal conductivity of the thermal management structure is determined by a design model, which is:

[0027] G T =f(h1,W1,W wall ,L spacer ), and the constraints of the design model are:

[0028] 0 max ;

[0029] h2=(h-h1)≥h critical ;

[0030] L lateral =W lateral ;

[0031] W wall-min ≤W wall ≤W wall-max ;

[0032] W 1-min ≤W1≤W 1-max ;

[0033] L spacer-min ≤L spacer ≤L spacer-max ;

[0034] Wherein, h is the sum of the heights of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the third direction, h max is the maximum value given by h, h1 is the height of the first semiconductor layer in the third direction, h2 is the height of the second semiconductor layer and the third semiconductor layer or the fourth semiconductor layer in the third direction, W1 is the width of the portion of the hollow cavity located between adjacent rectangular grooves in the first direction, W wall is the width from the sidewall of the hollow cavity to the outer wall of the second semiconductor layer in the first direction, L spacer ​W is the width of the distance between two connected matrix grooves in the first direction, wall-min and W 1-max It's W wall Given the maximum and minimum values, W 1-min and W 1-max is the maximum and minimum value given by W1, L spacer-min and L spacer-max It's L spacer Given the maximum and minimum values, h critical is the minimum anti-crosstalk height of h2, L lateral is the width from the sidewall of the rectangular groove to the outer sidewall of the second semiconductor layer in the first direction, W lateral is the width in the second direction from the sidewall of the rectangular groove to the outer sidewall of the second semiconductor layer.

[0035] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing an optoelectronic device packaging structure, comprising:

[0036] A first semiconductor layer is provided.

[0037] A second semiconductor layer is formed on the first semiconductor layer, and the second semiconductor layer and the first semiconductor layer are integrally formed.

[0038] A third semiconductor layer is formed on the second semiconductor layer, and a plurality of through holes are formed on the third semiconductor layer and are spaced apart from each other along the first direction and the second direction.

[0039] The second semiconductor layer is etched through the plurality of through-holes to form a hollow cavity in the second semiconductor layer.

[0040] A fourth semiconductor layer is filled in the plurality of through holes.

[0041] Parts of the third semiconductor layer and the second semiconductor layer are removed to form a plurality of rectangular grooves in the second semiconductor layer.

[0042] The plurality of rectangular grooves are spaced apart from each other along the first direction and respectively penetrate the second semiconductor layer. The hollow cavity surrounds the outer sides of the plurality of rectangular grooves along the first direction and the second direction. The first direction and the second direction are perpendicular to each other.

[0043] Furthermore, after forming the rectangular groove, the method may further include:

[0044] A plurality of through silicon vias (TSVs) are formed in the first semiconductor layer below each of the rectangular grooves by using a TSV process.

[0045] Furthermore, the material of the through silicon via may include a metal material.

[0046] Compared with the prior art, the present invention has at least the following beneficial effects:

[0047] As described above, in the optoelectronic device packaging structure provided by the present invention, the thermal management structure may include multiple semiconductor layers, wherein the second semiconductor layer located in the middle position is provided with a plurality of rectangular grooves arranged in a spaced relationship from each other, and a plurality of through-silicon vias (TSVs) are provided in the first semiconductor layer below each rectangular groove, and a hollow cavity (vacuum cavity) surrounding the first semiconductor layer is provided on the outside of each rectangular groove. On the one hand, by arranging different radiation detection components of the optoelectronic device in different rectangular grooves, the low thermal conductivity of the semiconductor material and the hollow cavity is utilized to isolate the thermal disturbance of the external alternating thermal field environment on the optoelectronic device, and to isolate the radiation crosstalk between different radiation detection components. On the other hand, through the TSVs below the rectangular grooves, the different radiation detection components are electrically connected to each other and to other external devices, while the TSVs serve as heat sinks for the radiation detection components, thereby achieving the purpose of timely dissipating the internal heat of the radiation detection components. That is, while isolating the thermal disturbance of the optoelectronic device in the external alternating thermal field environment, the internal temperature of the optoelectronic device is kept stable, thereby ultimately improving the efficiency and reliability of the optoelectronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following detailed description, they are used to explain the present application but do not constitute a limitation of the present application. In the accompanying drawings:

[0049] Figure 1 This is a three-dimensional illustration of a partial structure of a thermal management structure in an optoelectronic device packaging structure provided in one embodiment of the present invention.

[0050] Figure 2 for Figure 1 The thermal management structure is shown in a top view in the third direction (the direction perpendicular to the substrate surface).

[0051] Figure 3 for Figure 1 A cross-sectional view of the thermal management structure is shown in the second direction (a direction parallel to the substrate surface).

[0052] Figure 4 It is a schematic three-dimensional diagram of another partial structure of the optoelectronic device packaging structure provided in one embodiment of the present invention.

[0053] Figures 5 to 12 Schematic diagram of the structure of the optoelectronic device packaging structure during the preparation process provided in one embodiment of the present invention.

[0054] Wherein, the accompanying drawings are marked as follows:

[0055] 31-substrate, 311-substrate circuit, 200-thermal management structure, 21-a radiation detection component in an optoelectronic device, 201-first semiconductor layer, 202-second semiconductor layer, 203-third semiconductor layer, 204-fourth semiconductor layer, 11-hollow cavity, 12-rectangular groove, 121-through silicon via, 2031-perforation, 41-first filter, 42-second filter, D1-first direction, D2-second direction, D3-third direction.

[0056] In the drawings, like components are given like reference numerals, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0057] In order to make the technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present invention, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0058] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. It is understood that the meanings of "on...", "above..." and "above..." in the present invention should be interpreted in the broadest way, so that "on..." not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers. In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be arbitrarily combined without conflict.

[0059] For the convenience of description, a first direction, a second direction and a third direction are proposed below, wherein the first direction is parallel to the surface of the substrate or the first semiconductor layer, and corresponds to D1 in the accompanying drawing, hereinafter referred to as the first direction D1; the second direction is perpendicular to the first direction and is located in the same plane, and corresponds to D2 in the accompanying drawing, hereinafter referred to as the second direction D2; the third direction is perpendicular to the surface of the substrate or the first semiconductor layer, that is, the third direction is perpendicular to the plane where the first direction and the second direction are located, and the third direction corresponds to D3 in the accompanying drawing, hereinafter referred to as the third direction D3.

[0060] Please refer to Figure 1 , Figure 1 The figure shows a partial perspective view of the structure of the optoelectronic device package provided in one embodiment of the present invention. The optoelectronic device package structure of the present invention can be used to manufacture optoelectronic devices such as thermoelectric sensors. Without departing from the spirit of the present invention, the present invention can also be applied to other types of optoelectronic devices. Figure 1 As shown, the optoelectronic device packaging structure may include a substrate 31, at least one thermal management structure 200, and an optoelectronic device (not shown in full, only a radiation detection component 21 included therein is shown); wherein each thermal management structure 200 may include: a first semiconductor layer 201, a second semiconductor layer 202, a third semiconductor layer 203, and a fourth semiconductor layer 204.

[0061] Specifically, the first semiconductor layer 201 is located on the substrate 31, and the substrate 31 can be a PCB board. A substrate circuit 311 is formed on the substrate 31, and the substrate circuit 311 can be a plurality of electrical connection lines and pads to achieve electrical connection between different components in the same optoelectronic device and / or between different optoelectronic devices; exemplarily, the substrate circuit 311 can be electrically connected to the first semiconductor layer 201 and the components and / or devices therein, such as silicon through-holes 121, by using conductive glue, or can be electrically connected to the first semiconductor layer 201 and the components and / or devices therein, such as silicon through-holes 121, by using micro-bump technology, and is not limited thereto; the first semiconductor layer 201 is located on the substrate 31, and the optoelectronic device or a sensitive element in the optoelectronic device, such as a radiation detection component 21 of a thermoelectric sensor, is electrically connected to the substrate 31 through the silicon through-holes 121 located in the first semiconductor layer 201; the second semiconductor layer 202 is located on the first semiconductor layer 201, and the second semiconductor layer 202 includes a plurality of rectangular The plurality of rectangular grooves 12 and a hollow cavity 11 can be arranged in the second semiconductor layer 202 along the first direction D1 and / or the second direction D2, and the hollow cavity 11 can surround the outer sides of the plurality of rectangular grooves 12 along the first direction D1 and the second direction D2; in one embodiment, the shape of each of the rectangular grooves 12 can be a rectangular frame extending along the first direction D1 and the second direction D2, that is, the rectangular groove 12 is not provided with a top cover and a bottom, that is, the rectangular groove 12 is passed through Through the second semiconductor layer 202; the hollow cavity 11 can be a vacuum cavity structure extending continuously along the first direction D1 and the second direction D2, and the hollow cavity 11 surrounding the outside of each rectangular groove 12 is in the shape of a rectangular frame or an annular frame, that is, the hollow cavity 11 also has no top cover and bottom, that is, the hollow cavity 11 also passes through the second semiconductor layer 202, and the top surface of the hollow cavity 11 is flush with the top surface of the second semiconductor layer 202 (or at the same horizontal height).

[0062] Under this setting, since the second semiconductor layer 202 is located on the first semiconductor layer 201, and the first semiconductor layer 201 and the second semiconductor layer 202 are integrally formed, the first semiconductor layer 201 serves as the bottom of the plurality of rectangular grooves 12 and the hollow cavity 11. The third semiconductor layer 203 and the fourth semiconductor layer 204 are located on the same horizontal plane and are both located on the second semiconductor layer 202. That is, the third semiconductor layer 203 and the fourth semiconductor layer 204 jointly serve as the top cover of the hollow cavity 11 to combine the hollow cavity 11 into a closed vacuum cavity structure. The second semiconductor layer 202 located on both sides of the hollow cavity 11 serves as the side walls of the hollow cavity 11 (the left and right side walls distributed along the first direction D1).

[0063] Please refer to Figure 2 and Figure 3 , Figure 2 What is shown is Figure 1 a top view of the thermal management structure shown in the third direction D3; Figure 3 What is shown is Figure 1 a cross-sectional view of the thermal management structure shown in the second direction D2; As Figure 2 and Figure 3 shown, if the sum of the heights (or thicknesses) of the first semiconductor layer 201, the second semiconductor layer 202, and the third semiconductor layer 203 (or the fourth semiconductor layer 204) in the third direction D3 can be h, where the height (or thickness) of the first semiconductor layer 201 in the third direction D3 can be h1, the sum of the heights (or thicknesses) of the second semiconductor layer 202 (or the rectangular groove 12) and the third semiconductor layer 203 (and / or the fourth semiconductor layer 204) in the third direction D3 can be hz, the height (or thickness) of the third semiconductor layer 203 or the fourth semiconductor layer 204 in the third direction D3 can be h3, and the spacing distance between the side walls / outer side walls of adjacent rectangular grooves 12 in the first direction D1 (i.e., the width of the hollow cavity 11 between adjacent rectangular grooves 12 in the first direction D1) can be W1, then h2 = h - h1, W1 < h2, and the value of W1 is determined by the value of h2. For example, h2 can be 2 to 4 times that of W1, but not limited thereto. Moreover, the crosstalk situation between the radiation detection components 12 located in different rectangular grooves 12 is also related to the sum of the heights or thicknesses h2 of the second semiconductor layer 202 and the third semiconductor layer 203 (and / or the fourth semiconductor layer 204) in the third direction D3. For example, if it is assumed that the minimum anti-crosstalk height of the hollow cavity 11 between adjacent rectangular grooves 12 for the radiation detection components 12 located in adjacent rectangular grooves 12 is h critical , then h2 ≥ h critical .

[0064] It should be understood that according to the law of conservation of energy and the law of blackbody radiation, the heat source outside the optoelectronic device packaging structure can transfer heat to the optoelectronic device or its sensitive elements such as radiation detection components through three pathways: thermal conductivity of the thermal management structure itself, radiation thermal conductivity, and thermal conductivity of the gas in the optoelectronic device packaging structure shell (i.e., the central control cavity 11). Therefore, the total thermal conductivity G of the thermal management structure 200 in the embodiment of the present invention is obtained. T Can be: G T =G S +G r +G g , where G S is the thermal conductivity of the thermal management structure 200 itself, G r is the radiation thermal conductivity, G g is the gas thermal conductivity in the hollow cavity 11 of the thermal management structure 200. T G in the formula S The calculation formula can be:

[0065] ;

[0066] G ring-wall =λV ring-wall ;

[0067] V ring-wall =((W-2W lateral )*L lateral *h2)-(W-2W lateral )*W1*(h2-h3))+(2*L*W lateral *h2-2*L*W1*(h2-h3));

[0068] G spacer =λ*((W-2W lateral )*L lateral *h2-(W-2W lateral )*W1*(h2-h3));

[0069] G bottom =λ*W*L*h1;

[0070] Among them, G ring-wall is the thermal conductivity of the semiconductor material of the second semiconductor layer 202 constituting the hollow cavity 11 of the thermal management structure 200, G spacer is the thermal conductivity of the gas in the hollow cavity 11 constituting the thermal management structure 200, G bottomis the thermal conductivity of the semiconductor material of the first semiconductor layer 201 constituting the bottom of the thermal management structure 200, λ is the thermal conductivity of the semiconductor material of the second semiconductor layer 202 constituting the thermal management structure 200, L is the length of the first semiconductor layer 201 in the thermal management structure 200 in the first direction D1, W is the width of the first semiconductor layer 201 in the thermal management structure 200 in the second direction D2, h1 is the height of the first semiconductor layer 201 in the third direction D3, h2 is the sum of the heights of the second semiconductor layer 202 and the third semiconductor layer 203 (and / or the fourth semiconductor layer 204) in the third direction D3, h3 is the height (or thickness) of the third semiconductor layer 203 or the fourth semiconductor layer 204 in the third direction D3, W1 is the width of the portion of the hollow cavity 11 located between adjacent rectangular grooves 12 in the first direction D1, L spacer is the width of the distance between two connected matrix grooves 12 in the first direction D1, and L spacer =W1+2W wall , V ring-wall is the volume of the cavity wall of the hollow cavity 11 of the heat management structure 200 close to the outer sidewall of the second semiconductor layer 202, V spacer V is the volume of the cavity wall of the hollow cavity 11 of the heat management structure 200 away from the outer sidewall of the second semiconductor layer 202, bottom is the bottom volume of the thermal management structure 200 .

[0071] Thus, the heat management structure 200 with the hollow cavity 11 (vacuum isolation chamber) performs the radiative heat conduction. r It can be calculated by the following formula:

[0072] ;

[0073] in, and are the hemispherical infrared emissivities of the outer sidewall (the outer surface extending along the third direction D3) and the inner sidewall (the inner surface extending along the third direction D3) of the thermal management structure 200, respectively. A1 and A2 are the inner sidewall area and the outer sidewall area of ​​the thermal management structure 200, respectively. σ is the Stefan-Boltzmann constant, σ=5.67*10 -8 W / (m 2 *K 4 ), T1 and T2 are the temperatures of the outer sidewall and inner sidewall of the thermal management structure 200, respectively, in K. For ease of understanding, based on Figure 1 As shown, Figure 1 Reference numeral “ 200 a ” is used to identify the outer sidewall of the thermal management structure 200 , and reference numeral “ 200 b ” is used to identify the inner sidewall of the thermal management structure 200 .

[0074] Since the top of the rectangular groove 12 of the heat management structure 200 in the embodiment of the present invention is open (ie, there is no top cover), the gas thermal conductivity G of this part is not considered in the design of the heat management structure 200. g In order to minimize the impact of the external environment's thermal field on optoelectronic devices such as radiation detection components in thermoelectric sensors, it is hoped that the total thermal conductivity G of the thermal management structure 200 is T Obviously, the height or thickness h3 of the third semiconductor layer 203 or the fourth semiconductor layer 204 in the third direction D3 in the thermal management structure 200 in the embodiment of the present invention should be taken as the minimum value that meets the manufacturing process and structural mechanical strength.

[0075] Furthermore, in order to allow the heat received from the outside world by the optoelectronic device, such as the radiation detection component in the thermoelectric sensor (including the heat transferred through the thermal management structure 200 and the heat radiated from the measurement target and received by the optoelectronic device, such as the radiation detection component in the thermoelectric sensor) to diffuse to the thermal management structure 200, it is also desired that the thermal management structure 200 has a large heat capacity and a small thermal resistance.

[0076] Based on this, the total thermal conductance of the thermal management structure 200 in the embodiment of the present invention can be expressed as:

[0077] G T =G ring-wall +G spacer +G bottom =λ(V ring-wall +V spacer +V bottom );

[0078] Wherein, λ is the thermal conductivity of the semiconductor material (such as single crystal silicon) of the second semiconductor layer 202 of the thermal management structure 200, V ring-wall is the volume of the cavity wall of the hollow cavity 11 of the heat management structure 200 close to the outer sidewall of the second semiconductor layer 202, V spacer V is the volume of the cavity wall of the hollow cavity 11 of the heat management structure 200 away from the outer sidewall of the second semiconductor layer 202, bottom is the bottom volume of the thermal management structure 200 .

[0079] Furthermore, considering the need to prevent crosstalk between different radiation detection components in optoelectronic devices such as pyroelectric sensors, the above formula must also satisfy the following conditions:

[0080] h2≥h critical ;

[0081] Among them, h critical The minimum anti-crosstalk height can be calculated and determined based on the field angle of the optoelectronic device, such as the pyroelectric sensor, the installation position of the radiation detection component, and the size of the optical sensitive area.

[0082] In summary, the thermal conductivity of the thermal management structure in the embodiment of the present invention is determined by the design model, which is: G T =f(h1,W1,W wall ,L spacer ), and the constraints of the design model are:

[0083] 0 max ;

[0084] h2=(h-h1)≥h critical ;

[0085] L lateral =W lateral ;

[0086] W wall-min ≤W wall ≤W wall-max ;

[0087] W 1-min ≤W1≤W 1-max ;

[0088] L spacer-min ≤L spacer ≤L spacer-max ;

[0089] Wherein, h is the sum of the heights of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the third direction, h max is the maximum value given by h, h1 is the height of the first semiconductor layer in the third direction, h2 is the height of the second semiconductor layer and the third semiconductor layer or the fourth semiconductor layer in the third direction, W1 is the width of the portion of the hollow cavity located between adjacent rectangular grooves in the first direction, W wall is the width from the sidewall of the hollow cavity to the outer wall of the second semiconductor layer in the first direction, L spacer is the width of the distance between two connected matrix grooves in the first direction, and L spacer =W1+2W wall , W wall-min and W 1-max It's W wall Given the maximum and minimum values, W 1-min and W 1-max is the maximum and minimum value given by W1, L spacer-min and L spacer-max It's L spacer Given the maximum and minimum values, h critical is the minimum anti-crosstalk height of h2, L lateral is the width from the sidewall of the rectangular groove to the outer sidewall of the second semiconductor layer in the first direction, W​lateral is the width in the second direction from the sidewall of the rectangular groove to the outer sidewall of the second semiconductor layer.

[0090] In one embodiment, the first semiconductor layer 201, the second semiconductor layer 202, the third semiconductor layer 203 and the fourth semiconductor layer 204 are all made of semiconductor materials, wherein the first semiconductor layer 201 and the second semiconductor layer 202 are made of the same material, for example, a silicon substrate, a silicon-containing substrate or other suitable materials but not limited thereto, and the two are integrally formed, while the second semiconductor layer 202 and the third semiconductor layer 203 must be made of different materials, for example, the second semiconductor layer 202 is made of a silicon wafer, and the third semiconductor layer 203 can be made of a silicon wafer. The fourth semiconductor layer 204 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nitrogen-doped silicon carbide, a low-k dielectric material such as fluorosilicate glass, carbon silicon oxide, spin-on silicon glass, a porous low-k dielectric material, or a combination of the above materials. The material of the fourth semiconductor layer 204 may be the same as or different from the material of the first semiconductor layer 201 or the second semiconductor layer 202. For example, the material of the fourth semiconductor layer 204 may be silicon wafer or polysilicon, but is not limited thereto. The through silicon via 121 is filled with a metal material, such as copper or tungsten, but is not limited thereto.

[0091] Since the embodiment of the present invention does not adopt conventional TO packaging or other methods when packaging optoelectronic devices such as a thermoelectric sensor, but proposes a thermal management structure, and then encapsulates the radiation detection components of the thermoelectric sensor in different rectangular grooves of the thermal management structure, so as to achieve isolation of thermal disturbances of the external alternating thermal field environment on the optoelectronic device and isolation of radiation crosstalk between different radiation detection components through the low thermal conductivity of the hollow cavity of the thermal management structure and the material of the multi-layer semiconductor layer constituting the hollow cavity; and, through silicon vias under the rectangular grooves, it is also possible to achieve electrical connection between different radiation detection components and with other external devices while using the silicon vias as heat sinks for the radiation detection components, so as to achieve the purpose of timely extracting the internal heat of the radiation detection component, that is, to achieve the purpose of maintaining the internal temperature of the optoelectronic device stable.

[0092] Please refer to Figure 4 , Figure 4 The figure shows another partial structural perspective diagram of the optoelectronic device packaging structure provided in one embodiment of the present invention. It should be understood that a person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the optoelectronic device packaging structure of the present invention may also have other aspects and is not limited to the above, such as Figure 4As shown, after providing the heat management structure 200, a radiation detection component 21 of the pyroelectric sensor can be packaged in each rectangular groove 12 of the heat management structure 200, and the bottom of each radiation detection component 21 is in direct contact with the top of the silicon through-via 121 formed in the first semiconductor layer 201 at the bottom of the corresponding rectangular groove 12. Then, a filter can be further formed above each rectangular groove 12, for example Figure 4 The first filter 41 and the second filter 42 are shown, but the present invention is not limited thereto.

[0093] It should be understood that the embodiments of the present invention Figure 1 and Figure 4 Only two rectangular grooves 12 are provided in the thermal management structure 200. In other embodiments, the thermal management structure 200 may have more rectangular grooves 12. The specific number of rectangular grooves 12 may be determined based on the number of radiation detection components included in the optoelectronic device, such as a thermoelectric sensor, to be packaged in the thermal management structure 200. In other embodiments, the thermal management structure 200 may be used as a packaging structure for multiple optoelectronic devices, such as thermoelectric sensors. For example, each rectangular groove 12 in the thermal management structure 200 may enclose and package an optoelectronic device, such as a thermoelectric sensor, so that different optoelectronic devices, such as thermoelectric sensors, are isolated by the hollow cavity 11 between adjacent rectangular grooves 12 and the semiconductor material of the second semiconductor layer 202. The through-silicon via 121 in the first semiconductor layer 201 below each rectangular groove 12 serves as a heat sink or heat dissipation device for the corresponding optoelectronic device, such as a thermoelectric sensor.

[0094] In order to enable a person skilled in the art to easily understand the optoelectronic device packaging structure of the first to third embodiments of the present invention, the present invention further provides a method for preparing the optoelectronic device packaging structure. The following will further illustrate the method for preparing the optoelectronic device packaging structure proposed by the present invention in conjunction with various structural schematic diagrams of the method during the preparation process. Figures 5 to 12 Schematic diagram of the structure of the manufacturing method of the optoelectronic device packaging structure provided in an embodiment of the present invention during the manufacturing process.

[0095] See also Figure 5First, a deposition process such as at least one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process is used to form an integral first semiconductor layer 201 and a second semiconductor layer 202 (made of, for example, a silicon wafer). Then, a deposition process such as a chemical vapor deposition process is used to form the third semiconductor layer 203 (made of, for example, silicon dioxide or silicon nitride) on the surface of the second semiconductor layer 202. The third semiconductor layer 203 serves as a hard mask layer. Then, an etching method such as at least one of dry etching and wet etching is used to form a plurality of through-holes 2031 in the third semiconductor layer 203. The plurality of through-holes 2031 may be arranged at intervals along the first direction D1 and the second direction D2, and their projections on the first semiconductor layer 201 or the substrate 31 overlap with the projection of the hollow cavity 11.

[0096] See also Figure 6 Then, the second semiconductor layer 202 is etched downward through or along the plurality of through-holes 2031 using an etching process, such as a wet etching process, to form a hollow cavity 11 extending in the first direction D1 and the second direction D2 in the second semiconductor layer 202 below the plurality of through-holes 2031, and the etching stops when the top of the first semiconductor layer 201 is exposed. The hollow cavity 11 thus formed penetrates the total depth or length of the second semiconductor layer 202 in the third direction D3, thereby allowing the first semiconductor layer 201 below to serve as the bottom of the hollow cavity 11.

[0097] See also Figure 7 and Figure 8 , and then the fourth semiconductor layer 204 (material is, for example, polysilicon or doped polysilicon) can be filled in the plurality of through-holes 2031 by using a deposition process, such as a chemical deposition process, so that the third semiconductor layer 203 remaining after the plurality of through-holes 2031 are formed and the fourth semiconductor layer 204 located at the plurality of through-holes 2031 are at the same level, that is, the top surfaces are flush and the side walls are in contact with each other, thereby forming a top cover of the hollow cavity 11 located in the second semiconductor layer 202; it should be understood that in order to facilitate the observation of the structural shape of the hollow cavity 11 located in the second semiconductor layer 202, the embodiment of the present invention provides Figure 7 is a schematic diagram of a local structure of the thermal conductive structure 200 after removing part of the structure. Figure 8 for Figure 7 A perspective structural diagram of the local structure shown.

[0098] See also Figure 9 and Figure 10Then, an etching process, such as a dry etching process, can be used to sequentially remove a portion of the third semiconductor layer 203 and a portion of the second semiconductor layer 202 located thereunder vertically downward along the third direction D3, so as to form a plurality of rectangular grooves 12 spaced apart from each other along the first direction D1 and / or the second direction D2 in the second semiconductor layer 202 exposed after the removal of a portion of the third semiconductor layer 203; wherein each of the rectangular grooves 12 is used to encapsulate a radiation detection component of an optoelectronic device, such as a pyroelectric sensor, or to encapsulate an optoelectronic device, such as a pyroelectric sensor. Furthermore, in order to facilitate observation of the structural shape and location of the rectangular grooves 12 located in the second semiconductor layer 202, the embodiment of the present invention provides Figure 9 is a schematic diagram of a local structure of the thermal conductive structure 200 after removing part of the structure. Figure 10 for Figure 9 A perspective structural diagram of the local structure shown.

[0099] See also Figure 11 and Figure 12 , and then a through silicon via process can be further used to form a plurality of contact holes in the first semiconductor layer 201 exposed at the bottom of each rectangular groove 12, and then a metal material such as copper is filled in each contact hole, that is, a through silicon via 121 (contact hole filled with metal material) is formed in the first semiconductor layer 201 and used to electrically connect the substrate 31 and the optoelectronic device or a sensitive element in the optoelectronic device; similarly, in order to facilitate the observation of the structural shape and setting position of the through silicon via 121 located in the first semiconductor layer 201, the embodiment of the present invention provides Figure 11 is a schematic diagram of a local structure of the thermal conductive structure 200 after removing part of the structure. Figure 12 for Figure 11 A perspective structural diagram of the local structure shown.

[0100] In summary, the thermal management structure of the optoelectronic device packaging structure in the present invention may include multiple semiconductor layers, wherein the second semiconductor layer located in the middle position is provided with a plurality of rectangular grooves arranged in a spaced relationship from each other, a plurality of through-silicon vias (TSVs) are provided in the first semiconductor layer below each rectangular groove, and a hollow cavity (vacuum cavity) surrounding the first semiconductor layer is provided on the outside of each rectangular groove. On the one hand, by arranging different radiation detection components of the optoelectronic device in different rectangular grooves, the low thermal conductivity of the semiconductor material and the hollow cavity is utilized to isolate the thermal disturbance of the external alternating thermal field environment on the optoelectronic device, and to isolate the radiation crosstalk between different radiation detection components. On the other hand, through the TSVs below the rectangular grooves, the different radiation detection components are electrically connected to each other and to other external devices, while the TSVs serve as heat sinks for the radiation detection components, thereby achieving the purpose of timely dissipating the internal heat of the radiation detection components. That is, while isolating the thermal disturbance of the optoelectronic device in the external alternating thermal field environment, the internal temperature of the optoelectronic device is kept stable, thereby ultimately improving the efficiency and reliability of the optoelectronic device.

[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A photoelectric device packaging structure, characterized in that: include: substrate; At least one thermal management structure is located on the substrate, the thermal management structure comprising: a first semiconductor layer; a second semiconductor layer, located on the first semiconductor layer, comprising a plurality of rectangular grooves spaced apart from each other along a first direction and respectively penetrating the second semiconductor layer, and a hollow cavity surrounding the plurality of rectangular grooves along the first and second directions and located within the second semiconductor layer; a third semiconductor layer, located on the second semiconductor layer, wherein a projection of the third semiconductor layer overlaps with a projection of the second semiconductor layer in a third direction; The second semiconductor layer and the first semiconductor layer are integrally formed, the first direction and the second direction are perpendicular to each other, and the third direction is perpendicular to the plane where the first direction and the second direction are located.

2. The optoelectronic device packaging structure according to claim 1, wherein: The portion of the hollow cavity surrounding the outside of the rectangular groove is in the shape of a rectangular frame or an annular frame.

3. The optoelectronic device packaging structure according to claim 2, wherein: The top surface of the hollow cavity is flush with the top surface of the second semiconductor layer.

4. The optoelectronic device packaging structure according to claim 2, wherein: The width of the portion of the hollow cavity located between adjacent rectangular grooves in the first direction is a first width, and the height of the second semiconductor layer in the third direction is a first height, which is 2 to 4 times the value of the first width.

5. The optoelectronic device packaging structure according to claim 1, wherein: The thermal management structure further includes: A plurality of through silicon vias are arranged in the first semiconductor layer below the rectangular groove and spaced apart from each other along the first direction and / or the second direction.

6. The optoelectronic device packaging structure according to claim 1, wherein: The first semiconductor layer and the second semiconductor layer are made of the same material, and the second semiconductor layer and the third semiconductor layer are made of different materials.

7. The optoelectronic device packaging structure according to claim 1, wherein: The thermal management structure further includes: A fourth semiconductor layer is located on the second semiconductor layer, with its top flush with the top of the third semiconductor layer, its sidewall in contact with the third semiconductor layer, and in the third direction, the sum of the projections of the fourth semiconductor layer and the third semiconductor layer completely overlaps with the projection of the second semiconductor layer.

8. The optoelectronic device packaging structure according to claim 5, wherein: Also includes: The pyroelectric sensor includes a plurality of radiation detection components, wherein one of the radiation detection components is located in one of the rectangular grooves in the thermal management structure.

9. The optoelectronic device packaging structure according to claim 8, wherein: The bottom of the radiation detection component is in direct contact with the top of the through silicon via.

10. The optoelectronic device packaging structure according to claim 8, wherein: Also includes: An adhesive layer is located between the substrate and the first semiconductor layer, and / or between the radiation detection component and the first semiconductor layer.

11. The optoelectronic device packaging structure according to claim 10, wherein: The adhesive layer includes conductive glue.

12. The optoelectronic device packaging structure according to claim 7, wherein: The thermal conductivity of the thermal management structure is determined by a design model, which is: G T =f(h1,W1,W wall ,L spacer ), and the constraints of the design model are: 0 max ;​ h2=(h-h1)≥h critical ; L lateral =W lateral ; IN wall-min ≤W wall ≤W wall-max ; IN 1-min ≤W1≤W 1-max ; L spacer-min ≤L spacer ≤L spacer-max ; Wherein, h is the sum of the heights of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the third direction, h max is the maximum value given by h, h1 is the height of the first semiconductor layer in the third direction, h2 is the sum of the heights of the second semiconductor layer and the third semiconductor layer or the fourth semiconductor layer in the third direction, h3 is the height of the third semiconductor layer or the fourth semiconductor layer in the third direction, W1 is the width of the portion of the hollow cavity located between adjacent rectangular grooves in the first direction, W wall is the width from the sidewall of the hollow cavity to the outer wall of the second semiconductor layer in the first direction, L spacer is the width of the distance between two connected matrix grooves in the first direction, and L spacer =W1+2W wall , W wall-min and W 1-max It's W wall Given the maximum and minimum values, W 1-min and W 1-max is the maximum and minimum value given by W1, L spacer-min and L spacer-max It's L spacer Given the maximum and minimum values, h critical is the minimum anti-crosstalk height of h2, L lateral is the width from the sidewall of the rectangular groove to the outer sidewall of the second semiconductor layer in the first direction, W lateral is the width in the second direction from the sidewall of the rectangular groove to the outer sidewall of the second semiconductor layer.

13. A method for manufacturing a photovoltaic device packaging structure according to any one of claims 1 to 12, characterized in that: include: providing a first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer and the first semiconductor layer are integrally formed; forming a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is provided with a plurality of through holes spaced apart from each other along a first direction and a second direction; etching the second semiconductor layer through the plurality of through-holes to form a hollow cavity in the second semiconductor layer; filling the plurality of through holes with a fourth semiconductor layer; removing portions of the third semiconductor layer and the second semiconductor layer to form a plurality of rectangular grooves in the second semiconductor layer; The plurality of rectangular grooves are spaced apart from each other along the first direction and respectively penetrate the second semiconductor layer. The hollow cavity surrounds the outer sides of the plurality of rectangular grooves along the first direction and the second direction. The first direction and the second direction are perpendicular to each other.

14. The method for manufacturing a photoelectric device packaging structure according to claim 13, wherein: After forming the rectangular groove, the method further comprises: A plurality of through silicon vias (TSVs) are formed in the first semiconductor layer below each of the rectangular grooves by using a TSV process.

15. The method for manufacturing a photoelectric device packaging structure according to claim 14, wherein: The material of the through silicon via includes metal material.

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