Light-emitting element

Abstract

The light emitting element includes a bonding electrode and a light emitting stack including a first semiconductor layer, an active layer, and a second semiconductor layer disposed in this order on the bonding electrode. At least one protruding structure is defined on an upper surface of the light emitting stack, and the protruding structure includes a first protruding portion protruding in a direction away from the bonding electrode and defining a groove recessed in a direction facing the bonding electrode, and a second protruding portion protruding in the groove of the first protruding portion in a direction away from the bonding electrode.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0015232, filed on January 31, 2024, with the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a light - emitting element and a display device including the light - emitting element. Background art

[0004] A display device includes a light - emitting element that emits light. The display device displays an image by combining the light emitted from the light - emitting element.

[0005] Each of the light - emitting elements may be aligned (or disposed) at a preset position in the display device. In the case where the alignment of the light - emitting elements is defective, the display quality of the display device may deteriorate.

[0006] When the emission efficiency of the light - emitting element is improved, the display quality of the display device can also be improved. Summary of the invention

[0007] An object of the present disclosure is to provide a light - emitting element capable of improving display quality and a display device including the light - emitting element.

[0008] According to an embodiment of the present disclosure, a light - emitting element may include a bonding electrode and a light - emitting stack including a first semiconductor layer, an active layer, and a second semiconductor layer sequentially disposed on the bonding electrode. At least one protruding structure may be defined on the upper surface of the light - emitting stack, and the protruding structure may include a first protruding portion that protrudes in a direction away from the bonding electrode and defines a groove that is recessed in a direction facing the bonding electrode, and a second protruding portion that protrudes in a direction away from the bonding electrode in the groove of the first protruding portion.

[0009] In an embodiment, the second protruding portion may be spaced apart from the inner surface of the groove of the first protruding portion that is recessed in a direction facing the bonding electrode.

[0010] In an embodiment, the second protruding portion may include a 2 - 1 protruding portion having a height approximately equal to the depth of the groove and a 2 - 2 protruding portion disposed on the 2 - 1 protruding portion.

[0011] In an embodiment, the 2 - 2 protruding portion may have a substantially conical shape.

[0012] In an embodiment, the protruding structure and the second semiconductor layer may be integral.

[0013] In an embodiment, the first protrusion and the second protrusion may be integral.

[0014] In an embodiment, the protrusion structure may include a first protrusion structure disposed at the center of the upper surface of the light-emitting stack in a plan view.

[0015] In an embodiment, the protrusion structure may include a plurality of second protrusion structures, and the plurality of second protrusion structures may be symmetrically disposed with respect to the center of the upper surface of the light-emitting stack in a plan view.

[0016] In an embodiment, the first semiconductor layer may have a first polarity, and the second semiconductor layer may have a second polarity different from the first polarity.

[0017] In an embodiment, the second semiconductor layer may include a first doped portion and a second doped portion sequentially defined on the active layer, and a first average doping concentration of dopants in the first doped portion may be greater than a second average doping concentration of dopants in the second doped portion.

[0018] According to an embodiment of the present disclosure, a display device may include a light-emitting element connected between an anode electrode and a cathode electrode. The light-emitting element may include a bonding electrode and a light-emitting stack including a first semiconductor layer, an active layer, and a second semiconductor layer sequentially disposed on the bonding electrode. At least one protrusion structure may be defined on the upper surface of the light-emitting stack, and the protrusion structure may include a first protrusion protruding in a direction away from the bonding electrode and defining a groove recessed in a direction facing the bonding electrode, and a second protrusion protruding in a direction away from the bonding electrode in the groove of the first protrusion.

[0019] In an embodiment, the second protrusion may be spaced apart from an inner surface of the groove defined by the first protrusion.

[0020] In an embodiment, the second protrusion may include a 2-1 protrusion having a height approximately equal to the depth of the groove and a 2-2 protrusion disposed on the 2-1 protrusion.

[0021] In an embodiment, the 2-2 protrusion may have a substantially conical shape.

[0022] In an embodiment, the protrusion structure and the second semiconductor layer may be integral.

[0023] In an embodiment, the first protrusion and the second protrusion may be integral.

[0024] In an embodiment, the protrusion structure may include a first protrusion structure disposed at the center of the upper surface of the light-emitting stack in a plan view.

[0025] In an embodiment, the protruding structure may include a plurality of second protruding structures, and the plurality of second protruding structures may be symmetrically disposed with respect to the center of the upper surface of the light-emitting stack in a plan view.

[0026] In an embodiment, the bonding electrode may be disposed on the anode electrode and may be electrically connected to the anode electrode.

[0027] In an embodiment, the cathode electrode may be disposed on the anode electrode to face the anode electrode and may cover the upper surface of the light-emitting stack defining the protruding structure.

[0028] In a light-emitting element according to an embodiment of the present disclosure, the protruding structure defined on the upper surface of the light-emitting stack may include a first protrusion protruding in a direction away from the bonding electrode and defining a groove recessed in a direction facing the bonding electrode, and a second protrusion protruding in a direction away from the bonding electrode in the groove of the first protrusion.

[0029] A display device according to an embodiment of the present disclosure may include a light-emitting element.

[0030] In the case of transporting the light-emitting element, the protruding structure may provide sufficient fixing force to be fixed to the adhesive layer. Accordingly, the alignment reliability of the light-emitting element may be improved, and the display quality of the display device may be improved.

[0031] The uneven structure defined by the protruding structure may improve the light output efficiency by changing the critical angle of light emitted from the light-emitting element. Accordingly, the display quality of the display device may be improved.

[0032] It should be understood that this background art section is partly intended to provide useful background for understanding the technology. However, this background art section may also include ideas, concepts, or understandings that were not known or understood by those skilled in the relevant art before the effective filing date of the corresponding application of the subject matter disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other features of the present disclosure will become more apparent by describing embodiments of the present disclosure in further detail with reference to the accompanying drawings, in which:

[0034] Figure 1 is a block diagram showing a display device according to an embodiment;

[0035] Figure 2 is a block diagram showing one sub-pixel among sub-pixels included in the Figure 1 display device;

[0036] Figure 3 is a schematic plan view showing a display panel of a Figure 1 display device; [[ID=CO]]

[0037] Figure 4 is a schematic cross-sectional view showing an embodiment of a display panel; Figure 3

[0038] Figure 5 is a schematic cross-sectional view showing an embodiment of a display panel; Figure 3

[0039] Figure 6 is a schematic plan view showing a first embodiment of a light-emitting element included in a sub-pixel of; Figure 3

[0040] Figure 7 is a schematic cross-sectional view taken along line X1-X1' of; Figure 6

[0041] Figure 8 is a schematic plan view showing a second embodiment of a light-emitting element included in a sub-pixel of; Figure 3

[0042] Figure 9 is a schematic cross-sectional view taken along line X2-X2' of; Figure 8

[0043] Figure 10 is a schematic plan view showing a third embodiment of a light-emitting element included in a sub-pixel of; Figure 3

[0044] Figure 11 is a schematic plan view showing a fourth embodiment of a light-emitting element included in a sub-pixel of; Figure 3

[0045] Figure 12 is a schematic cross-sectional view taken along line X3-X3' of; Figure 11

[0046] Figure 13 is a schematic plan view showing a fifth embodiment of a light-emitting element included in a sub-pixel of; Figure 3

[0047] Figure 14 is a schematic cross-sectional view showing a method of providing a light-emitting element according to an embodiment;

[0048] Figure 15 is a schematic plan view showing an example of one of the pixels included in a display panel of; Figure 3

[0049] Figure 16 is a schematic cross-sectional view taken along line X4-X4' of; Figure 15 ​​​​​​​​​​​​

[0050] Figure 17 is a block diagram showing a display system according to an embodiment; and

[0051] Figures 18 to 21 is a schematic perspective view showing Figure 17 an application example of the display system of Detailed Embodiments

[0052] Hereinafter, embodiments are described in detail with reference to the accompanying drawings. It should be noted that, in the following description, parts for understanding the operation according to the present disclosure are described, and descriptions of other parts may be omitted so as not to obscure the subject matter of the present disclosure. The present disclosure may be implemented in other forms and is not limited to the embodiments described herein. However, the embodiments described herein are provided to those skilled in the art to which the present disclosure pertains to easily implement the technical spirit of the present disclosure in detail.

[0053] Throughout the specification, when a part is "connected" to another part, this case includes not only the case where the part and the other part are "directly connected", but also the case where the part and the other part are "indirectly connected" and yet another element is disposed therebetween. The terms used herein are for describing embodiments and are not intended to limit the present disclosure.

[0054] Throughout the specification, when a given part "includes" something, this case means that the part may further include another component without excluding the other component, unless otherwise stated.

[0055] "At least any one of X, Y, and Z" and "at least any one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). Here, "and / or" includes all combinations of one or more of the corresponding configurations.

[0056] In the drawings, for ease of description and clarity, the dimensions, thicknesses, ratios, and sizes of elements may be exaggerated. The same reference numerals always refer to the same elements.

[0057] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0058] In the specification and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or".

[0059] Here, terms such as first and second may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Thus, without departing from the scope disclosed herein, the first component may refer to the second component.

[0060] For descriptive purposes, spatially relative terms such as "beneath," "above," etc. may be used to describe the relationship between one element or feature and another(s) as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass other orientations in use, operation, and / or manufacture. For example, when the device shown in the figures is flipped, an element depicted as positioned "beneath" other elements or features will be positioned in the direction "above" the other elements or features. Thus, in an embodiment, the term "beneath" may include both upward and downward directions. The device may face other directions (e.g., rotated 90 degrees or in other directions), and thus the spatially relative terms used herein are to be interpreted accordingly.

[0061] Various embodiments are described with reference to the figures that schematically illustrate ideal embodiments. Thus, it will be appreciated that the shape may vary depending on, for example, tolerances and / or manufacturing techniques. Accordingly, the embodiments disclosed herein should not be construed as limited to the given shapes shown, and should be construed to include, for example, shape variations that occur due to manufacturing. As described above, the shapes shown in the figures may not represent the actual shape of the regions of the device, and the embodiments are not limited thereto.

[0062] The term "overlap" or "overlapping" means that a first object may be above or below, or on one side of, a second object, and conversely, the second object may be above or below, or on one side of, the first object. Additionally, the term "overlap" may include layering, stacking, facing or being oriented towards, extending throughout, covering or partially covering, or any other suitable terms that will be appreciated and understood by one of ordinary skill in the art.

[0063] The terms "face" and "be oriented towards" mean that a first element may be directly or indirectly opposite a second element. In cases where a third element is between the first element and the second element, the first element and the second element may be understood to be indirectly opposite each other, but still face each other.

[0064] When an element is described as "not overlapping" or "not overlapping with" another element, this may include the elements being spaced apart from each other, offset from each other, or separated from each other, or any other suitable terms that will be appreciated and understood by one of ordinary skill in the art.

[0065] As used in this specification, the terms "comprising," "comprises," "including," and / or "includes," "having," "has," and / or "with," and variations thereof specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0066] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation of the particular value as determined by a person of ordinary skill in the art. For example, the term "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0067] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted as idealized or overly formal meanings unless expressly so defined herein.

[0068] Figure 1 is a block diagram showing a display device according to an embodiment.

[0069] Refer to Figure 1 , the display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0070] The display panel DP may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through the first gate line GL1 to the m-th gate line GLm. The sub-pixels SP may be connected to the data driver 130 through the first data line DL1 to the n-th data line DLn.

[0071] The sub-pixels SP may generate light of two or more colors. For example, each of the sub-pixels SP may generate light such as red, green, blue, cyan, magenta, or yellow.

[0072] Two or more of the sub-pixels SP among the sub-pixels SP may configure a pixel PXL. For example, the pixel PXL may include three sub-pixels SP as shown in Figure 1 . The pixel PXL may emit light of various colors and various brightnesses according to the combination of light emitted from the sub-pixels SP included in the pixel PXL.

[0073] The gate driver 120 may be connected to sub-pixels SP arranged or disposed in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output gate signals to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, within the spirit and scope of the present disclosure, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0074] The gate driver 120 may be disposed on one side of the display panel DP. However, the embodiment is not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically divided drivers, and such drivers may be disposed on one side of the display panel DP and on the other side of the display panel DP opposite to that side. As described above, the gate driver 120 may be disposed around the display panel DP in various shapes according to embodiments.

[0075] The data driver 130 is connected to sub-pixels SP arranged or disposed in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, within the spirit and scope of the present disclosure, the data control signal DCS may include a source start signal, a source shift clock, a source output enable signal, and the like.

[0076] The data driver 130 may receive a voltage from the voltage generator 140. The data driver 130 may use the received voltage to apply data signals having gray-scale voltages corresponding to the image data DATA to the first data line DL1 to the n-th data line DLn. In a case where gate signals are applied to each of the first gate line GL1 to the m-th gate line GLm, data signals corresponding to the image data DATA may be applied to the data lines DL1 to DLn. Accordingly, the sub-pixels SP may generate light corresponding to the data signals, and the display panel DP may display an image.

[0077] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0078] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a voltage and supply the generated voltage to components such as the gate driver 120, the data driver 130, and the controller 150 of the display device DD. The voltage generator 140 may generate a voltage by receiving an input voltage from the outside of the display device DD and adjusting the received voltage.

[0079] The voltage generator 140 may generate a first power supply voltage and a second power supply voltage. The generated first power supply voltage and second power supply voltage may be provided to the sub-pixels SP through the power line PL. In an embodiment, at least one of the first power supply voltage and the second power supply voltage may be provided from outside the display device DD.

[0080] The voltage generator 140 may provide various voltages and / or signals. For example, the voltage generator 140 may provide one or more initialization voltages applied to the sub-pixels SP. For example, during a sensing operation for sensing the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixels SP, a predetermined reference voltage may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate the reference voltage and transmit the reference voltage to the data driver 130. For example, during a display operation for displaying an image on the display panel DP, a common pixel control signal may be applied to the sub-pixels SP, and the voltage generator 140 may generate the pixel control signal. In an embodiment, the voltage generator 140 may provide the pixel control signal to the sub-pixels SP through the pixel control line PXCL. In Figure 1 this case, the pixel control line PXCL is connected between the voltage generator 140 and the display panel DP, but the embodiment is not limited thereto. For example, the pixel control line PXCL may be connected between the gate driver 120 and the display panel DP. In this case, the pixel control signal may be transmitted from the voltage generator 140 to the pixel control line PXCL through the gate driver 120.

[0081] The controller 150 controls the overall operation of the display device DD. The controller 150 receives the input image data IMG and the corresponding control signal CTRL from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0082] The controller 150 may convert the input image data IMG such that the input image data IMG is suitable for the display device DD or the display panel DP, and the controller 150 may output the image data DATA. In an embodiment, the controller 150 may output the image data DATA by aligning the input image data IMG such that the input image data IMG is suitable for the sub-pixels SP of the row unit.

[0083] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. As Figure 1As shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally divided components within one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0084] Figure 2 is a block diagram showing one sub-pixel among the sub-pixels included in Figure 1 the display device. In Figure 2 among the sub-pixels SP of Figure 1 as an example, the sub-pixel SPij arranged or set in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) is shown.

[0085] Referring to Figure 2 the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0086] The light-emitting element LD may be connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. The first power supply voltage node VDDN may be connected to Figure 1 one of the power supply lines PL of Figure 1 and may receive the first power supply voltage. The second power supply voltage node VSSN may be connected to

[0087] the other of the power supply lines PL of

[0088] and may receive the second power supply voltage. The first power supply voltage may have a level higher than that of the second power supply voltage. Figure 1 the i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm of Figure 1The j-th data line DLj among the first data line DL1 to the n-th data line DLn. In response to a gate signal received through the i-th gate line GLi, the sub-pixel circuit SPC may control the light-emitting element LD to emit light according to a data signal received through the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC may also be connected to Figure 1 the pixel control line PXCL. In this case, the sub-pixel circuit SPC may further control the light-emitting element LD in response to a pixel control signal received through the pixel control line PXCL.

[0089] For such an operation, the sub-pixel circuit SPC may include circuit elements such as transistors and one or more capacitors.

[0090] The transistors of the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In an embodiment, the transistors of the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, within the spirit and scope of the present disclosure, the transistors of the sub-pixel circuit SPC may include amorphous semiconductor, single-crystalline semiconductor, polycrystalline semiconductor, oxide semiconductor, etc.

[0091] Figure 3 is a schematic plan view showing a display panel of a display device configured Figure 1 as such.

[0092] Referring to Figure 3 , the display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be provided around the display area DA.

[0093] The display panel DP may include sub-pixels SP provided in the display area DA. The sub-pixels SP may be arranged or provided along a first direction DR1 and a second direction DR2 intersecting (or crossing) the first direction DR1. For example, the sub-pixels SP may be arranged or provided in a matrix form along the first direction DR1 and the second direction DR2. As another example, the sub-pixels SP may be arranged or provided in a zigzag form along the first direction DR1 and the second direction DR2. The arrangement of the sub-pixels SP may vary according to the embodiment. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0094] Two or more of the sub-pixels SP may configure one pixel PXL. In Figure 3Among them, the pixel PXL includes three sub-pixels SP1, SP2, and SP3, but the implementation is not limited thereto. For example, the pixel PXL may include two sub-pixels SP. Hereinafter, for ease of description, it is assumed that the pixel PXL includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0095] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can generate light of one of various colors such as red, green, blue, cyan, magenta, and yellow. Hereinafter, for clear and concise description, it is assumed that the first sub-pixel SP1 is configured to generate red light, the second sub-pixel SP2 is configured to generate green light, and the third sub-pixel SP3 is configured to generate blue light.

[0096] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include at least one light-emitting element configured to generate light. In an embodiment, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of the same color. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate blue light. In other embodiments, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of different colors. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate red, green, and blue light, respectively.

[0097] A light-emitting diode display panel (LED display panel) using a micro-scale or nano-scale light-emitting diode as a light-emitting element and a self-emitting display panel such as an organic light-emitting display panel (OLED panel) using an organic light-emitting diode as a light-emitting element may be used as the display panel DP.

[0098] Components for controlling the sub-pixel SP may be provided in the non-display area NDA. Wires connected to the sub-pixel SP, for example, Figure 1 the first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL may be provided in the non-display area NDA.

[0099] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 may be provided in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 may be provided in the non-display area NDA. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be implemented as Figure 1A driver integrated circuit DIC separated from the display panel DP, and the driver integrated circuit DIC can be connected to a line provided in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as an integrated circuit separated from the display panel DP together with the data driver 130, the voltage generator 140, and the controller 150.

[0100] In an embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including sides with straight lines and / or curves. For example, within the spirit and scope of the present disclosure, the display area DA can have a shape such as a polygon, a circle, a semi-circle, an ellipse, etc.

[0101] In an embodiment, the display panel DP can have a flat display surface. In other embodiments, the display panel DP can have a display surface that is at least partially rounded. In an embodiment, the display panel DP can be bendable, foldable, or rollable. In such a case, the display panel DP and / or the substrate of the display panel DP can include a material having a flexible property.

[0102] Figure 4 is a schematic cross-sectional view showing Figure 3 an embodiment of the display panel.

[0103] Referring to Figure 4 , the display panel DP can include a substrate SUB and a pixel circuit layer PCL, a display element layer DPL, and an optical function layer LFL that are sequentially stacked on the substrate SUB in a third direction DR3 intersecting (or crossing) the first direction DR1 and the second direction DR2.

[0104] The substrate SUB can be formed of an insulating material such as glass or resin. For example, the substrate SUB can include a glass substrate. As another example, the substrate SUB can include a polyimide (PI) substrate. As another example, the substrate SUB can include a silicon wafer substrate formed using a semiconductor process.

[0105] In an embodiment, the substrate SUB can be formed of a flexible material that can be bent or folded, and can have a single-layer structure or a multi-layer structure. For example, the flexible material can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0106] The pixel circuit layer PCL may be disposed on the substrate SUB. The pixel circuit layer PCL may include an insulating layer and semiconductor patterns and conductive patterns disposed between the insulating layers. Within the spirit and scope of the present disclosure, the conductive patterns of the pixel circuit layer PCL may be used as circuit elements, lines, etc.

[0107] The circuit elements of the pixel circuit layer PCL may form Figure 3 the sub-pixel circuit SPC for each of the sub-pixels SP in. In other words, the circuit elements of the pixel circuit layer PCL may be provided as transistors and one or more capacitors of the sub-pixel circuit SPC.

[0108] The lines of the pixel circuit layer PCL may include lines connected to the sub-pixels SP. The lines of the pixel circuit layer PCL may include various signal lines and / or voltage lines for driving the display element layer DPL.

[0109] The display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include light-emitting elements of the sub-pixels SP.

[0110] The light function layer LFL may be disposed on the display element layer DPL. The light function layer LFL may include a light conversion pattern having color conversion particles and / or scattering particles. For example, the color conversion particles may include quantum dots. The quantum dots may change the wavelength (or color) of the light emitted from the display element layer DPL. The light function layer LFL may also include a light scattering pattern having scattering particles. In an embodiment, the light conversion pattern and the light scattering pattern may be omitted.

[0111] The light function layer LFL may also include a color filter layer including color filters. The color filters may selectively transmit light of a given wavelength (or a given color). In an embodiment, the color filter layer may be omitted.

[0112] A window for protecting the exposed surface (or the upper surface) of the display panel DP may be disposed on the light function layer LFL. The window may protect the display panel DP from external impacts. The window may be coupled or connected to the light function layer LFL through an optically transparent adhesive (or adhesion) member. The window may have a multi-layer structure selected from a glass substrate, a plastic film, and a plastic substrate. The multi-layer structure may be formed by a continuous process or an adhesion process using an adhesive layer. All or part of the window may be flexible.

[0113] Figure 5 is a schematic cross-sectional view showing Figure 3 an embodiment of the display panel.

[0114] Refer to Figure 5, the display panel DP' may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and an optical function layer LFL. The substrate SUB, the pixel circuit layer PCL, the display element layer DPL, and the optical function layer LFL may be configured identically (or similarly) to the substrate SUB, the pixel circuit layer PCL, the display element layer DPL, and the optical function layer LFL described in the reference Figure 4 Thus, the description of overlapping content may be omitted.

[0115] The input sensing layer ISL may sense a user input on the upper surface (or display surface) of the display panel DP'. The input sensing layer ISL may include components suitable for sensing an external object such as a user's hand or pen. For example, the input sensing layer ISL may include touch electrodes.

[0116] Figure 6 is a schematic plan view showing a first embodiment of a light-emitting element included in a sub-pixel of Figure 3 . Figure 7 is a schematic cross-sectional view taken along line X1-X1' of Figure 6 .

[0117] Referring to Figure 6 and Figure 7 , the light-emitting element LDa may include a bonding electrode BDE, a light-emitting stack EST, and an insulating layer 40. The light-emitting stack EST may include a first semiconductor layer 10, an active layer 20, and a second semiconductor layer 30. The light-emitting element LDa may be implemented as a vertical light-emitting stack in which the bonding electrode BDE, the first semiconductor layer 10, the active layer 20, and the second semiconductor layer 30 may be stacked in sequence along a third direction DR3.

[0118] The first semiconductor layer 10 is configured to provide holes. The first semiconductor layer 10 may have a first polarity. For example, the first semiconductor layer 10 may include at least one p-type semiconductor layer. For example, the first semiconductor layer 10 may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), and barium (Ba). However, the material configuring the first semiconductor layer 10 is not limited thereto, and various other materials may configure the first semiconductor layer 10. In an embodiment, the first semiconductor layer 10 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0119] The second semiconductor layer 30 may be disposed on the first semiconductor layer 10 and may be configured to provide electrons. The second semiconductor layer 30 may have a second polarity different from the first polarity. For example, the second semiconductor layer 30 may include at least one n-type semiconductor layer. For example, the second semiconductor layer 30 may include one of semiconductor materials such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), and tin (Sn). However, the material configuring the second semiconductor layer 30 is not limited thereto, and various other materials may configure the second semiconductor layer 30. In an embodiment, the second semiconductor layer 30 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0120] In an embodiment, the second semiconductor layer 30 may sequentially include a first doped portion 31 and a second doped portion 32 along a third direction DR3. The first doped portion 31 may be a region in which a dopant is doped at a relatively high concentration, and the second doped portion 32 may be a region in which a dopant is doped at a relatively low concentration or substantially no dopant is doped. For example, a first average doping concentration of the dopant in the first doped portion 31 may be greater than a second average doping concentration of the dopant in the second doped portion 32.

[0121] The active layer 20 may be disposed between the first semiconductor layer 10 and the second semiconductor layer 30, and may provide a region where electrons and holes recombine. When electrons and holes recombine in the active layer 20, the electrons and holes may migrate to a lower energy level, and thus light having a corresponding wavelength may be generated. The active layer 20 may be formed as a single quantum well structure or a multi-quantum well structure. In the case where the active layer 20 is formed as a multi-quantum well structure, units including a barrier layer, a strain enhancing layer, and a well layer may be stacked repeatedly with each other to form the active layer 20. However, the active layer 20 is not limited to the above structure.

[0122] The bonding electrode BDE may be disposed under (or below) the first semiconductor layer 10. The bonding electrode BDE may be electrically connected to the first semiconductor layer 10. The bonding electrode BDE may include a eutectic metal.

[0123] In an embodiment, a reflective electrode may also be provided between the bonding electrode BDE and the first semiconductor layer 10. In this case, the light output efficiency of the light emitted from the light-emitting element LDa can be improved. The reflective electrode may be formed of a conductive material having a predetermined reflectivity. The conductive material may include an opaque metal. For example, the opaque metal may include metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the material of the reflective electrode is not limited thereto.

[0124] The insulating layer 40 may cover a part of the outer peripheral surface of the light-emitting stack EST. For example, the insulating layer 40 may cover a part of the side surface and a part of the lower surface of the light-emitting stack EST. In this case, the insulating layer 40 may at least cover the side surface of the active layer 20. The insulating layer 40 can be used to prevent an electrical short circuit that may occur when the active layer 20 comes into contact with a conductive material other than the first semiconductor layer 10 and the second semiconductor layer 30. In an embodiment, the insulating layer 40 may be configured to expose the upper surface of the light-emitting stack EST.

[0125] In an embodiment, at least one protruding structure PSS may be defined on the upper surface of the light-emitting stack EST. For example, the protruding structure PSS may include a first protruding structure PSS1.

[0126] The protruding structure PSS may include a first protruding portion P1 and a second protruding portion P2. The first protruding portion P1 may protrude in a direction away from the bonding electrode BDE (e.g., the third direction DR3). The first protruding portion P1 may define a groove GR that is recessed in a direction facing the bonding electrode BDE (e.g., a direction opposite to the third direction DR3). The second protruding portion P2 may protrude in the groove GR in a direction away from the bonding electrode BDE.

[0127] In an embodiment, the second protruding portion P2 may be configured to be spaced apart from the inner surface P1_IS of the first protruding portion P1 that defines the groove GR. For example, the second protruding portion P2 may be surrounded by the inner surface P1_IS of the first protruding portion P1 in the groove GR. Thus, a separation space may be formed between the second protruding portion P2 and the inner surface P1_IS of the first protruding portion P1. When the protruding structure PSS is embedded in the adhesive layer PDMS (refer to Figure 14 ) of a transfer substrate SUB' (refer to Figure 14 ) described later, the separation space can be used to provide a fixing force.

[0128] In an embodiment, the second protrusion P2 may include a 2-1 protrusion P2-1 having a height equal to the depth of the groove GR and a 2-2 protrusion P2-2 provided on the 2-1 protrusion P2-1. The 2-1 protrusion P2-1 and the 2-2 protrusion P2-2 may have various shapes that can provide a greater fixing force to the adhesive layer PDMS (refer to Figure 14 ), which will be described later). For example, the 2-1 protrusion P2-1 may have a cylindrical shape. For example, the 2-2 protrusion P2-2 may have a conical shape.

[0129] In an embodiment, the protrusion structure PSS may be integral with the second semiconductor layer 30. For example, the protrusion structure PSS may be integral with the second doped portion 32. In this case, the first protrusion P1 and the second protrusion P2 may be integral, and the 2-1 protrusion P2-1 and the 2-2 protrusion P2-2 may be integral. For example, the first protrusion P1, the 2-1 protrusion P2-1, and the 2-2 protrusion P2-2 may be integral with the second doped portion 32.

[0130] In an embodiment, as shown in Figure 6 , in a plan view, the first protrusion structure PSS1 may be disposed at the center of the upper surface of the light-emitting stack EST. Therefore, it is possible to prevent the light-emitting element LDa of the adhesive layer PDMS (refer to Figure 14 ) fixed to the transfer substrate SUB' (refer to Figure 14 ), which will be described later, from tilting in a given direction.

[0131] In Figure 6 , the upper surface of the light-emitting stack EST is circular, but the present disclosure is not limited thereto. The upper surface of the light-emitting stack EST may be configured in various shapes having a closed curve shape.

[0132] Figure 8 FIG. Figure 3 is a schematic plan view showing a second embodiment of the light-emitting element included in the sub-pixel of Figure 9 FIG. Figure 8 is a schematic cross-sectional view taken along the line X2-X2' of

[0133] Hereinafter, the present disclosure will be described based on the differences between the light-emitting element LDb and the light-emitting element LDa described with reference to Figure 6 and Figure 7 , and the above content will be used to replace the parts omitted from the description.

[0134] Referring to Figure 8 and Figure 9 , the protrusion structure PSS may include two second protrusion structures PSS2. Each of the two second protrusion structures PSS2 may be configured to be the same as the referenceFigure 6 and Figure 7 is substantially the same as the first protruding structure PSS1 described above.

[0135] As Figure 8 shown in, in a plan view, two second protruding structures PSS2 can be symmetrically arranged with respect to the center C of the upper surface of the light-emitting stack EST. Therefore, it is possible to prevent the light-emitting element LDb fixed to the adhesive layer PDMS (refer to Figure 14 ) of the transfer substrate SUB' (refer to Figure 14 ) described later from tilting in a given direction.

[0136] Figure 10 is a schematic plan view showing a third embodiment of the light-emitting element included in the sub-pixel of Figure 3 .

[0137] Hereinafter, based on the difference between the light-emitting element LDb' and the light-emitting element LDb described with reference to Figure 8 and Figure 9 , the disclosure will be described, and the above content will be used to replace the parts omitted from the description.

[0138] Refer to Figure 10 , the protruding structure PSS may include four second protruding structures PSS2. Each of the four second protruding structures PSS2 can be configured to be substantially the same as the first protruding structure PSS1 described with reference to Figure 6 and Figure 7 .

[0139] As Figure 10 shown in, in a plan view, four second protruding structures PSS2 can be symmetrically arranged with respect to the center C of the upper surface of the light-emitting stack EST. Therefore, it is possible to prevent the light-emitting element LDb' fixed to the adhesive layer PDMS (refer to Figure 14 ) of the transfer substrate SUB' (refer to Figure 14 ) described later from tilting in a given direction.

[0140] Refer to Figures 8 to 10 , the number of the second protruding structures PSS2 is not limited to the above description. For example, within the range where it is possible to prevent the light-emitting element fixed to the adhesive layer PDMS (refer to Figure 14 ) of the transfer substrate SUB' (refer to Figure 14 ) described later from tilting, the number of the second protruding structures PSS2 can be variously changed. For example, six, eight or more second protruding structures PSS2 can be provided.

[0141] In this case, as the number of the protruding structures PSS increases, the adhesion of the adhesive layer PDMS fixed to the transfer substrate SUB' (refer to Figure 14 ) can be improved.Figure 14 ) The fixing force of the light-emitting element. As the number of the protruding structures PSS increases, due to the uneven structure formed on the upper surface of the light-emitting element, the critical angle of light can be changed, and thus the light output efficiency of the light-emitting element can be improved.

[0142] Figure 11 is a schematic plan view showing a fourth embodiment of the light-emitting element included in the Figure 3 sub-pixel. Figure 12 is a schematic cross-sectional view taken along the Figure 11 line X3-X3'.

[0143] Hereinafter, based on the differences between the light-emitting element LDc and the reference Figure 6 and Figure 7 described light-emitting element LDa and the reference Figure 8 and Figure 9 described light-emitting element LDb, the present disclosure will be described, and the above content will be used to replace the parts omitted from the description.

[0144] Reference Figure 11 and Figure 12 , the protruding structure PSS may include one first protruding structure PSS1 and two second protruding structures PSS2. Therefore, it is possible to more effectively prevent the light-emitting element LDc fixed to the transfer substrate SUB' (reference Figure 14 ) by the adhesive layer PDMS (reference Figure 14 ) from tilting in a given direction.

[0145] Figure 13 is a schematic plan view showing a fifth embodiment of the light-emitting element included in the Figure 3 sub-pixel.

[0146] Hereinafter, based on the differences between the light-emitting element LDc' and the reference Figure 6 and Figure 7 described light-emitting element LDa and the reference Figure 10 described light-emitting element LDb', the present disclosure will be described, and the above content will be used to replace the parts omitted from the description.

[0147] Reference Figure 13 , the protruding structure PSS may include one first protruding structure PSS1 and four second protruding structures PSS2. Therefore, it is possible to more effectively prevent the light-emitting element LDc' fixed to the transfer substrate SUB' (reference Figure 14 ) by the adhesive layer PDMS (reference Figure 14 ) from tilting in a given direction.

[0148] Reference Figures 11 to 13, the number of the second protruding structures PSS2 is not limited by the above description. For example, six, eight or more second protruding structures PSS2 can be provided. In this case, as the number of the protruding structures PSS increases, the fixing force of the light-emitting element fixed to the adhesive layer PDMS (refer to Figure 14 ) formed on the transfer substrate SUB' (refer to Figure 14 ) can be improved, and the light output efficiency of the light-emitting element can be improved.

[0149] Figure 14 is a schematic cross-sectional view showing a method of providing a light-emitting element according to an embodiment.

[0150] Refer to Figure 14 , the manufactured light-emitting element LD can be fixed to the adhesive layer PDMS formed on one surface or the surface of the transfer substrate SUB', and can be transported. Here, the light-emitting element LD can be one of the light-emitting elements LDa, LDb, LDb', LDc, and LDc' described in Figures 6 to 13 .

[0151] The protruding structure PSS of the light-emitting element LD can be embedded in the adhesive layer PDMS. Therefore, the light-emitting element LD can be fixed to the adhesive layer PDMS more effectively. Tilt of the light-emitting element LD can be effectively prevented.

[0152] The transfer substrate SUB' can be aligned to face the display element layer DPL formed on the substrate SUB. Specifically, the light-emitting element LD embedded in the adhesive layer PDMS can be aligned to face the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 formed on the display element layer DPL. In this case, components such as the first bank BNK1 exposing portions of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be additionally formed on the display element layer DPL.

[0153] A bonding substrate SUB” can be provided on the transfer substrate SUB'. The bonding substrate SUB” can be, for example, a quartz substrate. The laser L can be irradiated onto the bonding substrate SUB”. The pressure P can be applied to the transfer substrate SUB' through the bonding substrate SUB” in the direction facing the display element layer DPL (for example, the direction opposite to the third direction DR3). Therefore, heat and pressure for bonding the bonding electrode BDE of the light-emitting element LD to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be provided.

[0154] After bonding the bonding electrode BDE to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, the transfer substrate SUB' and the adhesive layer PDMS provided on one surface or surfaces of the transfer substrate SUB' can be removed. Accordingly, the light-emitting element LD bonded to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be provided.

[0155] Figure 15 is a schematic plan view showing an embodiment of one of the pixels included in the Figure 3 display panel.

[0156] Referring to Figure 15 , the pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged or provided in a first direction DR1. However, the arrangement of the pixel PXL is not limited thereto, and various changes may be made according to embodiments. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged or provided in a zigzag shape.

[0157] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be respectively provided in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first anode electrode AE1 may be provided as the anode electrode AE included in the sub-pixel circuit SPC (refer to Figure 2 ) of the first sub-pixel SP1. The second anode electrode AE2 may be provided as the anode electrode AE included in the sub-pixel circuit SPC of the second sub-pixel SP2. The third anode electrode AE3 may be provided as the anode electrode AE included in the sub-pixel circuit SPC of the third sub-pixel SP3.

[0158] One or more first light-emitting elements LD1, one or more second light-emitting elements LD2, and one or more third light-emitting elements LD3 may be provided on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first light-emitting element LD1 may be connected to the first anode electrode AE1. The second light-emitting element LD2 may be connected to the second anode electrode AE2. The third light-emitting element LD3 may be connected to the third anode electrode AE3. When the light-emitting elements are provided in each sub-pixel, each anode electrode may have a shape extending in a given direction (such as a second direction DR2), and the light-emitting elements connected thereto may be arranged or provided in the same direction.

[0159] The first light-emitting element LD1 may be provided as the light-emitting element LD included in the first sub-pixel SP1 (refer to Figure 2)。The second light-emitting element LD2 can be set as the light-emitting element LD included in the second sub-pixel SP2 (refer to Figure 2 )。The third light-emitting element LD3 can be set as the light-emitting element LD included in the third sub-pixel SP3 (refer to Figure 2 )。In the case where the light-emitting element is disposed in one sub-pixel, the light-emitting elements can be connected in parallel between the anode electrode and the cathode electrode, and can be set as Figure 2 the light-emitting element LD。

[0160] Each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be one of the light-emitting elements LDa, LDb, LDb', LDc, and LDc' described in reference Figures 6 to 13 。

[0161] Figure 16 is a schematic cross-sectional view taken along the line Figure 15 X4-X4'。

[0162] Refer to Figure 15 and Figure 16 , the pixel circuit layer PCL, the display element layer DPL, and the optical function layer LFL can be sequentially disposed on the substrate SUB。

[0163] The pixel circuit layer PCL can include an insulating layer, a semiconductor pattern, and a conductive pattern stacked on each other on the substrate SUB. The insulating layer can include a buffer layer BFL, one or more interlayer insulating layers ILD, and one or more passivation layers PSV1 and PSV2. The semiconductor pattern and the conductive pattern can be positioned between the insulating layers. The conductive pattern can include at least one material among copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0164] As described in reference Figure 2 , the sub-pixel circuit SPC (refer to Figure 2 ) of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can include a transistor and one or more capacitors. The semiconductor pattern and the conductive pattern of the pixel circuit layer PCL can be used as the transistor and the capacitor of the sub-pixel circuit SPC. The conductive pattern of the pixel circuit layer PCL can also be used as a line, for example, Figure 1 the first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL.

[0165] The buffer layer BFL may be provided on one surface or surfaces of the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into the circuit elements and lines included in the pixel circuit layer PCL. The buffer layer BFL may include an inorganic insulating layer containing an inorganic material. In an embodiment, the buffer layer BFL may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and metal oxides such as aluminum oxide. The buffer layer BFL may be provided as a single layer or multiple layers. In the case where the buffer layer BFL is provided as multiple layers, each layer may be formed of the same material or may be formed of different materials.

[0166] In an embodiment, one or more barrier layers may be provided between the substrate SUB and the buffer layer BFL. Each of the barrier layers may include polyimide.

[0167] The first transistor T_SP1, the second transistor T_SP2, and the third transistor T_SP3 corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively, may be provided on the buffer layer BFL. The first transistor T_SP1 may be one of the transistors of the sub-pixel circuit SPC included in the first sub-pixel SP1. The second transistor T_SP2 may be one of the transistors of the sub-pixel circuit SPC included in the second sub-pixel SP2. The third transistor T_SP3 may be one of the transistors of the sub-pixel circuit SPC included in the third sub-pixel SP3. Each of the first transistor T_SP1, the second transistor T_SP2, and the third transistor T_SP3 may be understood as the transistor among the transistors of the corresponding sub-pixel that is connected to the anode electrode.

[0168] The first transistor T_SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal ET1, and a second terminal ET2. The first terminal ET1 may be one of a source electrode and a drain electrode, and the second terminal ET2 may be the other of the source electrode and the drain electrode. For example, the first terminal ET1 may be the source electrode, and the second terminal ET2 may be the drain electrode.

[0169] The semiconductor pattern SCP may be provided on the buffer layer BFL. The semiconductor pattern SCP may include a first contact region that contacts the first terminal ET1 and a second contact region that contacts the second terminal ET2. The region between the first contact region and the second contact region may be a channel region. The channel region may overlap with the gate electrode GE of the first transistor T_SP1. The channel region may be a semiconductor pattern that is substantially free of doped impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. As the impurity, for example, a p-type impurity may be used, but the embodiment is not limited thereto.

[0170] The semiconductor pattern SCP may include one of various types of semiconductors (e.g., amorphous silicon semiconductor, single-crystalline silicon semiconductor, polycrystalline silicon semiconductor, low-temperature polycrystalline silicon semiconductor, and oxide semiconductor).

[0171] The interlayer insulating layers ILD stacked in sequence may be disposed on the semiconductor pattern SCP. The interlayer insulating layers ILD may be inorganic insulating layers including inorganic materials. For example, each of the interlayer insulating layers ILD may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and metal oxides such as aluminum oxide. However, the interlayer insulating layers ILD are not limited thereto. For example, one of the interlayer insulating layers ILD may include an organic insulating layer containing an organic material.

[0172] The interlayer insulating layers ILD may electrically isolate the conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers ILD from each other. For example, the interlayer insulating layer ILD may include a gate insulating layer GI disposed on the semiconductor pattern SCP. The gate insulating layer GI may be disposed between the semiconductor pattern SCP and the gate electrode GE such that the semiconductor pattern SCP is spaced apart from the gate electrode GE. In an embodiment, the gate insulating layer GI may be entirely disposed on the semiconductor pattern SCP and the buffer layer BFL to cover the semiconductor pattern SCP and the buffer layer BFL. As the number of layers required to form the conductive patterns and / or semiconductor patterns increases, the number of the interlayer insulating layers ILD may increase.

[0173] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap with the channel region of the semiconductor pattern SCP. In an embodiment, the gate electrode GE may be disposed as a single layer including at least one material among copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In an embodiment, the gate electrode GE may be disposed as a multi-layer including at least one material among molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag) as low-resistance materials.

[0174] The first terminal ET1 and the second terminal ET2 may be disposed on the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 may be in contact with the semiconductor pattern SCP through contact holes penetrating the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 may be in contact with the first contact region and the second contact region of the semiconductor pattern SCP, respectively. Each of the first terminal ET1 and the second terminal ET2 may include at least one material among copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0175] Although the first terminal ET1 and the second terminal ET2 are shown as separate electrodes electrically connected to the semiconductor pattern SCP, the embodiments are not limited thereto. In an embodiment, the first terminal ET1 may be a first contact region adjacent to one side of the channel region of the semiconductor pattern SCP, and the second terminal ET2 may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal ET1 may be electrically connected to the light-emitting element LD through a connection tool such as a bridging electrode disposed on at least one of the interlayer insulating layers ILD.

[0176] In an embodiment, the first transistor T_SP1 may be configured of a low-temperature polysilicon transistor. However, the embodiments are not limited thereto. For example, the first transistor T_SP1 may be configured of an oxide semiconductor transistor. In an embodiment, the sub-pixel circuit of each sub-pixel may include different types of transistors. For example, the first transistor T_SP1 may be configured of a low-temperature polysilicon transistor, and another transistor included in the sub-pixel circuit SPC of the first sub-pixel SP1 may be configured of an oxide semiconductor transistor. In this case, the oxide semiconductor of the corresponding oxide semiconductor transistor may be disposed on one of the interlayer insulating layers ILD instead of on the insulating layer of the semiconductor pattern SCP on which the first transistor T_SP1 is disposed.

[0177] In an embodiment, the case where the first transistor T_SP1 is a top-gate structure transistor is described as an example, but the embodiments are not limited thereto. For example, the first transistor T_SP1 may be a bottom-gate structure transistor. The structure of the first transistor T_SP1 may be variously changed.

[0178] Each of the second transistor T_SP2 and the third transistor T_SP3 may be configured similarly to the first transistor T_SP1. Therefore, the description of overlapping content may be omitted.

[0179] At least some of the various lines of the display panel DP and / or the display device DD may also be disposed on the interlayer insulating layer ILD.

[0180] The first passivation layer PSV1 may be disposed on the interlayer insulating layer ILD and the first terminal ET1 and the second terminal ET2. The first passivation layer PSV1 may be referred to as a protective layer or a via layer. The first passivation layer PSV1 may protect the components disposed thereunder (or below), and may provide a flat upper surface.

[0181] On the first passivation layer PSV1, a first connection pattern CP1, a second connection pattern CP2, and a third connection pattern CP3 may be provided. The first connection pattern CP1, the second connection pattern CP2, and the third connection pattern CP3 may be respectively connected to the first terminals ET1 of the first transistor T_SP1, the second transistor T_SP2, and the third transistor T_SP3 by passing through the first passivation layer PSV1. The first connection pattern CP1, the second connection pattern CP2, and the third connection pattern CP3 may include at least one material among copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0182] At least some of various lines of the display panel DP and / or the display device DD may also be provided on the first passivation layer PSV1.

[0183] The second passivation layer PSV2 may be provided on the first connection pattern CP1, the second connection pattern CP2, the third connection pattern CP3, and the first passivation layer PSV1. The second passivation layer PSV2 may protect the components disposed thereunder (or below), and may provide a flat upper surface.

[0184] Each of the first passivation layer PSV1 and the second passivation layer PSV2 may include an inorganic insulating layer containing an inorganic material and / or an organic insulating layer containing an organic material. The inorganic insulating layer may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and metal oxides such as aluminum oxide. The organic insulating layer may include at least one of, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0185] The first passivation layer PSV1 and the second passivation layer PSV2 may include the same material as one of the interlayer insulating layers ILD, but the embodiments are not limited thereto. Each of the first passivation layer PSV1 and the second passivation layer PSV2 may be provided as a single layer, but may also be provided as multiple layers.

[0186] The display element layer DPL may be provided on the second passivation layer PSV2. The display element layer DPL may include a first anode electrode AE1, a second anode electrode AE2, a third anode electrode AE3, a first bank BNK1, a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, an outer coating OCL, a cathode electrode CE, and a capping layer CPL.

[0187] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be respectively disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 on the pixel circuit layer PCL.

[0188] The first anode electrode AE1 can be electrically connected to the first connection pattern CP1 through a contact hole penetrating the second passivation layer PSV2. The second anode electrode AE2 can be electrically connected to the second connection pattern CP2 through another contact hole penetrating the second passivation layer PSV2. The third anode electrode AE3 can be electrically connected to the third connection pattern CP3 through yet another contact hole penetrating the second passivation layer PSV2. As described above, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be electrically connected to the first transistor T_SP1, the second transistor T_SP2, and the third transistor T_SP3, respectively.

[0189] The first bank BNK1 can be disposed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first bank BNK1 can have a first opening OP1 exposing portions of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be disposed in the first opening OP1 of the first bank BNK1. As described above, the first bank BNK1 can be provided as a pixel defining layer defining an area where the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 are positioned.

[0190] The first bank BNK1 can be configured to include a light-shielding material to prevent light mixing between adjacent sub-pixels. In an embodiment, the first bank BNK1 can include an organic material. For example, the first bank BNK1 can include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin. According to an embodiment, in order to further improve the light output efficiency, a reflective layer including a reflective material can also be provided on a side surface of the first bank BNK1 adjacent to the first opening OP1.

[0191] The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be disposed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, respectively. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be respectively bonded and coupled or connected to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. Each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be one of the light-emitting elements LDa, LDb, LDb', LDc, and LDc' described in Figures 6 to 13 the reference. Therefore, the description of overlapping content can be omitted.

[0192] The bonding electrode BDE of the first light-emitting element LD1 may be connected to the first anode electrode AE1. The bonding electrode BDE of the second light-emitting element LD2 may be connected to the second anode electrode AE2. The bonding electrode BDE of the third light-emitting element LD3 may be connected to the third anode electrode AE3. The upper surfaces of the second semiconductor layers 30 of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be connected to the cathode electrode CE. Accordingly, the first light-emitting element LD1 may be connected between the first anode electrode AE1 and the cathode electrode CE, the second light-emitting element LD2 may be connected between the second anode electrode AE2 and the cathode electrode CE, and the third light-emitting element LD3 may be connected between the third anode electrode AE3 and the cathode electrode CE.

[0193] The outer coating OCL may be disposed in the first opening OP1 in which the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 are disposed. The outer coating OCL may fixedly bond the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 such that the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 do not move. The outer coating OCL may protect the configuration disposed thereunder (or below) from foreign substances such as dust and moisture. The outer coating OCL may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OCL may include epoxy resin, but the embodiment is not limited thereto.

[0194] In an embodiment, the outer coating OCL may not be disposed on the upper surfaces of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may protrude into the optical functional layer LFL. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be at least partially positioned in the second opening OP2 of the second bank BNK2. For example, the height of the upper surface of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 from the substrate SUB may be higher than the lowest end of the reflective layer RFL. Accordingly, light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be provided to the optical functional layer LFL at a relatively high ratio.

[0195] The cathode electrode CE can be disposed on the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The cathode electrode CE can be entirely disposed on the first bank BNK1, the first light-emitting element LD1, the second light-emitting element LD2, the third light-emitting element LD3, and the outer coating OCL. The cathode electrode CE can contact the second semiconductor layer 30 of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 and the upper surface of the outer coating OCL. In this case, the cathode electrode CE can entirely cover the protruding structure PSS of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The cathode electrode CE can be electrically connected to Figure 2 the second power supply voltage node VSSN. The second power supply voltage applied to the second power supply voltage node VSSN can be transmitted to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 through the cathode electrode CE.

[0196] The cathode electrode CE can be configured to be substantially transparent or translucent to meet a predetermined light transmittance. In an embodiment, the cathode electrode CE can include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the cathode electrode CE is not limited thereto.

[0197] The capping layer CPL can be disposed on the cathode electrode CE. Within the spirit and scope of the present disclosure, the capping layer CPL can protect components such as the cathode electrode CE and the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 under (or below) the capping layer CPL from external water, moisture, etc. The capping layer CPL can include at least one of silicon oxide, silicon nitride, silicon oxynitride, and metal oxides such as aluminum oxide. However, the material of the capping layer CPL is not limited thereto.

[0198] The light function layer LFL can be disposed on the capping layer CPL. The light function layer LFL can include a second bank BNK2, a reflective layer RFL, a third passivation layer PSV3, a first light conversion pattern CCP1 and a second light conversion pattern CCP2, a light scattering pattern LSP, a low refractive index layer LRL, and a color filter layer CFL.

[0199] The second bank BNK2 can be disposed on the capping layer CPL. The second bank BNK2 can overlap with the first bank BNK1. The second bank BNK2 can have a second opening OP2 that overlaps with the first opening OP1.

[0200] The second bank BNK2 may be configured to include a light-shielding material to prevent light mixing between adjacent sub-pixels. In an embodiment, the second bank BNK2 may include an organic material. For example, the second bank BNK2 may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0201] The reflective layer RFL may be disposed on a side surface of the second bank BNK2 adjacent to the second opening OP2. The reflective layer RFL may be configured to reflect incident light and thus may improve light output efficiency. The reflective layer RFL may include a material suitable for reflecting light. The reflective layer RFL may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected from them. However, the embodiment is not limited thereto.

[0202] It can be understood that the emission area EMA and the non-emission area NEMA for the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are defined by the second bank BNK2. The area overlapping with the second bank BNK2 may correspond to the non-emission area NEMA. The area overlapping with the second opening OP2 of the second bank BNK2 may correspond to the emission area EMA.

[0203] The third passivation layer PSV3 may be disposed in the second opening OP2 on the capping layer CPL. The third passivation layer PSV3 may protect the components disposed thereunder (or below) the third passivation layer PSV3 and may provide a flat upper surface. The third passivation layer PSV3 may include the same material as one of the first passivation layer PSV1 and the second passivation layer PSV2, but the embodiment is not limited thereto.

[0204] The first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may be disposed in the second opening OP2 on the third passivation layer PSV3.

[0205] The first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of the incident light and convert the incident light into light of another color. The color conversion particles may scatter the incident light. In an embodiment, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0206] In an embodiment, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be configured to emit blue light. In this case, the first light conversion pattern CCP1 may include first color conversion particles QD1 configured to convert blue light into red light. The second light conversion pattern CCP2 may include second color conversion particles QD2 configured to convert blue light into green light. The light scattering pattern LSP may include scattering particles SCT that scatter blue light to improve the light output efficiency. Accordingly, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In an embodiment, at least one of the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may further include color conversion particles that convert blue light into white light.

[0207] In an embodiment, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be configured to emit red, green, and blue light, respectively. In this case, each of the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may include scattering particles SCT. As described above, the particles included in the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may be variously changed according to the color of the light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0208] In an embodiment, the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may be omitted.

[0209] The low refractive index layer LRL may be disposed on the second bank BNK2, the reflective layer RFL, the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP. The low refractive index layer LRL may have a refractive index lower than that of the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP. The low refractive index layer LRL may be configured to refract or totally reflect corresponding light according to the incident angle of the light. The low refractive index layer LRL may provide light that passes through the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP and returns to the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP. Accordingly, the light conversion efficiency and the light scattering efficiency of the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may be improved. In an embodiment, the low refractive index layer LRL may be omitted in a region corresponding to the third sub-pixel SP3.

[0210] The color filter layer CFL may be disposed on the low refractive index layer LRL. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, a third color filter CF3, and a light blocking pattern LBP.

[0211] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may overlap with the first light conversion pattern CCP, the second light conversion pattern CCP2, and the light scattering pattern LSP, respectively. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may selectively transmit light in a desired wavelength range. In the case where the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter. In the case where the second sub-pixel SP2 is a green sub-pixel, the second color filter CF2 may include a green color filter. In the case where the third sub-pixel SP3 is a blue sub-pixel, the third color filter CF3 may include a blue color filter. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may have a refractive index higher than that of the low refractive index layer LRL. However, the embodiments are not limited thereto, and the first color filter CF1, the second color filter CF2, and the third color filter CF3 may have a refractive index lower than or equal to that of the low refractive index layer LRL.

[0212] The light blocking pattern LBP may be disposed between the first color filter CF1, the second color filter CF2, and the third color filter CF3. It can be understood that the emission regions (or light output regions) EMA and the non-emission regions NEMA for the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are defined by the light blocking pattern LBP. The region overlapping with the light blocking pattern LBP may correspond to the non-emission region NEMA. The region not overlapping with the light blocking pattern LBP may correspond to the emission region EMA.

[0213] In an embodiment, the light-shielding pattern LBP may include at least one of various types of light-shielding materials. In an embodiment, each of the light-shielding patterns LBP may be provided in a multi-layer form in which at least two of the first color filter CF1, the second color filter CF2, and the third color filter CF3 overlap therein. For example, each of the light-shielding patterns LBP may be formed by overlapping the first color filter CF1, the second color filter CF2, and the third color filter CF3. As another example, the light-shielding pattern LBP between the first color filter CF1 and the second color filter CF2 among the light-shielding patterns LBP may be formed into a multi-layer in which the first color filter CF1 and the second color filter CF2 overlap therein, and the light-shielding pattern LBP between the second color filter CF2 and the third color filter CF3 among the light-shielding patterns LBP may be formed into a multi-layer in which the second color filter CF2 and the third color filter CF3 overlap therein. The light-shielding pattern LBP between the first color filter CF1 and the third color filter CF3 of an adjacent pixel may be formed into a multi-layer in which the first color filter CF1 and the third color filter CF3 overlap therein. As described above, each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may extend into the non-emitting area NEMA to form the light-shielding pattern LBP.

[0214] Figure 17 is a block diagram showing a display system according to an embodiment.

[0215] Referring Figure 17 , the display system 1000 may include a processor 1100 and a display device 1200.

[0216] The processor 1100 may perform various tasks and calculations. In an embodiment, within the spirit and scope of the present disclosure, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system to control the other components.

[0217] The processor 1100 may transmit input image data IMG and a control signal CTRL to the display device 1200. The display device 1200 may display an image based on the input image data IMG and the control signal CTRL. The display device 1200 may be configured to be similar to the display device DD described with reference to Figure 1 . In this case, the input image data IMG and the control signal CTRL may be provided as Figure 1 the input image data IMG and the control signal CTRL.

[0218] The display system 1000 may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smartphone, a portable computer, a tablet personal computer (PC), a watch phone, a car display, smart glasses, a portable multimedia player (PMP), a navigation device, and an ultra-mobile personal computer (UMPC). The display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0219] Figures 18 to 21 is a schematic perspective view showing Figure 17 an application example of the display system.

[0220] Reference Figure 18 , Figure 17 the display system 1000 of

[0221] can be applied to the smart watch 2000 including a display unit 2100 and a band unit 2200.

[0222] Reference Figure 19 , Figure 17 the display system 1000 of

[0223] can be applied to the car display system 3000. Here, the car display system 3000 may include a computing system provided inside and / or outside the vehicle to provide image data.

[0224] Reference Figure 20 , Figure 17 the display system 1000 of

[0225] The smart glasses 4000 may include a frame 4100 and a lens unit 4200. The frame 4100 may include a housing 4110 that supports the lens unit 4200 and leg units 4120 for a user to wear. The leg units 4120 may be connected to the housing 4110 by hinges and may be folded or unfolded relative to the housing 4110.

[0226] A battery, a touchpad, a microphone, a camera, etc. may be built into the frame 4100. A projector that outputs light, a processor that controls optical signals, etc. may be built into the frame 4100.

[0227] The lens unit 4200 may include an optical member that transmits or reflects light. In the spirit and scope of the present disclosure, for example, the lens unit 4200 may include glass, transparent synthetic resin, etc.

[0228] In order for a user's eyes to recognize visual information, the lens unit 4200 may reflect an image caused by an optical signal emitted from the projector of the frame 4100 through the rear surface of the lens unit 4200 (e.g., the surface facing the direction of the user's eyes). For example, the user may recognize visual information such as time and date displayed on the lens unit 4200. At this time, the projector and / or the lens unit 4200 may be a type of display device. The display device 1200 may be applied to the projector and / or the lens unit 4200.

[0229] Reference Figure 21 , Figure 17 the display system 1000 of may be applied to the head-mounted display device 5000.

[0230] The head-mounted display device 5000 may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 may be a wearable device for virtual reality or mixed reality.

[0231] The head-mounted display device 5000 may include a head mounting band 5100 and a display device housing 5200. The head mounting band 5100 may be connected to the display device housing 5200. The head mounting band 5100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 5000 to the user's head. The horizontal band may be configured to surround the side portion of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, the embodiments are not limited thereto. In the spirit and scope of the present disclosure, for example, the head mounting band 5100 may be implemented in the form of a spectacle frame, a helmet, etc.

[0232] The display device housing 5200 may accommodate the display system 1000 and / or the display device 1200.

[0233] Although described with reference to the above embodiments, it will be understood that various modifications and changes may be made to the present disclosure by those skilled in the art without departing from the spirit and scope of the described disclosure and the appended claims.

Claims

1. A light-emitting element, comprising: A bonding electrode; And A light-emitting stack including a first semiconductor layer, an active layer, and a second semiconductor layer sequentially disposed on the bonding electrode, Wherein at least one protruding structure is defined on the upper surface of the light-emitting stack, and The protruding structure includes: A first protrusion protruding in a direction away from the bonding electrode and defining a groove recessed in a direction facing the bonding electrode; and A second protrusion protruding in the direction away from the bonding electrode in the groove of the first protrusion.

2. The light-emitting element according to claim 1, wherein, The second protrusion is spaced apart from the inner surface of the first protrusion that defines the groove.

3. The light-emitting element according to claim 1, wherein, The second protrusion includes a 2-1 protrusion having a height equal to the depth of the groove and a 2-2 protrusion disposed on the 2-1 protrusion.

4. The light-emitting element according to claim 3, wherein, The 2-2 protrusion has a conical shape.

5. The light-emitting element according to claim 1, wherein, The protruding structure and the second semiconductor layer are integral.

6. The light-emitting element according to claim 5, wherein, The first protrusion and the second protrusion are integral.

7. The light-emitting element according to claim 1, wherein, The protruding structure includes a first protruding structure disposed at the center of the upper surface of the light-emitting stack in a plan view.

8. The light-emitting element according to claim 1, wherein The protruding structure includes a plurality of second protruding structures, and In a plan view, the plurality of second protruding structures are symmetrically disposed with respect to the center of the upper surface of the light-emitting stack.

9. The light-emitting element according to claim 1, wherein The first semiconductor layer has a first polarity, and The second semiconductor layer has a second polarity different from the first polarity.

10. The light-emitting element according to claim 9, wherein The second semiconductor layer includes a first doped portion and a second doped portion sequentially defined on the active layer, and A first average doping concentration of the dopant in the first doped portion is greater than a second average doping concentration of the dopant in the second doped portion.

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