Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a substrate; a light emitting element disposed on the substrate and including a sub-pixel electrode, an emission layer, and an opposite electrode; a capping layer disposed on the light emitting element; and a cell layer disposed on the capping layer and including a patterned metal layer and a metal oxide layer disposed on the metal layer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2024-0014315, filed with the Korean Intellectual Property Office on January 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] A display device is a device that visually displays data. The display device may be used as a display part for a small product (such as a mobile phone) or as a display part for a large product (such as a television).

[0005] The display device may include a liquid crystal display device that does not emit light by itself but uses light from a backlight source, or a light-emitting display device including a display element capable of emitting light, and the display element may include an emission layer. Summary of the Invention

[0006] One or more embodiments include a display device and a method of manufacturing the display device having improved reliability and efficiency. However, these objectives are illustrative and do not limit the scope of the present disclosure.

[0007] Additional aspects will be set forth in part in the following description, and in part will be apparent from the description, or may be learned by practice of the embodiments of the present disclosure.

[0008] According to one or more embodiments, a display device may include: a substrate; a light-emitting element disposed on the substrate and including a sub-pixel electrode, an emission layer, and a counter electrode; a capping layer disposed on the light-emitting element; and a meta-layer disposed on the capping layer and including a patterned metal layer and a metal oxide layer disposed on the metal layer.

[0009] According to an embodiment, when observed in a direction perpendicular to the substrate, the metal layer may be patterned into a plurality of rectangular shapes.

[0010] According to an embodiment, the metal layer may include aluminum (Al), and the metal oxide layer may include aluminum oxide (Al2O3).

[0011] According to an embodiment, the metal layer may include at least one selected from silver (Ag), gold (Au), molybdenum (Mo), and vanadium (V), and the metal oxide layer may include at least one selected from silver oxide (Ag2O), gold oxide (Au2O3), molybdenum oxide (MoO xat least one selected from and vanadium oxide (V2O5).

[0012] According to an embodiment, the meta-layer may have a thickness of about 5 nm to about 10 nm.

[0013] According to an embodiment, the metal layer may include silicon (Si), and the metal oxide layer may include silicon dioxide (SiO2).

[0014] According to an embodiment, as a result of the cross-cut test, the interfacial adhesion force between the metal layer and the metal oxide layer may be 5B.

[0015] According to an embodiment, the metal oxide layer may have a flat upper surface.

[0016] According to one or more embodiments, a method of manufacturing a display device may include: disposing a light-emitting element on a substrate, the light-emitting element including a sub-pixel electrode, an emission layer, and a counter electrode; disposing a capping layer on the light-emitting element; and forming a meta-layer on the capping layer, the meta-layer including a patterned metal layer and a metal oxide layer.

[0017] According to an embodiment, when viewed in a direction perpendicular to the substrate, the metal layer may be patterned into a plurality of rectangular shapes.

[0018] According to an embodiment, the formation of the meta-layer may include: disposing a meta-layer forming material on the capping layer; disposing a photoresist on at least a portion of the meta-layer forming material; and oxidizing at least a portion of the meta-layer forming material to form a patterned metal layer and a metal oxide layer.

[0019] According to an embodiment, the meta-layer forming material on which the photoresist is not disposed may be oxidized to form a metal oxide layer.

[0020] According to an embodiment, only a portion of the meta-layer forming material adjacent to the photoresist on which the photoresist is disposed may be oxidized to form a metal oxide layer.

[0021] According to an embodiment, the degree of oxidation of the meta-layer forming material on which the photoresist is disposed may be less than the degree of oxidation of the meta-layer forming material on which the photoresist is not disposed.

[0022] According to an embodiment, the thickness of the metal oxide layer disposed under the photoresist may be less than the thickness of the metal oxide layer on which the photoresist is not disposed.

[0023] According to an embodiment, the meta-layer forming material and the metal layer may include at least one selected from aluminum (Al), silver (Ag), gold (Au), molybdenum (Mo), and vanadium (V).

[0024] According to an embodiment, the metal oxide layer may include at least one selected from aluminum oxide (Al2O3), silver oxide (Ag2O), gold oxide (Au2O3), molybdenum oxide (MoO x ), and vanadium oxide (V2O5).

[0025] According to an embodiment, as a result of the cross-cut test, the interfacial adhesion force between the metal layer and the metal oxide layer may be 5B.

[0026] According to an embodiment, the thickness of the meta-layer forming material may be about 5 nm or more and about 10 nm or less.

[0027] According to an embodiment, the metal layer may include silicon (Si), and the metal oxide layer may include silicon dioxide (SiO2). BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0030] Figure 2 is a schematic diagram showing an equivalent circuit of a sub-pixel circuit electrically connected to a sub-pixel according to an embodiment;

[0031] Figure 3 is a schematic cross-sectional view of a display panel according to an embodiment;

[0032] Figure 4 is a schematic plan view of a metal layer of a meta-layer;

[0033] Figure 5A is a photographic image schematically showing a cross-section of a metal layer and a metal oxide layer;

[0034] Figure 5B is a photographic image schematically showing the result of testing the interfacial adhesion force between a metal layer and a metal oxide layer by cross-cut; and

[0035] Figure 6 、 Figure 7 、 Figure 8 and Figure 9 are schematic cross-sectional views showing a method of manufacturing a display device. DETAILED DESCRIPTION

[0036] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, the various embodiments are not necessarily exclusive and do not necessarily limit the present disclosure. For example, the specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment.

[0037] Unless otherwise specified in detail, the illustrated embodiments will be understood to provide the features of the present disclosure. Accordingly, unless otherwise specified in detail, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0038] The use of cross-hatching and / or shading in the drawings generally serves to clarify the boundaries between adjacent elements. Accordingly, unless otherwise specified in detail, the presence or absence of cross-hatching and / or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other feature, attribute, property, etc. of the elements. In addition, in the drawings, for clarity and / or descriptive purposes, the size and relative size of the elements may be exaggerated. When an embodiment can be implemented differently, a particular process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals and / or reference characters denote the same elements.

[0039] When an element or layer is referred to as "on", "connected to", or "coupled to" another element or layer, the element or layer can be directly on, connected to, or coupled to the other element or layer, or there can be intervening elements or intervening layers. However, when an element or layer is referred to as "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or intervening layers. For this reason, the term "connected" can refer to physical connection, electrical connection, and / or fluid connection with or without intermediate elements. In addition, the X direction, Y direction, and Z direction are not limited to the three axes of a rectangular coordinate system (such as the x-axis, y-axis, and z-axis), and can be interpreted in a broader sense. For example, the X direction, Y direction, and Z direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be understood as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0040] In the specification and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or".

[0041] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed hereinafter can be referred to as the second element without departing from the teachings of this disclosure.

[0042] Spatial relative terms such as "beneath", "below", "under", "lower", "above", "upper", "on top of", "higher" and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes and, thus, to describe the relationship of one element to another (or elements) as shown in the figures. In addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacturing. For example, if the device in the figures is turned over, an element described as "beneath" or "below" another element or feature will then be oriented "above" the other element or feature. Thus, the term "beneath" can encompass both an upper and a lower orientation. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative terms used herein may be interpreted accordingly.

[0043] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "above" another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, no intervening elements are present.

[0044] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly dictates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms. Additionally, when used in this specification, the terms "comprise", "comprising", "includes", and "including" specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about", and other similar terms are used as terms of approximation and not of degree, and, thus, are used to interpret the inherent deviations in measured, calculated, and / or provided values that would be recognized by one of ordinary skill in the art.

[0045] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures. Accordingly, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the particular shapes shown of regions, but will include deviations in shapes due to, for example, manufacturing. In this manner, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of the device, and thus are not necessarily intended to be limiting.

[0046] As is conventional in the art, some embodiments are described and illustrated in terms of functional blocks, units, and / or modules in the figures. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented by electronic circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Additionally, without departing from the scope of the inventive concept, each block, unit, and / or module of some embodiments may be physically separated into two or more interacting and discrete blocks, units, and / or modules. Further, without departing from the scope of the inventive concept, the blocks, units, and / or modules of some embodiments may be physically combined into more complex blocks, units, and / or modules.

[0047] Figure 1 is a schematic perspective view of a display device according to an embodiment.

[0048] The display device according to an embodiment may include a device for displaying dynamic images or static images, and may be used as a display screen for mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), and also for various products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices. The display device according to an embodiment may be used in wearable devices such as smartwatches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, the display device according to an embodiment may be used as a central information display (CID) arranged on the instrument panel of a vehicle, the center instrument panel of a vehicle, or the instrument panel of a vehicle, as an interior rearview mirror display replacing the side rearview mirror of a vehicle, and a display as an entertainment element for the rear seats of a vehicle arranged on the back surface of the front seats.

[0049] Referring to Figure 1 , the display device 1 may have an edge in a first direction and an edge in a second direction. Here, the first direction and the second direction may be directions intersecting each other. For example, the first direction and the second direction may be at an acute angle to each other. As another example, the first direction and the second direction may form an obtuse angle with each other, or may be orthogonal to each other. Hereinafter, the description will focus on the case where the first direction and the second direction are orthogonal to each other. For example, the first direction may be the X direction or the -X direction, and the second direction may be the Y direction or the -Y direction. A third direction perpendicular to the first direction and the second direction may be the Z direction or the -Z direction.

[0050] The display device 1 may include a display area DA and a peripheral area PA outside the display area DA. The display device 1 may provide a specific image by using light emitted from sub-pixels PX arranged in the display area DA. The peripheral area PA may be an area arranged outside the display area DA, and may be a non-display area in which sub-pixels PX are not arranged. The display area DA may be completely surrounded by the peripheral area PA.

[0051] Hereinafter, an organic light-emitting display device is described as an example of the display device according to an embodiment, but the display device of the present disclosure is not limited thereto. As another example, the display device of the present disclosure may be an inorganic light-emitting display device (or an inorganic electroluminescent (EL) display device) or a quantum dot light-emitting display device. For example, an emission layer of a display element included in the display device includes an organic material or an inorganic material. The display device may include an emission layer and quantum dots located on a path of light emitted from the emission layer.

[0052] Figure 2 is a schematic diagram showing an equivalent circuit of a sub-pixel circuit electrically connected to a sub-pixel according to an embodiment.

[0053] Reference Figure 2 , the sub-pixel PX (see Figure 1 ) can emit light through an organic light-emitting diode OLED, and the organic light-emitting diode OLED can be electrically connected to the sub-pixel circuit PC.

[0054] The sub-pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0055] The first transistor T1 may be a driving thin-film transistor connected to the driving voltage line PL and the storage capacitor Cst, and may control the driving current flowing from the driving voltage line PL and through the organic light-emitting diode OLED in response to the charge stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light with a specific brightness according to the driving current. The second electrode (e.g., cathode) of the organic light-emitting diode OLED may receive the second power supply voltage ELVSS.

[0056] The second transistor T2 may be a switching thin-film transistor connected to the signal line SL and the data line DL, and may transmit the data voltage (or data signal) Dm input from the data line DL to the first transistor T1 based on the scan signal (or scan voltage, switching voltage, switching signal) Sn input from the signal line SL.

[0057] The storage capacitor Cst may be connected to the driving voltage line PL and the first transistor T1. One electrode of the storage capacitor Cst may be connected to the driving voltage line PL, and the other electrode of the storage capacitor Cst may be connected to the gate of the first transistor T1. The storage capacitor Cst may store the charge corresponding to the difference between the first driving voltage ELVDD applied to the driving voltage line PL and the gate voltage of the first transistor T1, and may maintain the gate voltage of the first transistor T1.

[0058] The third transistor T3 may be a compensation thin-film transistor, and the gate of the third transistor T3 may be connected to the signal line SL. The source (or drain) of the third transistor T3 may be connected to the drain (or source) of the first transistor T1, and may be connected to the first electrode (e.g., anode) of the organic light-emitting diode OLED via the sixth transistor T6. The drain (or source) of the third transistor T3 may be connected to the other electrode of the storage capacitor Cst, the source (or drain) of the fourth transistor T4, and the gate of the first transistor T1. The third transistor T3 may be turned on according to the scan signal Sn received through the signal line SL, and may connect the gate and the drain of the first transistor T1 to each other to diode-connect the first transistor T1.

[0059] The fourth transistor T4 can be an initialization thin film transistor, and the gate of the fourth transistor T4 can be connected to the previous signal line SL-1. The drain (or source) of the fourth transistor T4 can be connected to the initialization voltage line VL. The source (or drain) of the fourth transistor T4 can be connected to the other electrode of the storage capacitor Cst, the drain (or source) of the third transistor T3, and the gate of the first transistor T1. The fourth transistor T4 can be turned on according to the previous scan signal Sn-1 received through the previous signal line SL-1, and perform an initialization operation of initializing the voltage of the gate of the first transistor T1 by transmitting the initialization voltage Vint to the gate of the first transistor T1.

[0060] The fifth transistor T5 can be an operation control thin film transistor, and the gate of the fifth transistor T5 can be connected to the emission control line EL. The source (or drain) of the fifth transistor T5 can be connected to the driving voltage line PL. The drain (or source) of the fifth transistor T5 can be connected to the source (or drain) of the first transistor T1 and the drain (or source) of the second transistor T2.

[0061] The sixth transistor T6 can be an emission control thin film transistor, and the gate of the sixth transistor T6 can be connected to the emission control line EL. The source (or drain) of the sixth transistor T6 can be connected to the drain (or source) of the first transistor T1 and the source (or drain) of the third transistor T3. The drain (or source) of the sixth transistor T6 can be electrically connected to the first electrode of the organic light emitting diode OLED. The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously according to the emission control signal En received through the emission control line EL to transmit the first driving voltage ELVDD to the organic light emitting diode OLED, and a driving current flows to the organic light emitting diode OLED.

[0062] The seventh transistor T7 can be an initialization thin film transistor for initializing the first electrode of the organic light emitting diode OLED. The gate of the seventh transistor T7 can be connected to the next signal line SL+1. The source (or drain) of the seventh transistor T7 can be connected to the first electrode of the organic light emitting diode OLED. The drain (or source) of the seventh transistor T7 can be connected to the initialization voltage line VL. The seventh transistor T7 can be turned on according to the next scan signal Sn+1 received through the next signal line SL+1 to initialize the first electrode of the organic light emitting diode OLED.

[0063] In Figure 2 it shows the fourth transistor T4 and the seventh transistor T7 respectively connected to the previous signal line SL-1 and the next signal line SL+1. However, both the fourth transistor T4 and the seventh transistor T7 can be connected to the previous signal line SL-1 and be driven according to the previous scan signal Sn-1.

[0064] One electrode of the storage capacitor Cst may be connected to the driving voltage line PL. The other electrode of the storage capacitor Cst may connect together the gate of the first transistor T1, the drain (or source) of the third transistor T3, and the source (or drain) of the fourth transistor T4.

[0065] The second electrode of the organic light emitting diode OLED may receive the second power supply voltage ELVSS. The organic light emitting diode OLED may emit light by receiving a driving current from the first transistor T1.

[0066] In an embodiment, all of the transistors T1 to T7 may include a semiconductor layer containing silicon. However, the present disclosure is not limited thereto.

[0067] In an embodiment, at least one of the transistors T1 to T7 may include a semiconductor layer containing an oxide, and the remaining transistors may include a semiconductor layer containing silicon. Figure 3 The first transistor T1 directly affecting the brightness of the display panel 10 may be a silicon semiconductor including polysilicon with high reliability, and thus a display panel 10 with high resolution may be achieved.

[0068] The oxide semiconductor has a high carrier mobility and a low leakage current, and thus, even if the driving time is long, its voltage drop is not large. For example, even during low-frequency driving, the color change of the image due to the voltage drop is not large, and thus low-frequency driving is possible. As described above, since the oxide semiconductor has the advantage of low leakage current, the oxide semiconductor may be used in at least one of the third transistor T3 and the fourth transistor T4 connected to the gate of the first transistor T1 to prevent the leakage current that may flow to the gate of the first transistor T1 and reduce the power consumption. Signal lines and / or voltage lines may be added to Figure 2 the sub-pixel circuit PC. Transistors other than the third transistor T3 and the fourth transistor T4 may include a semiconductor layer containing an oxide. For example, the seventh transistor T7 may include a semiconductor layer containing an oxide.

[0069] Figure 2 The equivalent circuit diagram showing one sub-pixel includes seven transistors and one capacitor, but the present disclosure is not limited thereto. The number of transistors and capacitors may be different from the number of transistors and capacitors shown in Figure 2 .

[0070] Figure 3 is a schematic cross-sectional view of a display panel according to an embodiment. Specifically, Figure 3 schematically shows a cross-sectional view of a display area of a display device according to an embodiment. Figure 4 is a schematic plan view of a metal layer of a meta layer.Figure 5A is a photographic image schematically showing a cross section of a metal layer and a metal oxide layer, and Figure 5B is a photographic image schematically showing the result of testing the interfacial adhesion between the metal layer and the metal oxide layer by cross-cutting.

[0071] Referring to Figure 3 , the display panel 10 may include a substrate 100, a buffer layer 111, an inorganic insulating layer IIL, an organic insulating layer OIL, a sub-pixel circuit PC, a connection electrode CM, an organic light emitting diode OLED, a pixel defining layer 118, and a meta layer 300. For example, in a display area DA (see Figure 1 ) of the display panel 10, the substrate 100, the buffer layer 111, the inorganic insulating layer IIL, the organic insulating layer OIL, the sub-pixel circuit PC, the connection electrode CM, the organic light emitting diode OLED, and the pixel defining layer 118 may be arranged.

[0072] The substrate 100 may include a first base layer 100a, a first barrier layer 100b, a second base layer 100c, and a second barrier layer 100d. In an embodiment, the first base layer 100a, the first barrier layer 100b, the second base layer 100c, and the second barrier layer 100d may be sequentially stacked in the thickness direction of the substrate 100.

[0073] At least one of the first base layer 100a and the second base layer 100c may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, triacetyl cellulose, cellulose acetate propionate, etc.

[0074] The first barrier layer 100b and the second barrier layer 100d may include a barrier layer that prevents the penetration of external foreign substances, and may be a single layer or multiple layers including an inorganic material (such as silicon nitride (SiN x ), silicon oxide (SiO x ), and / or silicon oxynitride (SiO x N y ).

[0075] The buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 may include an inorganic insulating material (such as silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and silicon oxide (SiO x ), and may be a single layer or multiple layers including the above inorganic insulating materials.

[0076] The inorganic insulating layer IIL may be disposed on the buffer layer 111. The inorganic insulating layer IIL may include a first inorganic insulating layer 112, a second inorganic insulating layer 113, and a third inorganic insulating layer 114.

[0077] The sub-pixel circuit PC may be disposed in the display area DA. The sub-pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0078] The semiconductor layer Act may be disposed on the buffer layer 111. The semiconductor layer Act may include polysilicon. In another example, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The semiconductor layer Act may include a channel region, and a drain region and a source region respectively disposed on both sides of the channel region.

[0079] The gate electrode GE may be disposed on the semiconductor layer Act. The gate electrode GE may overlap with the channel region. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multi-layer or a single layer including the above materials.

[0080] The first inorganic insulating layer 112 may be disposed between the semiconductor layer Act and the gate electrode GE. The first inorganic insulating layer 112 may include an inorganic insulating material such as silicon oxide (SiO x )、silicon nitride (SiN x )、silicon oxynitride (SiO x N y )、aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x , which may be ZnO or ZnO2).

[0081] The second inorganic insulating layer 113 may be disposed above the gate electrode GE. The second inorganic insulating layer 113 may cover the gate electrode GE. The second inorganic insulating layer 113 may include an inorganic insulating material such as silicon oxide (SiO x )、silicon nitride (SiN x )、silicon oxynitride (SiO x N y )、aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x , which may be ZnO or ZnO2).

[0082] The upper electrode CE2 of the storage capacitor Cst may be disposed on the second inorganic insulating layer 113. The upper electrode CE2 may overlap with the gate electrode GE disposed thereunder. The gate electrode GE, the upper electrode CE2 overlapping with the gate electrode GE, and the second inorganic insulating layer 113 interposed between the gate electrode GE and the upper electrode CE2 may form the storage capacitor Cst. The gate electrode GE may serve as the lower electrode CE1 of the storage capacitor Cst.

[0083] As described above, the storage capacitor Cst and the thin film transistor TFT may overlap each other. However, the present disclosure is not limited thereto. For example, the storage capacitor Cst is formed not to overlap with the thin film transistor TFT. The lower electrode CE1 of the storage capacitor Cst may be a component separated from the gate electrode GE of the thin film transistor TFT and may be provided separately from the gate electrode GE of the thin film transistor TFT.

[0084] The upper electrode CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers containing the above materials.

[0085] The third inorganic insulating layer 114 may be disposed on the upper electrode CE2. The third inorganic insulating layer 114 may cover the upper electrode CE2. The third inorganic insulating layer 114 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x , which may be ZnO or ZnO2). The third inorganic insulating layer 114 may be a single layer or multiple layers including the above inorganic insulating materials.

[0086] The drain electrode DE and the source electrode SE may each be located on the third inorganic insulating layer 114. The drain electrode DE and the source electrode SE may each be connected to the semiconductor layer Act through contact holes provided in the first inorganic insulating layer 112, the second inorganic insulating layer 113, and the third inorganic insulating layer 114. The drain electrode DE and the source electrode SE may include materials having good electrical conductivity. The drain electrode DE and the source electrode SE may include conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be multiple layers or a single layer including the above materials. For example, the drain electrode DE and the source electrode SE may have a multilayer structure of Ti / Al / Ti.

[0087] An organic insulating layer OIL may be disposed on an inorganic insulating layer IIL. The organic insulating layer OIL may include a first organic insulating layer 115 and a second organic insulating layer 116. In Figure 3 the figure, an organic insulating layer OIL including two layers is shown, but the present disclosure is not limited thereto. The organic insulating layer OIL may include three or four layers.

[0088] The first organic insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first organic insulating layer 115 may include polymethyl methacrylate (PMMA) or a general polymer such as polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-containing polymer, a parylene polymer, a polyvinyl alcohol polymer, and mixtures thereof.

[0089] A connection electrode CM may be disposed on the first organic insulating layer 115. The connection electrode CM may be connected to the drain electrode DE or the source electrode SE through a contact hole in the first organic insulating layer 115. The connection electrode CM may include a material having good electrical conductivity. The connection electrode CM may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multi-layer or a single layer including the above materials. For example, the connection electrode CM may have a multi-layer structure of Ti / Al / Ti.

[0090] The second organic insulating layer 116 may be disposed on the connection electrode CM. The second organic insulating layer 116 may cover the connection electrode CM. The second organic insulating layer 116 may include the same or different materials as the first organic insulating layer 115.

[0091] A light-emitting diode may be disposed on the second organic insulating layer 116. For example, an organic light-emitting diode OLED may be disposed on the second organic insulating layer 116. In another example, although not shown, an inorganic light-emitting diode or the like may be disposed on the second organic insulating layer 116.

[0092] The organic light-emitting diode OLED may emit red light, green light, or blue light, or emit red light, green light, blue light, or white light. The organic light-emitting diode OLED may include a sub-pixel electrode 211, an emission layer 212b, a functional layer 212f, a counter electrode 213, and a capping layer 215.

[0093] The sub-pixel electrode 211 may be disposed on the second organic insulating layer 116. The sub-pixel electrode 211 may be electrically connected to the connection electrode CM through a contact hole defined in the second organic insulating layer 116. The sub-pixel electrode 211 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the sub-pixel electrode 211 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In an embodiment, the sub-pixel electrode 211 may further include a film above or below the above reflective layer, and the film includes ITO, IZO, ZnO, or In2O3. For example, the sub-pixel electrode 211 may have a multilayer structure of ITO / Ag / ITO.

[0094] The pixel defining layer 118 may be disposed on the sub-pixel electrode 211, and the pixel defining layer 118 has an opening defined to expose at least a part of the sub-pixel electrode 211. The emission region of the light emitted from the organic light-emitting diode OLED may be defined by the opening defined in the pixel defining layer 118. For example, the width of the opening may correspond to the width of the emission region.

[0095] The pixel defining layer 118 may include an inorganic insulating material. For example, the pixel defining layer 118 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. In another example, the pixel defining layer 118 may include an organic insulating material and an inorganic insulating material. In an embodiment, the pixel defining layer 118 may include a light-blocking material. The light-blocking material may include carbon black, carbon nanotubes, a resin or slurry containing a black dye, metal particles (such as nickel particles, aluminum particles, molybdenum particles, and alloy particles thereof), metal oxide particles (for example, chromium oxide particles), or metal nitride particles (for example, chromium nitride particles), etc. In the case where the pixel defining layer 118 includes a light-blocking material, the reflection of external light caused by the metal structure disposed below the pixel defining layer 118 may be reduced.

[0096] The emission layer 212b may be disposed in the opening of the pixel defining layer 118. The emission layer 212b may include a high molecular weight organic material or a low molecular weight organic material that emits light of a specific color.

[0097] The functional layer 212f may include a first functional layer 212a and a second functional layer 212c. The first functional layer 212a may be disposed between the sub-pixel electrode 211 and the emission layer 212b, and the second functional layer 212c may be disposed between the emission layer 212b and the counter electrode 213. However, at least one of the first functional layer 212a and the second functional layer 212c may be omitted. Hereinafter, a detailed description will be given focusing on the case where the first functional layer 212a and the second functional layer 212c are respectively provided.

[0098] The first functional layer 212a may include a hole transport layer HTL and / or a hole injection layer HIL. The second functional layer 212c may include an electron transport layer ETL and / or an electron injection layer EIL. Similar to the counter electrode 213 to be described later, the first functional layer 212a and / or the second functional layer 212c may be a common layer formed to completely cover the substrate 100.

[0099] The counter electrode 213 may be disposed on the functional layer 212f. The counter electrode 213 may include a conductive material having a low work function. For example, the counter electrode 213 may include a transparent layer or a semi-transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In another example, the counter electrode 213 may further include a layer containing indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) on the transparent layer or the semi-transparent layer including the above materials.

[0100] In an embodiment, a capping layer 215 may be disposed on the counter electrode 213. The capping layer 215 may include an inorganic material (e.g., lithium fluoride (LiF)) or / and an organic material.

[0101] In an embodiment, referring to Figure 3 and Figure 4 , a meta layer 300 may be disposed on the capping layer 215. The meta layer 300 may include a metal layer 301 and a metal oxide layer 302. The metal oxide layer 302 may be disposed on the metal layer 301.

[0102] When the light emitted from the organic light-emitting diode (OLED) can be incident on the interface 213s1 between the counter electrode 213 and the encapsulation layer 215 (e.g., dielectric) or on the interface 213s2 between the counter electrode 213 and the second functional layer 212c (e.g., dielectric), photons of the light can combine with free electrons of the counter electrode 213 to generate surface plasmon polaritons (SPPs). SPPs are electromagnetic waves that move along the interface between a metal and a dielectric and can include both the charge movement of the metal contained in the counter electrode 213 and the electromagnetic waves of the dielectric. As a result, light loss may occur in which the light emitted from the organic light-emitting diode (OLED) cannot be emitted to the outside.

[0103] In an embodiment, a meta-layer 300 including a metal layer 301 and a metal oxide layer 302 disposed on the metal layer 301 can be disposed on the encapsulation layer 215. The meta-layer 300 can be arranged to be in contact with the upper surface of the encapsulation layer 215 and thus adjacent to the interface 213s1 between the counter electrode 213 and the encapsulation layer 215 or the interface 213s2 between the counter electrode 213 and the second functional layer 212c where SPPs are generated. When the light emitted from the organic light-emitting diode (OLED) is incident on the interface 301s between the metal layer 301 and the metal oxide layer 302 (e.g., dielectric) of the meta-layer 300, photons of the light and free electrons of the metal layer 301 combine with each other to generate localized surface plasmons (LSPs), in which the free electrons of the metal layer 301 oscillate collectively on the localized surface. Due to the LSPs on the interface 301s between the metal layer 301 and the metal oxide layer 302, an electromagnetic field can be generated on the interface 301s between the metal layer 301 and the metal oxide layer 302.

[0104] Photons captured at the interface 213s1 between the counter electrode 213 and the encapsulation layer 215 or at the interface 213s2 between the counter electrode 213 and the second functional layer 212c can be released to the outside due to the generation of an electromagnetic field adjacent to the photons at the interface 301s between the metal layer 301 and the metal oxide layer 302 of the meta-layer 300 disposed on the encapsulation layer 215, thereby improving the light extraction efficiency. For example, the electromagnetic field at the interface 213s1 between the counter electrode 213 and the encapsulation layer 215 or the electromagnetic field at the interface 213s2 between the counter electrode 213 and the second functional layer 212c can interact with the electromagnetic field adjacent to it at the interface 301s between the metal layer 301 and the metal oxide layer 302 of the meta-layer 300 disposed on the encapsulation layer 215, such that the photons captured at the interfaces 213s1 and 213s2 can be released to the outside, improving the light extraction efficiency.

[0105] The metal layer 301 of the meta-layer 300 can be a patterned metal layer 301. As Figure 4As shown, when observed in a direction perpendicular to the substrate 100, the metal layer 301 of the meta-layer 300 can be provided in a rectangular shape. Due to the design characteristic that the metal layer 301 of the meta-layer 300 is patterned in a rectangular shape, the reflectivity of light incident on the display device from the outside can be reduced. In other embodiments, the material of the metal layer 301 of the meta-layer 300 can absorb external light in a specific wavelength range and reduce the reflectivity of light incident on the display device.

[0106] The metal layer 301 of the meta-layer 300 can include aluminum (Al). Since the metal layer 301 of the meta-layer 300 and the metal oxide layer 302 are formed using the meta-layer forming material 300a (see Figure 6 ), in the case where the metal layer 301 of the meta-layer 300 includes aluminum (Al), the metal oxide layer 302 can include aluminum oxide (Al2O3). Aluminum (Al) can form plasmons in the entire visible light range, and thus, the metal layer 301 can include aluminum (Al) in order to effectively form LSPs at the interface 301s between the metal layer 301 and the metal oxide layer 302. However, the present disclosure is not limited thereto. In another embodiment, the metal layer 301 of the meta-layer 300 can include silicon (Si). The metal oxide layer 302 can include silicon dioxide (SiO2). The metal layer 301 and the metal oxide layer 302 of the meta-layer 300 can each include silver (Ag) and silver oxide (Ag2O), gold (Au) and gold oxide (Au2O3), molybdenum (Mo) and molybdenum oxide (MoO x ), or vanadium (V) and vanadium oxide (V2O5).

[0107] After the meta-layer forming material 300a (see Figure 6 ) is disposed on the substrate 100, at least a part of the meta-layer forming material 300a (see Figure 6 ) can be oxidized to form the metal oxide layer 302, and the unoxidized meta-layer forming material 300a (see Figure 6 ) can form the patterned metal layer 301. The metal oxide layer 302 and the metal layer 301 can be formed by a chemical reaction that oxidizes at least a part of the meta-layer forming material 300a, rather than simply forming the metal oxide layer 302 on the metal layer 301, and thus, the metal layer 301 and the metal oxide layer 302 can be chemically bonded to each other. In the case where the metal oxide layer 302 and the metal layer 301 are formed by oxidizing at least a part of the meta-layer forming material 300a, the interfacial adhesion force between the metal layer 301 and the metal oxide layer 302 can be improved compared to the case where the metal oxide layer 302 is physically disposed on the metal layer 301.

[0108] Referring to Figure 5A, the photographic image on the left shows a cross-section in the case where a metal oxide layer is physically disposed on a metal layer, and the photographic image on the right shows a cross-section in the case where a metal oxide layer 302 and a metal layer 301 are formed by oxidizing at least a part of the meta-layer forming material 300a (see Figure 6 ). Compared with the case where the metal oxide layer is physically disposed on the metal layer (the photographic image on the left), in the case where the metal oxide layer 302 and the metal layer 301 are formed by oxidizing at least a part of the meta-layer forming material 300a (the photographic image on the right), the boundary between the metal layer 301 and the metal oxide layer 302 is blurred.

[0109] Referring to Figure 5B , the interfacial adhesion force between the metal layer 301 (see Figure 3 ) and the metal oxide layer 302 (see Figure 3 ) can be measured using a cross-cut test. The photographic image on the left shows the result of the cross-cut test in the case where the metal oxide layer is physically disposed on the metal layer, and the photographic image on the right shows the result of the cross-cut test in the case where a metal oxide layer 302 and a metal layer 301 are formed by oxidizing at least a part of the meta-layer forming material 300a (see Figure 6 ). The cross-cut test is a method of quantitatively detecting the magnitude of the adhesion force according to the ratio of the remaining film when the surface of the film is scratched with a fork-shaped knife and the film is peeled off with a standard tape. If the adhesion force is excellent, 100% of the film can be retained (5B); and if the adhesion force is relatively low, the remaining percentage of the film due to peeling may be less than 35% (0B). Referring to the photographic image on the left, in the case where the metal oxide layer is physically disposed on the metal layer, it is found that, as a result of the cross-cut test, the ratio of the remaining metal oxide layer is less than 35% (0B). On the other hand, referring to the photographic image on the right, in the case where at least a part of the meta-layer forming material 300a is oxidized to form the metal oxide layer 302 and the metal layer 301, the result of the cross-cut test shows that the ratio of the remaining metal oxide layer 302 is 100% (5B).

[0110] In addition, since the metal oxide layer 302 and the metal layer 301 are formed by a chemical reaction of oxidizing at least a part of the meta-layer forming material 300a, the upper surface of the metal oxide layer 302 on the metal layer 301 can be flat.

[0111] The thickness t1 of the meta-layer 300 (the layer including the metal layer 301 and the metal oxide layer 302) (see Figure 3) can be from about 5 nm to about 10 nm. In the case where the thickness t1 of the meta-layer 300 is less than about 5 nm, this thickness may not be sufficient to generate LSP at the interface 301s between the metal layer 301 and the metal oxide layer 302 (see Figure 3 ) If the thickness of the meta-layer 300 exceeds about 10 nm, the light emitted from the organic light-emitting diode OLED (see Figure 3 ) may not be transmitted to the outside, and the light extraction efficiency may be reduced.

[0112] Return reference Figure 3 , although not shown, a packaging layer can be provided on the organic light-emitting diode OLED. Specifically, the packaging layer can be provided on the counter electrode 213 and / or the capping layer 215. In an embodiment, the packaging layer can include at least one inorganic layer and at least one organic layer. The packaging layer can include a first inorganic packaging layer, an organic packaging layer, and a second inorganic packaging layer stacked in sequence.

[0113] The first inorganic packaging layer and the second inorganic packaging layer can include at least one inorganic material selected from the group consisting of alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide (ZnO x , which can be ZnO or ZnO2), silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic packaging layer and the second inorganic packaging layer can be a single layer or multiple layers including the above materials. The organic packaging layer can include polymer materials. The polymer materials can include acrylic resins, epoxy resins, polyimides, and polyethylene. In an embodiment, the organic packaging layer can include acrylate.

[0114] Although not shown, a touch sensor layer including a touch insulating layer and a conductive layer can be provided on the packaging layer.

[0115] Figure 3 The display device shown in

[0116] Figures 6 - 9 is a top-emitting display device, and the meta-layer 300 provided on the organic light-emitting diode OLED is shown, but the present disclosure is not limited thereto. In another embodiment, the meta-layer 300 according to the embodiment and its manufacturing process can be applied to a bottom-emitting display device, and the meta-layer 300 according to the embodiment can be provided below the organic light-emitting diode OLED. Figures 6 - 9 Schematically shows along Figure 4 The cross-sectional view taken along the line II-II' of the plan view of the metal layer of the meta-layer.

[0117] Refer to Figures 6 - 9 , manufacturing the display device 1 (see Figure 1) The method may include disposing a light-emitting element DPE on a substrate 100, the light-emitting element DPE including a sub-pixel electrode 211 (see Figure 3 ), an emission layer 212b (see Figure 3 ), and a counter electrode 213 (see Figure 3 ), disposing a capping layer 215 on the light-emitting element DPE, and forming a meta-layer 300 including a patterned metal layer 301 and a metal oxide layer 302 on the capping layer 215.

[0118] Referring to Figure 6 , a sub-pixel circuit layer PCL including a sub-pixel circuit PC as shown in Figure 3 may be disposed on the substrate 100. A light-emitting element DPE including an organic light-emitting diode OLED (see Figure 3 ) may be disposed on the sub-pixel circuit layer PCL. The organic light-emitting diode OLED (see Figure 3 ) includes a sub-pixel electrode 211 (see Figure 3 ), an emission layer 212b (see Figure 3 ), and a counter electrode 213 (see Figure 3 ). A capping layer 215 may be disposed on the light-emitting element DPE.

[0119] A meta-layer forming material 300a may be disposed on the capping layer 215. The meta-layer forming material 300a may include aluminum (Al) or silicon (Si).

[0120] Referring to Figure 7 and Figure 8 , a photoresist PR may be disposed on at least a part of the meta-layer forming material 300a. At least a part of the meta-layer forming material 300a on which the photoresist PR is disposed may be oxidized to form a patterned metal layer 301 and a metal oxide layer 302. The degree of oxidation of the meta-layer forming material 300a on which the photoresist PR is disposed may be less than the degree of oxidation of the meta-layer forming material 300a on which no photoresist PR is disposed.

[0121] Most of the meta-layer forming material 300a on which no photoresist PR is disposed may be oxidized to form a metal oxide layer 302. The meta-layer forming material 300a on which no photoresist PR is disposed may also be oxidized to its lower part adjacent to the upper surface of the capping layer 215 to form a metal oxide layer 302. On the other hand, only a part of the meta-layer forming material 300a on which the photoresist PR is disposed and adjacent to the photoresist PR may be oxidized to form a metal oxide layer 302. In other words, the thickness of the metal oxide layer 302 disposed under the photoresist PR may be less than the thickness of the metal oxide layer 302 without the photoresist PR.

[0122] Instead of physically stacking the metal oxide layer 302 on the metal layer 301, the patterned metal layer 301 and the metal oxide layer 302 are formed by oxidizing at least a part of the meta-layer forming material 300a. Thus, the metal layer 301 and the metal oxide layer 302 can be chemically bonded to each other.

[0123] In the case where the metal oxide layer 302 is formed by oxidizing the meta-layer forming material 300a including aluminum (Al), the metal oxide layer 302 may include aluminum oxide (Al2O3). In another example, in the case where the metal oxide layer 302 is formed by oxidizing the meta-layer forming material 300a including silicon (Si), the metal oxide layer 302 may include silicon dioxide (SiO2).

[0124] Aluminum (Al) can form protons in the entire visible light range. To effectively form LSP at the interface 301s between the metal layer 301 and the metal oxide layer 302, the metal layer 301 may include aluminum (Al). However, the present disclosure is not limited thereto. In another embodiment, the metal layer 301 of the meta-layer 300 may include silicon (Si). The metal oxide layer 302 may include silicon dioxide (SiO2).

[0125] Since at least a part of the meta-layer forming material 300a is oxidized to form the metal oxide layer 302, the upper surface of the metal oxide layer 302 can be flat. The unoxidized meta-layer forming material 300a can form the patterned metal layer 301. As Figure 4 shown, the patterned metal layer 301 is provided in a rectangular shape and can reduce the reflectivity of light incident from the outside of the display device 1 (see Figure 1 ).

[0126] In the case where the metal oxide layer 302 is physically stacked on the metal layer 301, a process of patterning the metal layer 301 may be necessary. Since the process of patterning the metal layer 301 requires an imprint process and an etching process, the process of patterning the metal layer 301 may involve a complex process, and the time required for the manufacturing process of the display device 1 may increase.

[0127] In an embodiment, in the case where the meta-layer forming material 300a is provided and the metal oxide layer 302 is formed by oxidizing at least a part of the meta-layer forming material 300a, a process of patterning the metal layer 301 and a process of physically stacking the metal oxide layer 302 are not required. Thus, the efficiency of the manufacturing process of the display device 1 can be improved, and the time required for the manufacturing process can be shortened.

[0128] The thickness t2 of the meta-layer forming material 300a (the meta-layer 300 including the metal layer 301 and the metal oxide layer 302) (seeFigure 7 ) The meta layer can be from about 5 nm to about 10 nm. In the case where the thickness t2 of the meta layer forming material 300a is less than about 5 nm, this thickness may be insufficient to generate LSP at the interface 301s between the metal layer 301 and the metal oxide layer 302. If the thickness t2 of the meta layer forming material 300a exceeds about 10 nm, the light emitted from the light-emitting element may not be transmitted to the outside, and the light extraction efficiency may be reduced.

[0129] Referring to Figure 9 , the photoresist PR provided on the metal layer 301 and the metal oxide layer 302 can be removed (see Figure 8 ).

[0130] In an embodiment, the meta layer 300 including the metal layer 301 and the metal oxide layer 302 can be provided on the capping layer 215 adjacent to the capping layer 215 to form LSP and an electromagnetic field at the interface 301s between the metal layer 301 and the metal oxide layer 302, so as to release the photons trapped in the interface 213s1 between the counter electrode 213 and the capping layer 215 or in the interface 213s2 between the counter electrode 213 and the second functional layer 212c, and improve the light extraction efficiency of the display device 1 (see Figure 1 ).

[0131] Since the patterned metal layer 301 and the metal oxide layer 302 are formed by oxidizing at least a part of the meta layer forming material 300a, a process of patterning the metal layer 301 or a process of physically stacking the metal oxide layer 302 may not be required, and thus the efficiency of the manufacturing process of the display device 1 can be improved and the time required for the manufacturing process can be reduced.

[0132] In summarizing the detailed description, those skilled in the art will appreciate that various changes and modifications can be made to the preferred embodiments without substantially departing from the principles, spirit, and scope of the present disclosure. Therefore, the disclosed preferred embodiments of the present disclosure are used only in a general and descriptive sense and are not for the purpose of limitation.

[0133] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the above-disclosed embodiments can be implemented individually or in combination with each other.

[0134] The disclosed embodiments in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be illustrated by the appended claims, and it should be noted that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, wherein, The display device includes: a substrate; a light-emitting element disposed on the substrate and including a sub-pixel electrode, an emission layer, and a counter electrode; a capping layer disposed on the light-emitting element; and a meta-layer disposed on the capping layer and including a patterned metal layer and a metal oxide layer disposed on the metal layer.

2. The display device according to claim 1, wherein, When observed in a direction perpendicular to the substrate, the metal layer is patterned into a plurality of rectangular shapes.

3. The display device according to claim 1, wherein, The metal layer and the metal oxide layer include the same metal.

4. The display device according to claim 1, wherein, The metal layer includes aluminum, and the metal oxide layer includes aluminum oxide.

5. The display device according to claim 1, wherein the metal layer includes at least one selected from silver, gold, molybdenum, and vanadium, and the metal oxide layer includes at least one selected from silver oxide, gold oxide, molybdenum oxide, and vanadium oxide.

6. The display device according to claim 1, wherein, The meta-layer has a thickness of 5 nm to 10 nm.

7. The display device according to claim 1, wherein, The metal layer includes silicon, and the metal oxide layer includes silicon dioxide.

8. The display device according to claim 1, wherein, As a result of a cross-cut test, the interfacial adhesion force between the metal layer and the metal oxide layer is 5B.

9. The display device according to claim 1, wherein, The metal oxide layer has a flat upper surface.

10. A method of manufacturing a display device, wherein, The method includes: disposing a light-emitting element on a substrate, the light-emitting element including a sub-pixel electrode, an emission layer, and a counter electrode; disposing a capping layer on the light-emitting element; and forming a meta-layer on the capping layer, the meta-layer including a patterned metal layer and a metal oxide layer.

11. The method according to claim 10, wherein, When observed in a direction perpendicular to the substrate, the metal layer is patterned into a plurality of rectangular shapes.

12. The method according to claim 10, wherein The forming of the meta-layer includes: disposing a meta-layer forming material on the capping layer; disposing a photoresist on at least a part of the meta-layer forming material; and oxidizing at least a part of the meta-layer forming material to form the patterned metal layer and the metal oxide layer.

13. The method according to claim 12, wherein, The meta-layer forming material on which the photoresist is not disposed is oxidized to form the metal oxide layer.

14. The method according to claim 13, wherein, Only a part of the meta-layer forming material on which the photoresist is disposed and adjacent to the photoresist is oxidized to form the metal oxide layer.

15. The method according to claim 14, wherein, The degree of oxidation of the meta-layer forming material on which the photoresist is disposed is less than the degree of oxidation of the meta-layer forming material on which the photoresist is not disposed.

16. The method according to claim 14, wherein, The thickness of the metal oxide layer disposed under the photoresist is less than the thickness of the metal oxide layer on which the photoresist is not disposed.

17. The method according to claim 12, wherein, The meta-layer forming material and the metal layer include at least one selected from aluminum, silver, gold, molybdenum, and vanadium.

18. The method according to claim 10, wherein, The metal oxide layer includes at least one selected from aluminum oxide, silver oxide, gold oxide, molybdenum oxide, and vanadium oxide.

19. The method according to claim 10, wherein As a result of a cross-cut test, the interfacial adhesion force between the metal layer and the metal oxide layer is 5B.

20. The method according to claim 12, wherein The meta-layer forming material has a thickness of 5 nm to 10 nm.

21. The method according to claim 10, wherein, The metal layer includes silicon, and the metal oxide layer includes silicon dioxide.

Images