SiC semiconductor device

Abstract

A SiC semiconductor device according to the present invention comprises: a SiC layer including a main surface; a trench structure formed on the main surface and extending in a first extension direction in a plan view; and a planar electrode-type gate structure disposed on the main surface and extending in a second extension direction other than the first extension direction in plan view.

Description

Technical Field

[0001] This application claims the priority of Japanese Patent Application No. 2022-212613, filed with the Japan Patent Office on December 28, 2022, and the entire content of this application is incorporated herein by reference. The present disclosure relates to a SiC semiconductor device. Background Art

[0002] Patent Document 1 (US2015 / 0028351A1) discloses an electronic device having an impurity region in a silicon carbide layer introduced by a channel implantation method.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: US Patent Application Publication No. 2015 / 0028351 Summary of the Invention

[0006] The present disclosure provides a novel SiC semiconductor device.

[0007] The present disclosure provides a SiC semiconductor device, including: a SiC layer including a main surface; a trench structure formed on the main surface and extending in a first extension direction in a plan view; and a planar electrode type gate structure disposed on the main surface and extending in a second extension direction other than the first extension direction in a plan view.

[0008] The present disclosure provides a SiC semiconductor device, including: a SiC layer of a first conductivity type including a main surface and having an axial channel along a stacking direction; a trench structure formed on the main surface and partitioning a bottom portion and a lower side region of the SiC layer; a column region of a second conductivity type formed in the lower side region and extending along the axial channel; and a planar electrode type gate structure disposed on the main surface and overlapping with the trench structure and the column region in the stacking direction.

[0009] The above or other objects, features, and effects become clear through the detailed description with reference to the accompanying drawings. Brief Description of the Drawings

[0010] Figure 1 It is a plan view showing a SiC semiconductor device in a specific embodiment.

[0011] Figure 2 It is along Figure 1 The cross-sectional view taken along line II-II shown.

[0012] Figure 3 It is a plan view showing a layout example of a chip.

[0013] Figure 4 It is a perspective view showing an example of chip layout.

[0014] Figure 5 is a top view showing the active area.

[0015] Figure 6 It is a cross-sectional perspective view showing the active area.

[0016] Figure 7 It is a cross-sectional perspective view showing the active area.

[0017] Figure 8 It is an enlarged cross-sectional view showing the groove structure.

[0018] Figure 9 It is an enlarged cross-sectional view showing the groove structure.

[0019] Figure 10 It is an enlarged cross-sectional view showing the gate structure.

[0020] Figure 11 It is an enlarged cross-sectional view showing the gate structure.

[0021] Figure 12 This is a graph showing an example of the n-type concentration gradient in the high-concentration region.

[0022] Figure 13 This is a graph showing a comparative example of the n-type concentration gradient in the high-concentration region.

[0023] Figure 14 This is a graph showing an example of the p-type concentration gradient in the pillar region.

[0024] Figure 15 It is a perspective view showing the structure of the outer peripheral area.

[0025] Figure 16 It is a cross-sectional view showing a main part of the outer peripheral area.

[0026] Figure 17 It is a cross-sectional view showing a main part of the outer peripheral area.

[0027] Figure 18 This is a schematic diagram showing a wafer used in manufacturing a SiC semiconductor device.

[0028] Figure 19 This is a flowchart showing an example of a method for manufacturing a SiC semiconductor device.

[0029] Figure 20A It is a cross-sectional perspective view showing an example of a method for manufacturing a SiC semiconductor device.

[0030] Figure 20B Yes Figure 20ACross-sectional perspective view of the subsequent process.

[0031] Figure 20C It represents Figure 20B Cross-sectional perspective view of the subsequent process.

[0032] Figure 20D It represents Figure 20C Cross-sectional perspective view of the subsequent process.

[0033] Figure 20E It represents Figure 20D Cross-sectional perspective view of the subsequent process.

[0034] Figure 20F It represents Figure 20E Cross-sectional perspective view of the subsequent process.

[0035] Figure 20G It represents Figure 20F Cross-sectional perspective view of the subsequent process.

[0036] Figure 20H It represents Figure 20G Cross-sectional perspective view of the subsequent process.

[0037] Figure 20I It represents Figure 20H Cross-sectional perspective view of the subsequent process.

[0038] Figure 20J It represents Figure 20I Cross-sectional perspective view of the subsequent process.

[0039] Figure 20K It represents Figure 20J Cross-sectional perspective view of the subsequent process.

[0040] Figure 20L ] It represents Figure 20K Cross-sectional perspective view of the subsequent process.

[0041] Figure 20M It represents Figure 20L Cross-sectional perspective view of the subsequent process.

[0042] Figure 20N It represents Figure 20M Cross-sectional perspective view of the subsequent process.

[0043] Figure 20O It represents Figure 20N Cross-sectional perspective view of the subsequent process.

[0044] Figure 20P It represents Figure 20O Cross-sectional perspective view of the subsequent process.

[0045] Figure 20Q It representsFigure 20P Cross-sectional perspective view of subsequent processes.

[0046] Figure 20R It represents Figure 20Q Cross-sectional perspective view of subsequent processes.

[0047] Figure 21A It is a schematic diagram for explaining the measurement process of crystal orientation.

[0048] Figure 21B It is a schematic diagram for explaining the measurement process of crystal orientation.

[0049] Figure 22A It is a schematic diagram for explaining the ion implantation process.

[0050] Figure 22B It is a schematic diagram for explaining the ion implantation process.

[0051] Figure 23 It is a cross-sectional perspective view of a SiC semiconductor device showing a first modified example.

[0052] Figure 24 It is a cross-sectional perspective view of a SiC semiconductor device showing a second modified example.

[0053] Figure 25 It is a cross-sectional perspective view of a SiC semiconductor device showing a third modified example.

[0054] Figure 26 It is a cross-sectional perspective view of a SiC semiconductor device showing a fourth modified example. Detailed implementation mode

[0055] Hereinafter, with reference to the accompanying drawings, the specific mode will be described in detail. The accompanying drawings are all schematic diagrams, not strictly drawn, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. The same reference numerals are assigned to the corresponding structures between the accompanying drawings, and the repeated descriptions are omitted or simplified. For the structures with omitted or simplified descriptions, the descriptions made before the omission or simplification are applied.

[0056] When the statement "substantially" is used in this specification, this statement includes not only the numerical value (form) equal to the numerical value (form) of the comparison object, but also the numerical error (form error) within the range of ±10% based on the numerical value (form) of the comparison object. In the following description, the terms "first", "second", "third", etc. are used, but they are notations given to the names of each structure to clarify the description order, and are not given with the intention of limiting the names of each structure.

[0057] In the following description, the conductivity type of a semiconductor (impurity) is represented by "p-type" or "n-type". However, "p-type" may also be referred to as "first conductivity type", and "n-type" may be referred to as "second conductivity type". Of course, "n-type" may also be referred to as "first conductivity type", and "p-type" may be referred to as "second conductivity type". "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is, unless otherwise specified, at least one of boron, aluminum, gallium, and indium. The pentavalent element is, unless otherwise specified, at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0058] Figure 1 is a top view of the SiC semiconductor device 1 showing a specific manner. Figure 2 is along Figure 1 the cross-sectional view taken along the line II-II shown. Figure 3 is a top view showing an example of the layout of the chip 2. Figure 4 is a perspective view showing an example of the layout of the chip 2. Figure 5 is a top view showing the active region 8.

[0059] Figure 6 is a cross-sectional perspective view showing the trench structure 20. Figure 7 is a cross-sectional perspective view showing the trench structure 20. Figure 8 is an enlarged cross-sectional view showing the trench structure 20. Figure 9 is an enlarged cross-sectional view showing the trench structure 20. Figure 10 is an enlarged cross-sectional view showing the gate structure 37. Figure 11 is an enlarged cross-sectional view showing the gate structure 37.

[0060] Referring to Figures 1 to 11 , the SiC semiconductor device 1 includes a chip 2 containing a SiC single crystal. The chip 2 may also be referred to as a "SiC chip" or a "semiconductor chip". The chip 2 is composed of a hexagonal SiC single crystal in this embodiment and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has various polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this manner, an example in which the chip 2 is composed of a 4H-SiC single crystal is shown, but the chip 2 may also be composed of other polytypes.

[0061] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed as quadrilaterals when viewed from above in the vertical direction Z (hereinafter simply referred to as "viewed from above"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may also be formed as squares or rectangles when viewed from above.

[0062] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal. In this case, it is preferred that the first main surface 3 is formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0063] In the circumferential direction of the chip 2 starting from the first side surface 5A (counterclockwise in Figure 1 ), the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and are opposed to each other in a second direction Y that intersects (specifically, is orthogonal to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and are opposed to each other in the first direction X.

[0064] In this manner, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0065] The XY plane including the first direction X and the second direction Y forms a horizontal plane orthogonal to the vertical direction Z. Hereinafter, the axis extending along the vertical direction Z may sometimes be expressed as the "vertical axis". In addition, hereinafter, the first direction X and the second direction Y may sometimes be expressed as the "horizontal direction". The horizontal direction is also the direction extending along the first main surface 3.

[0066] Refer to Figure 4 , the chip 2 (the first main surface 3 and the second main surface 4) has a deviation angle θo that is inclined at a predetermined angle with respect to the c-plane of the SiC single crystal in a predetermined deviation direction Do. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by an amount of the deviation angle θo from the vertical axis toward the deviation direction Do. In addition, the c-plane of the SiC single crystal is inclined by an amount of the deviation angle θo with respect to the horizontal plane.

[0067] The deviation direction Do is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The deviation angle θo can also exceed 0° and be 10° or less. The deviation angle θo can have a value belonging to any one of the ranges of more than 0° and 1° or less, 1° or more and 2.5° or less, 2.5° or more and 5° or less, 5° or more and 7.5° or less, and 7.5° or more and 10° or less.

[0068] The deviation angle θo is preferably 5° or less. The deviation angle θo is particularly preferably 2° or more and 4.5° or less. The deviation angle θo is typically set in the range of 4° ± 0.1°. Of course, this specification does not exclude the case where the deviation angle θo is 0° (i.e., the case where the first main surface 3 is the front with respect to the c-plane).

[0069] The chip 2 includes an n-type base layer 6 made of a SiC single crystal. The base layer 6 can also be referred to as a "base SiC layer", a "base region", etc. The base layer 6 extends in a layered manner in the horizontal direction, forming a part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this manner, the base layer 6 is composed of a substrate made of a SiC single crystal (i.e., a SiC substrate). The base layer 6 has the aforementioned deviation direction Do and deviation angle θo.

[0070] The base layer 6 has a first axial channel C1 along the stacking direction. The first axial channel C1 is a region (channel) where the interatomic distance (atomic spacing) of the SiC single crystal constituting the base layer 6 is relatively wide, and is surrounded by atomic columns of the crystal axis extending in the stacking direction (crystal growth direction).

[0071] That is, the first axial channel C1 is a region where the sparse atomic columns extend in the stacking direction, and is a region where the atomic columns (interatomic distance / atomic density) in the horizontal direction are sparse when viewed from above. The first axial channel C1 is preferably a region surrounded by atomic columns along a low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values of "a1", "a2", "a3", and "c" with respect to the Miller indices (a1, a2, a3, c) are all expressed as 2 or less (preferably 1 or less) (the same applies hereinafter in this specification).

[0072] In this manner, the first axial channel C1 is formed by a region surrounded by atomic columns along the c-axis ((0001) axis) of the SiC single crystal. That is, the first axial channel C1 extends along the c-axis and has the aforementioned deviation direction Do and deviation angle θo. In other words, the first axial channel C1 is inclined by the amount of the deviation angle θo from the vertical axis toward the deviation direction Do.

[0073] The base layer 6 may also have 1×10 18 cm -3 or more and 1×10 21 cm -3The following n-type impurity concentration is taken as the peak. The base layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted by a single type of pentavalent element. The n-type impurity concentration of the base layer 6 is particularly preferably adjusted by a pentavalent element other than phosphorus. In this manner, the n-type impurity concentration of the base layer 6 is adjusted by nitrogen.

[0074] The base layer 6 has a first thickness T1. The first thickness T1 can be 5 μm or more and 300 μm or less. The first thickness T1 can have a value belonging to any one of the ranges of 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, and 250 μm or more and 300 μm or less. The first thickness T1 is preferably 50 μm or more and 250 μm or less.

[0075] The chip 2 includes a semiconductor layer 7 made of a single crystal of SiC laminated on the base layer 6. The semiconductor layer 7 can also be referred to as a "SiC layer", a "semiconductor region", etc. The semiconductor layer 7 extends in a layered manner in the horizontal direction, forming a part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The semiconductor layer 7 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that grows crystallographically starting from the base layer 6.

[0076] The semiconductor layer 7 has a lower end and an upper end. The lower end of the semiconductor layer 7 is the starting point of crystal growth, and the upper end of the semiconductor layer 7 is the ending point of crystal growth. The lower end of the semiconductor layer 7 is also the bottom of the semiconductor layer 7. Since the semiconductor layer 7 grows continuously crystallographically from the base layer 6, the lower end of the semiconductor layer 7 coincides with the upper end of the base layer 6.

[0077] The boundary between the base layer 6 and the semiconductor layer 7 may not be visually recognizable and can be evaluated and / or determined indirectly based on other structures and elements. The semiconductor layer 7 has a deviation direction Do and a deviation angle θo that are substantially the same as those of the base layer 6.

[0078] The semiconductor layer 7 has a second axis channel C2 along the stacking direction. The second axis channel C2 is a region (channel) where the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the semiconductor layer 7 and is surrounded by atomic columns along the crystal axis extending in the stacking direction (crystal growth direction).

[0079] That is, the second axis channel C2 is a region where the sparse atomic columns extend in the stacking direction and is a region where the atomic columns in the horizontal direction (interatomic distance / atomic density) are sparse when viewed from above. The second axis channel C2 is preferably a region surrounded by atomic columns along a low-index crystal axis among the crystal axes.

[0080] In this manner, the second-axis channel C2 is constituted by a region surrounded by atomic columns along the c-axis of the SiC single crystal. That is, the second-axis channel C2 extends along the c-axis and has a deviation direction Do and a deviation angle θo. In other words, the second-axis channel C2 is inclined from the vertical axis by an amount of the deviation angle θo toward the deviation direction Do. Further, the second-axis channel C2 substantially coincides with the first-axis channel C1.

[0081] The n-type impurity concentration of the semiconductor layer 7 is preferably less than the n-type impurity concentration of the base layer 6. The semiconductor layer 7 may also have an n-type impurity concentration of 1×10 15 cm -3 or more and 1×10 18 cm -3 or less as a peak value. The n-type impurity concentration of the semiconductor layer 7 may also be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the semiconductor layer 7 may also have a concentration gradient that increases and / or decreases in the stacking direction (crystal growth direction).

[0082] In this manner, the n-type impurity concentration of the semiconductor layer 7 is adjusted by nitrogen. The semiconductor layer 7 may also have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the semiconductor layer 7 may also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The semiconductor layer 7 preferably includes a pentavalent element other than phosphorus.

[0083] The n-type impurity concentration of the semiconductor layer 7 is preferably adjusted by nitrogen at least. In the case where the semiconductor layer 7 includes two or more pentavalent elements, the semiconductor layer 7 preferably includes nitrogen and a pentavalent element other than nitrogen. In this case, the semiconductor layer 7 preferably includes either or both of arsenic and antimony as pentavalent elements other than phosphorus and nitrogen.

[0084] The semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 1 μm or more and 10 μm or less. The second thickness T2 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The second thickness T2 is preferably 2 μm or more and 8 μm or less.

[0085] The SiC semiconductor device 1 includes an active region 8 set in the chip 2. The active region 8 is set inside the chip 2 at a distance from the peripheral edge (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 8 is set to have a polygonal shape (a quadrilateral shape in this manner) with four sides parallel to the peripheral edge of the chip 2 in a plan view. The planar area of the active region 8 is preferably 50% or more and 90% or less of the planar area of the first main surface 3.

[0086] The SiC semiconductor device 1 includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is disposed in the region between the peripheral edge of the chip 2 and the active region 8 in a plan view. The peripheral region 9 extends in a strip shape along the active region 8 in a plan view and is set to surround the active region 8 in a multi-sided ring shape (a four-sided ring shape in this case).

[0087] The SiC semiconductor device 1 includes an active surface 10, an outer surface 11, and first to fourth connecting surfaces 12A to 12D formed on the first main surface 3. The active surface 10, the outer surface 11, and the first to fourth connecting surfaces 12A to 12D define an active mesa 13 on the first main surface 3.

[0088] The active surface 10 may also be referred to as the "first surface portion", the outer surface 11 may be referred to as the "second surface portion", the first to fourth connecting surfaces 12A to 12D may be referred to as the "connecting surface portions", and the active mesa 13 may be referred to as the "mesa surface portion". The active surface 10, the outer surface 11, and the first to fourth connecting surfaces 12A to 12D (i.e., the active mesa 13) can be regarded as components of the chip 2 (the first main surface 3).

[0089] The active surface 10 is formed in the active region 8. That is, the active surface 10 is formed at a distance from the peripheral edge (the first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the inside. The active surface 10 has a flat surface extending in the first direction X and the second direction Y. In this case, the active surface 10 is formed of the c-plane (Si plane). In this case, the active surface 10 is formed to have a quadrilateral shape with four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0090] The outer surface 11 is formed in the peripheral region 9. That is, the outer surface 11 is formed outside the active surface 10. The outer surface 11 is recessed in the thickness direction (toward the second main surface 4 side) of the chip 2 with respect to the active surface 10. Specifically, in this case, the outer surface 11 is recessed by a depth less than the thickness of the semiconductor layer 7 to expose the semiconductor layer 7. That is, the outer surface 11 faces the base layer 6 with a part of the semiconductor layer 7 interposed therebetween, exposing the semiconductor layer 7.

[0091] The outer surface 11 extends in a strip shape along the active surface 10 in a plan view and is formed in a ring shape (specifically, a four-sided ring shape) surrounding the active surface 10. The outer surface 11 has a flat surface extending in the first direction X and the second direction Y and is formed substantially parallel to the active surface 10. In this case, the outer surface 11 is formed of the c-plane (Si plane). The outer surface 11 is connected to the first to fourth side surfaces 5A to 5D.

[0092] The outer peripheral surface 11 has an outer peripheral depth DO. The outer peripheral depth DO can be 0.1 μm or more and 2 μm or less. The outer peripheral depth DO can have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The outer peripheral depth DO is preferably 0.1 μm or more and 1.5 μm or less.

[0093] The first to fourth connection surfaces 12A to 12D extend in the vertical direction Z and connect the active surface 10 and the outer peripheral surface 11. The first connection surface 12A is located on the side of the first side surface 5A, the second connection surface 12B is located on the side of the second side surface 5B, the third connection surface 12C is located on the side of the third side surface 5C, and the fourth connection surface 12D is located on the side of the fourth side surface 5D. The first connection surface 12A and the third connection surface 12C extend in the first direction X and face each other in the second direction Y. The second connection surface 12B and the fourth connection surface 12D extend in the second direction Y and face each other in the first direction X.

[0094] The first to fourth connection surfaces 12A to 12D can extend substantially vertically between the active surface 10 and the outer peripheral surface 11 in a manner that divides the active mesa 13 into a quadrangular prism shape. The first to fourth connection surfaces 12A to 12D can also be inclined obliquely downward from the active surface 10 to the outer peripheral surface 11 in a manner that divides the active mesa 13 into a frustum of a quadrangular pyramid shape. In this way, the active mesa 13 is divided into protrusions by the semiconductor layer 7 on the first main surface 3. The active mesa 13 is formed only in the semiconductor layer 7 and not in the base layer 6.

[0095] Refer to Figures 6 to 11 The SiC semiconductor device 1 includes an n-type high-concentration region 15 formed at least in a portion of the semiconductor layer 7 located in the active region 8. The high-concentration region 15 has an n-type impurity concentration higher than the n-type impurity concentration of the semiconductor layer 7. In this manner, the high-concentration region 15 is led out from the active region 8 to the outer peripheral region 9. That is, the high-concentration region 15 is led out from a portion of the semiconductor layer 7 located in the active region 8 to a portion of the semiconductor layer 7 located in the outer peripheral region 9. The high-concentration region 15 is exposed from the outer peripheral surface 11.

[0096] Moreover, the high-concentration region 15 extends from the outer peripheral region 9 toward the first to fourth side surfaces 5A to 5D and is exposed from the first to fourth side surfaces 5A to 5D. Of course, the high-concentration region 15 can also be formed in the semiconductor layer 7 at intervals from the first to fourth side surfaces 5A to 5D toward the inside. In this case, the peripheral portion of the high-concentration region 15 can be located within the active region 8 or within the outer peripheral region 9.

[0097] The high-concentration region 15 has an upper end portion on the upper end side of the semiconductor layer 7 and a lower end portion on the lower end side of the semiconductor layer 7. In this manner, the upper end portion of the high-concentration region 15 is in a region on the upper end side of the semiconductor layer 7 with respect to the middle portion of the thickness range of the semiconductor layer 7, and the lower end portion of the high-concentration region 15 is in a region on the lower end side of the semiconductor layer 7 with respect to the middle portion of the thickness range of the semiconductor layer 7.

[0098] Although specific illustrations are omitted, the upper end portion of the high-concentration region 15 may also be exposed from the first main surface 3. Of course, the upper end portion of the high-concentration region 15 may also be formed at an interval from the upper end of the semiconductor layer 7 (i.e., the semiconductor layer 7) toward the lower end side, and face the first main surface 3 with a part (upper end portion) of the semiconductor layer 7 interposed therebetween. Such a structure is determined by analyzing the n-type impurity concentration (concentration gradient) of the high-concentration region 15.

[0099] The distance between the first main surface 3 and the upper end portion of the high-concentration region 15 may be 0 μm or more and 1 μm or less. The distance between the first main surface 3 and the upper end portion of the high-concentration region 15 may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0100] The lower end portion of the high-concentration region 15 is formed at an interval from the lower end of the semiconductor layer 7 (i.e., the base layer 6) toward the upper end side, and faces the base layer 6 with a part (lower end portion) of the semiconductor layer 7 interposed therebetween. The distance between the lower end of the semiconductor layer 7 and the lower end portion of the high-concentration region 15 may also exceed 0 μm and be 5 μm or less. The distance between the lower end of the semiconductor layer 7 and the lower end portion of the high-concentration region 15 may have a value belonging to any one of the ranges of exceeding 0 μm and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less.

[0101] The high-concentration region 15 has a thickness smaller than the second thickness T2 of the semiconductor layer 7. The thickness of the high-concentration region 15 may be 1 μm or more and less than 10 μm. The thickness of the high-concentration region 15 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and less than 10 μm. The thickness of the high-concentration region 15 is preferably 2 μm or more and 8 μm or less. Of course, the lower end portion of the high-concentration region 15 may also cross the boundary portion between the base layer 6 and the semiconductor layer 7 and be located in the base layer 6.

[0102] The high-concentration region 15 is composed of an n-type channel region that extends along the second-axis channel C2 within the semiconductor layer 7 in a cross-sectional view. That is, the high-concentration region 15 is composed of an impurity region introduced parallel or substantially parallel to a region (second-axis channel C2) surrounded by atomic columns along a low-index crystal axis within the semiconductor layer 7, and extends obliquely with respect to the first main surface 3.

[0103] Therefore, the high-concentration region 15 has a deviation direction Do and a deviation angle θo that are substantially the same as the deviation direction Do and the deviation angle θo of the second-axis channel C2. In other words, the high-concentration region 15 is inclined by an amount of the deviation angle θo in the deviation direction Do from the vertical axis. The high-concentration region 15 is composed of a single impurity region having a thickness (depth) along the middle part of the second-axis channel C2 that crosses the semiconductor layer 7.

[0104] The high-concentration region 15 may also have a peak n-type impurity concentration of 1×10 15 cm -3 or more and 1×10 18 cm -3 or less. The n-type impurity concentration of the high-concentration region 15 is preferably adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the high-concentration region 15 can also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0105] The high-concentration region 15 preferably includes pentavalent elements other than nitrogen and phosphorus. The n-type impurity concentration of the high-concentration region 15 is preferably adjusted by at least one of arsenic, antimony, and bismuth. In view of ease of acquisition, the n-type impurity concentration of the high-concentration region 15 is preferably adjusted by arsenic or antimony.

[0106] Hereinafter, the n-type concentration gradient of the high-concentration region 15 will be specifically described. Figure 12 It is a graph (simulation) showing an example of the n-type concentration gradient of the high-concentration region 15. Figure 13 It is a graph (simulation) showing a comparative example of the n-type concentration gradient of the high-concentration region 15. In Figure 12 and Figure 13 the vertical axis represents the n-type impurity concentration of the high-concentration region 15, and the horizontal axis represents the depth along the second-axis channel C2 with the first main surface 3 as a reference (zero point).

[0107] In Figure 12 and Figure 13 it has 1×10 15 cm -3The region with the n-type impurity concentration above is defined as the high-concentration region 15 and is illustrated as a graph. The numerical values of the impurity concentration, thickness, etc. shown below are examples for explaining the basic structure of the high-concentration region 15 based on the concentration gradient, and are not shown with the intention of uniquely defining the structure of the high-concentration region 15. The impurity concentration, thickness, etc. are adjusted to various values according to the implantation conditions (dose, implantation temperature, implantation energy, etc.) of the pentavalent element.

[0108] Figure 12 It is a graph in the case where the high-concentration region 15 is formed by the channel implantation method. Figure 12 It shows the concentration gradient of the high-concentration region 15 when a predetermined pentavalent element (here arsenic) is introduced into the semiconductor layer 7 parallel or substantially parallel to the second-axis channel C2 with an implantation energy of 500 keV or more and 800 keV or less.

[0109] The dose of the pentavalent element is 1×10 13 cm -2 . The thickness of the semiconductor layer 7 is about 5 μm. In Figure 12 , the concentration gradient in the case where the high-concentration region 15 is formed with an implantation energy of 1500 keV or more and 2500 keV or less is indicated by a dashed line.

[0110] On the other hand, Figure 13 It is a graph when the high-concentration region 15 is formed by the random implantation method. Figure 13 It shows the concentration gradient of the high-concentration region 15 when a predetermined pentavalent element (here arsenic) is introduced into the semiconductor layer 7 in a random direction with an implantation energy of 500 keV or more and 800 keV or less.

[0111] The random direction is a direction not parallel (substantially parallel) to the second-axis channel C2 (for example, the vertical direction Z). The dose of the pentavalent element is 1×10 13 cm -2 . The thickness of the semiconductor layer 7 is about 5 μm. In Figure 13 , the concentration gradient in the case where the high-concentration region 15 is formed with an implantation energy of 1500 keV or more and 2500 keV or less is indicated by a dashed line.

[0112] Referring to Figure 12 , the high-concentration region 15 has a thickness of 2.1 μm or more and 2.4 μm or less, has an upper end portion that is separated from the first main surface 3 toward the lower end side of the semiconductor layer 7, and a lower end portion that is separated from the lower end of the semiconductor layer 7 toward the upper end side. The high-concentration region 15 has a concentration gradient that gradually decreases from the upper end portion side toward the lower end portion side.

[0113] Specifically, the n-type impurity concentration in the high-concentration region 15 has a concentration gradient including a first increasing portion 16, a first peak portion 17, a first slow portion 18, and a first decreasing portion 19 from the upper end portion side toward the lower end portion side. The first increasing portion 16 is the portion forming the upper end portion of the high-concentration region 15, and the n-type impurity concentration gradually increases from the upper end portion toward the lower end portion side at a relatively steep increasing rate to the first peak portion 17.

[0114] The first peak portion 17 is the portion having the first peak value P1 (maximum value) of the n-type impurity concentration. The first peak portion 17 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the n-type impurity concentration changes from increasing (increasing tendency) to decreasing (decreasing tendency).

[0115] The first slow portion 18 is formed in the region on the lower end portion side of the first peak portion 17, and is the portion where the impurity concentration gradually decreases at a relatively slow decreasing rate. That is, the first slow portion 18 is the portion that maintains a certain n-type impurity concentration within a certain depth range, and forms the main body portion of the high-concentration region 15. The n-type impurity concentration of the first slow portion 18 decreases within the concentration range less than the n-type impurity concentration of the first peak portion 17.

[0116] The first slow portion 18 is defined by the portion having a concentration decreasing rate of 50% or less within a thickness range of at least 0.5 μm. In the Figure 12 example, the first slow portion 18 has a thickness of 0.8 μm or more and 1.1 μm or less, and has a concentration decreasing rate of 50% or less within this thickness range.

[0117] The first slow portion 18 occupies a thickness range of more than 1 / 4 in the high-concentration region 15. Specifically, the proportion of the first slow portion 18 in the high-concentration region 15 is 1 / 3 or more. The proportion of the first slow portion 18 in the high-concentration region 15 is typically 1 / 2 or less (less than 1 / 2). Of course, the proportion of the first slow portion 18 in the high-concentration region 15 can also be 1 / 2 or more.

[0118] The first decreasing portion 19 is the portion forming the lower end portion of the high-concentration region 15. The first decreasing portion 19 has a concentration decreasing rate larger than the concentration decreasing rate in the first slow portion 18, and is the portion where the n-type impurity concentration gradually decreases from the first slow portion 18 toward the lower end portion. The concentration decreasing rate per unit thickness of the first decreasing portion 19 is larger than the concentration decreasing rate per unit thickness of the first slow portion 18.

[0119] In the case of the channel implantation method, the thickness (depth) of the high-concentration region 15 increases as the implantation energy increases. The depth position of the upper end portion of the high-concentration region 15 with respect to the first main surface 3 increases as the implantation energy increases. The thicknesses of the first increasing portion 16, the first peak portion 17, the first slow portion 18, and the first decreasing portion 19 increase as the implantation energy increases. On the other hand, the first peak value P1 of the high-concentration region 15 decreases as the implantation energy increases. This is because as the implantation energy increases, pentavalent elements are introduced into a deeper region, and the n-type impurity concentration in this deeper region increases.

[0120] On the contrary, the depth position of the upper end portion of the high-concentration region 15 with respect to the first main surface 3 decreases as the implantation energy decreases. The thicknesses of the first increasing portion 16, the first peak portion 17, the first slow portion 18, and the first decreasing portion 19 decrease as the implantation energy decreases. On the other hand, the first peak value P1 of the high-concentration region 15 increases as the implantation energy decreases. This is because as the implantation energy decreases, pentavalent elements are trapped in a shallow region.

[0121] On the other hand, referring to Figure 13 , in the case of the random implantation method, the high-concentration region 15 has the first increasing portion 16, the first peak portion 17 (the first peak value P1), and the first decreasing portion 19 in the range of 0.5 μm. On the other hand, there is no first slow portion 18 having a thickness of 0.5 μm or more. In addition, in the case of the random implantation method, as the implantation energy increases, the depth position of the first peak portion 17 (the first peak value P1) with respect to the first main surface 3 increases, but the thickness of the high-concentration region 15 is less than 2 μm. That is, even if the implantation energy is increased, the thickness does not change significantly.

[0122] It can be seen from this that the SiC single crystal has a physical property in which impurities are difficult to diffuse. However, in the case of the random implantation method, for the semiconductor layer 7 having a relatively large second thickness T2 (for example, 1 μm or more), it is difficult to form a high-concentration region 15 having a relatively large thickness (for example, a thickness of 1 μm or more and 5 μm or less) composed of a single region.

[0123] The SiC semiconductor device 1 includes a plurality of trench structures 20 of a trench electrode type formed on the first main surface 3 (the active surface 10) in the active region 8. A potential other than the gate potential is applied to the trench structure 20. In this way, a reference potential that is the reference for the circuit operation is applied to the trench structure 20. For example, the reference potential is the ground potential or the source potential. The trench structure 20 may also be referred to as a "field trench structure", a "trench source structure", etc.

[0124] A plurality of trench structures 20 are arranged at intervals inside from the periphery (first to fourth connection surfaces 12A to 12D) of the active surface 10 in the active region 8. In this manner, the plurality of trench structures 20 are arranged at intervals in a first arrangement direction Da1 and are each formed in a strip shape extending in a first extension direction De1. In this manner, the first arrangement direction Da1 is the first direction X (m-axis direction), and the first extension direction De1 is the second direction Y (a-axis direction).

[0125] That is, the plurality of trench structures 20 are arranged at intervals in the m-axis direction and each extend in the a-axis direction. In addition, in this manner, the plurality of trench structures 20 are arranged in a striped shape extending along the a-axis direction (second direction Y). The first extension direction De1 coincides with the deviation direction Do of the semiconductor layer 7.

[0126] The plurality of trench structures 20 are formed at intervals from the lower end (base layer 6) of the semiconductor layer 7 toward the first main surface 3 (active surface 10) side and face the base layer 6 with a part of the semiconductor layer 7 interposed therebetween. The plurality of trench structures 20 demarcate a lower region 7a in a region between the bottom wall of the plurality of trench structures 20 and the lower end (base layer 6) of the semiconductor layer 7.

[0127] In this manner, the plurality of trench structures 20 are formed at intervals from the bottom of the high-concentration region 15 toward the first main surface 3 (active surface 10) side and face a part (lower end portion) of the semiconductor layer 7 with a part (lower end portion) of the high-concentration region 15 interposed therebetween. That is, the lower region 7a is formed by a part (lower end portion) of the semiconductor layer 7 and a part (lower end portion) of the high-concentration region 15.

[0128] Preferably, the plurality of trench structures 20 are formed at intervals from the middle portion of the thickness range of the high-concentration region 15 toward the active surface 10 side. Of course, the plurality of trench structures 20 may also be formed at a depth position crossing the middle portion of the thickness range of the high-concentration region 15.

[0129] Each trench structure 20 has a trench width WT in the first arrangement direction Da1 and a trench depth DT in the vertical direction Z. The trench width WT is preferably smaller than the second thickness T2 of the semiconductor layer 7. The trench width WT is preferably smaller than the thickness of the high-concentration region 15.

[0130] The trench width WT can be 0.1 μm or more and 5 μm or less. The trench width WT can have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0131] The trench depth DT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench depth DT is preferably less than the thickness of the high-concentration region 15. Particularly preferably, the trench depth DT is substantially equal to the outer peripheral depth DO described above. Of course, the trench depth DT can be equal to or greater than the outer peripheral depth DO, or can be less than the outer peripheral depth DO.

[0132] The trench depth DT is preferably greater than the trench width WT. That is, it is preferred that the plurality of trench structures 20 each have an aspect ratio DT / WT that extends in a longitudinally long columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT.

[0133] The trench depth DT can be 0.1 μm or more and 5 μm or less. The trench depth DT can have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less.

[0134] The plurality of trench structures 20 are arranged at intervals of a trench pitch PT in the first arrangement direction Da1. The trench pitch PT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench pitch PT is preferably less than the thickness of the high-concentration region 15. The trench pitch PT can also be less than the trench depth DT. Of course, the trench pitch PT can also be greater than the trench depth DT.

[0135] The trench pitch PT can be 0.1 μm or more and 5 μm or less. The trench pitch PT can have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The trench pitch PT is preferably 0.5 μm or more and 1.5 μm or less.

[0136] Each trench structure 20 includes a trench 21, an insulating film 22, and an embedded electrode 23. The trench 21 is formed in the active surface 10 and defines the wall surfaces (side walls and bottom wall) of the trench structure 20. The bottom wall of the trench 21 preferably has a portion that extends flatly.

[0137] Particularly preferably, the flat portion of the bottom wall extends substantially parallel to the first main surface 3. That is, the bottom wall of the trench 21 preferably has a deviation angle θo that is inclined at a predetermined angle in a predetermined deviation direction Do with respect to the c plane. That is, the bottom wall of the trench 21 preferably has a flat portion that extends along the deviation direction Do. Of course, the bottom wall may be curved in an arc shape toward the lower end side of the semiconductor layer 7.

[0138] The insulating film 22 covers the wall surfaces of the trench 21. The insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this manner, the insulating film 22 has a single-layer structure composed of a silicon oxide film. The insulating film 22 particularly preferably includes a silicon oxide film composed of the oxide of the chip 2.

[0139] The embedded electrode 23 is embedded in the trench 21 and faces the semiconductor layer 7 with the insulating film 22 interposed therebetween. In this manner, the embedded electrode 23 faces the high-concentration region 15 with the insulating film 22 interposed therebetween. The embedded electrode 23 may include p-type or n-type conductive polysilicon.

[0140] The SiC semiconductor device 1 includes a plurality of p-type column regions 24 formed at intervals in the horizontal direction in the semiconductor layer 7. Specifically, the plurality of column regions 24 are formed in the lower region 7a in the semiconductor layer 7. That is, the plurality of column regions 24 are formed in the thickness range between the lower end of the semiconductor layer 7 and the bottom walls of the plurality of trench structures 20.

[0141] A plurality of column regions 24 are arranged at intervals along a first arrangement direction Da1 within the lower region 7a, and are each formed as a strip extending along a first extension direction De1. That is, the plurality of column regions 24 are arranged at intervals in the m-axis direction (first direction X) and extend in the a-axis direction (second direction Y) of the SiC single crystal. In addition, the plurality of column regions 24 are formed as stripe shapes extending along the a-axis direction (second direction Y). The extension direction of the plurality of column regions 24 coincides with the deviation direction Do of the semiconductor layer 7.

[0142] The plurality of column regions 24 overlap with the plurality of trench structures 20 in the stacking direction. Specifically, the plurality of column regions 24 overlap with the plurality of trench structures 20 in a one-to-one correspondence in the stacking direction. The plurality of column regions 24 are formed at intervals inward from the periphery (first to fourth connection surfaces 12A to 12D) of the active surface 10 in the active region 8.

[0143] In the second direction Y, the both end portions of the plurality of column regions 24 may also be located on the inner side of the active region 8 with respect to the both end portions of the plurality of trench structures 20. In the second direction Y, the both end portions of the plurality of column regions 24 may also be located on the peripheral side of the active region 8 with respect to the both end portions of the plurality of trench structures 20.

[0144] The plurality of column regions 24 have upper end portions located on the bottom wall side of the trench structures 20 and lower end portions located on the lower side of the semiconductor layer 7. In this manner, the upper end portions of the plurality of column regions 24 are located in the region on the bottom wall side of the trench structures 20 with respect to the middle portion of the thickness range of the lower region 7a, and the lower end portions of the plurality of column regions 24 are located in the region on the lower side of the semiconductor layer 7 with respect to the middle portion of the thickness range of the lower region 7a.

[0145] The depth positions of the upper end portions of the plurality of column regions 24 with respect to the outer peripheral surface 11 are formed at intervals on the lower side of the semiconductor layer 7. The upper end portions of the plurality of column regions 24 are formed at intervals from the bottom walls of the plurality of trench structures 20 toward the lower side of the semiconductor layer 7, and face the plurality of trench structures 20 across a part of the semiconductor layer 7.

[0146] Specifically, the upper end portions of the plurality of column regions 24 face the plurality of trench structures 20 across a part of the high-concentration region 15. That is, the upper end portions of the plurality of column regions 24 are electrically connected to the high-concentration region 15 having a relatively high concentration. Of course, the upper end portions of the plurality of column regions 24 may also be connected to the bottom walls of the plurality of trench structures 20.

[0147] The intermediate distance between the bottom walls of the plurality of trench structures 20 and the upper ends of the plurality of pillar regions 24 may also be 0 μm or more and 1 μm or less. The intermediate distance may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0148] The lower ends of the plurality of pillar regions 24 extend through the bottom of the high-concentration region 15 and are led out into the semiconductor layer 7. That is, the plurality of pillar regions 24 include a portion located between the bottom of the high-concentration region 15 and the bottom walls of the plurality of trench structures 20, and a portion located between the lower end of the semiconductor layer 7 and the bottom of the high-concentration region 15. The lower ends of the plurality of pillar regions 24 are electrically connected to the semiconductor layer 7 with a lower concentration.

[0149] The cross-sectional area of the portion of the plurality of pillar regions 24 located within the high-concentration region 15 is preferably larger than the cross-sectional area of the portion of the plurality of pillar regions 24 located within the semiconductor layer 7. Of course, the cross-sectional area of the portion of the plurality of pillar regions 24 located within the high-concentration region 15 may also be smaller than the cross-sectional area of the portion of the plurality of pillar regions 24 located within the semiconductor layer 7.

[0150] In this manner, the lower ends of the plurality of pillar regions 24 are formed at intervals from the lower end of the semiconductor layer 7 toward the bottom side of the high-concentration region 15, and face the base layer 6 with a part of the semiconductor layer 7 interposed therebetween. Of course, the lower ends of the plurality of pillar regions 24 may also extend through the boundary between the semiconductor layer 7 and the base layer 6 and be located within the base layer 6. When the lower end of the high-concentration region 15 is located within the base layer 6, the lower ends of the plurality of pillar regions 24 may also extend through the bottom of the high-concentration region 15 within the base layer 6.

[0151] The lower-end distance between the lower end of the semiconductor layer 7 and the lower ends of the plurality of pillar regions 24 may be 0 μm or more and 2 μm or less. The lower-end distance may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0152] Of course, in the case where a relatively thick high-concentration region 15 is formed, the lower ends of the plurality of pillar regions 24 may also be formed at intervals from the bottom of the high-concentration region 15 toward the bottom walls of the trench structures 20. That is, the plurality of pillar regions 24 may also be electrically connected to the high-concentration region 15 at both the upper end and the lower end.

[0153] The plurality of column regions 24 are formed of a p-type channel region that extends along the second-axis channel C2 in a cross-sectional view. That is, the column regions 24 are impurity regions introduced in the semiconductor layer 7 parallel or substantially parallel to a region (second-axis channel C2) surrounded by atomic rows along a low-index crystal axis, and extend obliquely with respect to the first main surface 3.

[0154] Therefore, the plurality of column regions 24 have a deviation direction Do and a deviation angle θo that are substantially the same as the deviation direction Do and the deviation angle θo of the second-axis channel C2. In other words, the plurality of column regions 24 are inclined by an amount of the deviation angle θo from the vertical axis toward the deviation direction Do. The plurality of column regions 24 are formed of a single region having a thickness (depth) of an intermediate portion that crosses the lower region 7a along the second-axis channel C2.

[0155] The plurality of column regions 24 may also have a p-type impurity concentration of 1×10 15 cm -3 or more and 1×10 18 cm -3 or less as a peak value. The p-type impurity concentration of the column region 24 is preferably adjusted by at least one trivalent element. The p-type impurity concentration of the column region 24 is particularly preferably adjusted by a trivalent element belonging to a heavy element heavier than carbon.

[0156] That is, the column region 24 preferably includes a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this manner, the p-type impurity concentration of the column region 24 is adjusted by aluminum.

[0157] The plurality of column regions 24 each have a column width WC in the first arrangement direction Da1. The column width WC may be substantially equal to the trench width WT. The column width WC may be greater than the trench width WT. The column width WC may be less than the trench width WT. The column width WC may be less than the trench depth DT. The column width WC may be greater than the trench depth DT. The column width WC is preferably less than the second thickness T2 of the semiconductor layer 7. The column width WC is preferably less than the thickness of the high-concentration region 15.

[0158] The column width WC may be 0.1 μm or more and 5 μm or less. The column width WC may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0159] The plurality of column regions 24 each have a column thickness TC (region depth). Preferably, the column thickness TC is less than the second thickness T2 of the semiconductor layer 7. Preferably, the column thickness TC is less than the thickness of the high-concentration region 15. The column thickness TC is preferably greater than the trench width WT. The column thickness TC is preferably equal to or greater than the trench depth DT. More preferably, the column thickness TC is greater than the trench depth DT. Of course, the column thickness TC may also be less than the trench depth DT.

[0160] The column thickness TC may be 1 to 5 times the trench depth DT. The ratio TC / DT of the column thickness TC to the trench depth DT may have a value belonging to any of the ranges of 1 or more and 1.5 or less, 1.5 or more and 2 or less, 2 or more and 2.5 or less, 2.5 or more and 3 or less, 3 or more and 3.5 or less, 3.5 or more and 4 or less, 4 or more and 4.5 or less, and 4.5 or more and 5 or less.

[0161] The column thickness TC is preferably greater than the column width WC. That is, the plurality of column regions 24 preferably each have an aspect ratio TC / WC that extends longitudinally in a columnar shape along the second-axis channel C2. The aspect ratio TC / WC is the ratio of the column thickness TC to the column width WC.

[0162] The column thickness TC is preferably 1 μm or more and 5 μm or less. The column thickness TC may have a value belonging to any of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0163] The plurality of column regions 24 are formed at intervals of a column pitch PC in the first arrangement direction Da1. The column pitch PC may also be substantially equal to the trench pitch PT. The column pitch PC may be greater than the trench pitch PT. The column pitch PC may also be less than the trench pitch PT.

[0164] The column pitch PC is preferably less than the column thickness TC. The column pitch PC is preferably less than the trench depth DT. The column pitch PC is preferably less than the second thickness T2 of the semiconductor layer 7. The column pitch PC is preferably less than the thickness of the high-concentration region 15.

[0165] The column pitch PC can be 0.1 μm or more and 5 μm or less. The column pitch PC can have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The column pitch PC is preferably 0.5 μm or more and 1.5 μm or less.

[0166] Hereinafter, the p-type concentration gradient in the column region 24 will be specifically described. Figure 14 It is a graph showing an example of the p-type concentration gradient in the column region 24. In Figure 14 the vertical axis represents the p-type impurity concentration in the column region 24, and the horizontal axis represents the depth along the second axis channel C2 with the bottom wall of the trench structure 20 as a reference (zero point).

[0167] In Figure 14 a region having a p-type impurity concentration of 1×10 15 cm -3 or more is defined as the column region 24 and is shown as a graph. The numerical values of the impurity concentration, thickness, etc. shown below are examples for explaining the basic structure of the column region 24 based on the concentration gradient, and are not shown for the purpose of uniquely defining the structure of the column region 24. The impurity concentration, thickness, etc. are adjusted to various values according to the implantation conditions (dose, implantation temperature, implantation energy, etc.) of the trivalent element.

[0168] Figure 14 It is a graph in the case where the column region 24 is formed by the channel implantation method. Figure 14 It represents the concentration gradient of the column region 24 when a predetermined trivalent element (here aluminum) is introduced into the lower region 7a parallel or substantially parallel to the second axis channel C2 with an implantation energy of 500 keV or more and 800 keV or less.

[0169] The dose of the trivalent element is 1×10 13 cm -2 . The trench depth DT is about 1 μm, and the thickness of the lower region 7a is about 4 μm. In Figure 14 the concentration gradient in the case where the column region 24 is formed with an implantation energy of 1500 keV or more and 2500 keV or less is indicated by a dotted line.

[0170] Refer to Figure 14, the pillar region 24 has a thickness of 2.5 μm or more and 2.8 μm or less, and has an upper end portion that is separated from the bottom wall of the trench structure 20 toward the lower end side of the semiconductor layer 7, and a lower end portion that is separated from the lower end of the semiconductor layer 7 toward the upper end side.

[0171] The p-type impurity concentration of the pillar region 24 has a concentration gradient including a second increasing portion 25, a second peak portion 26, a second gradual portion 27, and a second decreasing portion 28 from the upper end portion side toward the lower end portion side. The second increasing portion 25 is the portion that forms the upper end portion of the pillar region 24, and the p-type impurity concentration gradually increases from the upper end portion toward the lower end portion side at a relatively steep increasing rate to the second peak portion 26. In this manner, the second increasing portion 25 is located within the high-concentration region 15 and is electrically connected to the high-concentration region 15.

[0172] The second peak portion 26 is the portion having the second peak value P2 (maximum value) of the p-type impurity concentration. The second peak portion 26 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from increasing (increasing tendency) to decreasing (decreasing tendency). The second peak portion 26 is electrically connected to the high-concentration region 15. In this manner, the second peak value P2 is located on the lower end side of the semiconductor layer 7 compared to the first peak value P1 of the high-concentration region 15.

[0173] The second gradual portion 27 is formed in a region on the lower end portion side of the second peak portion 26 and is the portion where the impurity concentration gradually decreases at a relatively slow decreasing rate. That is, the second gradual portion 27 is the portion that maintains a certain p-type impurity concentration within a certain depth range and forms the main body portion of the pillar region 24. The p-type impurity concentration of the second gradual portion 27 decreases within a concentration range that is less than the p-type impurity concentration of the second peak portion 26.

[0174] The second gradual portion 27 is defined by a portion having a concentration decrease rate of 50% or less within a thickness range of at least 0.5 μm. In Figure 14 the example, the second gradual portion 27 has a thickness of 1 μm or more and 1.3 μm or less, and has a concentration decrease rate of 50% or less within this thickness range. The second gradual portion 27 is located within the high-concentration region 15 and is electrically connected to the high-concentration region 15. The second gradual portion 27 may also have a portion within the thickness range between the lower end of the semiconductor layer 7 and the lower end portion of the high-concentration region 15 and is electrically connected to the semiconductor layer 7.

[0175] The second gradual portion 27 occupies a thickness range of more than 1 / 4 in the pillar region 24. Specifically, the proportion of the second gradual portion 27 in the pillar region 24 is 1 / 3 or more. The proportion of the second gradual portion 27 in the pillar region 24 is typically 1 / 2 or less (less than 1 / 2). Of course, the proportion of the second gradual portion 27 in the pillar region 24 may also be 1 / 2 or more.

[0176] The second decreasing portion 28 is a part that forms the lower end portion of the column region 24. The second decreasing portion 28 has a concentration decreasing rate greater than that in the second slow portion 27, and is a portion where the p-type impurity concentration gradually decreases from the second slow portion 27 toward the lower end portion. The concentration decreasing rate per unit thickness of the second decreasing portion 28 is greater than the concentration decreasing rate per unit thickness of the second slow portion 27. The second decreasing portion 28 is located in the thickness range between the lower end of the semiconductor layer 7 and the lower end portion of the high-concentration region 15 and is electrically connected to the semiconductor layer 7.

[0177] In the case of the channel implantation method, the thickness (depth) of the column region 24 increases as the implantation energy increases. The depth position of the upper end portion of the column region 24 relative to the bottom wall of the trench structure 20 increases as the implantation energy increases. The thicknesses of the second increasing portion 25, the second peak portion 26, the second slow portion 27, and the second decreasing portion 28 increase as the implantation energy increases. On the other hand, the second peak value P2 of the column region 24 decreases as the implantation energy increases. This is because as the implantation energy increases, trivalent elements are introduced into a deeper region, and the p-type impurity concentration in this deeper region increases.

[0178] On the contrary, the depth position of the upper end portion of the column region 24 relative to the bottom wall of the trench structure 20 decreases as the implantation energy decreases. The thicknesses of the second increasing portion 25, the second peak portion 26, the second slow portion 27, and the second decreasing portion 28 decrease as the implantation energy decreases. On the other hand, the second peak value P2 of the column region 24 increases as the implantation energy decreases. This is because as the implantation energy decreases, the introduction of trivalent elements is hindered in a shallower region.

[0179] In the case of the column region 24, since trivalent elements are introduced into the semiconductor layer 7 instead of pentavalent elements, even if the same process conditions as those of the high-concentration region 15 are applied, it is necessary to pay attention to the fact that the concentration distribution and thickness (depth) of the column region 24 are different from those of the high-concentration region 15. Therefore, in order to achieve an appropriate charge balance, it is preferable to separately set the process conditions for the column region 24 and the high-concentration region 15.

[0180] The SiC semiconductor device 1 includes a plurality of n-type drift regions 29 formed in the semiconductor layer 7. Each of the plurality of drift regions 29 is formed by a region in the semiconductor layer 7 divided by the plurality of column regions 24. The plurality of drift regions 29 are arranged at intervals along a first arrangement direction Da1 in the semiconductor layer 7 and are each formed in a strip shape extending along a first extension direction De1.

[0181] That is, a plurality of drift regions 29 are arranged at intervals in the m-axis direction (first direction X) and extend in the a-axis direction (second direction Y) of the SiC single crystal. The plurality of drift regions 29 are formed in a stripe shape extending in the a-axis direction (second direction Y). The extending direction of the plurality of drift regions 29 coincides with the deviation direction Do of the semiconductor layer 7.

[0182] In this manner, the plurality of drift regions 29 are formed by a part of the semiconductor layer 7 and a part of the high-concentration region 15. The part of the plurality of drift regions 29 including the high-concentration region 15 is constituted by an n-type channel region extending along the second-axis channel C2.

[0183] The plurality of drift regions 29 and the plurality of column regions 24 together form a plurality of pn junctions having charge balance. The state of having charge balance means that, with respect to the plurality of column regions 24 adjacent to each other, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the plurality of drift regions 29.

[0184] In the present embodiment, a plurality of n-type drift regions 29 (semiconductor layer 7) whose concentration is adjusted by the high-concentration region 15 and a plurality of p-type column regions 24 whose concentration is adjusted form charge balance. The plurality of drift regions 29 form a superstructure with the plurality of column regions 24 in the lower region 7a.

[0185] Refer to Figures 6 to 11 , the SiC semiconductor device 1 includes a plurality of p-type main body regions 30 formed in the surface layer portion of the first main surface 3 (active surface 10). The plurality of main body regions 30 are respectively formed in the regions between the plurality of trench structures 20 adjacent to each other in the surface layer portion of the first main surface 3 (active surface 10). The plurality of main body regions 30 are arranged at intervals along the first extension direction De1 and are connected to the plurality of trench structures 20 located on both sides.

[0186] A plurality of main body regions 30 on one side arranged along the side wall of one side of the trench structure 20 and a plurality of main body regions 30 on the other side arranged along the side wall of the other side of the trench structure 20 are opposed to each other in a one-to-one correspondence. That is, the plurality of main body regions 30 are arranged in a matrix at intervals in the first arrangement direction Da1 and the first extension direction De1 in a plan view.

[0187] The plurality of main body regions 30 have portions exposed from the side walls of the trenches 21 at the open ends of the trenches 21 and are opposed to the buried electrodes 23 with the insulating film 22 interposed therebetween. The plurality of main body regions 30 are formed at intervals from the bottom walls of the plurality of trench structures 20 toward the active surface 10 side and are opposed to the plurality of drift regions 29 in the stacking direction.

[0188] A plurality of outermost main regions 30 located on the peripheral side of the active surface 10 may also be formed at intervals inward from the periphery (first to fourth connection surfaces 12A to 12D) of the active surface 10 in the surface layer portion of the active surface 10. The plurality of outermost main regions 30 are preferably formed at intervals inward from both ends of the plurality of trench structures 20 in the surface layer portion of the active surface 10. Of course, the plurality of outermost main regions 30 may also be located on the peripheral side of the active surface 10 relative to both ends of the plurality of trench structures 20. In this case, the plurality of outermost main regions 30 may also be exposed from the first to fourth connection surfaces 12A to 12D.

[0189] Preferably, the length of the first extension direction De1 of the main region 30 is greater than the pillar width WC. Preferably, the length of the first extension direction De1 of the main region 30 is greater than the pillar pitch PC. Preferably, the length of the first extension direction De1 of the main region 30 is greater than the trench width WT. Preferably, the length of the first extension direction De1 of the main region 30 is greater than the trench pitch PT.

[0190] Of course, the length of the first extension direction De1 of the main region 30 may also be less than the pillar width WC. The length of the first extension direction De1 of the main region 30 may also be less than the pillar pitch PC. The length of the first extension direction De1 of the main region 30 may also be less than the trench width WT. The length of the first extension direction De1 of the main region 30 may also be less than the trench pitch PT.

[0191] The main region 30 is composed of a random region introduced into the surface layer portion of the semiconductor layer 7 by a random implantation method of the semiconductor layer 7. Therefore, different from the pillar region 24, the main region 30 does not have a slow portion such as the first slow portion 18. The main region 30 has a thickness smaller than that of the pillar region 24 in the direction along the second axis channel C2.

[0192] The main region 30 may also have a peak p-type impurity concentration of 1×10 15 cm -3 or more and 1×10 18 cm -3 or less. The p-type impurity concentration (peak) of the main region 30 may also be less than the p-type impurity concentration (peak) of the pillar region 24. Of course, the p-type impurity concentration (peak) of the main region 30 may also be higher than the p-type impurity concentration (peak) of the pillar region 24.

[0193] The p-type impurity concentration of the main region 30 is preferably adjusted by at least one trivalent element. The trivalent element of the main region 30 may be at least one of boron, aluminum, gallium, and indium.

[0194] The SiC semiconductor device 1 includes a plurality of n-type surface drift regions 31 respectively divided in regions between a plurality of body regions 30 in a region between adjacent ones of the plurality of trench structures 20. The plurality of surface drift regions 31 are each constituted by a part of the semiconductor layer 7 and are electrically connected to the plurality of drift regions 29 located directly therebelow. The surface drift region 31 may include a part of the high-concentration region 15.

[0195] The plurality of surface drift regions 31 on one side arranged along the side wall on one side of the trench structure 20 and the plurality of surface drift regions 31 on the other side arranged along the side wall on the other side of the trench structure 20 are opposed to each other in a one-to-one correspondence. That is, the plurality of surface drift regions 31 are arranged in a matrix at intervals in a first arrangement direction Da1 and a first extension direction De1 in a plan view.

[0196] Preferably, the length of the surface drift region 31 in the first extension direction De1 is larger than the pillar width WC. Preferably, the length of the surface drift region 31 in the first extension direction De1 is larger than the pillar pitch PC. Preferably, the length of the surface drift region 31 in the first extension direction De1 is larger than the trench width WT. Preferably, the length of the surface drift region 31 in the first extension direction De1 is larger than the trench pitch PT.

[0197] Of course, the length of the surface drift region 31 in the first extension direction De1 may also be smaller than the pillar width WC. The length of the surface drift region 31 in the first extension direction De1 may also be smaller than the pillar pitch PC. The length of the surface drift region 31 in the first extension direction De1 may also be smaller than the trench width WT. The length of the surface drift region 31 in the first extension direction De1 may also be smaller than the trench pitch PT.

[0198] The SiC semiconductor device 1 includes a plurality of p-type intermediate regions 32 in regions in the semiconductor layer 7 respectively between the bottom walls of the plurality of trench structures 20 and the plurality of pillar regions 24. In this manner, the plurality of intermediate regions 32 are in a region between the bottom wall of one trench structure 20 and the upper end portion of one pillar region 24.

[0199] The plurality of intermediate regions 32 are respectively formed at intervals along the first extension direction De1 (second direction Y) directly below the corresponding trench structures 20. Specifically, the plurality of intermediate regions 32 are arranged at intervals in the first extension direction De1 (second direction Y) in such a manner that they are located on an imaginary straight line connecting the plurality of body regions 30 in the first arrangement direction Da1 (first direction X) in a plan view.

[0200] That is, with respect to the trench structures 20 of one side and the other side, a plurality of intermediate regions 32 on one side located directly below the trench structure 20 of one side are formed at intervals in a first arrangement direction Da1 (first direction X) from a plurality of intermediate regions 32 on the other side located directly below the trench structure 20 of the other side.

[0201] A plurality of intermediate regions 32 on one side face a plurality of intermediate regions 32 on the other side in a one-to-one correspondence in the first arrangement direction Da1 (first direction X) with a part of the semiconductor layer 7 (a part of the high-concentration region 15) therebetween. Of course, a plurality of intermediate regions 32 on one side may also face a region between a plurality of intermediate regions 32 on the other side in a one-to-one correspondence in the first arrangement direction Da1.

[0202] In a first extension direction De1, each intermediate region 32 preferably has a width smaller than the length of the main body region 30. The width of each intermediate region 32 may also be greater than the pillar width WC. The width of each intermediate region 32 may also be greater than the pillar pitch PC. Of course, the width of each intermediate region 32 may also be smaller than the pillar width WC. The width of each intermediate region 32 may also be smaller than the pillar pitch PC.

[0203] The width of each intermediate region 32 may also be greater than the trench width WT. The width of each intermediate region 32 may also be greater than the trench pitch PT. Of course, the width of each intermediate region 32 may also be smaller than the trench width WT. The width of each intermediate region 32 may also be smaller than the trench pitch PT.

[0204] The plurality of intermediate regions 32 are respectively connected to the bottom wall of the trench structure 20 and the upper end portions of the pillar regions 24. The plurality of intermediate regions 32 also have portions that extend from the region directly below the trench structure 20 to both sides of the trench structure 20 and extend along the side walls of the trench structure 20.

[0205] The plurality of intermediate regions 32 are electrically connected to the main body region 30 in the surface layer portion of the first main surface 3 (active surface 10). That is to say, the plurality of intermediate regions 32 electrically connect the plurality of pillar regions 24 to the main body region 30. Therefore, the electrically floating state of the plurality of pillar regions 24 is suppressed.

[0206] The plurality of intermediate regions 32 may also extend in the vertical direction Z within the main body region 30 along the side walls of the trench structure 20 and be exposed from the first main surface 3. In this case, the plurality of intermediate regions 32 may also have portions that extend in the horizontal direction in the surface layer portion of the first main surface 3. The intermediate regions 32 of the plurality of trench structures 20 that are adjacent in the first arrangement direction Da1 (first direction X) are formed at intervals in the surface layer portion of the first main surface 3. Of course, the adjacent intermediate regions 32 may also be connected to each other in the surface layer portion of the first main surface 3.

[0207] A plurality of intermediate regions 32 mitigate the electric field with respect to the trench structure 20. The plurality of intermediate regions 32 do not necessarily need to form charge balance together with the plurality of drift regions 29. Of course, the plurality of intermediate regions 32 may also form a plurality of pn junctions having charge balance together with the plurality of drift regions 29.

[0208] The plurality of intermediate regions 32 are composed of random regions introduced into the surface portions of the plurality of drift regions 29 by a random implantation method of the semiconductor layer 7. That is, the plurality of intermediate regions 32 have a thickness smaller than the thickness of the plurality of column regions 24 in the direction along the second-axis channel C2. In addition, the plurality of intermediate regions 32 do not have a second slow portion 27 having a thickness of 0.5 μm or more in the second-axis channel C2 bidirection.

[0209] The plurality of intermediate regions 32 may also have a p-type impurity concentration of 1×10 15 cm -3 or more and 1×10 18 cm -3 or less as a peak value. The intermediate region 32 may also have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the main body region 30.

[0210] The p-type impurity concentration (peak value) of the intermediate region 32 may also be smaller than the p-type impurity concentration (peak value) of the main body region 30. The p-type impurity concentration (peak value) of the intermediate region 32 may also be higher than the p-type impurity concentration (peak value) of the column region 24. The p-type impurity concentration (peak value) of the intermediate region 32 may also be smaller than the p-type impurity concentration (peak value) of the column region 24.

[0211] The p-type impurity concentration of the intermediate region 32 is preferably adjusted by at least one trivalent element. The trivalent element of the intermediate region 32 may be the same type as the trivalent element of the column region 24, or may be a different type from the trivalent element of the column region 24. The trivalent element of the intermediate region 32 may be at least one of boron, aluminum, gallium, and indium.

[0212] The SiC semiconductor device 1 includes a plurality of source regions 33 formed on both sides of the plurality of trench structures 20 in the surface portion of the first main surface 3 (active surface 10). The plurality of source regions 33 are respectively formed in the surface portions of the plurality of main body regions 30. In this manner, two source regions 33 are formed separately in the surface portion of each main body region 30.

[0213] The plurality of source regions 33 have an n-type impurity concentration (peak value) higher than that of the semiconductor layer 7. The n-type impurity concentration of the plurality of source regions 33 is higher than the n-type impurity concentration of the high-concentration region 15. The plurality of source regions 33 may also have a concentration of 1×10 18 cm -3 or more and 1×10 21 cm -3The following n-type impurity concentration is taken as the peak value.

[0214] A plurality of source regions 33 are formed at intervals in a first extending direction De1 in a surface layer portion of each body region 30. Specifically, one source region 33 is formed in the surface layer portion on one end side of the body region 30, and the other source region 33 is formed at an interval from the one source region 33 in the first extending direction De1 in the surface layer portion on the other end side of the body region 30. The plurality of source regions 33 are connected to a plurality of trench structures 20 located on both sides.

[0215] One plurality of source regions 33 arranged along a side wall on one side of the trench structure 20 and the other plurality of source regions 33 arranged along a side wall on the other side of the trench structure 20 are opposed to each other in a one-to-one correspondence. That is, the plurality of source regions 33 are arranged in a matrix at intervals in a first arrangement direction Da1 and a first extending direction De1 in a plan view.

[0216] The plurality of source regions 33 have portions exposed from the side walls of the trench 21 at an open end of the trench 21, and are opposed to the buried electrode 23 with an insulating film 22 interposed therebetween. The plurality of source regions 33 are formed at intervals from the bottom of the body region 30 toward the active surface 10 side, and are opposed to the drift region 29 (semiconductor layer 7 / high concentration region 15) directly below with a part of the body region 30 interposed therebetween in a stacking direction.

[0217] One source region 33 is formed at intervals from one end portion of each body region 30 toward the inside, and together with the corresponding surface layer drift region 31 in the surface layer portion on one end side of each body region 30, divides a channel Ch that forms a current path. The other source region 33 is formed at intervals from the other end portion of each body region 30 toward the inside, and together with the corresponding surface layer drift region 31 in the surface layer portion on the other end side of each body region 30, divides a channel Ch that forms a current path.

[0218] That is, the plurality of source regions 33 together with the plurality of surface layer drift regions 31 divide a plurality of channels Ch extending in a horizontal direction (first arrangement direction Da1 and first extending direction De1). One plurality of channels Ch divided along a side wall on one side of the trench structure 20 and the other plurality of channels Ch arranged along a side wall on the other side of the trench structure 20 are opposed to each other in a one-to-one correspondence. That is, the plurality of channels Ch are divided into a matrix at intervals in a first arrangement direction Da1 and a first extending direction De1 in a plan view.

[0219] The SiC semiconductor device 1 includes a plurality of contact regions 34 formed in a region between a plurality of trench structures 20 in a surface layer portion of a first main surface 3 (active surface 10). The plurality of contact regions 34 are respectively formed in surface layer portions of a plurality of main regions 30. In this manner, two contact regions 34 are formed in the surface layer portion of each main region 30.

[0220] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the main region 30. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of column regions 24. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of intermediate regions 32. The plurality of contact regions 34 may also have a p-type impurity concentration of 1×10 18 cm -3 or more and 1×10 21 cm -3 or less as a peak value.

[0221] The plurality of contact regions 34 are respectively formed in a region between adjacent plurality of source regions 33 in surface layer portions of the plurality of main regions 30. The plurality of contact regions 34 are electrically connected to the plurality of intermediate regions 32 via the main regions 30. That is, the plurality of contact regions 34 are electrically connected to the plurality of column regions 24 via the plurality of intermediate regions 32.

[0222] The plurality of contact regions 34 are connected to the plurality of trench structures 20 located on both sides. The plurality of contact regions 34 on one side arranged along a side wall of one side of the trench structure 20 and the plurality of contact regions 34 on the other side arranged along a side wall of the other side of the trench structure 20 are opposed to each other in a one-to-one correspondence. That is, the plurality of contact regions 34 are arranged in a matrix at intervals in a first arrangement direction Da1 and a first extension direction De1 in a plan view.

[0223] The plurality of contact regions 34 are preferably located on an imaginary straight line connecting the plurality of intermediate regions 32 in the first arrangement direction Da1 (first direction X) in a plan view. In this case, the plurality of contact regions 34 may also be connected to the intermediate regions 32 within the main region 30. Of course, the plurality of contact regions 34 may also be offset from the plurality of intermediate regions 32 in the first extension direction De1. In this case, the plurality of contact regions 34 may be connected to the plurality of intermediate regions 32 or may be formed at intervals from the plurality of intermediate regions 32.

[0224] The plurality of contact regions 34 have a portion exposed from the side wall of the trench 21 at an opening end of the trench 21, and are opposed to the buried electrode 23 with an insulating film 22 interposed therebetween. The plurality of contact regions 34 are formed at intervals from the bottom of the main region 30 toward the active surface 10 side, and are opposed to the semiconductor layer 7 (high concentration region 15) with a part of the main region 30 interposed therebetween.

[0225] In this manner, an example of a configuration in which a plurality of contact regions 34 are separately formed from a plurality of intermediate regions 32 is shown. However, the plurality of contact regions 34 may also be formed using a part of the plurality of intermediate regions 32. That is to say, a part of the plurality of intermediate regions 32 located within the main body region 30 may be regarded as the contact regions 34.

[0226] Hereinafter, the structure on the outer peripheral region 9 side is shown. Figure 15 It is a perspective view showing the structure of the outer peripheral region 9. Figure 16 It is a cross-sectional view showing a main part of the outer peripheral region 9. Figure 17 It is a cross-sectional view showing a main part of the outer peripheral region 9.

[0227] The SiC semiconductor device 1 includes a p-type well region 35 formed in the surface layer portion of the outer peripheral surface 11. The well region 35 is formed at intervals from the peripheral edge (first to fourth side surfaces 5A to 5D) of the outer peripheral surface 11 toward the active surface 10 in a plan view, and extends in a band shape along the active surface 10. In this manner, the well region 35 is formed in a ring shape (specifically, a quadrilateral ring shape) surrounding the active surface 10 in a plan view.

[0228] The well region 35 is led out from the surface layer portion of the outer peripheral surface 11 toward the first to fourth connection surfaces 12A to 12D, and extends along the surface layer portions of the first to fourth connection surfaces 12A to 12D. The well region 35 may also be electrically connected to the main body region 30 in the surface layer portion of the active surface 10. The well region 35 may be electrically connected to a plurality of column regions 24.

[0229] The well region 35 is formed at intervals from the lower end of the semiconductor layer 7 toward the outer peripheral surface 11 side, and faces the base layer 6 with a part of the semiconductor layer 7 interposed therebetween. Specifically, the well region 35 is formed at intervals from the bottom of the high-concentration region 15 toward the outer peripheral surface 11 side, and is located on the bottom side of the high-concentration region 15 with respect to the bottom wall of the trench structure 20. The well region 35 forms a pn junction with the semiconductor layer 7 (high-concentration region 15).

[0230] The well region 35 is composed of a random region introduced into the surface layer portion of the semiconductor layer 7 by a random implantation method for the semiconductor layer 7. The well region 35 has a thickness smaller than that of the high-concentration region 15 in the direction along the second axis channel C2. In addition, the thickness of the well region 35 is smaller than the thickness of the column region 24.

[0231] Unlike the column region 24, the well region 35 does not have a slow portion having a thickness of 0.5 μm or more. The well region 35 may also have 1×10 15 cm -3 or more and 1×10 18 cm -3The following p-type impurity concentration is taken as the peak value. The well region 35 has a p-type impurity concentration lower than that of the contact region 34.

[0232] The p-type impurity concentration of the well region 35 may also be higher than that of the main body region 30. Of course, the p-type impurity concentration of the well region 35 may also be lower than that of the main body region 30. The p-type impurity concentration of the well region 35 may also be approximately equal to the p-type impurity concentration of the intermediate region 32. Of course, the p-type impurity concentration of the well region 35 may be higher than or lower than the p-type impurity concentration of the intermediate region 32.

[0233] The p-type impurity concentration of the well region 35 is preferably adjusted by at least one trivalent element. The trivalent element of the well region 35 may be the same type as the trivalent element of the column region 24 or may be a different type from the trivalent element of the column region 24. The trivalent element of the well region 35 may be at least one of boron, aluminum, gallium, and indium.

[0234] The SiC semiconductor device 1 includes at least one (preferably 2 or more and 20 or less) p-type field region 36 formed in the surface layer portion of the outer peripheral surface 11 (the first main surface 3) in the outer peripheral region 9. The number of the plurality of field regions 36 is typically 4 or more and 8 or less. The plurality of field regions 36 are formed in an electrically floating state to relieve the electric field in the chip 2 at the peripheral portion of the first main surface 3. The number, width, depth, p-type impurity concentration, etc. of the field regions 36 are arbitrary and can take various values according to the electric field to be relieved.

[0235] In this manner, the plurality of field regions 36 are arranged at intervals from the periphery of the active surface 10 (the first to fourth connection surfaces 12A to 12D) and the periphery of the chip 2 (the first to fourth side surfaces 5A to 5D). Specifically, the plurality of field regions 36 are arranged at intervals from the well region 35 toward the peripheral side of the outer peripheral surface 11.

[0236] The plurality of field regions 36 are formed in a strip shape extending along the active region 8 in a plan view. Each of the plurality of field regions 36 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. In this manner, the plurality of field regions 36 are formed in a ring shape (specifically, a quadrilateral ring shape) surrounding the active region 8 (i.e., the plurality of column regions 24) in a plan view.

[0237] The plurality of field regions 36 are formed at intervals from the lower end of the semiconductor layer 7 toward the outer peripheral surface 11 side within the semiconductor layer 7, forming a pn junction with the semiconductor layer 7. The plurality of field regions 36 preferably have a bottom portion located on the outer peripheral surface 11 side with respect to the middle portion of the thickness range of the semiconductor layer 7. The plurality of field regions 36 are preferably formed at intervals from the bottom of the high-concentration region 15 toward the outer peripheral surface 11 side within the high-concentration region 7, forming a pn junction with the semiconductor layer 15.

[0238] In this manner, a plurality of field regions 36 are formed to be spaced apart from the plurality of pillar regions 24 on the peripheral side of the chip 2. Therefore, the plurality of field regions 36 do not face the plurality of pillar regions 24 in the stacking direction. The plurality of field regions 36 are located on the bottom side of the semiconductor layer 7 (high-concentration region 15) with respect to the bottom wall of the trench structure 20.

[0239] The bottom of the plurality of field regions 36 may also be located on the bottom side of the semiconductor layer 7 (high-concentration region 15) with respect to the depth position of the upper end portions of the plurality of pillar regions 24. Of course, the bottom of the plurality of field regions 36 may also be located on the bottom wall side of the trench structure 20 with respect to the depth position of the upper end portions of the plurality of pillar regions 24.

[0240] The plurality of field regions 36 are formed of random regions introduced into the surface portion of the semiconductor layer 7 by a random implantation method for the semiconductor layer 7. The plurality of field regions 36 have a thickness smaller than the thickness of the high-concentration region 15 in the direction along the second-axis channel C2. In addition, the thickness of the plurality of field regions 36 is smaller than the thickness of the pillar regions 24.

[0241] Unlike the pillar regions 24 and the like, the plurality of field regions 36 do not have a slow portion having a thickness of 0.5 μm or more. The plurality of field regions 36 may also have a peak p-type impurity concentration of 1×10 15 cm -3 or more and 1×10 18 cm -3 or less. The p-type impurity concentration of the field regions 36 may also be substantially equal to the p-type impurity concentration of the main body region 30. The p-type impurity concentration of the plurality of field regions 36 may also be higher than the p-type impurity concentration of the main body region 30. The p-type impurity concentration of the plurality of field regions 36 may be lower than the p-type impurity concentration of the main body region 30.

[0242] The p-type impurity concentration of the plurality of field regions 36 is preferably adjusted by at least one trivalent element. The trivalent element of the field regions 36 may be the same type as the trivalent element of the pillar regions 24, or may be a different type from the trivalent element of the pillar regions 24. The trivalent element of the field regions 36 may be at least one of boron, aluminum, gallium, and indium.

[0243] The plurality of field regions 36 preferably have a width different from the pillar width WC of the pillar regions 24. That is, the electric field relaxation effect brought about by the plurality of field regions 36 is preferably adjusted by being separated from the plurality of pillar regions 24. The width of the plurality of field regions 36 is particularly preferably greater than the pillar width WC. Of course, the width of the plurality of field regions 36 may also be smaller than the pillar width WC. In addition, the width of the pillar regions 24 may also be substantially equal to the pillar width WC.

[0244] The plurality of field regions 36 are preferably formed at a pitch different from the pillar pitch PC of the pillar regions 24. The pitch of the plurality of field regions 36 is particularly preferably greater than the pillar pitch PC. The pitch of the plurality of field regions 36 may be less than the pillar pitch PC. The pitch of the plurality of field regions 36 may also be approximately equal to the pillar pitch PC.

[0245] Referring again to Figures 5 to 11 , the SiC semiconductor device 1 includes a plurality of planar electrode type gate structures 37 disposed on the first main surface 3 (active surface 10). The gate structures 37 may also be referred to as "planar gate structures". A potential (second potential) different from the potential (first potential) applied to the trench structure 20 is applied to the plurality of gate structures 37. Specifically, a gate potential as a control potential is applied to the plurality of gate structures 37.

[0246] The plurality of gate structures 37 are arranged at intervals inward from the periphery (first to fourth connection surfaces 12A to 12D) of the active surface 10 in the active region 8. The plurality of gate structures 37 are arranged at intervals on the first main surface 3 so as to overlap the plurality of channels Ch in the stacking direction, and control the inversion and non-inversion of the plurality of channels Ch in the body region 30 in response to the gate potential.

[0247] Specifically, the plurality of gate structures 37 are arranged at intervals in a second arrangement direction Da2 other than the first arrangement direction Da1, and are each formed in a strip shape extending in a second extension direction De2 other than the first extension direction De1. In this way, the plurality of gate structures 37 are arranged at intervals in the second arrangement direction Da2 orthogonal to the first arrangement direction Da1, and extend in the second extension direction De2 orthogonal to the first extension direction De1.

[0248] That is, the plurality of gate structures 37 are arranged at intervals in the a-axis direction (second direction Y) of the SiC single crystal, and extend in the m-axis direction (first direction X) of the SiC single crystal. In addition, the plurality of gate structures 37 are arranged in a striped shape extending along the m-axis direction (first direction X). The second extension direction De2 is orthogonal to the deviation direction Do of the SiC single crystal.

[0249] The plurality of gate structures 37 cross (specifically, are orthogonal to) the plurality of trench structures 20, the plurality of pillar regions 24, and the plurality of drift regions 29 in a plan view, and cover the plurality of channels Ch adjacent in the first arrangement direction Da1 (second extension direction De2). When observing one trench structure 20, the plurality of gate structures 37 cross a plurality of portions of one trench structure 20. The plurality of gate structures 37 are electrically insulated from the plurality of trench structures 20 at the crossing portions with the plurality of trench structures 20.

[0250] A plurality of gate structures 37 are in the region between two adjacent trench structures 20, respectively straddling two main body regions 30 adjacent in the first extension direction De1 (second arrangement direction Da2), and respectively covering a corresponding surface layer drift region 31. The plurality of gate structures 37 partially cover the source region 33 on one side formed in one of the main body regions 30 and partially cover the source region 33 on the other side formed in the other main body region 30. The plurality of gate structures 37 expose a plurality of contact regions 34.

[0251] In this manner, the plurality of gate structures 37 are arranged offset from the imaginary straight line connecting the plurality of intermediate regions 32 in the first arrangement direction Da1 (first direction X) toward the first extension direction De1 (second arrangement direction Da2) in a top view. Therefore, the plurality of gate structures 37 are located in the region between the plurality of intermediate regions 32 in a top view. Of course, the plurality of gate structures 37 may also have a portion located on the imaginary straight line connecting the plurality of intermediate regions 32 in the first arrangement direction Da1 (first direction X).

[0252] The gate structure 37 has a gate width WG in the second arrangement direction Da2. The gate width WG is preferably greater than the pillar width WC. The gate width WG is preferably greater than the pillar pitch PC. The gate width WG is preferably greater than the trench width WT. The gate width WG is preferably greater than the trench pitch PT. Of course, the gate width WG may also be less than the pillar width WC. The gate width WG may also be less than the pillar pitch PC. The gate width WG may also be less than the trench width WT. The gate width WG may also be less than the trench pitch PT.

[0253] The plurality of gate structures 37 are arranged at a gate pitch PG in the second arrangement direction Da2. The gate pitch PG may be greater than the pillar width WC. The gate pitch PG may also be less than the pillar width WC. The gate pitch PG may be less than the pillar thickness TC. The gate pitch PG may be greater than the pillar thickness TC. The gate pitch PG may also be greater than the pillar pitch PC. The gate pitch PG may also be less than the pillar pitch PC.

[0254] The gate pitch PG may also be greater than the trench width WT. The gate pitch PG may also be less than the trench width WT. The gate pitch PG may also be less than the trench depth DT. The gate pitch PG may be greater than the trench depth DT. The gate pitch PG may be greater than the trench pitch PT. The gate pitch PG may also be less than the trench pitch PT.

[0255] The gate pitch PG is less than the first thickness T1. The gate pitch PG may also be less than the second thickness T2. The gate pitch PG may also be greater than the second thickness T2. The gate pitch PG may also be less than the thickness of the high-concentration region 15. The gate pitch PG may also be greater than the thickness of the high-concentration region 15.

[0256] Each gate structure 37 has a stacked structure including a gate insulating film 38 and a gate electrode 39 stacked in order from the side of the first main surface 3. The gate insulating film 38 has a portion covering a part of the first main surface 3 in a film form and a portion covering a plurality of trench structures 20 in a film form. The gate insulating film 38 covers the wall surface (side wall) of the trench 21, the insulating film 22, and the buried electrode 23 in a film form within the trench 21.

[0257] The gate insulating film 38 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this manner, the gate insulating film 38 has a single-layer structure composed of a silicon oxide film. In this case, the portion of the gate insulating film 38 covering the first main surface 3 may include silicon oxide containing carbon. On the other hand, the portion of the gate insulating film 38 covering the buried electrode 23 may include a silicon oxide film made of an oxide of the buried electrode 23 (polysilicon oxide).

[0258] The gate electrode 39 covers the gate insulating film 38 in a film form. Specifically, the gate electrode 39 has a portion covering a part of the first main surface 3 in a film form with the gate insulating film 38 interposed therebetween and a portion covering a plurality of trench structures ......

[0259] The gate electrode 39 faces a plurality of body regions 30, a plurality of surface drift regions 31, a plurality of source regions 33, and a plurality of channels Ch on the first main surface 3 with the gate insulating film 38 interposed therebetween. In the trench 21, the gate electrode 39 covers the wall surface (side wall) of the trench 21, the insulating film 22, and the buried electrode 23 in a film form with the gate insulating film 38 interposed therebetween.

[0260] The gate electrode 39 is electrically insulated from the buried electrode 23 through the gate insulating film 38 in the trench 21. The gate electrode 39 may also include p-type or n-type conductive polysilicon. The conductivity type of the gate electrode 39 may be the same as the conductivity type of the buried electrode 23. The conductivity type of the gate electrode 39 may be different from the conductivity type of the buried electrode 23. In the stacking direction, the thickness of the gate electrode 39 is preferably smaller than the thickness of the buried electrode 23.

[0261] When a gate potential is applied to the gate electrode 39, a plurality of channels Ch directly below the gate electrode 39 become in a conducting state. Thereby, a current path is formed from a plurality of drift regions 29 through a plurality of surface drift regions 31 to a plurality of source regions 33.

[0262] That is, in a region below the plurality of trench structures 20, a current path extending in the vertical direction Z along the plurality of drift regions 29 is formed. Further, in a region between the plurality of trench structures 20, a current path extending in the vertical direction Z along the plurality of trench structures 20 and a plurality of current paths extending in the horizontal direction in the plurality of channels Ch (regions between the plurality of surface drift regions 31 and the plurality of source regions 33) are formed.

[0263] The SiC semiconductor device 1 includes an interlayer insulating film 41 covering the first main surface 3. The interlayer insulating film 41 may also be referred to as an "insulating film", an "interlayer film", an "intermediate insulating film", etc. In this manner, the interlayer insulating film 41 has a stacked structure including a first insulating film 42 and a second insulating film 43. The first insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first insulating film 42 particularly preferably includes a silicon oxide film formed of an oxide of the chip 2 (semiconductor layer 7).

[0264] The first insulating film 42 selectively covers the first main surface 3 in the active region 8 and the peripheral region 9. Specifically, the first insulating film 42 selectively covers the active surface 10, the peripheral surface 11, and the first to fourth connection surfaces 12A to 12D. The first insulating film 42 is connected to the insulating film 22 and the gate insulating film 38 on the active surface 10, exposing the buried electrode 23 and the gate electrode 39.

[0265] The first insulating film 42 covers the well region 35 and the plurality of field regions 36 on the peripheral surface 11. In this manner, the first insulating film 42 is connected to the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 42 may also be formed at intervals from the periphery of the peripheral surface 11 inward, exposing the semiconductor layer 7 from the peripheral edge portion of the peripheral surface 11. The first insulating film 42 covers the body region 30 and the well region 35 on the first to fourth connection surfaces 12A to 12D.

[0266] The second insulating film 43 is stacked on the first insulating film 42. The second insulating film 43 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 41 preferably includes a silicon oxide film. The second insulating film 43 covers the first main surface 3 with the first insulating film 42 interposed therebetween in the active region 8 and the peripheral region 9. Specifically, the second insulating film 43 selectively covers the active surface 10, the peripheral surface 11, and the first to fourth connection surfaces 12A to 12D with the first insulating film 42 interposed therebetween.

[0267] The second insulating film 43 covers the multiple trench structures 20 (buried electrodes 23) and the multiple gate structures 37 (gate electrodes 39) in the active region 8. The second insulating film 43 covers the well region 35 and the multiple field regions 36 in the peripheral region 9 via the first insulating film 42. In this embodiment, the second insulating film 43 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 43 can also be formed at intervals inward from the periphery of the peripheral surface 11, so that the periphery of the first principal surface 3 is exposed together with the first insulating film 42.

[0268] The SiC semiconductor device 1 includes a plurality of contact openings 44 formed in the interlayer insulating film 41. The plurality of contact openings 44 include a plurality of contact openings 44 (not shown) that expose the plurality of gate structures 37 (gate electrodes 39) and a plurality of contact openings 44 that expose the plurality of trench structures 20 (buried electrodes 23) and the plurality of source regions 33.

[0269] A plurality of contact openings 44 for the trench structures 20 are formed in regions between adjacent gate structures 37, exposing the trench structures 20, the source regions 33, and the contact regions 34. Specifically, the contact openings 44 are arranged at intervals in the second arrangement direction Da2 so as to be located between the gate structures 37, and are each formed in a strip shape extending in the second extension direction De2.

[0270] Thus, the contact openings 44 expose the trench structures 20 (buried electrodes 23), the source regions 33, and the contact regions 34 along the second extension direction De2. In this manner, the contact openings 44 also expose portions of the intermediate regions 32 exposed from the first main surface 3.

[0271] SiC semiconductor device 1 includes a sidewall structure 45 disposed within interlayer insulating film 41 so as to cover at least one of first to fourth connecting surfaces 12A to 12D. Sidewall structure 45 is disposed on first insulating film 42 and covered by second insulating film 43. Sidewall structure 45 mitigates the step formed between active surface 10 and outer peripheral surface 11.

[0272] Sidewall structure 45 is formed in a strip shape extending along at least one of first to fourth connecting surfaces 12A to 12D. In this embodiment, sidewall structure 45 is formed in an annular shape (specifically, a four-sided annular shape) extending along first to fourth connecting surfaces 12A to 12D so as to surround active surface 10 when viewed from above.

[0273] The sidewall structure 45 may also have a portion that extends in a film shape along the outer peripheral surface 11 and a portion that extends in a film shape along the first to fourth connection surfaces 12A to 12D. In this manner, the sidewall structure 45 is formed at an interval from the innermost field region 36 toward the active surface 10, and faces the well region 35 with the first insulating film 42 interposed therebetween in the horizontal direction and the stacking direction. The sidewall structure 45 may also face the main body region 30 with the first insulating film 42 interposed therebetween.

[0274] Refer to Figure 1 , the SiC semiconductor device 1 includes a gate pad 50 disposed on the interlayer insulating film 41. The gate pad 50 is an electrode to which a gate potential is externally applied. The gate pad 50 may also be referred to as a "gate pad electrode", a "first pad electrode", etc. The gate pad 50 may also have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in order from the side of the interlayer insulating film 41.

[0275] In this manner, the gate pad 50 is disposed on a portion of the interlayer insulating film 41 that covers the active region 8. Specifically, the gate pad 50 is disposed on the active surface 10 at an interval from the outer peripheral surface 11 in a plan view. The gate pad 50 is disposed in a region at the center of a side (the second connection surface 12B in this manner) of the active surface 10 that is close in a plan view.

[0276] Of course, the gate pad 50 may also be disposed in a region along any one of the central portions of the first to fourth connection surfaces 12A to 12D. Of course, the gate pad 50 may also be disposed at any corner of the active surface 10 in a plan view. In addition, the gate pad 50 may also be disposed at the center of the active surface 10 in a plan view. In this manner, the gate pad 50 is formed in a quadrilateral shape in a plan view.

[0277] The SiC semiconductor device 1 includes at least one (a plurality in this manner) gate wiring 51 led out from the gate pad 50 to the interlayer insulating film 41. The gate wiring 51 may also be referred to as a "wiring", a "wiring electrode", etc. In this manner, the plurality of gate wirings 51 are disposed on the active surface 10 at an interval from the outer peripheral surface 11 in a plan view.

[0278] The plurality of gate wirings 51 may also have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in order from the side of the interlayer insulating film 41. In this manner, the plurality of gate wirings 51 include a first gate wiring 51A and a second gate wiring 51B.

[0279] The first gate wiring 51A extends linearly along the periphery of the active surface 10 in a manner that it is led out from the gate pad 50 toward the first connection surface 12A side and intersects (specifically, is orthogonal to) a part (specifically, one end portion) of the plurality of gate structures 37. The first gate wiring 51A penetrates the interlayer insulating film 41 through a plurality of contact openings 44 and is electrically connected to one end portion of the plurality of gate structures 37 (gate electrodes 39).

[0280] The second gate wiring 51B extends linearly along the periphery of the active surface 10 in a manner that it is led out from the gate pad 50 toward the third connection surface 12C side and intersects (specifically, is orthogonal to) a part (specifically, the other end portion) of the plurality of gate structures 37. The second gate wiring 51B penetrates the interlayer insulating film 41 through a plurality of contact openings 44 and is electrically connected to the other end portion of the plurality of gate structures 37 (gate electrodes 39).

[0281] The SiC semiconductor device 1 includes a source pad 52 disposed on the interlayer insulating film 41 at an interval from the gate pad 50 and the gate wiring 51. The source pad 52 is an electrode to which a source potential is externally applied. The source pad 52 may also be referred to as a "source pad electrode", a "second pad electrode", etc. The source pad 52 may also have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in order from the interlayer insulating film 41 side.

[0282] In this manner, the source pad 52 is disposed on the active surface 10 at an interval from the outer peripheral surface 11 in a plan view. In this manner, the source pad 52 is formed in a polygonal shape having a concave portion recessed along the gate pad 50 in a plan view. Of course, the source pad 52 may also be formed in a quadrilateral shape in a plan view.

[0283] The source pad 52 faces the plurality of gate structures 37 with the interlayer insulating film 41 therebetween and is electrically insulated from the plurality of gate structures 37. The source pad 52 penetrates the interlayer insulating film 41 through a plurality of contact openings 44 and is electrically connected to the plurality of trench structures 20, the plurality of body regions 30, the plurality of intermediate regions 32, the plurality of source regions 33, and the plurality of contact regions 34. That is, the source pad 52 is electrically connected to the plurality of pillar regions 24 via the body regions 30 and the plurality of intermediate regions 32.

[0284] The SiC semiconductor device 1 includes a drain pad 53 covering the second main surface 4. The drain pad 53 is an electrode to which a drain potential is externally applied. The drain pad 53 may also be referred to as a "drain pad electrode", a "third pad electrode", etc. The drain pad 53 forms an ohmic contact with the base layer 6 exposed from the second main surface 4.

[0285] That is, the drain pad 53 is electrically connected to the plurality of drift regions 29 via the base layer 6. The drain pad 53 may also cover the entire region of the second main surface 4 in a manner connected to the periphery (the first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 53 may also cover the second main surface 4 at intervals from the periphery of the chip 2 so that the peripheral portion of the chip 2 is exposed.

[0286] The breakdown voltage that can be applied between the source pad 52 and the drain pad 53 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value belonging to any one of the ranges of 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or less, and 2500V or more and 3000V or less.

[0287] Figure 18 FIG. is a schematic diagram of a wafer 60 used in the manufacture of the SiC semiconductor device 1. The wafer 60 is a base material of the base layer 6 and includes a SiC single crystal. The wafer 60 is formed in a flat disk shape. Of course, the wafer 60 may also be formed in a flat rectangular parallelepiped shape. The wafer 60 has a first wafer main surface 61 on one side, a second wafer main surface 62 on the other side, and a wafer side surface 63 connecting the first wafer main surface 61 and the second wafer main surface 62.

[0288] The first wafer main surface 61 corresponds to the upper end of the base layer 6, and the second wafer main surface 62 corresponds to the lower end of the base layer 6. The first wafer main surface 61 and the second wafer main surface 62 are formed by the c-plane of the SiC single crystal. The first wafer main surface 61 is formed by the silicon plane of the SiC single crystal, and the second wafer main surface 62 is formed by the carbon plane of the SiC single crystal. The wafer 60 (the first wafer main surface 61 and the second wafer main surface 62) has the aforementioned deviation direction Do and deviation angle θo.

[0289] The wafer 60 has a mark 64 indicating the crystal orientation of the SiC single crystal on the wafer side surface 63. The mark 64 may include either or both of an orientation plane and an orientation notch. The orientation plane is composed of a cut portion that is linear when viewed from above. The orientation notch is composed of a cut portion that is cut into a concave shape (e.g., a pointed shape) toward the central portion of the first wafer main surface 61 when viewed from above.

[0290] The mark 64 may also include either or both of a first orientation plane extending in the m-axis direction and a second orientation plane extending in the a-axis direction. The mark 64 may also include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. In Figure 18 FIG., an orientation plane extending in the m-axis direction (the first direction X) is shown when viewed from above.

[0291] For example, on the wafer 60, a plurality of device regions 65 and a plurality of predetermined cutting lines 66 are set by alignment marks or the like. Each device region 65 is a region corresponding to the SiC semiconductor device 1. The plurality of device regions 65 are each set in a quadrilateral shape when viewed from above.

[0292] In this manner, the plurality of device regions 65 are set in a matrix shape along the first direction X and the second direction Y when viewed from above. The plurality of device regions 65 are respectively set at intervals from the periphery of the first main surface 61 of the wafer 60 toward the inside when viewed from above. The plurality of predetermined cutting lines 66 are set in a lattice shape extending along the first direction X and the second direction Y so as to divide the plurality of device regions 65.

[0293] Figure 19 It is a flowchart showing an example of the manufacturing method of the SiC semiconductor device 1. Figures 20A to 20R It is a cross-sectional perspective view showing an example of the manufacturing method of the SiC semiconductor device 1. Figures 21A to 21B It is a schematic diagram for explaining the measurement process of the crystal orientation. [[ID=1 It is a schematic diagram for explaining the ion implantation process. ​ A cross-sectional perspective view showing a part of the active region 8 of one device region 65.

[0294] First, referring to ​ , the preparation process of the aforementioned wafer 60 is carried out (step S1 of ​ ). Next, referring to ​ , the formation process of the semiconductor layer 7 is carried out (step S2 of ​ ). The semiconductor layer 7 is formed starting from the first main surface 61 (wafer 60) by the epitaxial growth method.

[0295] Next, the measurement process of the crystal orientation of the semiconductor layer 7 is carried out (step S3 of ​ ). The crystal orientation of the semiconductor layer 7 includes the process of measuring the deviation angle θo of the semiconductor layer 7. That is, this process includes the process of measuring the crystal orientation of the second axis channel C2 of the semiconductor layer 7.

[0296] The wafer 60 is cut out from an ingot (SiC ingot) as a crystal block, but there is a risk of error in the deviation angle θo due to process errors. When there is an error in the deviation angle θo of the wafer 60, the deviation angle θo of the semiconductor layer 7 also has a process error, which becomes an obstacle in the channel implantation process. Therefore, it is preferable to obtain data (information) on the deviation angle θo before the channel implantation process and carry out the channel implantation process based on the data (information) of the deviation angle θo.

[0297] Referring to ​, in this process, the crystal orientation of the semiconductor layer 7 is measured by the X-ray diffraction method (so-called ω-2θ measurement method) using the X-ray diffraction apparatus 67. The X-ray diffraction apparatus 67 may also be referred to as an “XRD (X-ray Diffraction) apparatus”.

[0298] The X-ray diffraction apparatus 67 includes an irradiation unit 68 and a detection unit 69, and performs the rocking curve measurement method. The irradiation unit 68 irradiates the upper end of the semiconductor layer 7 (the first wafer main surface 61 of the wafer 60) with incident X-rays L1 having a predetermined incident angle ω. The incident angle ω is defined by the angle between the incident X-rays L1 and the upper end of the semiconductor layer 7 (the first wafer main surface 61 of the wafer 60).

[0299] The detection unit 69 is disposed at an angular position of the diffraction angle 2θ (θ is the Bragg angle) with respect to the irradiation position of the wafer 60 with respect to the incident X-rays L1, and detects the diffracted X-rays L2. The diffraction angle 2θ is the angle between the incident direction of the incident X-rays L1 and the diffraction direction of the diffracted X-rays L2.

[0300] In the rocking curve measurement method, in a state where the diffraction angle 2θ is fixed, the incident angle ω is displaced within a small angular range, and a rocking curve representing the intensity of the diffracted X-rays L2 (intensity distribution of the diffracted X-rays L2) is measured. The rocking curve has the intensity of the diffracted X-rays L2 on the vertical axis and the incident angle ω on the horizontal axis. The incident angle ω is obtained at the angular position where the intensity of the diffracted X-rays L2 takes a peak.

[0301] In this process, the rocking curve measurement method is performed only on one place (for example, the central part) of the upper end of the semiconductor layer 7 (the first wafer main surface 61 of the wafer 60). In the case of assuming an in-plane deviation of the deviation angle θo, the rocking curve measurement method may also be performed on a plurality of portions (for example, the central part and the peripheral part) of the upper end of the semiconductor layer 7 (the first wafer main surface 61 of the wafer 60).

[0302] In ​ , the measurement portions in the case where the rocking curve measurement method is performed on a plurality of portions (here, five portions) of the upper end of the semiconductor layer 7 are shown. The deviation angle θo of the semiconductor layer 7 is set to about 4° here. In ​ , the first to fifth measurement points Po1 to Po5 are shown.

[0303] The first measurement point Po1 is set at the central part of the semiconductor layer 7. The second measurement point Po2 is set at the peripheral part of the semiconductor layer 7 at an interval from the first measurement point Po1 toward one side in the second direction Y (the side opposite to the mark 64). The third measurement point Po3 is set at the peripheral part of the semiconductor layer 7 at an interval from the first measurement point Po1 toward one side in the first direction X (the right side with respect to the mark 64).

[0304] The fourth measurement point Po4 is set at an interval from the first measurement point Po1 to the other side (the side of the marker 64) in the second direction Y on the peripheral portion of the semiconductor layer 7. The fifth measurement point Po5 is set at an interval from the first measurement point Po1 to the other side (left side with respect to the marker 64) in the first direction X on the peripheral portion of the semiconductor layer 7.

[0305] The measurement results of the incident angle ω, diffraction angle 2θ, and deviation angle θo at the first to fifth measurement points Po1 to Po5 are shown in Table 1 below. The deviation angle θo is obtained by the calculation formula of "ω - (2θ × 1 / 2)" using the incident angle ω and the diffraction angle 2θ.

[0306] Table 1

[0307] Table 1

[0308]

[0309] As shown in Table 1, the average value of the deviation angle θo at the first to fifth measurement points Po1 to Po5 is 4.036°, and the standard deviation of these deviation angles θo is 0.009° (±0.01°). From this, it can be seen that the in-plane deviation of the deviation angle θo generated at the upper end of the semiconductor layer 7 (the first main surface 61 of the wafer 60) is extremely small and is at a level that does not pose an obstacle to the channel implantation process.

[0310] Therefore, it can be understood that there is no problem with at least one measurement part with respect to the upper end (the first main surface 61) of the semiconductor layer 7. For example, the measurement part can also be any one or more (all) of the first to fifth measurement points Po1 to Po5. For example, the measurement part can also be only the first measurement point Po1. By reducing the measurement part (the number of measurements), the manufacturing man-hours (manufacturing cost) can be reduced.

[0311] Of course, the deviation angle θo can also be measured at multiple parts of the upper end (the first main surface 61) of the semiconductor layer 7, and the implantation angle corresponding to the in-plane deviation of the deviation angle θo can be set in the channel implantation process. In this case, the manufacturing man-hours (manufacturing cost) increase, but the in-plane error formed in the column region 24 of the semiconductor layer 7 is appropriately suppressed.

[0312] The deviation angle θo of the semiconductor layer 7 is substantially the same as the deviation angle θo of the wafer 60. Therefore, the crystal orientation measurement process can also be performed on the wafer 60 before the formation process of the semiconductor layer 7. However, from the viewpoint of accuracy, it is preferable to perform the crystal orientation measurement process on the semiconductor layer 7.

[0313] Next, referring to ​ , the formation process of the high-concentration region 15 is performed ( ​Step S4). The formation process of the high-concentration region 15 includes a channel implantation process of a pentavalent element (n-type impurity) into the semiconductor layer 7. In this process, the pentavalent element is introduced into the entire region of the semiconductor layer 7. The semiconductor layer 7 (wafer 60) has a deviation angle θo that is inclined at a predetermined angle in a predetermined deviation direction Do with respect to the first wafer main surface 61. The channel implantation process is carried out based on the data (information) of the deviation angle θo.

[0314] Referring to ​ , in the random implantation method, a pentavalent element is introduced into the semiconductor layer 7 at a predetermined implantation energy in a direction intersecting the second-axis channel C2 (deviation angle θo) (also refer to ​ ). For example, in the random implantation method, the pentavalent element is implanted along the vertical direction Z perpendicular to the upper end (first wafer main surface 61) of the semiconductor layer 7.

[0315] In the case of the random implantation method, since the pentavalent element is introduced along the direction where the atomic rows are denser in a plan view, the pentavalent element collides with the atomic rows at a relatively shallow depth position. Therefore, the introduction of the pentavalent element into a relatively deep depth position of the semiconductor layer 7 is hindered by the atomic rows. As a result, a high-concentration region 15 without the first slow portion 18 is formed.

[0316] On the other hand, referring to ​ , in the channel implantation method, the implantation angle of the pentavalent element with respect to the semiconductor layer 7 is controlled, and the pentavalent element is introduced into the semiconductor layer 7 at a predetermined implantation energy along the second-axis channel C2 (in this case, the c-axis of the SiC single crystal) (also refer to ​ ). In this case, either one or both of the implantation angle of the pentavalent element with respect to the semiconductor layer 7 and the inclination angle of the semiconductor layer 7 with respect to the implantation angle of the pentavalent element are adjusted.

[0317] For example, the wafer 60 can also be supported horizontally, and the pentavalent element is introduced into the semiconductor layer 7 along the second-axis channel C2. Of course, the wafer 60 can also be supported in a state where it is inclined by the deviation angle θo with respect to the horizontal, and the pentavalent element is introduced into the semiconductor layer 7 along the second-axis channel C2. Through any combination of the implantation energy of the pentavalent element and the implantation temperature of the pentavalent element, a high-concentration region 15 with a predetermined thickness is formed at a predetermined depth position.

[0318] The implantation energy of the pentavalent element can be 100 keV or more and 2000 keV or less. The implantation energy can have a value belonging to any one of the ranges of 100 keV or more and 250 keV or less, 250 keV or more and 500 keV or less, 500 keV or more and 750 keV or less, 750 keV or more and 1000 keV or less, 1000 keV or more and 1250 keV or less, 1250 keV or more and 1500 keV or less, 1500 keV or more and 1750 keV or less, and 1750 keV or more and 2000 keV or less.

[0319] The implantation temperature of the pentavalent element can be adjusted within the range of 0°C or more and 1500°C or less. The implantation temperature can have a value belonging to any one of the ranges of 0°C or more and 25°C or less, 25°C or more and 50°C or less, 50°C or more and 100°C or less, 100°C or more and 250°C or less, 250°C or more and 500°C or less, 500°C or more and 750°C or less, 750°C or more and 1000°C or less, 1000°C or more and 1250°C or less, and 1250°C or more and 1500°C or less.

[0320] The implantation angle of the pentavalent element is preferably set within the range of ±2° with respect to the axis along the second-axis channel C2 (in this case, the c-axis of the SiC single crystal) as a reference (0°). The implantation angle of the pentavalent element is particularly preferably set within the range of ±1° with respect to the axis along the second-axis channel C2 (in this case, the c-axis of the SiC single crystal) as a reference (0°).

[0321] In the case of the channel implantation method, the pentavalent element is introduced along the second-axis channel C2 where the atomic rows are relatively sparse in a plan view. The pentavalent element travels in the second-axis channel C2 while repeatedly performing small-angle scattering through the channeling effect and reaches a relatively deep depth position in the semiconductor layer 7. That is, in the case of the channel implantation method, the probability of the pentavalent element colliding with the atomic rows of the SiC single crystal is reduced. The pentavalent element is preferably arsenic or antimony.

[0322] After the implantation process of the pentavalent element, the pentavalent element can be electrically activated by an annealing method, and at the same time, lattice defects and the like generated in the semiconductor layer 7 can be repaired. The annealing temperature of the semiconductor layer 7 can be 500°C or more and 2000°C or less.

[0323] Next, referring to ​ , the formation process of the first mask 71 having a predetermined pattern is performed (step S5 of ​ ). The first mask 71 is preferably an organic mask (resist mask). The first mask 71 is disposed on the upper end of the semiconductor layer 7 and has a plurality of first openings 71a that expose the regions where the multi-body regions 30 are to be formed.

[0324] The plurality of first openings 71a are each formed as a strip extending along the second extension direction De2 (the first direction X) and are spaced apart in the second arrangement direction Da2 (the second direction Y). That is, the plurality of first openings 71a have an extension direction that extends in a direction orthogonal to the deviation direction Do when viewed from above.

[0325] Next, a step of forming the plurality of main regions 30 ( ​ step S6) is performed. The step of forming the plurality of main regions 30 includes a step of randomly implanting a trivalent element (p-type impurity) into the semiconductor layer 7. For example, in the random implantation method, the trivalent element is implanted in the vertical direction Z perpendicular to the upper end (the first wafer main surface 61) of the semiconductor layer 7 via the plurality of first openings 71a of the first mask 71. As a result, the plurality of main regions 30 are formed in the surface layer portion of the semiconductor layer 7.

[0326] The plurality of main regions 30 are each formed as a strip extending along the second extension direction De2 (the first direction X). Of course, the plurality of main regions 30 may also be formed in a matrix shape at intervals in the first direction X and the second direction Y in consideration of the layout of the plurality of trench structures 20 (trenches 21). After the step of forming the plurality of main regions 30, the first mask 71 is removed.

[0327] Next, referring to ​ , a step of forming the plurality of source regions 33 ( ​ step S7) is performed. The plurality of source regions 33 are formed by introducing a pentavalent element into the surface layer portion of the semiconductor layer 7 (the plurality of main regions 30) by a random implantation method via a mask (not shown) having a predetermined layout.

[0328] In addition, a step of forming the plurality of contact regions 34 ( ​ step S8) is performed. The plurality of contact regions 34 are formed by introducing a trivalent element into the surface layer portion of the semiconductor layer 7 (the plurality of main regions 30) by a random implantation method via a mask (not shown) having a predetermined layout. The step of forming the contact regions 34 may also be performed before the step of forming the source regions 33.

[0329] Next, referring to ​ , a step of forming the second mask 72 having a predetermined pattern ( ​ step S9) is performed. The second mask 72 is preferably an inorganic mask (hard mask). The second mask 72 is disposed on the upper end of the semiconductor layer 7 and has a plurality of second openings 72a that expose the regions where the plurality of trenches 21 are to be formed.

[0330] A plurality of second openings 72a are formed at intervals in a first arrangement direction Da1 (first direction X), and are each divided into a strip extending in a first extension direction De1 (second direction Y). That is, the plurality of second openings 72a have an extension direction that extends along a deviation direction Do in a plan view. In addition, the second mask 72 has second openings 72a (not shown) that expose regions where the outer peripheral surface 11 is to be formed. The second openings 72a for the outer peripheral surface 11 are formed in a lattice shape along a plurality of cutting predetermined lines 66.

[0331] Next, a forming step of a plurality of trenches 21 ( ​ step S10) is performed. In the forming step of the trenches 21, unnecessary portions of the semiconductor layer 7 are removed by an etching method via the second mask 72. The etching method can be either a wet etching method or a dry etching method or both.

[0332] The etching method is preferably an RIE (Reactive Ion Etching) method. Thereby, a plurality of trenches 21 are formed at the upper end of the semiconductor layer 7. In addition, an active surface 10, an outer peripheral surface 11, and first to fourth connection surfaces 12A to 12D are formed at the upper end of the semiconductor layer 7. After the forming step of the plurality of trenches 21, the second mask 72 is removed.

[0333] Next, referring to ​ , a forming step of a third mask 73 having a predetermined pattern ( ​ step S11) is performed. The third mask 73 is preferably an organic mask (resist mask). The third mask 73 is disposed on the upper end of the semiconductor layer 7 and has a plurality of third openings 73a that expose the plurality of trenches 21 in a one-to-one correspondence.

[0334] The plurality of third openings 73a are formed at intervals in a first arrangement direction Da1 (first direction X), and are each divided into a strip extending in a first extension direction De1 (second direction Y). That is, the plurality of third openings 73a have an extension direction that extends along a deviation direction Do in a plan view.

[0335] Next, a forming step of a plurality of column regions 24 ( ​ step S12) is performed. The forming step of the plurality of column regions 24 includes a channel implantation step of a trivalent element (p-type impurity) into the semiconductor layer 7. The trivalent element is introduced into the lower region 7a of the semiconductor layer 7 from the plurality of third openings 73a of the third mask 73 via the bottom walls of the plurality of trenches 21. The channel implantation step is performed based on the data (information) of the deviation angle θo described above.

[0336] In the channel implantation method, the implantation angle of the trivalent element with respect to the semiconductor layer 7 is controlled, and the trivalent element is introduced into the semiconductor layer 7 along the second-axis channel C2 (in this case, the c-axis of the SiC single crystal) with a predetermined implantation energy. In this case, either or both of the implantation angle of the trivalent element with respect to the semiconductor layer 7 and the tilt angle of the semiconductor layer 7 with respect to the implantation angle of the trivalent element are adjusted.

[0337] For example, the wafer 60 can also be horizontally supported, and the trivalent element can be introduced into the semiconductor layer 7 along the second-axis channel C2. Of course, the wafer 60 can also be supported in a state tilted by a deviation angle θo with respect to the horizontal, and the trivalent element can be introduced into the semiconductor layer 7 along the second-axis channel C2. By any combination of the implantation energy of the trivalent element and the implantation temperature of the trivalent element (the temperature of the wafer 60), a plurality of column regions 24 having a predetermined thickness are formed at a predetermined depth position.

[0338] The implantation energy of the trivalent element can be 100 KeV or more and 2000 KeV or less. The implantation energy can have a value belonging to any one of the ranges of 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.

[0339] The implantation energy of the column region 24 can be approximately equal to the implantation energy of the high-concentration region 15, or can be different from the implantation energy of the high-concentration region 15. The implantation energy of the column region 24 can be equal to or higher than the implantation energy of the high-concentration region 15. The implantation energy of the column region 24 can be less than the implantation energy of the high-concentration region 15.

[0340] The implantation temperature of the trivalent element can be adjusted within the range of 0 °C or more and 1500 °C or less. The implantation temperature can have a value belonging to any one of the ranges of 0 °C or more and 25 °C or less, 25 °C or more and 50 °C or less, 50 °C or more and 100 °C or less, 100 °C or more and 250 °C or less, 250 °C or more and 500 °C or less, 500 °C or more and 750 °C or less, 750 °C or more and 1000 °C or less, 1000 °C or more and 1250 °C or less, and 1250 °C or more and 1500 °C or less.

[0341] The implantation temperature of the column region 24 may be approximately equal to the implantation temperature of the high-concentration region 15, or may be different from the implantation temperature of the high-concentration region 15. The implantation temperature of the column region 24 may also be higher than the implantation temperature of the high-concentration region 15. The implantation temperature of the column region 24 may be lower than the implantation temperature of the high-concentration region 15.

[0342] The implantation angle of the trivalent element is preferably set within a range of ±2° with respect to the axis along the second-axis channel C2 (in this case, the c-axis of the SiC single crystal) as a reference (0°). The implantation angle of the trivalent element is particularly preferably set within a range of ±1° with respect to the axis along the second-axis channel C2 (in this case, the c-axis of the SiC single crystal) as a reference (0°).

[0343] In the case of the channel implantation method, the trivalent element is introduced along the second-axis channel C2 where the atomic rows are relatively sparse in a plan view. The trivalent element travels in the second-axis channel C2 while repeatedly performing small-angle scattering through the channeling effect and reaches a relatively deep depth position in the semiconductor layer 7. That is, in the case of the channel implantation method, the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.

[0344] At this time, it is preferable to introduce a trivalent element belonging to a heavy element heavier than carbon into the semiconductor layer 7. That is, the trivalent element is preferably a trivalent element other than boron (at least one of aluminum, gallium, and indium). The trivalent element is aluminum in this case.

[0345] The plurality of third openings 73a have an extending direction (first extending direction De1) extending along the deviation direction Do, and the implantation angle of the trivalent element is inclined toward the deviation direction Do. Therefore, in a cross-sectional view orthogonal to the extending direction, the trivalent element is introduced into the semiconductor layer 7 substantially perpendicularly with respect to the bottom wall of the trench 21 through the plurality of third openings 73a.

[0346] Thereby, it is suppressed that the plurality of column regions 24 are formed in the semiconductor layer 7 in an inclined posture. In addition, it is suppressed that the wall surfaces of the plurality of third openings 73a become a shield for the incident path of the trivalent element. Thereby, the process error of the plurality of column regions 24 caused by the shielding of the wall surfaces of the plurality of third openings 73a is suppressed. Therefore, the accuracy of charge balance is improved.

[0347] After the implantation process of the trivalent element, the trivalent element can be electrically activated by an annealing method, and at the same time, lattice defects and the like generated in the semiconductor layer 7 can be repaired. The annealing temperature of the semiconductor layer 7 may be 500°C or higher and 2000°C or lower. Thereby, while forming the plurality of column regions 24 and the plurality of drift regions 29, a superstructure is formed.

[0348] The annealing method for the column region 24 can also serve as the annealing method for the high-concentration region 15. In this case, the annealing method for the high-concentration region 15 before the formation process of the column region 24 can also be omitted. Refer to​ , after the process of forming the plurality of column regions 24, the third mask 73 is removed.

[0349] Next, referring to ​ , the process of forming the fourth mask 74 having a predetermined pattern is performed (step S13 of ​ ). The fourth mask 74 is preferably an organic mask (resist mask). The fourth mask 74 is disposed on the upper end of the semiconductor layer 7 and has a plurality of fourth openings 74a that selectively expose the plurality of trenches 21. The plurality of fourth openings 74a are divided into a matrix at intervals in the first direction X (first arrangement direction Da1) and the second direction Y (first extension direction De1), and a part of the plurality of trenches 21 is respectively exposed.

[0350] Next, the process of forming the plurality of intermediate regions 32 is performed (step S14 of ​ ). The process of forming the plurality of intermediate regions 32 includes a process of introducing a trivalent element into the semiconductor layer 7 at a predetermined implantation energy in a direction intersecting with the second axis channel C2 (deviation angle θo) by a random implantation method via the fourth mask 74. The trivalent element is introduced into the semiconductor layer 7 (high concentration region 15) from the plurality of fourth openings 74a via the wall surfaces (side walls and bottom walls) of the plurality of trenches 21. The trivalent element can be introduced into the semiconductor layer 7 one or more times.

[0351] In the case of introducing the trivalent element multiple times, the trivalent element can be introduced into different depth positions of the semiconductor layer 7 in multiple stages with multiple implantation energies. The trivalent element can also be introduced into the semiconductor layer 7 (high concentration region 15) via the wall surfaces (side walls and bottom walls) of the plurality of trenches 21 by an inclined ion implantation method. Referring to ​ , after the process of forming the plurality of intermediate regions 32, the fourth mask 74 is removed.

[0352] The process of forming the plurality of intermediate regions 32 can also be used as the process of forming the well regions 35. The well regions 35 are formed by introducing a trivalent element into the semiconductor layer 7 (high concentration region 15) from the fourth openings 74a that expose the well regions 35 via the outer peripheral surface 11 and the first to fourth connection surfaces 12A to 12D. Of course, the well regions 35 can also be formed by introducing a trivalent element into the surface layer portion of the semiconductor layer 7 by a random implantation method via a mask different from the fourth mask 74.

[0353] Although specific illustrations are omitted, before the process of forming the well regions 35 or after the process of forming the well regions 35, the process of forming the plurality of field regions 36 is performed. The plurality of field regions 36 are formed by introducing a trivalent element into the surface layer portion of the semiconductor layer 7 by a random implantation method via a mask (not shown) having a predetermined layout.

[0354] Next, referring to​ , perform the step of forming the base insulating film 75 ( ​ step S15). The base insulating film 75 serves as the base for the insulating film 22, the gate insulating film 38, and the first insulating film 42. The base insulating film 75 can be formed by either or both of CVD (Chemical Vapor Deposition) method and oxidation treatment method.

[0355] Typically, the base insulating film 75 is formed by a thermal oxidation treatment method. The portion of the base insulating film 75 covering the wall surfaces of the plurality of trenches 21 is formed as the insulating film 22. The portion of the base insulating film 75 covering the upper end of the semiconductor layer 7 becomes the gate insulating film 38. The portion of the base insulating film 75 covering the regions other than the insulating film 22 and the gate insulating film 38 becomes the first insulating film 42.

[0356] Next, refer to ​ , perform the step of forming the buried electrodes 23 ( ​ step S16). This step includes the step of forming a first base electrode film 76 on the base insulating film 75. In this manner, the first base electrode film 76 includes conductive polysilicon. The first base electrode film 76 backfills the plurality of trenches 21 and covers the upper end of the semiconductor layer 7. The first base electrode film 76 can also be formed by CVD method.

[0357] Next, refer to ​ , remove the unnecessary portions of the first base electrode film 76 by an etching method. Remove the unnecessary portions of the first base electrode film 76 until the base insulating film 75 is exposed. The etching method can be either or both of a wet etching method and a dry etching method. Thereby, a plurality of buried electrodes 23 are respectively buried in the plurality of trenches 21, and a plurality of trench structures 20 are formed.

[0358] Next, refer to ​ , perform the step of forming the gate insulating film 38 ( ​ step S17 in). The gate insulating film 38 can also be formed by either or both of CVD method and oxidation treatment method. The gate insulating film has typically formed by a thermal oxidation treatment method. The gate insulating film 38 covers the electrode surface of the buried electrodes 23 in a film shape and is integrated with the base insulating film 75.

[0359] In the case of precisely controlling the film thickness of the gate insulating film 38, the portion of the base insulating film 75 outside the trench 21 (i.e., the portion covering the upper end of the semiconductor layer 7, the portion covering the embedded electrode 23, etc.) may be removed after the step of forming the embedded electrode 23 and before the step of forming the gate insulating film 38. Then, in the step of forming the gate insulating film 38, the gate insulating film 38 can be formed so as to integrally cover the upper end of the semiconductor layer 7 and the electrode surface of the embedded electrode 23.

[0360] Next, refer to ​ , performing the gate electrode 39 forming step ( ​ This step includes forming a second base electrode film 77 on the insulating film 22. In this embodiment, the second base electrode film 77 includes conductive polysilicon. The second base electrode film 77 covers the upper end of the semiconductor layer 7 and the plurality of trench structures 20 (buried electrodes 23) via the gate insulating film 38. The second base electrode film 77 can also be formed by CVD.

[0361] Next, refer to ​ , a step of forming a fifth mask 78 having a predetermined pattern is performed ( ​ Step S19). The fifth mask 78 is preferably an organic mask (resist mask). The fifth mask 78 is arranged on the second base electrode film 77 so as to cover the area where the multiple gate electrodes 39 are to be formed. The fifth mask 78 has multiple fifth openings 78a that expose the area outside of the fifth openings. The multiple fifth openings 78a are arranged at intervals in the second arrangement direction Da2 (second direction Y) and are each divided into strips extending in the second extension direction De2 (first direction X).

[0362] Next, unnecessary portions of the second base electrode film 77 are removed by etching through the fifth mask 78. The unnecessary portions of the second base electrode film 77 are removed until the gate insulating film 38 is exposed. The etching method may be either wet etching or dry etching, or both. This simultaneously forms a plurality of gate electrodes 39 and a planar electrode-type gate structure 37. After the gate structure 37 is formed, the fifth mask 78 is removed.

[0363] Next, refer to ​ , the second insulating film 43 is formed ( ​ The second insulating film 43 may also be formed by CVD. Thus, the interlayer insulating film 41 including the first insulating film 42 and the second insulating film 43 is formed.

[0364] Next, refer to ​ , a step of forming a sixth mask 79 having a predetermined pattern is performed ( ​Step S21). The sixth mask 79 is preferably an organic mask (resist mask). The sixth mask 79 is disposed on the interlayer insulating film 41 and has a plurality of sixth openings 79a exposing regions where a plurality of contact openings 44 are to be formed. The plurality of sixth openings 79a are arranged at intervals in the second arrangement direction Da2 (second direction Y) in a region between the plurality of gate electrodes 39 and are each divided into a strip extending along the second extension direction De2 (first direction X).

[0365] Next, unnecessary portions of the interlayer insulating film 41 are removed by an etching method via the sixth mask 79. The unnecessary portions of the interlayer insulating film 41 are removed until the upper end of the semiconductor layer 7 is exposed. The etching method can be either a wet etching method or a dry etching method or both. Thus, a plurality of contact openings 44 are formed in the interlayer insulating film 41.

[0366] Next, a process of forming the gate pad 50, the gate wiring 51, and the source pad 52 is performed ( ​ Step S22). The gate pad 50, the gate wiring 51, and the source pad 52 are formed by depositing a metal film on the interlayer insulating film 41 by sputtering and then forming into a predetermined layout by an etching method via a mask (not shown) having a predetermined layout.

[0367] Next, a process of forming the drain pad 53 is performed ( ​ Step S23). The drain pad 53 is formed by depositing a metal film on the second main surface 62 of the wafer by sputtering. Then, the wafer 60 is cut along a plurality of cutting predetermined lines 66 ( ​ Step S24). Through the above processes, a plurality of SiC semiconductor devices 1 are manufactured from one wafer 60.

[0368] Hereinafter, a modified example of the SiC semiconductor device 1 is shown. The features of the modified examples shown below can also be combined and applied. ​ is a cross-sectional perspective view showing a first modified example of the SiC semiconductor device 1. In the aforementioned SiC semiconductor device 1, the first arrangement direction Da1 of the plurality of trench structures 20 is the m-axis direction (first direction X), and the first extension direction De1 of the plurality of trench structures 20 is the a-axis direction (second direction Y).

[0369] In contrast, in the SiC semiconductor device 1 of the first modified example, the first arrangement direction Da1 is the a-axis direction (second direction Y), and the first extension direction De1 is the m-axis direction (first direction X). That is, the plurality of trench structures 20 are each formed as a strip extending in the m-axis direction (first direction X) and are arranged at intervals in the a-axis direction (second direction Y).

[0370] The arrangement directions of the multiple main body regions 30, the arrangement directions of the multiple surface drift regions 31, the arrangement directions of the multiple pillar regions 24, the arrangement directions of the multiple intermediate regions 32, and the arrangement directions of the multiple source regions 33 are changed from the a-axis direction to the m-axis direction according to the layout of the multiple trench structures 20.

[0371] In this case, the extending direction of the multiple pillar regions 24 intersects (specifically, is orthogonal to) the deviation direction Do of the SiC single crystal. Therefore, the multiple pillar regions 24 are inclined by an amount of approximately the deviation angle θo from the vertical axis toward the deviation direction Do in a cross-sectional view observed from the m-plane of the SiC single crystal. Therefore, in view of the accuracy of charge balance, it is preferable that the multiple pillar regions 24 extend along the deviation direction Do.

[0372] The multiple gate structures 37 are arranged at intervals in a second arrangement direction Da2 other than the first arrangement direction Da1, and are each formed in a strip shape extending in a second extending direction De2 other than the first extending direction De1. In this example, the multiple gate structures 37 are arranged at intervals in a second arrangement direction Da2 orthogonal to the first arrangement direction Da1, and extend in a second extending direction De2 orthogonal to the first extending direction De1.

[0373] That is, the second arrangement direction Da2 is the m-axis direction (the first direction X), and the second extending direction De2 is the a-axis direction (the second direction Y). The multiple gate structures 37 are arranged at intervals in the m-axis direction (the first direction X), and are each formed in a strip shape extending in the a-axis direction (the second direction Y).

[0374] Of course, regarding the multiple trench structures 20, the first arrangement direction Da1 is a direction other than the a-axis direction and the m-axis direction, and the first extending direction De1 is a direction other than the a-axis direction and the m-axis direction. That is, the multiple trench structures 20 may also extend in a direction intersecting both the a-axis direction and the m-axis direction.

[0375] In this case, the arrangement direction of the multiple pillar regions 24 becomes a direction other than the a-axis direction and the m-axis direction, and the extending direction of the multiple pillar regions 24 becomes a direction other than the a-axis direction and the m-axis direction. That is, the multiple pillar regions 24 extend in a direction intersecting both the a-axis direction and the m-axis direction.

[0376] On the other hand, it may also be that the second arrangement direction Da2 of the multiple gate structures 37 is one of the a-axis direction and the m-axis direction, and the second extending direction De2 of the multiple gate structures 37 is the other of the a-axis direction and the m-axis direction. In this case, the multiple gate structures 37 may also intersect the multiple trench structures 20 non-orthogonally.

[0377] Of course, the second arrangement direction Da2 of the plurality of gate structures 37 may also be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 of the plurality of gate structures 37 may also be a direction other than the a-axis direction and the m-axis direction. That is, the plurality of gate structures 37 may also extend in a direction intersecting both the a-axis direction and the m-axis direction. In this case, the plurality of gate structures 37 may be orthogonal to the plurality of trench structures 20, or may intersect the plurality of trench structures 20 non-orthogonally.

[0378] ​ is a cross-sectional perspective view of the SiC semiconductor device 1 showing a second modification. In the above-described manner, the SiC semiconductor device 1 has the high-concentration region 15. In contrast, the SiC semiconductor device 1 of the second modification does not have the high-concentration region 15. In this case, the plurality of trench structures 20, the plurality of body regions 30, the plurality of surface drift regions 31, the plurality of column regions 24, the plurality of drift regions 29, and the plurality of intermediate regions 32 are formed in the semiconductor layer 7.

[0379] ​ is a cross-sectional perspective view of the SiC semiconductor device 1 showing a third modification. In ​ the illustration of the interlayer insulating film 41 is omitted. In the above-described SiC semiconductor device 1, a potential other than the gate potential is applied to the trench structure 20. However, in the SiC semiconductor device 1 of the third modification, the trench structure 20 is formed as a trench gate structure, and the gate potential is applied to the trench structure 20.

[0380] That is, the gate structure 37 has the same potential as the trench structure 20. The gate electrode 39 may be integrally formed with the buried electrode 23, or may be physically isolated from the buried electrode 23 via the gate insulating film 38. ​ An example in which the gate electrode 39 is integrally formed with the buried electrode 23 is shown.

[0381] The aforementioned gate pad 50 (the plurality of gate wirings 51) is electrically connected to the plurality of trench structures 20 and the plurality of gate structures 37. The plurality of gate wirings 51 penetrate the interlayer insulating film 41 via the plurality of contact openings 44 and are connected to either or both of the plurality of buried electrodes 23 and the plurality of gate electrodes 39. Such a structure is achieved by adjusting the layout of the aforementioned plurality of contact openings 44.

[0382] On the other hand, the source pad 52 is electrically connected to the plurality of body regions 30, the plurality of intermediate regions 32, the plurality of source regions 33, and the plurality of contact regions 34 via the plurality of contact openings 44, and faces the plurality of trench structures 20 and the plurality of gate structures 37 with the interlayer insulating film 41 interposed therebetween. That is, the source pad 52 is electrically separated from the plurality of trench structures 20 and the plurality of gate structures 37. Such a structure is achieved by adjusting the layout of the aforementioned plurality of contact openings 44.

[0383] In the SiC semiconductor device 1 of the third modification, a channel Ch is also formed in a region between the source region 33 and the drift region 29 in the main body region 30 along the side wall of the trench structure 20.

[0384] ​ FIG. is a cross-sectional perspective view showing a SiC semiconductor device 1 of a fourth modification. The SiC semiconductor device 1 of the fourth modification further includes an n-type buffer layer 86 made of single-crystalline SiC laminated on the base layer 6. The buffer layer 86 is also a constituent element of the chip 2. The buffer layer 86 may also be referred to as a "buffer SiC layer", a "buffer region", etc.

[0385] The buffer layer 86 extends in a layered manner in the horizontal direction, forming the middle part of the chip 2 and a part of the first to fourth side surfaces 5A to 5D. The buffer layer 86 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that grows crystallographically starting from the base layer 6.

[0386] The buffer layer 86 has a lower end and an upper end. The lower end of the buffer layer 86 is the crystal growth starting point, and the upper end of the buffer layer 86 is the crystal growth ending point. Since the buffer layer 86 grows continuously from the base layer 6, the lower end of the buffer layer 86 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the buffer layer 86 may not be visually recognizable and can be evaluated and / or determined indirectly based on other structures and elements. The buffer layer 86 has a deviation direction Do and a deviation angle θo that are substantially the same as those of the base layer 6.

[0387] The buffer layer 86 has a third-axis channel C3 along the stacking direction. The third-axis channel C3 is a region (channel) with a relatively wide atomic distance (atomic spacing) between atoms of the SiC single crystal constituting the buffer layer 86, and is surrounded by atomic rows along the crystal axis extending in the stacking direction (crystal growth direction).

[0388] That is, the third-axis channel C3 is a region where the atomic rows are sparse and extends in the stacking direction, and is a region where the atomic rows in the horizontal direction (atomic distance / atomic density) are sparse when viewed from above. The third-axis channel C3 is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.

[0389] In this manner, the third-axis channel C3 is composed of a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the third-axis channel C3 extends along the c-axis and has a deviation direction Do and a deviation angle θo. In other words, the third-axis channel C3 is inclined by an amount of the deviation angle θo from the vertical axis toward the deviation direction Do.

[0390] The n-type impurity concentration of the buffer layer 86 is preferably less than the n-type impurity concentration of the base layer 6. The buffer layer 86 may also have 1×10 15 cm-3 equal to or greater than 1×10 18 cm -3 and equal to or less than as the peak value of the n-type impurity concentration. The n-type impurity concentration of the buffer layer 86 may also be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the buffer layer 86 may also have a concentration gradient that increases and / or decreases in the stacking direction (crystal growth direction).

[0391] The buffer layer 86 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the buffer layer 86 may also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The buffer layer 86 preferably includes a pentavalent element other than phosphorus.

[0392] The n-type impurity concentration of the buffer layer 86 is preferably adjusted by nitrogen at least. In the case where the buffer layer 86 includes two or more pentavalent elements, the buffer layer 86 preferably includes nitrogen and a pentavalent element other than nitrogen. In this case, the buffer layer 86 preferably includes either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0393] The buffer layer 86 has a third thickness T3. The third thickness T3 is preferably less than the first thickness T1 of the base layer 6. The third thickness T3 is preferably 1 μm or more. The third thickness T3 is preferably 5 μm or less. The third thickness T3 may have a value belonging to any range of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0394] The semiconductor layer 7 is stacked on the buffer layer 86. The semiconductor layer 7 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that crystallizes and grows starting from the buffer layer 86. Therefore, the semiconductor layer 7 has a deviation direction Do and a deviation angle θo that are substantially the same as those of the buffer layer 86. In addition, the second axis channel C2 and the third axis channel C3 are substantially the same.

[0395] The second thickness T2 of the semiconductor layer 7 is preferably greater than the third thickness T3. Of course, the second thickness T2 may also be less than the third thickness T3. In addition, the second thickness T2 may also be substantially equal to the third thickness T3.

[0396] The above-described manner can also be implemented in other ways. For example, in the foregoing manner, the base layer 6, the semiconductor layer 7, and the buffer layer 86 each including a SiC single crystal were used. However, at least one or all of the base layer 6, the semiconductor layer 7, and the buffer layer 86 may also include a single crystal of a wide-bandgap semiconductor other than the SiC single crystal.

[0397] A wide-bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. As a single crystal of a wide-bandgap semiconductor, silicon carbide (SiC), gallium nitride (GaN), diamond (C), gallium oxide (Ga2O3), etc. can be exemplified. The base layer 6, the semiconductor layer 7, and the buffer layer 86 may be composed of the same type of single crystal or different types of single crystals.

[0398] The above-described channel implantation process (the process of implanting impurities into a region where atomic columns are sparse) can also be applied to a single crystal that forms a cubic crystal. Therefore, the single crystal of the wide-bandgap semiconductor can be a cubic crystal or a hexagonal crystal. In the case where a cubic single crystal is applied to at least one or all of the base layer 6, the semiconductor layer 7, and the buffer layer 86, these axial channels are formed by regions surrounded by atomic columns along the low-index crystal axes among the crystal axes of the cubic crystal.

[0399] The low-index crystal axes of a cubic crystal are crystal axes in which, with respect to the Miller indices (h, k, l), the absolute values of "h", "k", and "l" are all represented by 2 or less (preferably 1 or less). Of course, at least one or all of the base layer 6, the semiconductor layer 7, and the buffer layer 86 may also include single-crystalline silicon.

[0400] In the above-described manner, an n-type base layer 6 is shown. However, a p-type base layer 6 can also be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the foregoing description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type base layer 6 can also be a p-type region including a trivalent element introduced into the surface layer portion of the second main surface 4 of the chip 2 by ion implantation.

[0401] Hereinafter, characteristic examples extracted from this specification and the drawings are shown. Hereinafter, the alphanumerics in parentheses, etc. represent the corresponding components, etc. in the foregoing manner, but are not intended to limit the scope of each item (Clause) to the foregoing manner. The "semiconductor device" in the following items can be replaced with "SiC semiconductor device", "wide-bandgap semiconductor device", "semiconductor switching device", "MISFET device", "IGBT device", etc. as needed.

[0402] [A1] A semiconductor device 1, comprising: a semiconductor layer 7 including a main surface 3; a trench structure 20 formed in the main surface 3 and extending in a first extension direction De1 in a plan view; and a planar electrode type gate structure 37 disposed on the main surface 3 and extending in a second extension direction De2 other than the first extension direction De1 in a plan view.

[0403] [A2] The semiconductor device 1 according to A1, wherein the gate structure 37 intersects the trench structure 20 and is electrically insulated from the trench structure 20 at the intersection portion with the trench structure 20.

[0404] [A3] The semiconductor device 1 according to A1 or A2, wherein a potential other than the gate potential is applied to the trench structure 20, and the gate potential is applied to the gate structure 37.

[0405] [A4] The semiconductor device 1 according to any one of A1 to A3, wherein the first extension direction De1 is the a-axis direction of the semiconductor layer 7, and the second extension direction De2 is a direction other than the a-axis direction.

[0406] [A5] The semiconductor device 1 according to any one of A1 to A4, further comprising: the semiconductor layer 7 of the first conductivity type (n-type); a lower region 7a, which is divided into a region between the bottom of the semiconductor layer 7 and the trench structure 20; and a column region 24 of the second conductivity type, which is formed in the lower region 7a.

[0407] [A6] The semiconductor device 1 according to A5, wherein the column region 24 extends along the first extension direction De1 in a plan view, and the gate structure 37 intersects the column region 24 in a plan view.

[0408] [A7] The semiconductor device 1 according to A5 or A6, wherein the semiconductor layer 7 has an axial channel C2 along the stacking direction, and the column region 24 extends along the axial channel C2.

[0409] [A8] The semiconductor device 1 according to A7, wherein the column region 24 crosses the middle portion of the thickness range of the lower region 7a along the axial channel C2.

[0410] [A9] The semiconductor device 1 according to A7 or A8, wherein the semiconductor layer 7 has a deviation angle θo that is inclined in a deviation direction Do with respect to the vertical axis Z, and the axial channel C2 has the deviation angle θo that is inclined in the deviation direction Do with respect to the vertical axis Z.

[0411] [A10] The semiconductor device 1 according to any one of A5 to A9, wherein the column region 24 has a thickness TC that is greater than the depth DT of the trench structure 20 in the thickness direction of the semiconductor layer 7.

[0412] [A11]For the semiconductor device 1 according to any one of A5 to A10, the column region 24 has an upper end portion on the side of the trench structure 20 and a lower end portion on the bottom side of the semiconductor layer 7, and has a concentration gradient that gradually decreases from the upper end portion toward the lower end portion.

[0413] [A12]For the semiconductor device 1 according to A11, wherein the concentration gradient includes: a peak P2 on the upper end portion side; and a slow portion 27, whose impurity concentration gradually decreases at a decreasing rate slower than the peak P2 in the region on the lower end portion side.

[0414] [A13]For the semiconductor device 1 according to A12, wherein the slow portion 27 occupies a thickness range of more than 1 / 4 in the column region 24.

[0415] [A14]For the semiconductor device 1 according to any one of A5 to A13, wherein the column region 24 is formed on the bottom side of the semiconductor layer 7 at an interval from the trench structure 20.

[0416] [A15]For the semiconductor device 1 according to A14, further including an intermediate region 32 of a second conductivity type, which is formed in the region between the trench structure 20 and the column region 24.

[0417] [A16]For the semiconductor device 1 according to A15, further including a body region 30 of a second conductivity type (p-type), which is formed in the surface layer portion of the main surface 3, the trench structure 20 penetrates the body region 30, the intermediate region 32 is electrically connected to the body region 30 and the column region 24, and the gate structure 37 covers the body region 30.

[0418] [A17]For the semiconductor device 1 according to A16, further including a source region 33 of a first conductivity type (n-type), which is formed on the side of the trench structure 20 in the surface layer portion of the body region 30, and the gate structure 37 covers the source region 33.

[0419] [A18]For the semiconductor device 1 according to any one of A5 to A17, further including a high-concentration region 15 of a first conductivity type (n-type), which has an impurity concentration higher than that of the semiconductor layer 7 and is formed in the surface layer portion of the main surface 3, the trench structure 20 is formed on the main surface 3 side at an interval from the bottom of the high-concentration region 15, the lower side region 7a includes a part of the high-concentration region 15, and the column region 24 includes a part located within the high-concentration region 15.

[0420] [A19]The semiconductor device 1 according to A18, wherein the column region 24 crosses the bottom of the high-concentration region 15.

[0421] [A20]A semiconductor device 1 includes: a semiconductor layer 7 of a first conductivity type n-type, which includes a main surface 3 and has an axial channel C2 along the stacking direction; a trench structure 20, which is formed on the main surface 3 and divides the bottom of the semiconductor layer 7 and the lower-side region 7a; a column region 24 of a second conductivity type (p-type), which is formed in the lower-side region 7a and extends along the axial channel C2; and a planar electrode type gate structure 37, which is disposed on the main surface 3 and overlaps with the trench structure 20 and the column region 24 in the stacking direction.

[0422] [A21]The semiconductor device 1 according to any one of A1 to A20, wherein the semiconductor layer 7 is a SiC layer 7 including a SiC single crystal.

[0423] Above, the specific modes have been described in detail, but these are merely specific examples showing the technical content. Various technical ideas extracted from this specification are not limited to the description order, the order of the mode examples, the order of the modification examples, etc. within the specification, and can be appropriately combined among them.

[0424] Symbol Explanation

[0425] 1—Semiconductor device; 3—First main surface; 7—Semiconductor layer; 7a—Lower-side region; 15—High-concentration region; 20—Trench structure; 24—Column region; 27—Second slow portion; 30—Body region; 32—Intermediate region; 33—Source region; 37—Gate structure; C2—Second axial channel; DT—Trench depth; De1—First extension direction; De2—Second extension direction; Do—Deviation direction; P2—Peak; TC—Column thickness; θo—Deviation angle; Z—Vertical direction.

Claims

1. A SiC semiconductor device, characterized in that, Comprising: a SiC layer including a main surface; a trench structure formed in the main surface and extending in a first extending direction in a plan view; and a planar electrode type gate structure disposed on the main surface and extending in a second extending direction other than the first extending direction in a plan view.

2. The SiC semiconductor device according to claim 1, wherein the gate structure intersects the trench structure and is electrically insulated from the trench structure at the intersection portion with the trench structure.

3. The SiC semiconductor device according to claim 1 or 2, wherein a potential other than the gate potential is applied to the trench structure, and the gate potential is applied to the gate structure.

4. The SiC semiconductor device according to any one of claims 1 to 3, wherein the first extending direction is the a-axis direction of the SiC single crystal, and the second extending direction is a direction other than the a-axis direction.

5. The SiC semiconductor device according to any one of claims 1 to 4, characterized in that, Further comprising: the SiC layer of a first conductivity type; a lower side region divided into a region between the bottom of the SiC layer and the trench structure; and a column region of a second conductivity type formed in the lower side region.

6. The SiC semiconductor device according to claim 5, wherein the column region extends in the first extending direction in a plan view, and the gate structure intersects the column region in a plan view.

7. The SiC semiconductor device according to claim 5 or 6, wherein the SiC layer has an axial channel along the stacking direction, and the column region extends along the axial channel.

8. The SiC semiconductor device according to claim 7, wherein the column region crosses the middle portion of the thickness range of the lower side region along the axial channel.

9. The SiC semiconductor device according to claim 7 or 8, wherein the SiC layer has a deviation angle inclined toward a deviation direction with respect to a vertical axis, and the axial channel has the deviation angle inclined toward the deviation direction with respect to the vertical axis.

10. The SiC semiconductor device according to any one of claims 5 to 9, wherein the column region has a thickness greater than the depth of the trench structure in the thickness direction of the SiC layer.

11. The SiC semiconductor device according to any one of claims 5 to 10, wherein the column region has an upper end portion on the trench structure side and a lower end portion on the bottom side of the SiC layer, and has a concentration gradient gradually decreasing from the upper end portion toward the lower end portion.

12. The SiC semiconductor device according to claim 11, wherein the concentration gradient includes: a peak on the upper end portion side; and a slow portion in which the impurity concentration gradually decreases at a slower reduction rate in a region on the lower end portion side than the peak.

13. The SiC semiconductor device according to claim 12, wherein the slow portion occupies a thickness range of more than 1 / 4 in the column region.

14. The SiC semiconductor device according to any one of claims 5 to 13, wherein The column region is formed on the bottom side of the SiC layer at an interval from the trench structure.

15. The SiC semiconductor device according to claim 14, wherein it further includes an intermediate region of a second conductivity type, and the intermediate region of the second conductivity type is formed in a region between the trench structure and the column region.

16. The SiC semiconductor device according to claim 15, wherein it further includes a body region of a second conductivity type, and the body region of the second conductivity type is formed in a surface layer portion of the main surface, the trench structure penetrates the body region, the intermediate region is electrically connected to the body region and the column region, the gate structure covers the body region.

17. The SiC semiconductor device according to claim 16, wherein it further includes a source region of a first conductivity type, and the source region of the first conductivity type is formed on a side of the trench structure in the surface layer portion of the body region, the gate structure covers the source region.

18. The SiC semiconductor device according to any one of claims 5 to 17, wherein it further includes a high-concentration region of a first conductivity type, and the high-concentration region of the first conductivity type has an impurity concentration higher than that of the SiC layer and is formed in a surface layer portion of the main surface, the trench structure is formed on the main surface side at an interval from the bottom of the high-concentration region, the lower side region includes a part of the high-concentration region, the column region includes a part located within the high-concentration region.

19. The SiC semiconductor device according to claim 18, wherein the column region crosses the bottom of the high-concentration region.

20. A SiC semiconductor device, characterized in that, Comprising: A SiC layer of a first conductivity type, which includes a main surface and has an axial channel along the stacking direction; A trench structure, which is formed on the main surface and divides the bottom and the lower side region of the SiC layer; A column region of a second conductivity type, which is formed in the lower side region and extends along the axial channel; And A planar electrode type gate structure, which is disposed on the main surface and overlaps with the trench structure and the column region in the stacking direction.

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