Inductive current zero-cross detection system and controller for DC-DC converter

Abstract

The invention discloses an inductive current zero-cross detection system and a controller for a DC-DC converter. The inductive current zero-cross detection system comprises a detection current module which is used for generating a detection current corresponding to a low-side power tube based on voltages at two ends of the low-side power tube in the DC-DC converter and a state signal of the low-side power tube; the self-adaptive reference current module is used for generating corresponding reference current based on the voltage at the two ends of the low-side power tube, the state signal of the low-side power tube and the inductive current zero-crossing signal; and the logic processing module is used for generating an inductive current zero-crossing signal based on a pulse width modulation (PWM) control signal, the detection current and the reference current of the DC-DC converter.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to an inductor current zero-crossing detection system and a controller used in a DC-DC converter. Background Art

[0002] DC-DC (DC / DC) voltage converters are widely used in various electronic systems, including wireless communication devices, IoT mobile terminals, and portable power supplies. Efficiency and power loss are key performance indicators for DC / DC voltage converters. DC / DC voltage converters inherently experience power loss, and their efficiency rapidly decreases when operating under light loads. For DC / DC step-down converters, shutting down the low-side power switch promptly after detecting the inductor current crossing zero when operating in DCM (discontinuous conduction mode) can effectively improve light-load efficiency. Because the signal level is very small when the inductor current approaches zero, it is difficult to ensure the accuracy of the zero-crossing detection signal. Poor accuracy can lead to premature or late shutdown of the low-side power switch, resulting in power losses and reduced efficiency of the DC / DC step-down converter. Summary of the Invention

[0003] An inductor current zero-crossing detection system for a DC-DC converter according to an embodiment of the present invention includes: a detection current module for generating a detection current corresponding to a low-side power tube in the DC-DC converter based on a voltage across the low-side power tube and a status signal of the low-side power tube; an adaptive reference current module for generating a corresponding reference current based on the voltage across the low-side power tube, the status signal of the low-side power tube, and an inductor current zero-crossing signal; and a logic processing module for generating an inductor current zero-crossing signal based on a pulse width modulation (PWM) control signal of the DC-DC converter, the detection current, and the reference current.

[0004] A controller for a DC-DC converter according to an embodiment of the present invention includes the above-mentioned inductor current zero-crossing detection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0006] Figure 1 A schematic block diagram showing the system architecture of a traditional DC-DC converter is shown.

[0007] Figure 2 A schematic block diagram of an inductor current zero-crossing detection system for a DC-DC converter according to an embodiment of the present invention is shown.

[0008] Figure 3 Shown in Figure 2 The figure shows a schematic block diagram of an example structure of an adaptive reference current module in an inductor current zero-crossing detection system.

[0009] Figure 4 Shown in Figure 3 FIG. 1 is a schematic block diagram of an example structure of a dynamic latch comparator in an adaptive reference current module.

[0010] Figure 5 Shown in Figure 3 A schematic block diagram of an example structure of a reference current generating circuit in an adaptive reference current module is shown.

[0011] Figure 6 Shown in Figure 3 The schematic block diagram of the example structure of the adaptive reference current module is shown.

[0012] Figure 7 A schematic block diagram shows an exemplary structure of an inductor current zero-crossing detection system used in a DC-DC converter according to an embodiment of the present invention.

[0013] Figure 8 Shown in Figure 7 Figure 2 shows an example waveform diagram of an inductor current zero-crossing detection system. DETAILED DESCRIPTION

[0014] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed in order to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, components and algorithms without departing from the spirit of the present invention. In the accompanying drawings and the following description, well-known structures and technologies are not shown in order to avoid unnecessary ambiguity in the present invention. In addition, it should be noted that the term "A is connected to B" used herein can mean "A is directly connected to B" or "A is indirectly connected to B via one or more other elements."

[0015] The accuracy of the zero-crossing detection signal in traditional inductor current zero-crossing detection is difficult to guarantee, which may lead to a large error between the indication time of the zero-crossing detection signal and the actual current zero-crossing time. As a result, the low-side power tube is turned off too early or too late due to the zero-crossing detection signal. If the low-side power tube is turned off too early before the current crosses zero, the parasitic diode of the low-side power tube will generate loss due to freewheeling. If the low-side power tube is turned off too late after the current crosses zero, the current direction and the inductor current during the period when the low-side power tube is turned on will be lost as load current, thereby reducing the efficiency of the DC-DC converter.

[0016] In view of the accuracy issues of the zero-crossing detection signal in traditional inductor current zero-crossing detection, an inductor current zero-crossing detection system for a DC-DC converter is proposed according to an embodiment of the present invention. In this system, an adaptive reference current module generates a corresponding reference current based on the actual voltage across the low-side power transistor, a status signal, and the inductor current zero-crossing signal, thereby adaptively adjusting the reference current. The generated inductor current zero-crossing signal has a relatively small error, enabling accurate and timely shutdown of the low-side power transistor, thereby improving the efficiency of the DC-DC converter under light load.

[0017] Figure 1 FIG. 1 shows a schematic block diagram of the system architecture of a conventional DC-DC converter. Figure 1 As shown, the DC-DC converter 100 includes at least a controller 101, a drive circuit 102, a high-side power transistor MH, a low-side power transistor ML, and an inductor L. The controller 101 outputs a pulse width modulation (PWM) control signal to the drive circuit 102. The drive circuit 102 generates a high-side drive signal for driving the high-side power transistor MH and a low-side drive signal for driving the low-side power transistor ML based on the PWM control signal. The high-side power transistor MH and the low-side power transistor ML are connected in series between the input voltage VIN and the power ground PGND. The inductor L filters the switch node SW connected to the high-side power transistor MH and the low-side power transistor ML and generates the output voltage Vout of the DC-DC converter. In this embodiment, the inductor current zero-crossing detection system utilizes Figure 1 The relevant signal in the DC-DC converter outputs an inductor current zero-crossing signal, which is used to indicate the inductor current I flowing through the inductor L L Whether it is zero-crossing, when the inductor current is zero-crossing, the signal indicates that the inductor current I L From the positive zero crossing, the controller 101 controls the low-side power transistor ML to turn off.

[0018] Figure 2 FIG. 1 shows a schematic block diagram of an inductor current zero-crossing detection system for a DC-DC converter according to an embodiment of the present invention. Figure 2As shown, an inductor current zero-crossing detection system 200 for a DC-DC converter includes: a detection current module 210 for generating a detection current Is corresponding to the low-side power tube ML based on the voltage across the low-side power tube ML in the DC-DC converter (i.e., the voltage between SW and PGND) and the state signal LG_FB of the low-side power tube ML; an adaptive reference current module 220 for generating a corresponding reference current Iref based on the voltage across the low-side power tube ML, the state signal LG_FB of the low-side power tube ML, and the inductor current zero-crossing signal ZCD; and a logic processing module 230 for generating the inductor current zero-crossing signal ZCD based on the PWM control signal of the DC-DC converter, the detection current Is, and the reference current Iref. The state signal LG_FB is used to indicate whether the actual state of the low-side power tube ML is on or off, for example, a low level indicates off and a high level indicates on, and can be obtained by detecting the low-side power tube ML through a Schmitt trigger. The level of the state signal LG_FB of the low-side power tube ML changes with the shutdown action of the low-side power tube ML.

[0019] Figure 3 Shown in Figure 2 FIG. 1 is a schematic block diagram of an example structure of an adaptive reference current module in an inductor current zero-crossing detection system. Figure 3 As shown, in some embodiments, the adaptive reference current module 220 includes: a dynamic latch comparator 221, which is used to determine the voltage comparison signal Comp0 based on the voltage across the low-side power tube ML when the enable signal ck1 is in a valid state; a timing control circuit 222, which is used to generate the enable signal ck1 based on the state signal LG_FB of the low-side power tube and the inductor current zero-crossing signal ZCD, and generate the current adjustment signal Si according to the voltage comparison signal Comp0; and a reference current generating circuit 223, which is used to adjust the reference current Iref based on the current adjustment signal Si and output it.

[0020] In some embodiments, the dynamic latch comparator 221 is further configured to: generate the voltage comparison signal Comp0 and then latch the voltage comparison signal Comp0 ; and reset the voltage comparison signal Comp0 when the enable signal ck1 is in an invalid state.

[0021] Figure 4 Shown in Figure 3 FIG. 1 is a schematic block diagram of an example structure of a dynamic latch comparator in an adaptive reference current module. Figure 4As shown, in some embodiments, the dynamic latch comparator 221 includes switch tubes Mc1-Mc13, a resistor R1, a capacitor C1, an inverter INV0 and a current source I1, and wherein: the first end of Mc1, the first end of Mc2, the first end of Mc3, the first end of Mc4, the control end of Mc13, and the first end of the current source I1 are connected to the preset power supply terminal AVDD; the control end of Mc1, the control end of Mc4, the control end of Mc9, the control end of Mc10, and the control end of Mc11 receive the enable signal ck1; the second end of Mc1, the second end of Mc2, the control end of Mc3, and the control end of Mc6 are connected to the first end of Mc5; the second end of Mc3, the second end of Mc4, the control end of Mc2, the control end of Mc5, and the first end of Mc6 are connected to the input end of the inverter INV0; and the output end of the inverter INV0 outputs the current. voltage comparison signal Comp0; the control end of Mc7, the control end of Mc8, the control end and the first end of Mc12, and the second end of the current source I1 are connected to the first end of the capacitor C1; the second end of Mc5 is connected to the first end of Mc7, the second end of Mc6 is connected to the first end of Mc8, the second end of Mc7 is connected to the first end of Mc9, the second end of Mc9 is connected to the first end of Mc11, the second end of Mc8 is connected to the first end of Mc10, and the second end of Mc12 is connected to the first end of Mc13; the first end of the resistor R1 is connected to the second end of Mc11, and the second end of the resistor R1 receives the switch node voltage (that is, connected to the switch node SW) among the voltages across the low-side power tube; and the second end of Mc10, the second end of Mc13, and the second end of the capacitor C1 receive the power ground voltage (that is, connected to the power ground PGND) among the voltages across the low-side power tube. Among them, Mc1-Mc4 can be implemented by P-channel field-effect transistors, Mc5-Mc13 can be implemented by N-channel field-effect transistors. Since the SW node voltage is relatively high, in order to adapt to high-voltage applications, Mc11 can select a high-voltage-resistant N-channel field-effect transistor. The high-voltage-resistant port is generally the drain of the transistor, so the drain of Mc11, i.e., the second end, is connected to the SW node through the resistor R1.

[0022] like Figure 4As shown, in the initial state of the dynamic latch comparator 221, the enable signal ck1 is at a low level, representing an inactive state. When a comparison is required, the enable signal ck1 becomes a high level, representing an active state. At this time, the dynamic latch comparator 221 begins to determine the difference between the voltage at the drain of Mc11 (i.e., the voltage drop between the voltage of SW and the voltage of R1) and the voltage at the drain of Mc10 (i.e., the voltage of PGND). If the voltage at the drain of Mc11 is lower than the voltage at the drain of Mc10, Comp0 is at a low level. If the voltage at the drain of Mc11 is higher than the voltage at the drain of Mc10, Comp0 is at a high level. Due to the presence of R1, SW is not directly compared with PGND. Instead, a lower potential is used as the comparison threshold. For example, assuming PGND is at zero potential, with R1 present, Comp0 is at a low level when the potential of SW is less than -0.35V, and is at a high level when SW is not less than -0.35V. Furthermore, once the dynamic latch comparator 221 generates the voltage comparison signal Comp0, Comp0 will be locked. Even if the voltage of SW jumps in the opposite direction later, Comp0 will not change again until the enable signal ck1 becomes a low level indicating an invalid state, and Comp0 is reset to the initial state.

[0023] Figure 5 Shown in Figure 3 Schematic block diagram of an example structure of a reference current generating circuit in an adaptive reference current module. Figure 5As shown, in some embodiments, the reference current generating circuit 223 includes a fixed current source unit that outputs a constant first current I31, and an adaptive current source unit that outputs a corresponding second current I32 based on a current adjustment signal Si, and the reference current Iref is the sum of the first current I31 and the second current I32. Specifically, in some embodiments, the adaptive current source unit includes switch tubes Ma1-Ma7, a capacitor switch tube MC, a pull-up current source Iup, a pull-down current source Idn, and a resistor R3, and the fixed current source unit includes switch tubes Ma8, Ma9, and a bias current source I0. The first end of the bias current source I0, the first end of the pull-up current source Iup, the first end of Ma4, and the first end of Ma5 are connected to a preset power supply terminal AVDD; the first end of Ma1 is connected to the second end of the pull-up current source Iup, and the control end receives the up-regulation signal UP in the current adjustment signal Si; the second end of Ma1, the first end of Ma2, and the control end of Ma3 are connected to the control end of MC; the control end of Ma2 receives the down-regulation signal DN, the first end of Ma4, and the control end of Ma5 in the current adjustment signal Si. The two ends are connected to the first end of the pull-down current source Idn; the first end of Ma3 is connected to the second end and the control end of Ma4, and the control end of Ma5; the second end of Ma3 is connected to the first end of resistor R3; the second end of Ma5 is connected to the first end and the control end of Ma6, and the control end of 7Ma; the first end of Ma7 outputs a second current I32; the control end of Ma8, the first end and the control end of Ma9 are connected to the second end of the bias current source I0; the first end of Ma8 outputs a first current I31; the first end of Ma7 is connected to the first end of Ma8; the second end of the pull-down current source Idn, the first and second ends of MC, the second end of resistor R3, the second end of Ma6, the second end of Ma7, the second end of Ma8, and the second end of Ma9 are connected to the preset ground terminal GND. Among them, Ma1, Ma4, and Ma5 are P-channel field-effect transistors, and MC, Ma2, Ma3, Ma6-Ma9 are N-channel field-effect transistors.

[0024] like Figure 5As shown, the reference current generating circuit 223 adjusts whether the reference current Iref increases or decreases according to the up-regulation signal UP or the pull-down signal DN in the current adjustment signal Si. The bias current source I0 outputs a constant first current I31 through the mirrors of Ma8 and Ma9, which serves as a part of the reference current Iref and is used to set an initial state of the ZCD. MC acts as a MOS capacitor, and UP and DN are pulse signals. If UP and DN are both low, the pull-up current source Iup charges MC, and the voltage of the gate node VC of MC increases, thereby increasing the drain current flowing through Ma3. The drain current of Ma3 is copied to Ma5 through the current mirror Ma4, and then copied to Ma7 through Ma6. The drain current of M7a is the second current I32, which is a part of the reference current Iref. Therefore, when DN maintains a low level and UP is a low-level pulse signal, the VC voltage increases and the second current I32 increases; when DN is a high-level pulse signal and UP maintains a high level, the VC voltage decreases and the second current I32 decreases. That is to say, when the UP pulse arrives, the second current I32 increases and the reference current Iref increases. When the DN pulse arrives, the second current I32 decreases and the output reference current Iref decreases.

[0025] Figure 6 Shown in Figure 3 The schematic block diagram of the example structure of the adaptive reference current module is shown in FIG. Figure 6As shown, in some embodiments, the timing control circuit 222 includes a first inverter INV1, a second inverter INV2, a first AND gate AG1, a second AND gate AG2, a third AND gate AG3, a fourth AND gate AG4, a first D flip-flop DFF1, a second D flip-flop DFF2, a first delay unit DU1, a second delay unit DU2, a third delay unit DU3, and a pulse generating unit 601, and wherein: the first input end of the first AND gate AG1 receives the state signal LG_FB of the low-side power tube ML through the first inverter INV1, and the second input end receives the inductor current zero-crossing signal ZCD; the first delay unit DU1, the second delay unit DU2, and the third delay unit DU3 are connected in series between the output end of the first AND gate AG1 and the input end of the pulse generating unit 601; the first input end of the second AND gate AG2 is connected to the output end of the first delay unit DU2, the second delay unit DU2, and the third delay unit DU3; The second input terminal is connected to the inverting output terminal of the second D flip-flop DFF2, and the output terminal outputs the enable signal ck1; the input terminal of the first D flip-flop DFF1 receives the voltage comparison signal Comp0, the clock enable terminal is connected to the output terminal of the second delay unit DU2, the in-phase output terminal is connected to the first input terminal of the third AND gate AG3, and the inverting output terminal is connected to the first input terminal of the fourth AND gate AG4; the input terminal of the second D flip-flop DFF2 receives a preset high-level signal "1", and the clock enable terminal is connected to the output terminal of the third delay unit DU3; the pulse generating unit 601 is used to be triggered by the signal at the input terminal to generate a pulse signal, and send it to the second input terminal of the third AND gate AG3 and the second input terminal of the fourth AND gate AG4; and the third AND gate AG3 outputs the up-regulation signal UP in the current adjustment signal Si through the second inverter INV2, and the fourth AND gate AG4 outputs the down-regulation signal DN in the current adjustment signal Si.

[0026] Figure 7 FIG2 is a schematic block diagram showing an exemplary structure of an inductor current zero-crossing detection system for a DC-DC converter according to an embodiment of the present invention. Figure 7As shown, in some embodiments, the current detection module 210 includes switch tubes Md1-Md11, an inverter INV3, and a current source I2, and wherein: the source of Md1, the source of Md2, the source of Md3, the gate of Md6, the source of Md10, and the source of Md11 are connected to the preset power supply terminal AVDD; the drain and gate of Md1, the gate of Md2, and the gate of Md3 are connected to the first terminal of the current source I2, and the second terminal of the current source I2 is connected to the preset ground terminal GND; the drain of Md2 and the drain of Md4 are connected to the gate of Md9; the gate and drain of Md10 and the gate of Md11 are connected to the Md The drain of Md9 is connected to the gate of Md4, the gate and drain of Md5; the source of Md4 is connected to the source of Md6, and the source of Md5 is connected to the source of Md7, the drain of Md8, and the source of Md9; the gate of Md7 and the input of inverter INV3 receive the state signal LG_FB of the low-side power tube; the drain of Md6 and the source of Md8 receive the power ground voltage (i.e., connected to the power ground PGND) of the voltage across the low-side power tube; the drain of Md7 receives the switch node voltage (i.e., connected to the switch node SW) of the voltage across the low-side power tube; and the drain of Md11 outputs the detection current Is. Among them, the switching tubes Md1, Md2, Md3, Md10, and Md11 are all P-channel field-effect transistors, and Md4-Md9 are all N-channel field-effect transistors. Since the SW node voltage is high, to adapt to high-voltage scenarios and consider matching issues, Md6 and Md7 can be implemented using high-voltage-resistant N-channel field-effect transistors. The high-voltage-resistant port is generally the drain of the transistor, so the drains of Md6 and Md7 are connected to PGND and SW, respectively.

[0027] like Figure 7 As shown, in some embodiments, the logic processing module 230 includes an inverter INV4 and an RS trigger. The input terminal of the inverter INV4 receives the comparison result of the detection current Is and the reference current Iref. The set terminal S of the RS trigger is connected to the output terminal of the inverter INV4, the reset terminal R receives the PWM control signal, and the in-phase output terminal Q outputs the inductor current zero-crossing signal ZCD. Specifically, the RS trigger can be implemented by two NOR gates I3 and I4. Figure 7 As shown, the input end of the inverter INV4 is connected to the output end of the detection current module 210 and the output end of the adaptive reference current module 220. If the detection current Is is greater than the reference current Iref, the input end of the inverter INV4 is a high level. If the detection current Is is less than the reference current Iref, the input end of the inverter INV4 is a low level.

[0028] like Figure 7As shown, the detection object of the current detection module 210 is the current of the low-side power tube ML. Because the freewheeling phase of the inductor L is freewheeling through the low-side power tube ML, the current value flowing through the low-side power tube ML is equal to the inductor current I L The same, so only need to detect the current zero crossing of the low-side power tube ML to determine the inductor current zero crossing. When the low-side power tube ML is turned off, the LG_FB signal is 0, Md7 is disconnected, Md8 is turned off, and the detection current module 210 is maintained at a DC operating point, thereby greatly reducing the settling time of the op amp loop and improving the response speed of the detection current module 210. When the low-side power tube ML is turned on, Md6, Md7 and the low-side power tube ML are matched. If the on-resistance of Md6 and Md7 is expressed as R S , the on-resistance of the low-side power tube ML is expressed as R ON Due to the clamping effect of the op amp loop, the source voltage of Md6 is equal to the source voltage of Md7. Assuming that the bias current flowing through Md6 and Md7 is I 01 , the drain current flowing through Md9 is I D9 , then we can list the equation:

[0029] I 01 R S =(I 01 +I D9 )R S +V sw ; (1)

[0030] Where V sw is the SW node voltage, which can be expressed as V sw =-I L R on , substituted into formula (1), and after sorting, we can get:

[0031]

[0032] The drain current of Md9 is copied through Md10 and Md11. If the size ratio of the transistors Md10 and Md11 is N, the drain current of Md11 is the detection current I output by the detection current module 210. S , which can be expressed as:

[0033]

[0034] From formula (3), it can be seen that the detection current module 210 outputs a current that is proportional to the inductor current I L Proportional to the sense current I S The detection current Is will be compared with the reference current Iref to determine the zero crossing point of the inductor current. When the low-side power tube ML is turned on, the inductor current I L Gradually decreases, when I S <Iref When the input of the inverter INV4 is pulled low, the RS trigger composed of I3 and I4 is set to a high level, and the ZCD signal output from the inverting output terminal changes from a low level to a high level, indicating that the inductor current has crossed zero. Therefore, the reference current I ref The change of can adjust the ZCD transition threshold.

[0035] Figure 8 Shown in Figure 7 The example waveform diagram of the inductor current zero-crossing detection system is shown in FIG. Figure 8 As shown, after the inductor current zero-crossing detection system determines that the current crosses zero, the inductor current signal ZCD output by the inductor current zero-crossing detection system changes from a low level to a high level. Then, based on the change of ZCD, the controller will turn off the low-side power tube ML, and the adaptive reference current module 220 starts to work at the same time. If the inductor current is still flowing when the ZCD changes from a low level to a high level, the body diode of the low-side power tube ML will continue to flow after the low-side power tube ML is turned off, and the voltage of the SW node is negative, indicating that the shutdown action of the low-side power tube ML occurs too early. If the inductor current has already crossed zero when the ZCD changes from a low level to a high level, the voltage of the SW node quickly becomes a positive voltage after the low-side power tube ML is turned off, indicating that the shutdown action of the low-side power tube ML occurs too late. Therefore, by detecting the positive or negative of the SW node voltage when the ZCD changes and the low-side power tube ML is turned off, it can be judged whether the shutdown of the low-side power tube ML occurs too early or too late, that is, whether the moment of ZCD change is too early or too late. If it is too early, the reference current Iref can be reduced to make the next moment when ZCD changes from a low level to a high level closer to the current zero crossing point; if it is too late, the reference current Iref can be increased to make the next moment when ZCD changes from a low level to a high level closer to the current zero crossing point, thereby realizing adaptive adjustment of the reference current Iref, so that the inductor current I L Converges to 0.

[0036] When the low-side power tube ML is turned off, the coupling between the gate and the drain causes the SW node to become negative, and the inductor current I L The voltage of the SW node rises slowly when the inductor current crosses zero. The voltage equilibrium point of the SW node is a negative value. Therefore, the resistor R1 in the dynamic latch comparator 221 generates an offset voltage, so that the SW voltage corresponding to the flip point of the output signal Comp0 of the dynamic latch comparator 221 is a negative value. In this way, when ZCD changes from a low level to a high level, the inductor current I L It can converge to be closer to 0. It is worth noting that the absolute value of the flip threshold corresponding to the flip point of Comp0 in the dynamic latch comparator 221 cannot be greater than the turn-on threshold of the body diode of the low-side power tube ML, otherwise the comparator can only judge whether the low-side power tube ML is turned off too late.

[0037] like Figure 1 and Figure 6 As shown, the coupling when the low-side power tube ML is turned off causes the SW node voltage to drop. The SW node voltage needs to wait for a certain time to recover before it can be used for judgment by the dynamic latch comparator 221. Therefore, the first delay unit DU1 delays the enable signal ck1 that triggers the dynamic latch comparator 221; the voltage comparison signal Comp0 output by the dynamic latch comparator 221 needs a certain time to stabilize, so the second delay unit DU2 delays the CKD signal that triggers the first D flip-flop DFF1; the first D flip-flop DFF1 needs a certain time to output a stable signal for the third AND gate AG3 and the fourth AND gate AG4, so the third delay unit DU3 delays the signal that triggers the pulse generating unit 601, so that the pulse signal output by the pulse generating unit 601 corresponds to the output of the first D flip-flop DFF1 in time.

[0038] Combine Figure 6 and Figure 8 The working principle of the adaptive reference current module is as follows: If ZCD changes from low level to high level, the inductor current I L If the voltage has not yet crossed zero, the SW node voltage is negative after the low-side power tube ML is turned off. After the low-side power tube ML is turned off, the state signal LG_FB signal becomes low, so that the enable signal ck1 output by the second AND gate AG2 becomes high, indicating a valid state. The dynamic latch comparator 221 is enabled and outputs a low-level voltage comparison signal Comp0. After passing through the second delay unit DU2, Comp0 is latched into the first D flip-flop DFF1. At the same time, the second D flip-flop DDF2 outputs the RST signal to reset the enable signal ck1 to a low level indicating an invalid state, resetting Comp0. At this time, the UP path is closed and the DN path is opened. After passing through the third delay unit DU3, the pulse generating circuit 601 generates a pulse signal and transmits it to the DN port. Therefore, the reference current Iref decreases. The inductor current at the next time ZCD changes from a low level to a high level will be closer to zero than the inductor current at the time of this ZCD change. After multiple adjustments, the inductor current I L It will slowly converge to near 0. Similarly, if ZCD changes from low level to high level, the inductor current I LAfter the low-side power transistor ML has passed zero, the SW node voltage is positive after the low-side power transistor ML is turned off. After the low-side power transistor ML is turned off, the LG_FB signal becomes low. The enable signal ck1 output by the second AND gate AG2 is high, indicating a valid state. The dynamic latch comparator 221 is enabled and outputs a high-level voltage comparison signal Comp0. After passing through the second delay unit DU2, Comp0 is latched into the first D flip-flop DFF1. At the same time, the RST signal resets ck1 to a low level, indicating an invalid state, and Comp0 is reset. At this time, the DN path is closed and the UP path is opened. After passing through the third delay unit DU3, the pulse generating circuit 601 generates a pulse signal and transmits it to the UP port. Therefore, the reference current Iref increases. The inductor current at the next time ZCD changes from a low level to a high level will be closer to zero than the inductor current at the time of the current ZCD change. After multiple adjustments, the inductor current at the time of the ZCD change gradually converges to near 0.

[0039] The present invention also discloses a controller for a DC-DC converter, including the inductor current zero-crossing detection system of the above embodiment. For details of the inductor current zero-crossing detection system, please refer to the description of the above embodiment and will not be repeated here.

[0040] The present invention may be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the present invention. Therefore, the present embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention is defined by the appended claims rather than the foregoing description, and all modifications coming within the meaning and scope of equivalents of the claims are intended to be included within the scope of the present invention.

Claims

1. An inductor current zero-crossing detection system for a DC-DC converter, comprising: A detection current module, configured to generate a detection current corresponding to a low-side power tube in a DC-DC converter based on a voltage across the low-side power tube and a status signal of the low-side power tube; An adaptive reference current module, configured to generate a corresponding reference current based on the voltage across the low-side power tube, the state signal of the low-side power tube, and the inductor current zero-crossing signal; as well as A logic processing module is configured to generate the inductor current zero-crossing signal based on a pulse width modulation (PWM) control signal of the DC-DC converter, the detection current, and the reference current.

2. The inductor current zero-crossing detection system according to claim 1, wherein: The adaptive reference current module includes: A dynamic latch comparator, configured to determine a voltage comparison signal based on the voltage across the low-side power transistor when the enable signal is in a valid state; a timing control circuit, configured to generate the enable signal based on the state signal of the low-side power tube and the inductor current zero-crossing signal, and generate a current adjustment signal according to the voltage comparison signal; and The reference current generating circuit is used to adjust the reference current based on the current adjustment signal and output the reference current.

3. The inductor current zero-crossing detection system according to claim 2, wherein: The dynamic latch comparator is further configured to: locking the voltage comparison signal after generating the voltage comparison signal; and When the enable signal is in an invalid state, the voltage comparison signal is reset.

4. The inductor current zero-crossing detection system according to claim 3, wherein: The dynamic latch comparator includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube, a thirteenth switch tube, a resistor, a capacitor, an inverter, and a current source, and wherein: The first end of the first switch tube, the first end of the second switch tube, the first end of the third switch tube, the first end of the fourth switch tube, the control end of the thirteenth switch tube, and the first end of the current source are connected to a preset power supply end; The control end of the first switch tube, the control end of the fourth switch tube, the control end of the ninth switch tube, the control end of the tenth switch tube, and the control end of the eleventh switch tube receive the enable signal; The second end of the first switch tube, the second end of the second switch tube, the control end of the third switch tube, and the control end of the sixth switch tube are connected to the first end of the fifth switch tube; The second end of the third switch tube, the second end of the fourth switch tube, the control end of the second switch tube, the control end of the fifth switch tube, and the first end of the sixth switch tube are connected to the input end of the inverter; The output terminal of the inverter outputs the voltage comparison signal; The control end of the seventh switch tube, the control end of the eighth switch tube, the control end and the first end of the twelfth switch tube, and the second end of the current source are connected to the first end of the capacitor; The second end of the fifth switching transistor is connected to the first end of the seventh switching transistor, the second end of the sixth switching transistor is connected to the first end of the eighth switching transistor, the second end of the seventh switching transistor is connected to the first end of the ninth switching transistor, the second end of the ninth switching transistor is connected to the first end of the eleventh switching transistor, the second end of the eighth switching transistor is connected to the first end of the tenth switching transistor, and the second end of the twelfth switching transistor is connected to the first end of the thirteenth switching transistor; The first end of the resistor is connected to the second end of the eleventh switch tube, and the second end of the resistor receives the switch node voltage of the voltage across both ends of the low-side power tube; and The second end of the tenth switching tube, the second end of the thirteenth switching tube, and the second end of the capacitor receive the power ground voltage among the voltages across the low-side power tube.

5. The inductor current zero-crossing detection system according to claim 2, wherein: The reference current generating circuit includes a fixed current source unit that outputs a constant first current, and an adaptive current source unit that outputs a corresponding second current based on the current adjustment signal. The reference current is the sum of the first current and the second current.

6. The inductor current zero-crossing detection system according to claim 5, wherein: The adaptive current source unit includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, a capacitor switch tube, a pull-up current source, a pull-down current source and a resistor, and the fixed current source unit includes an eighth switch tube, a ninth switch tube and a bias current source. The first end of the bias current source, the first end of the pull-up current source, the first end of the fourth switch tube, and the first end of the fifth switch tube are connected to a preset power supply end; The first end of the first switch tube is connected to the second end of the pull-up current source, and the control end receives the upward adjustment signal in the current adjustment signal; The second end of the first switch tube, the first end of the second switch tube, and the control end of the third switch tube are connected to the control end of the capacitor switch tube; The control end of the second switch tube receives the downward adjustment signal in the current adjustment signal, and the second end is connected to the first end of the pull-down current source; The first end of the third switch tube is connected to the second end and the control end of the fourth switch tube and the control end of the fifth switch tube; The second end of the third switch tube is connected to the first end of the resistor; The second end of the fifth switch tube is connected to the first end and the control end of the sixth switch tube and the control end of the seventh switch tube; The first end of the seventh switch tube outputs the second current; The control end of the eighth switch tube, the first end and the control end of the ninth switch tube are connected to the second end of the bias current source; The first end of the eighth switch tube outputs the first current; The first end of the seventh switching tube is connected to the first end of the eighth switching tube; The second end of the pull-down current source, the first and second ends of the capacitor switch tube, the second end of the resistor, the second end of the sixth switch tube, the second end of the seventh switch tube, the second end of the eighth switch tube, and the second end of the ninth switch tube are connected to a preset ground end.

7. The inductor current zero-crossing detection system according to claim 6, wherein: The timing control circuit includes a first inverter, a second inverter, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first D flip-flop, a second D flip-flop, a first delay unit, a second delay unit, a third delay unit, and a pulse generating unit, and wherein: The first input end of the first AND gate receives the state signal of the low-side power tube through the first inverter, and the second input end receives the inductor current zero-crossing signal; A first delay unit, a second delay unit, and a third delay unit are connected in series between the output end of the first AND gate and the input end of the pulse generating unit; The first input terminal of the second AND gate is connected to the output terminal of the first delay unit, the second input terminal is connected to the inverting output terminal of the second D flip-flop, and the output terminal outputs the enable signal; The input terminal of the first D flip-flop receives the voltage comparison signal, the clock enable terminal is connected to the output terminal of the second delay unit, the non-inverting output terminal is connected to the first input terminal of the third AND gate, and the inverting output terminal is connected to the first input terminal of the fourth AND gate; The input end of the second D flip-flop receives a preset high level signal, and the clock enable end is connected to the output end of the third delay unit; The pulse generating unit is configured to generate a pulse signal triggered by a signal at the input terminal, and send the pulse signal to the second input terminal of the third AND gate and the second input terminal of the fourth AND gate; and The third AND gate outputs the up-regulation signal in the current adjustment signal through the second inverter, and the fourth AND gate outputs the down-regulation signal in the current adjustment signal.

8. The inductor current zero-crossing detection system according to claim 1, wherein: The current detection module includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube, an inverter, and a current source, and wherein: The first end of the first switch tube, the first end of the second switch tube, the first end of the third switch tube, the control end of the sixth switch tube, the first end of the tenth switch tube, and the first end of the eleventh switch tube are connected to a preset power supply end; The second terminal and the control terminal of the first switch tube, the control terminal of the second switch tube, and the control terminal of the third switch tube are connected to the first terminal of the current source, and the second terminal of the current source is connected to a preset ground terminal; The second end of the second switch tube and the first end of the fourth switch tube are connected to the control end of the ninth switch tube; The control end and the second end of the tenth switch tube and the control end of the eleventh switch tube are connected to the first end of the ninth switch tube; The second end of the third switch tube is connected to the control end of the fourth switch tube, the control end of the fifth switch tube and the first end; The second end of the fourth switch tube is connected to the first end of the sixth switch tube, and the second end of the fifth switch tube is connected to the first end of the seventh switch tube, the first end of the eighth switch tube, and the second end of the ninth switch tube; The control terminal of the seventh switch tube and the input terminal of the inverter receive the state signal of the low-side power tube, the second terminal of the sixth switch tube and the second terminal of the eighth switch tube receive the power ground voltage among the voltages across the low-side power tube, and the second terminal of the seventh switch tube receives the switch node voltage among the voltages across the low-side power tube; and The second end of the eleventh switch tube outputs the detection current.

9. The inductor current zero-crossing detection system according to claim 1 , wherein the logic processing module comprises an inverter and an RS flip-flop, wherein an input terminal of the inverter receives a comparison result between the detection current and the reference current, a set terminal of the RS flip-flop is connected to an output terminal of the inverter, a reset terminal receives a PWM control signal, and a non-inverting output terminal outputs the inductor current zero-crossing signal.

10. A controller for a DC-DC converter, comprising the inductor current zero-crossing detection system according to any one of claims 1 to 9.

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