Device and method for testing detection equipment of semiconductor device

Abstract

The embodiment of the invention provides a device and a method for testing detection equipment of a semiconductor device. The device comprises a semiconductor substrate; the defect pattern is located on the semiconductor substrate; and a positioning pattern on the semiconductor substrate and disposed adjacent to the defect pattern. In this way, the device integrating the defect pattern and the positioning pattern is provided, the device can be used for conducting defect detection performance testing and can also be used for testing the positioning capacity of detection equipment, and samples do not need to be replaced according to different testing contents.

Description

Technical Field

[0001] The present disclosure generally relates to the field of chip testing tools, and more particularly to an apparatus, method, electronic device, computer-readable storage medium, computer program product, and chip for testing a detection device of a semiconductor device. Background Art

[0002] Electronic design automation (EDA) software is widely used in chip design. With various EDA software, engineers can easily carry out chip design, such as architecture design and register-transfer-level (RTL) code design, synthesis, design for test (DFT), physical development, and signoff. With the help of various manufacturing equipment and testing technologies, engineers can also easily manufacture chips.

[0003] The manufacture of semiconductor devices requires high-precision equipment, such as semiconductor electron beam detection equipment. As the detection equipment is used, some deviations or performance degradation may occur, so the detection equipment needs to be tested and calibrated. For example, the testing and calibration of semiconductor electron beam detection equipment includes many aspects such as electron optical testing, detector performance testing, alignment error testing, and defect detection performance testing. It is usually necessary to use samples of some semiconductor devices to test and calibrate the detection equipment. However, the current samples used for testing and calibration are not ideal. How to design standard test samples for semiconductor detection equipment requires further research. Summary of the Invention

[0004] In view of the above problems, the embodiments of the present disclosure aim to provide a device (also called a "sample") for testing detection equipment of semiconductor devices, which can integrate test patterns for multiple test functions into one, has flexible size, and is convenient for testing detection equipment during acceptance, daily use, and regular maintenance, thereby reducing testing costs.

[0005] According to a first aspect of the present disclosure, an apparatus for testing a detection device of a semiconductor device is provided, comprising: a semiconductor substrate; a defect pattern located on the semiconductor substrate; and a positioning pattern located on the semiconductor substrate and arranged adjacent to the defect pattern.

[0006] In this way, a device integrating defect patterns and positioning patterns is provided, which can be used for both defect detection performance testing and positioning capability testing of detection equipment, without the need to replace samples for different test contents.

[0007] In some embodiments of the first aspect, the apparatus further comprises: an electron optical test pattern located on the semiconductor substrate and arranged adjacent to the defect pattern; and a two-dimensional grating pattern located on the semiconductor substrate and arranged adjacent to the defect pattern, the positioning pattern, and the electron optical test pattern.

[0008] In this way, the apparatus provided by the embodiments of the present disclosure can also be used to perform electronic optical testing, as well as to test the deformation field and image stitching error of the detection equipment.

[0009] In some embodiments of the first aspect, the defect pattern includes one or more basic units, and at least a portion of the one or more basic units includes defects.

[0010] In this way, basic units for generating defect patterns are provided, and it can be designed so that some basic units include defects while other basic units do not, thereby providing samples with different defect patterns.

[0011] In some embodiments of the first aspect, the defects in the first basic unit and the second basic unit in the one or more units are different in one or more of the following: the number of defects; the defect structure; the defect type; the defect size; and the location of the defect in the basic unit.

[0012] In this way, it can be designed so that basic units having different defect patterns are provided, thereby enabling the formation of samples having different defect patterns.

[0013] In some embodiments of the first aspect, each of the one or more basic cells comprises one of the following: a dot pattern; a line pattern; a static random access memory (SRAM) pattern; and a logic pattern.

[0014] In this way, four basic units for defect patterns are provided.

[0015] In some embodiments of the first aspect, a size of the defect is 10% to 80% of a critical size of the basic unit.

[0016] In this way, the size of the defects can be adjusted and a wider size range can be covered.

[0017] In some embodiments of the first aspect, the positioning pattern includes one or more basic units, and each of the one or more basic units includes a positioning block and a coding block, the positioning block is used to determine the relative position of the center of the imaging field of view in the positioning pattern, and the coding block is used to determine the absolute coordinate position of the center of the imaging field of view.

[0018] In this way, a basic unit for generating a positioning pattern and its specific structure are provided, which can accurately locate the absolute position of the center of the imaging field of view and expand the size of the entire positioning pattern to any area.

[0019] In some embodiments of the first aspect, the coding block includes one or more binary coding blocks, and each of the one or more binary coding blocks is located to the right of or above the positioning block.

[0020] In this way, a specific arrangement of coding blocks and positioning blocks in the positioning pattern is provided.

[0021] In some embodiments of the first aspect, the critical size of the positioning block is larger than the critical size of the encoding block.

[0022] In this way, by setting the positioning block to a larger size, it is helpful to quickly identify the relative position of the center of the imaging field of view in the positioning pattern.

[0023] In some embodiments of the first aspect, a critical dimension of the positioning block is 400 nm, a critical dimension of the encoding block is 150 nm, and a repetition interval of the positioning block is 2 um.

[0024] In this way, better sizes and repetition intervals of the positioning block and the encoding block are provided to more accurately locate the absolute position of the center of the imaging field of view.

[0025] In some embodiments of the first aspect, the electronic optical test pattern includes one or more basic units, each basic unit includes one or more sub-units, each sub-unit includes one or more micro units, and each micro unit includes one of the following: a vertical stripe pattern; a horizontal stripe pattern; a dot matrix pattern; and a triangular matrix pattern.

[0026] In this way, a basic unit for generating an electro-optical test pattern and its specific structure are provided, which can perform various electro-optical tests on a detection device.

[0027] In some embodiments of the first aspect, the pattern in each sub-unit in each basic unit has a different critical dimension.

[0028] In this way, patterns with different critical dimensions can be used for electronic optical testing, which helps to improve the accuracy of the detection equipment.

[0029] In some embodiments of the first aspect, each sub-unit has a positioning mark, and the positioning mark indicates a critical dimension of the pattern in the sub-unit where the positioning mark is located.

[0030] In this manner, a method for determining critical dimensions of an electro-optical test pattern is provided.

[0031] In some embodiments of the first aspect, the positioning mark includes a cross mark and a small square, and the relative positions of the cross mark and the small square indicate the critical dimension of the pattern in the subunit where the cross mark and the small square are located.

[0032] In this way, a specific method for determining the critical dimension of an electronic optical test pattern is provided, which can conveniently perform the determination of the critical dimension.

[0033] In some embodiments of the first aspect, the detection device includes a multi-electron beam test system, the multi-electron beam test system includes multiple electron beams, and the distance between adjacent electron beams in the multiple electron beams is equal to the distance between adjacent patterns in the electronic optical test pattern.

[0034] In this way, the device provided by the embodiment of the present disclosure can be used in multi-electron beam detection equipment, and the repetition interval of the electron optical test pattern is adapted to the interval of the electron beam, ensuring that all electron beams can observe the same electron optical test pattern at the same time, thereby improving test efficiency.

[0035] In some embodiments of the first aspect, the two-dimensional grating pattern comprises one or more lattice grating units.

[0036] In this way, a specific structure of a two-dimensional grating pattern is provided, which can test the deformation field and image stitching error of the detection equipment.

[0037] In some embodiments of the first aspect, the one or more lattice grating units have one or more sizes.

[0038] In this way, the deformation field and image stitching error of the detection equipment can be tested for various sizes, thereby improving the detection accuracy of the detection equipment.

[0039] In some embodiments of the first aspect, the device is a whole wafer or a single chip.

[0040] In this way, the form and size of the device can be made flexible. It can be used as a whole wafer for overall detection by detection equipment, or it can be embedded in the detection equipment as a single chip, and can be flexibly adapted to detection equipment with different structures.

[0041] According to a second aspect of the present disclosure, a method for testing a semiconductor device inspection device is provided. The method comprises: causing the inspection device to photograph the defect pattern in the apparatus according to the first aspect to obtain one or more images; and determining, based on an analysis of the one or more images, the capture rate of defects of different sizes in the defect pattern by the inspection device.

[0042] In this manner, a method for performing defect inspection on a semiconductor inspection device is provided.

[0043] According to a third aspect of the present disclosure, a method for testing a semiconductor device inspection device is provided. The method comprises: causing the inspection device to inspect the defect pattern in the apparatus according to the first aspect N times; determining the number of intersections and the number of unions of defects captured by the N inspections; and determining the inspection repeatability of the inspection device based on the number of intersections and the number of unions, where N is an integer greater than or equal to 2.

[0044] In this manner, a method for determining the repeatability of defect detection by semiconductor inspection equipment is provided.

[0045] According to a fourth aspect of the present disclosure, a method for testing a semiconductor device inspection device is provided. The method comprises: causing the inspection device to photograph the positioning pattern in the apparatus according to the first aspect to obtain one or more images; determining the relative position of the center of the imaging field of view within the positioning pattern based on the positioning blocks in the positioning pattern; and determining the absolute coordinate position of the center of the imaging field of view based on the encoding blocks in the positioning pattern.

[0046] In this way, a method for performing positioning accuracy inspection on semiconductor inspection equipment is provided.

[0047] In some embodiments of the fourth aspect, the method further includes: moving the field of view of the detection device from a first position to a second position multiple times continuously, wherein the first position is a starting position and the second position is a target position; based on the positioning block and the encoding block, determining a third position to which the detection device actually moves each time; and determining a positioning error of the detection device based on an error between the second position and the third position.

[0048] In this way, the positioning capability of the detection device can be quantified and the overall positioning error of the detection device can be determined.

[0049] According to a fifth aspect of the present disclosure, a method for testing semiconductor device testing equipment is provided. The method comprises: adjusting the height of a translation stage in the testing equipment, the translation stage supporting the apparatus according to the first aspect; causing each of at least one electron beam in the testing equipment to capture an electron optical test pattern in the apparatus at different translation stage heights, thereby obtaining one or more images; and calculating the sharpness of each electron beam based on the one or more images.

[0050] In this way, a method for performing electronic optical testing on a semiconductor testing device is provided, which is capable of measuring the focus height consistency of the testing device.

[0051] According to a sixth aspect of the present disclosure, a method for testing a semiconductor device inspection device is provided. The method comprises: causing the inspection device to photograph the two-dimensional grating pattern in the apparatus according to the first aspect to obtain one or more images; stitching the one or more images together; and determining an image stitching error of the inspection device based on the offset between grating stripes in the two-dimensional grating pattern.

[0052] In this way, a method for detecting image stitching errors in semiconductor testing equipment is provided.

[0053] According to the seventh aspect of the present disclosure, an electronic device is provided, comprising at least one processor and at least one memory, wherein the at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, and when the instructions are executed by the at least one processor, the electronic device performs operations according to the method in any one of the second to sixth aspects above.

[0054] According to an eighth aspect of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the operations of the method according to any one of the above-mentioned second to sixth aspects are implemented.

[0055] According to a ninth aspect of the present disclosure, a computer program or computer program product is provided. The computer program or computer program product is tangibly stored on a computer-readable medium and includes computer-executable instructions that, when executed, implement the operations of the method according to any one of the second to sixth aspects above.

[0056] According to a tenth aspect of the present disclosure, a chip or a chip system is provided, which includes a processing circuit configured to perform the operation of the method according to any one of the second to sixth aspects.

[0057] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown in an illustrative and non-limiting manner.

[0059] Figure 1 An example flow chart showing the chip design and manufacturing process;

[0060] Figure 2 A schematic structural diagram of an apparatus for testing a detection device of a semiconductor device according to some embodiments of the present disclosure is shown;

[0061] Figure 3A A schematic diagram illustrating a basic unit of a defect pattern according to some embodiments of the present disclosure is shown.

[0062] Figure 3B Schematic diagrams illustrating various defective basic units of defect patterns according to some embodiments of the present disclosure.

[0063] Figure 4A A schematic diagram showing the internal arrangement of defect patterns according to some embodiments of the present disclosure;

[0064] Figure 4B A schematic diagram showing a further refined internal arrangement of a defect pattern according to some embodiments of the present disclosure.

[0065] Figure 5A A schematic diagram illustrating a basic unit of a positioning pattern according to some embodiments of the present disclosure is shown;

[0066] Figure 5B A schematic diagram illustrating an encoding method of a coding block of a positioning pattern according to some embodiments of the present disclosure is shown;

[0067] Figure 6 A schematic diagram illustrating a basic unit of an electron optical detection pattern according to some embodiments of the present disclosure;

[0068] Figure 7 shows a schematic diagram of a two-dimensional grating pattern according to some embodiments of the present disclosure;

[0069] Figure 8 An example flow chart of a method for performing defect detection on a detection device of a semiconductor device according to some embodiments of the present disclosure is shown;

[0070] Figure 9 An example flow chart showing a method for testing the repeatability of defect detection performed by a detection device of a semiconductor device according to some embodiments of the present disclosure is shown;

[0071] Figure 10 A schematic diagram is shown for testing the repeatability of defect detection of a semiconductor device detection device according to some embodiments of the present disclosure;

[0072] Figure 11 An example flow chart of a method for performing positioning accuracy testing on a testing device for a semiconductor device according to some embodiments of the present disclosure is shown;

[0073] Figure 12 An exemplary flow chart illustrating a method for performing electron optical inspection on an inspection device for a semiconductor device according to some embodiments of the present disclosure is shown;

[0074] Figure 13 A schematic diagram showing the change in sharpness of each electron beam in a multi-electron beam detection device as it scans in the Z direction according to some embodiments of the present disclosure;

[0075] Figure 14 An example flow chart of a method for detecting image stitching errors in a semiconductor device inspection device according to some embodiments of the present disclosure is shown;

[0076] Figure 15A A schematic diagram showing an uncorrected image stitching error between different pictures obtained using a two-dimensional grating pattern according to some embodiments of the present disclosure;

[0077] Figure 15B A schematic diagram showing that image stitching errors between different pictures obtained using a two-dimensional grating pattern have been corrected according to some embodiments of the present disclosure; and

[0078] Figure 16 A schematic block diagram of an example device that can be used to implement embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0079] The principles and spirit of the present disclosure will be described below with reference to several exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these specific embodiments is only intended to enable those skilled in the art to better understand and implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those of ordinary skill in the art.

[0080] The term "including" and its variations used in this document indicate open inclusion, that is, "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one other embodiment". Terms such as "upper", "lower", "front", and "rear" indicating placement or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the principles of the present disclosure, and do not indicate or imply that the referred elements must have a specific orientation, be constructed or operate in a specific orientation, and therefore should not be understood as limiting the present disclosure.

[0081] Figure 1 A flowchart illustrating an example chip design and manufacturing process 100 is shown. The design and manufacturing process 100 begins with specification development 110. During specification development 110, the functional and performance requirements for the integrated circuit are determined. During chip design 120, circuit design is performed using EDA software to obtain, for example, a layout file for chip manufacturing. Depending on the type of circuit (e.g., digital or analog), design 120 may include different design steps. During manufacturing 140, integrated circuits are formed on wafers through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. During packaging 150, the wafers are cut to obtain bare dies, which are then packaged through processes such as bonding, soldering, and molding to produce chips. The resulting chips are tested during testing 160 to ensure that the performance of the finished chips meets the requirements determined in specification development 110. Chips that pass the tests 170 can be delivered to customers. It should be understood that the above process is merely illustrative and does not limit the scope of this disclosure. In some cases, the chip design and manufacturing process may vary. For example, a tape-out may be performed before manufacturing 140. A small number of chips obtained from the tape-out may be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates that the tape-out has failed and the chip design may need to be adjusted or redesigned.

[0082] In some embodiments, the design 120 of the digital circuit may illustratively include architecture design 121, RTL design 123, functional simulation 125, synthesis 127, timing analysis 129, DFT 131, verification check 133, layout and routing 135, design rule check (DRC) 137, and layout generation 139. Architecture design 121, for example, includes designing the architecture of the chip. For example, EDA software can be used to determine the types and number of components or sub-circuits included in the chip system, as well as the functions, connections, and interactions of each component or sub-circuit. At the stage of RTL design 123, a hardware programming language such as Verilog or VHDL can be used to describe the determined chip architecture in code at the RTL level. Functional simulation 125 is also called RTL-level behavioral simulation or front-end simulation. The purpose of functional simulation is to analyze the correctness of the logical relationship of the design circuit. Synthesis 127 can convert the RTL into a gate-level netlist. Synthesis 127 may include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis may first convert the RTL code into a general Boolean equation and compile it. The netlist may be optimized based on constraints imposed by the designer, such as delay and area, and then the RTL netlist may be mapped to the process library to generate a gate-level netlist.

[0083] Timing analysis 129 includes static timing analysis, which primarily involves calculating and predicting the timing of digital circuits. Timing analysis of paths within digital circuits determines whether timing closure has been achieved, thereby ensuring that the timing of various circuits meets various timing requirements. This type of digital circuit verification is typically performed statically and does not require simulation of digital logic. During the DFT 131 stage, various hardware logics can be embedded in the design to improve chip testability (including controllability and observability). Using this logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits. DFT can, for example, include scan chain-based testing methods or built-in self-test (BIST). During the verification check 133 stage, the circuit can be formally verified and / or subjected to equivalence checking. Formal verification can use mathematical methods to prove the correctness or incorrectness of a circuit based on one or more formal specifications or properties. Formal verification can include, for example, abstract interpretation, formal model checking (also known as property checking), and theorem proving. Equivalence checking can be used to verify whether the register transfer level design is consistent with the gate-level netlist, and between gate-level netlists.

[0084] In the stage of layout and routing 135, the chip circuit can be laid out (placement) and routed (routing). The layout can reasonably arrange the gate-level netlist generated by logic synthesis 127 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing generally expects the total routing to be short, the routing delay to meet timing requirements, and to comply with process routing rules (such as routing density). Although layout and routing are described separately here, this is only illustrative and does not limit the scope of this disclosure. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.

[0085] During the DRC 137 stage, the layout can be checked for potential open circuits, short circuits, or adverse effects that violate design rules. After passing the DRC, a file representing the layout, such as a GDSII file, an OASIS file, or the like, can be generated 139 by the EDA software. It will be understood that the above steps are merely exemplary and do not limit the scope of the present disclosure. In the actual design process, the above steps can be added, deleted, or modified according to design needs. In addition, some of the above steps can be implemented by different EDA software or integrated into one or more EDA software. The present disclosure is not limited to this.

[0086] As mentioned above, in order to obtain high-precision semiconductor electron beam detection equipment, it is necessary to perform multiple tests and calibrations on it, and different tests may be required at different times (for example, acceptance, routine testing, and regular maintenance). However, existing test samples are usually only for a single test, and different tests require the replacement of different test samples. There is a lack of unified standard samples for testing semiconductor electron beam detection equipment. Moreover, the existing test samples come in a variety of sizes and are not customized for semiconductor electron beam detection equipment, and may not be able to adapt to semiconductor electron beam detection equipment. Therefore, it is necessary to study standard test samples for semiconductor electron beam detection equipment.

[0087] In order to solve or alleviate the above-mentioned problems and potential other problems, a device (i.e., a "sample") for testing semiconductor device detection equipment is proposed in each embodiment of the present disclosure. The device is designed to integrate test patterns for multiple test functions into one, and has flexible size to facilitate testing of detection equipment during acceptance, daily use, and regular maintenance, reduce testing costs, and solve some other potential problems.

[0088] Figure 2 FIG. 2 shows a schematic structural diagram of an apparatus (sample) 200 for testing a semiconductor device detection device according to some embodiments of the present disclosure. Figure 2 As shown, the device 200 includes a semiconductor substrate 210, a defect pattern 220, and a positioning pattern 230. The defect pattern 220 is located on the semiconductor substrate 210. The positioning pattern 230 is located on the semiconductor substrate 210 and is arranged adjacent to the defect pattern 220. In some embodiments, the device 200 may further include an electron optical test pattern 240 and two-dimensional grating patterns 250-1 and 250-2. The electron optical test pattern 240 is located on the semiconductor substrate 210 and is arranged adjacent to the defect pattern 220. The two-dimensional grating patterns 250-1 and 250-2 are located on the semiconductor substrate 210 and are arranged adjacent to the defect pattern 220, the positioning pattern 230, and the electron optical test pattern 240.

[0089] It should be understood that Figure 2 The device may include other additional patterns and modules not shown, or may omit some of the patterns shown. Figure 2 The number of each pattern in the device can be one or more, and the arrangement position of each pattern can be adjusted. The scope of the present disclosure is not limited to this. For ease of understanding, the following will be combined with Figures 3A to 15B right Figure 2 Provide explanation.

[0090] Defect pattern 220 can be used to test the defect detection performance of semiconductor inspection equipment. To measure the detection equipment's capture rate and false capture rate for different defects, the present disclosure constructs a basic defect repeating unit, thereby providing a defect pattern with defects of different structures, types, sizes, and densities. Defect pattern 220 can include one or more basic units, and at least a portion of the one or more basic units include defects. In this way, basic units for generating defect patterns are provided, and can be designed so that some basic units include defects while others do not, thereby providing samples with different defect patterns.

[0091] Figure 3A Schematic diagram showing a basic unit of a defect pattern according to some embodiments of the present disclosure. Figure 3A As shown, each basic unit may include one of the following: a dot pattern; a line pattern; a static random access memory (SRAM) pattern; and a logic pattern.

[0092] Figure 3B Schematic diagrams of various defective basic units according to defect patterns of some embodiments of the present disclosure are shown. In some embodiments, one or more of the following defects in the first basic unit and the second basic unit in one or more units may be different: the number of defects; the defect structure; the defect type; the defect size; and the location of the defect in the basic unit. Defects may, for example, include various types such as residues, voids, protrusions, intrusions, openings, bridges, and displacements. The size of the defect can be set arbitrarily. As an example, the size of the defect can be 10% to 80% of the critical dimension (CD) of the basic unit, so that the size of the defect can be adjusted to cover a wider range of sizes. Figure 3 shows that 12 basic units containing different defects are designed for each of the four pattern types: dot matrix, linear, SRAM, and logic. In this way, it can be designed to provide basic units with different defect patterns, so that samples with different defect patterns can be formed.

[0093] In some embodiments, the ratio of defect-free basic units to defective basic units can be adjusted to any ratio to generate defect patterns with varying defect densities. The defect density represents the ratio of defective basic units to all basic units in the defect pattern. For example, a defect density of 5% indicates that defective basic units account for 5% of all basic units in the defect pattern.

[0094] Figure 4AA schematic diagram illustrating the internal arrangement of a defect pattern 400A according to some embodiments of the present disclosure is shown. As shown in FIG4 , the defect pattern 400A includes four types of patterns, and each type of pattern has four partitions, corresponding to critical dimensions of 30 nm, 50 nm, 100 nm, and 200 nm, respectively.

[0095] In some embodiments, each partition has four small areas, each small area may have defect patterns of different densities, and the four small areas have different orientations, so that the semiconductor inspection equipment's ability to capture defects with different orientations can be verified. Figure 4B A schematic diagram showing a further refined internal arrangement of a defect pattern according to some embodiments of the present disclosure.

[0096] Figure 4B That is, the internal arrangement corresponding to each partition, for example Figure 4A The internal arrangement of the 30nm partition of the dot matrix. Figure 4B As shown, it includes four small areas with different orientations, and each small area further contains four defect patterns with different densities.

[0097] Positioning pattern 230 can be used to test the positioning capability of semiconductor testing equipment. To measure the positioning capability of the testing equipment, it is necessary to know the precise position of the center of the imaging field of view of the testing equipment at any time. The present disclosure constructs a positioning pattern to calculate the precise position of the current imaging field of view center through image recognition.

[0098] Figure 5A Schematic diagram of a basic unit of a positioning pattern according to some embodiments of the present disclosure is shown. Figure 5A As shown, the positioning pattern includes one or more basic units, and each of the one or more basic units includes a positioning block and a coding block. Figure 5A The right side shows an enlarged view of a basic unit and the positioning block and coding block therein. The positioning block can be used to determine the relative position of the center of the imaging field of view in the positioning pattern, thereby achieving a rough positioning of the center of the imaging field of view. The coding block is used to determine the absolute coordinate position of the center of the imaging field of view, thereby achieving a precise positioning of the center of the imaging field of view. As an example, the positioning block can be a square block, and the coding block can include one or more binary coding blocks, and each of the one or more binary coding blocks can be located to the right or above the positioning block. The critical dimension of the positioning block can be larger than the critical dimension of the coding block, which helps to quickly identify the relative position of the center of the imaging field of view in the positioning pattern. As an example, the critical dimension of the positioning block can be 400nm, the critical dimension of the coding block can be 150nm, and the repetition interval of the positioning block can be 2um. In this way, better sizes and repetition intervals of the positioning block and the coding block are provided to more accurately locate the absolute position of the center of the imaging field of view.

[0099] Figure 5B A schematic diagram illustrating a coding method for coding blocks of positioning patterns according to some embodiments of the present disclosure is shown. The coding block of each basic unit is represented by two parts: a binary coding block above the positioning block and a binary coding block to the right of the positioning block.

[0100] As an example, the X-direction code is represented by the code block above the positioning block, where H1, H2, and H3 represent the binary code of the code block above. The area with a circular hole represents 1, and the area without a circular hole represents 0. After horizontally splicing H3, H2, and H1, the binary code of the code block above is formed. Figure 5B The X-direction code of the positioning block is: 0110 10100010.

[0101] The Y-direction code is represented by the code block to the right of the positioning block, where V1, V2, and V3 represent the binary code of the code block to the right. V3, V2, and V1 are rotated up and down and then spliced vertically to form the binary code of the code block to the right. Figure 5B The Y direction code of the positioning block is: 0110 1010 0011.

[0102] By using the above example of encoding blocks and positioning blocks, the entire positioning pattern can be expanded to any area. In this way, the electron beam detection device can capture any position of the positioning pattern and accurately locate the absolute position of the center of the imaging system's field of view at that time.

[0103] The electro-optical test pattern 240 may be used to test the electro-optical performance of a semiconductor testing device. Figure 6 FIG. 6 is a schematic diagram showing a basic unit 600 of an electron optical detection pattern according to some embodiments of the present disclosure. The electron optical detection pattern includes Figure 6 One or more basic units 600 are shown, each of which includes one or more subunits (e.g., 610-1 to 610-4), each of which includes one or more microunits. Each microunit includes one of the following: a vertical stripe pattern; a horizontal stripe pattern; a dot matrix pattern; and a triangular matrix pattern. The vertical and horizontal stripe patterns can be used for magnification calibration testing, while the dot matrix and triangular matrix patterns can be used for resolution and astigmatism testing. Thus, a basic unit for generating electro-optical test patterns and its specific structure are provided, enabling various electro-optical tests on detection equipment.

[0104] In some embodiments, the patterns in each subunit of each basic unit 600 can have different critical dimensions, such as 50nm, 100nm, 200nm, and 600nm. In this way, patterns with different critical dimensions can be used for electronic optical testing, which helps to improve the accuracy of the detection equipment. In some embodiments, the patterns in each subunit can be arranged according to a 50% duty cycle, and the spacing within the pattern (for example, the spacing between two vertical stripes of a vertical stripe pattern) can be 100nm to 1200nm.

[0105] refer to Figure 6 As an example, each basic unit 600 may include four subunits 610-1 to 610-4, each subunit including four 40um*40um micro units. The critical dimensions of the patterns inside the subunits 610-1 to 610-4 are 50um, 100nm, 200nm, and 600nm, respectively.

[0106] In some embodiments, each subunit has a positioning mark that indicates the critical dimension of the pattern in the subunit in which it is located. Thus, a method for determining the critical dimension of an electronic optical test pattern is provided. Figure 6 As shown, the positioning mark can include a cross mark and a small square, and the relative position of the cross mark and the small square indicates the critical dimension of the pattern in the subunit where they are located. For example, in subunit 610-1, if the small square is located to the left of the cross mark, it indicates that the critical dimension of the pattern within subunit 610-1 is 50 μm; in subunit 610-2, if the small square is located above the cross mark, it indicates that the critical dimension of the pattern within subunit 610-2 is 100 μm; in subunit 610-3, if the small square is located to the right of the cross mark, it indicates that the critical dimension of the pattern within subunit 610-3 is 200 μm; in subunit 610-4, if the small square is located below the cross mark, it indicates that the critical dimension of the pattern within subunit 610-4 is 600 μm. In this way, a specific method for determining the critical dimension of an electronic optical test pattern is provided, which can conveniently perform critical dimension determination.

[0107] In some embodiments, the semiconductor detection equipment includes a multi-electron beam test system, which includes multiple electron beams, and the distance between adjacent electron beams in the multiple electron beams is equal to the distance between adjacent patterns in the electron optical test pattern. For example, assuming that the distance between adjacent electron beams in the multiple electron beams is 160um, it can be designed so that the distance between adjacent patterns in the electron optical test pattern is also 160um. In this way, the sample provided by the embodiment of the present disclosure can be used for multi-electron beam detection equipment, and the repetition interval of the electron optical test pattern is adapted to the interval of the electron beams, ensuring that all electron beams can observe the same electron optical test pattern at the same time, thereby improving test efficiency.

[0108] The two-dimensional grating patterns 250 - 1 and 250 - 2 may be used to test the deformation field and / or image stitching error of a semiconductor testing device. Figure 7 A schematic diagram of a two-dimensional grating pattern 700 according to some embodiments of the present disclosure is shown. The two-dimensional grating pattern includes one or more grating units, and the one or more grating units can have one or more sizes. As an example, the side length D1 of the grating pattern can be 400nm or 1000nm, and the spacing D2 of the grating pattern can be 100nm or 300nm. In this way, the deformation field and image stitching error of the detection equipment can be tested for various sizes, thereby improving the detection accuracy of the detection equipment.

[0109] In some embodiments, the device (sample) according to the embodiments of the present disclosure can be a whole wafer or a single chip. This allows for flexibility in form and size, allowing the device to be used as a whole wafer for overall testing in a testing device or as a single chip embedded in a testing device, allowing for flexible adaptation to testing devices with different structures.

[0110] By using the device described in accordance with the above embodiment, test patterns for multiple test functions are integrated into a single device, and the device size is flexible, which facilitates testing of the detection equipment during acceptance, daily use, and regular maintenance, thereby reducing testing costs. As an example, the device described in accordance with the above embodiment can be used to perform defect detection performance testing on semiconductor detection equipment, including: defect capture rate and false capture rate testing, detection performance boundary testing, throughput testing, measurement system repeatability and reproducibility (gauge repeatability & reproducibility, GRR) testing, etc. The device described in accordance with the above embodiment can also be used to perform alignment error testing on semiconductor detection equipment, including: positioning accuracy testing, repeated positioning error testing, etc. The device described in accordance with the above embodiment can also be used to perform electronic optical performance testing on semiconductor detection equipment, including: resolution testing, signal-to-noise ratio (SNR) testing, contrast-to-noise ratio (CNR), magnification testing, focus height consistency testing, image centering testing, scanning step error testing, beam array consistency testing, deformation field testing, grayscale consistency testing, orthogonality of output (whether there is an angle between different beam outputs) testing, electromagnetic interference (EMI) testing, rigidity drift testing, etc. The device described according to the above embodiment can also be used to perform detector performance tests on semiconductor detection equipment, including: detector performance consistency test, secondary electron collection efficiency test (when the walking distance (WD) and landing energy (LE) are constant, adjust the voltage of the projection lens (PL) to find the highest collection efficiency) test, etc.

[0111] The following will be combined Figures 8 to 15B The following specifically introduces an example process of performing various tests using the device disclosed herein.

[0112] Figure 8 FIG. 8 is an example flow chart of a method 800 for performing defect detection on a detection device of a semiconductor device according to some embodiments of the present disclosure. It should be understood that Figure 8 The method may include other additional steps not shown, or some steps shown may be omitted. The scope of the present disclosure is not limited thereto.

[0113] In 810 , the inspection device is caused to photograph the defect pattern 220 in the apparatus according to the present disclosure to obtain one or more images. Next, in 820 , based on analysis of the one or more images, the detection device's capture rate for defects of different sizes in the defect pattern 220 is determined.

[0114] For a designed device, the size and number of defects it contains are known. As an example, the capture rates of defects of different sizes in the defect pattern 220 by the inspection equipment can be statistically analyzed as shown in Table 1.

[0115] Table 1

[0116]

[0117] The size x represents the size of the defect in the X direction (horizontal direction), and the size y represents the size of the defect in the Y direction (vertical direction).

[0118] Based on the statistical results shown in Table 1, we can determine the capture sensitivity and detection boundaries of current semiconductor inspection equipment for defects of different sizes. For example, assuming the threshold for determining the detection boundary is 50%, the statistical results show that the smallest defect size with a capture rate greater than 50% is the detection boundary.

[0119] In some embodiments, the detection capabilities of different detection devices can be compared. As an example, assuming there are three detection devices A, B, and C, based on the statistical results shown in Table 1, the detection capabilities of the three detection devices can be quantitatively compared, as shown in Table 2.

[0120] Table 2

[0121]

[0122] In Table 2, M0 to M5 represent sizes of different defects from small to large. Table 2 shows the capture rate, average capture rate, and average interference rate of the detection equipment for defects of sizes M0 to M5. The capture rate of the detection equipment for defects of sizes M0 to M5 represents the ratio of the number of defects captured to the total number of defects of that size for each size in M0 to M5. For example, a capture rate of 50% for defects of size M0 of detection equipment A may be the ratio of 50 defects captured of size M0 to 100 total number of defects of that size. The average capture rate represents the ratio of the total number of defects captured by the detection equipment for defects of sizes M0 to M5 to the total number of defects of sizes M0 to M5. The average interference rate represents the ratio of the total number of defects mistakenly captured by the detection equipment for defects of sizes M0 to M5 to the total number of defects of sizes M0 to M5.

[0123] As shown in Table 2, Inspection Device A has the highest average capture rate, indicating good defect recognition performance, but also has a high average interference rate, indicating a high probability of false detection. Furthermore, Inspection Device A has the best detection margin, identifying over 50% of defects with a minimum size of M0. Inspection Device C has the worst detection margin, identifying only over 70% of defects with a size of M3. Although Inspection Device B has a higher average capture rate than Inspection Device C, and its detection margin is superior to that of Inspection Device C, Inspection Device C has a lower average interference rate.

[0124] Figure 9 FIG. 9 is an example flow chart of a method 900 for testing the repeatability of defect detection of a semiconductor device detection device according to some embodiments of the present disclosure. It should be understood that Figure 9 The method may include other additional steps not shown, or some steps shown may be omitted. The scope of the present disclosure is not limited thereto.

[0125] At 910, the inspection equipment performs N inspections on the defect pattern 220 in the apparatus according to the present disclosure. Next, at 920, the number of intersections and the number of unions of defects detected during the N inspections are determined. At 930, the inspection repeatability of the inspection equipment is determined based on the number of intersections and the number of unions. N is an integer greater than or equal to 2. In this way, the repeatability of defect inspection performed by the semiconductor inspection equipment can be determined.

[0126] Figure 10 A schematic diagram is shown for testing the repeatability of defect detection for a semiconductor device inspection device according to some embodiments of the present disclosure. As an example, assume that the inspection device performs three inspections on a defect pattern 220 in an apparatus according to the present disclosure. The number of defects captured in each of the three inspections (i.e., the number of intersections of defects) is determined, such as the number of black ellipses shown in 1010 to 1030. The total number of defects captured in the three inspections (i.e., the number of unions of defects) is determined. Then, the ratio of the number of intersections of defects to the number of unions of defects is calculated to determine the repeatability of the defect detection.

[0127] In some embodiments, the repeatability of different detection devices can be quantitatively compared, as shown in Table 3.

[0128] Table 3

[0129]

[0130] In Table 3, it can be seen that inspection device A has the worst defect detection repeatability, and inspection device C has the best defect detection repeatability.

[0131] Figure 11FIG1 shows an example flow chart of a method 1100 for performing positioning accuracy detection on a detection device of a semiconductor device according to some embodiments of the present disclosure. It should be understood that Figure 11 The method may include other additional steps not shown, or some steps shown may be omitted. The scope of the present disclosure is not limited thereto.

[0132] At 1110, the inspection equipment captures the positioning pattern 230 in the apparatus according to the present disclosure, obtaining one or more images. At 1120, the relative position of the center of the imaging field of view within the positioning pattern 230 is determined based on the positioning blocks in the positioning pattern 230. Next, at 1130, the absolute coordinate position of the center of the imaging field of view is determined based on the encoding blocks in the positioning pattern 230. This allows for positioning accuracy testing of semiconductor inspection equipment.

[0133] In some embodiments, method 1100 further includes: moving the field of view of the detection device from the first position to the second position continuously for multiple times, wherein the first position is the starting position and the second position is the target position; based on the positioning block and the coding block, determining the third position to which the detection device actually moves each time; and based on the error between the second position and the third position, determining the positioning error of the detection device. As an example, the field of view of the detection device can be moved from the starting position (X1, Y1) to the target position (X2, Y2) for multiple times continuously. Based on the shooting of the positioning pattern 230 and the analysis of the positioning block and the coding block, it is determined that the detection device moves to the actual position (X3, Y3) each time. Calculate the error between the actual position (X3, Y3) and the target position (X2, Y2) each time and its average error, so as to obtain the overall positioning error of the detection device. In this way, the positioning capability of the detection device can be quantified and the overall positioning error of the detection device can be determined.

[0134] In some embodiments, method 1100 further includes: continuously photographing a specific position of positioning pattern 230 for a long period of time, calculating the change in the position of the center of the field of view of the inspection device over time, and thereby determining the rigidity drift of the inspection device over time. In this way, the stability of the electron beam inspection device over time can be determined.

[0135] Figure 12 FIG1 shows an example flow chart of a method 1200 for performing electron optical inspection on an inspection device of a semiconductor device according to some embodiments of the present disclosure. It should be understood that Figure 12 The method may include other additional steps not shown, or some steps shown may be omitted. The scope of the present disclosure is not limited thereto.

[0136] At 1210, the height of a translation stage in a detection device, which carries a device according to the present disclosure, is adjusted. At 1220, for different translation stage heights, each of at least one electron beam in the detection device captures an electron optical test pattern 240 in the device, obtaining one or more images. Next, at 1230, the sharpness of each electron beam is calculated based on the one or more images.

[0137] Figure 13 A schematic diagram of the change in sharpness of each electron beam in a multi-electron beam detection device according to some embodiments of the present disclosure as the sharpness of each electron beam scans in the Z direction is shown. As an example, the detection device can be focused on the dot pattern area of the electron optical test pattern 240, where the spacing of the dot pattern area is the same as the spacing between different electron beams, so that the pattern seen by each beam is the same. Adjust the height of the displacement stage (i.e., the height in the Z direction), move the displacement stage from position Z1 to position Z2, and take a picture of each electron beam for each step of movement, and calculate the sharpness of the image corresponding to each electron beam accordingly. Figure 13 As shown, the height difference between the best focus of each electron beam can be intuitively seen, so that the focusing height consistency of the detection equipment can be measured.

[0138] In some embodiments, the resolution and CNR of the current image can be determined by photographing the dot matrix area of the electronic optical test pattern 240 and then processing the obtained image.

[0139] In some embodiments, the magnification of the detection device may be determined by photographing the horizontal stripe pattern and the vertical stripe pattern of the electronic optical test pattern 240 and then processing the obtained images.

[0140] Figure 14 FIG1 shows an example flow chart of a method 1400 for detecting image stitching errors in a semiconductor device inspection device according to some embodiments of the present disclosure. It should be understood that Figure 14 The method may include other additional steps not shown, or some steps shown may be omitted. The scope of the present disclosure is not limited thereto.

[0141] At 1410, a detection device is caused to capture a two-dimensional grating pattern in an apparatus according to the present disclosure to obtain one or more images. At 1420, the one or more images are stitched together. Next, at 1430, an image stitching error of the detection device is determined based on the offset between grating stripes in the two-dimensional grating pattern.

[0142] Figure 15AFIG. 1 is a schematic diagram showing an uncorrected image stitching error between different images obtained using a two-dimensional grating pattern according to some embodiments of the present disclosure. Figure 15A As shown, the stitched pictures 1510 and 1520 are stitched left and right, and there is an image stitching error between the two. Figure 15B FIG. 1 is a schematic diagram showing that the image stitching errors between different pictures obtained by using a two-dimensional grating pattern according to some embodiments of the present disclosure have been corrected. Figure 15B As shown, the image stitching error between stitched images 1510 and 1520 has been corrected. By calculating the offset of the grating stripes between stitched images 1510 and 1520, the image stitching error in the Y direction (vertical direction) of stitched images 1510 and 1520 can be determined. Similarly, when images 1510 and 1520 are stitched together, the image stitching error in the X direction (horizontal direction) of stitched images 1510 and 1520 can be determined.

[0143] In some embodiments, the detection device can be made to continuously scan and photograph the two-dimensional grating pattern, and the deformation field of the detection device can be determined by calculating the actual offset of each pixel in the photographed image based on the known actual morphology of the two-dimensional grating.

[0144] According to the above-mentioned scheme of the present disclosure, an apparatus and method for testing detection equipment of semiconductor devices are provided, which can integrate test patterns for multiple test functions into one, have flexible size, and are convenient for testing the detection equipment during acceptance, daily use, and regular maintenance, thereby reducing testing costs.

[0145] It should be noted that the above combination Figures 2 to 15B The examples are merely illustrative and should not be construed as limiting the embodiments of the present disclosure.

[0146] It should be understood that in the embodiments of the present disclosure, expressions such as "first," "second," and "third" are intended to indicate that multiple objects may be different, but do not exclude the possibility that two objects are identical. Expressions such as "first," "second," and "third" should not be construed as limiting the embodiments of the present disclosure.

[0147] It should also be understood that the above content is only intended to help those skilled in the art better understand the embodiments of the present disclosure, and is not intended to limit the scope of the embodiments of the present disclosure. Those skilled in the art may make various modifications, variations, or combinations based on the above content. Such modifications, variations, or combinations are also within the scope of the embodiments of the present disclosure.

[0148] Figure 16 A schematic block diagram of an example device 1600 is shown, which may be used to implement embodiments of the present disclosure.

[0149] As shown in the figure, device 1600 includes a central processing unit (CPU) 1601, a read-only memory (ROM) 1602, and a random access memory (RAM) 1603. CPU 1601 can perform various appropriate actions and processes according to computer program instructions stored in ROM 1602 and / or RAM 1603 or computer program instructions loaded from storage unit 1608 into ROM 1602 and / or RAM 1603. Various programs and data required for the operation of device 1600 can also be stored in ROM 1602 and / or RAM 1603. CPU 1601 and ROM 1602 and / or RAM 1603 are connected to each other via bus 1604. Input / output (I / O) interface 1605 is also connected to bus 1604.

[0150] Various components in device 1600 are connected to I / O interface 1605, including an input unit 1606, such as a keyboard and mouse; an output unit 1607, such as various types of displays and speakers; a storage unit 1608, such as a magnetic disk and optical disk; and a communication unit 1609, such as a network card, a modem, a wireless communication transceiver, etc. Communication unit 1609 allows device 1600 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0151] The CPU 1601 may be a variety of general and / or specialized processing components with processing and computing capabilities. Some examples that may be implemented include, but are not limited to, a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc., which may be referred to as a computing unit accordingly. The CPU 1601 performs the various methods and processes described above, such as methods 800, 900, 1100, 1200, and 1400. For example, in some embodiments, the various processes described above may be implemented as a computer software program, specifically an EDA program, which is tangibly contained in a computer-readable medium, such as a storage unit 1608. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1600 via the ROM 1602 and / or the RAM 1603 and / or the communication unit 1609. When the computer program is loaded into ROM 1602 and / or RAM 1603 and executed by CPU 1601, one or more steps of the process described above may be performed. Alternatively, in other embodiments, CPU 1601 may be configured to perform the various processes described above in any other appropriate manner (e.g., by means of firmware).

[0152] For example, Figure 16 The device 1600 in the embodiment may be implemented as a computing device, or may be implemented as a chip or chip system in a computing device, which is not limited in the embodiments of the present disclosure.

[0153] The present disclosure also provides a chip that may include an input interface, an output interface, and a processing circuit. In the present disclosure, the input interface and the output interface may be used to implement signaling or data interaction, while the processing circuit may be used to implement signaling or data information generation and processing.

[0154] The embodiments of the present disclosure further provide a chip system, including a processor for supporting a computing device to implement the functions involved in any of the above embodiments. In one possible design, the chip system may also include a memory for storing necessary program instructions and data. When the processor executes the program instructions, the device in which the chip system is installed implements the method involved in any of the above embodiments. Exemplarily, the chip system may be composed of one or more chips, or may include chips and other discrete devices.

[0155] An embodiment of the present disclosure further provides a processor for coupling with a memory, wherein the memory stores instructions. When the processor executes the instructions, the processor executes the methods and functions involved in any of the above embodiments.

[0156] An embodiment of the present disclosure further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the methods and functions involved in any of the above embodiments.

[0157] An embodiment of the present disclosure further provides a computer-readable storage medium having computer instructions stored thereon. When a processor executes the instructions, the processor executes the methods and functions involved in any of the above embodiments.

[0158] In general, various embodiments of the present disclosure may be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be executed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flow charts, or using some other pictorial representation, it should be understood that the blocks, devices, systems, techniques, or methods described herein may be implemented as, by way of non-limiting example, hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or a controller or other computing device, or some combination thereof.

[0159] The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product includes computer-executable instructions, such as instructions included in program modules, which are executed in a device on a real or virtual processor of a target to perform the process / method as described above with reference to the accompanying drawings. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform specific tasks or implement specific abstract data types. In various embodiments, the functionality of program modules can be combined or divided between program modules as needed. The machine-executable instructions for the program modules can be executed in local or distributed devices. In distributed devices, program modules can be located in local and remote storage media.

[0160] The computer program code for implementing the disclosed method can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device so that the program code, when executed by the computer or other programmable data processing device, causes the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code can be executed entirely on a computer, partially on a computer, as an independent software package, partially on a computer and partially on a remote computer or entirely on a remote computer or server.

[0161] In the context of the present disclosure, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like. Examples of signals may include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.

[0162] A computer-readable medium may be any tangible medium that contains or stores a program for or in connection with an instruction execution system, apparatus, or device. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of computer-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0163] In addition, although adopting specific order to describe each operation, this should be understood as not being limited to requiring such operation to be performed in the specific order shown or in sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although comprising some specific implementation details in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation also can be implemented in a plurality of implementations individually or in the mode of any suitable subcombination.

[0164] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A device for testing a semiconductor device detection device, comprising: semiconductor substrates; a defect pattern located on the semiconductor substrate; as well as A positioning pattern is located on the semiconductor substrate and is arranged adjacent to the defect pattern.

2. The apparatus according to claim 1, further comprising: an electro-optical test pattern located on the semiconductor substrate and arranged adjacent to the defect pattern; as well as A two-dimensional grating pattern is located on the semiconductor substrate and is arranged adjacent to the defect pattern, the positioning pattern, and the electro-optical test pattern.

3. The device according to claim 1 or 2, wherein: The defect pattern includes one or more basic units, and at least a portion of the one or more basic units includes defects.

4. The device according to claim 3, wherein The defects in the first and second base units of the one or more units are different from one or more of the following: Number of defects; defective structure; Defect type; defect size; and The location of the defect in the basic unit.

5. The device according to claim 3 or 4, wherein: Each of the one or more basic units includes one of the following: Dot pattern; Linear pattern; Static random access memory (SRAM) patterns; and Logical pattern.

6. The device according to any one of claims 3 to 5, wherein: The size of the defect is 10% to 80% of the critical size of the basic unit.

7. The device according to any one of claims 1 to 6, wherein: The positioning pattern includes one or more basic units, and each of the one or more basic units includes a positioning block and a coding block, the positioning block is used to determine the relative position of the center of the imaging field of view in the positioning pattern, and the coding block is used to determine the absolute coordinate position of the center of the imaging field of view.

8. The device according to claim 7, wherein The coding block includes one or more binary coding blocks, and each of the one or more binary coding blocks is located on the right side or above the positioning block. 9 . The apparatus according to claim 7 , wherein a critical size of the positioning block is larger than a critical size of the encoding block. 10 . The device according to claim 9 , wherein the critical dimension of the positioning block is 400 nm, the critical dimension of the coding block is 150 nm, and the repetition interval of the positioning block is 2 μm.

11. The device according to claim 2, wherein The electronic optical test pattern includes one or more basic units, each basic unit includes one or more subunits, each subunit includes one or more micro units, and each micro unit includes one of the following: vertical stripe pattern; horizontal striped pattern; Dot pattern; as well as Triangular array pattern.

12. The device according to claim 11, wherein The patterns in each sub-unit in each basic unit have different critical dimensions.

13. The device according to claim 12, wherein Each sub-unit has a positioning mark, and the positioning mark indicates a critical dimension of the pattern in the sub-unit where the positioning mark is located. 14 . The apparatus according to claim 13 , wherein the positioning mark comprises a cross mark and a small square, and the relative positions of the cross mark and the small square indicate the critical dimension of the pattern in the subunit where the cross mark and the small square are located.

15. The device according to any one of claims 11 to 14, wherein The detection device includes a multi-electron beam test system, which includes a plurality of electron beams. A distance between adjacent electron beams in the plurality of electron beams is equal to a distance between adjacent patterns in the electron optical test pattern.

16. The device according to claim 2, wherein The two-dimensional grating pattern includes one or more lattice grating units.

17. The device according to claim 16, wherein The one or more lattice grating elements have one or more sizes.

18. The device according to any one of claims 1 to 17, wherein: The device is either an entire wafer or a single chip.

19. A method for testing a semiconductor device detection device, comprising: causing the detection device to photograph the defect pattern in the device according to claim 1 to obtain one or more pictures; as well as Based on the analysis of the one or more pictures, a capture rate of the inspection device for defects of different sizes in the defect pattern is determined.

20. A method for testing a semiconductor device detection device, comprising: causing the inspection device to inspect the defect pattern in the apparatus according to claim 1 N times; Determine the number of intersections and unions of defects captured by the N detections; as well as determining the detection repeatability of the detection device based on the number of intersections and the number of unions, Wherein, N is an integer greater than or equal to 2.

21. A method for testing a semiconductor device detection device, comprising: causing the detection device to photograph the positioning pattern in the apparatus according to claim 1 to obtain one or more pictures; Determining the relative position of the center of the imaging field of view in the positioning pattern based on the positioning blocks in the positioning pattern; as well as Based on the coding blocks in the positioning pattern, the absolute coordinate position of the center of the imaging field of view is determined.

22. The method according to claim 21, further comprising: Moving the field of view of the detection device from a first position to a second position multiple times in succession, wherein the first position is a starting position and the second position is a target position; determining a third position to which the detection device actually moves each time based on the positioning block and the encoding block; and Based on an error between the second position and the third position, a positioning error of the detection device is determined.

23. A method for testing a semiconductor device detection device, comprising: Adjust the height of the displacement stage in the detection device, the displacement stage carries The device according to claim 2; for different stage heights, causing each of at least one electron beam in the detection device to photograph the electron optical test pattern in the apparatus to obtain one or more images; as well as The sharpness of each electron beam is calculated based on the one or more images.

24. A method for testing a semiconductor device detection device, comprising: causing the detection device to photograph the two-dimensional grating pattern in the apparatus according to claim 2 to obtain one or more pictures; splicing the one or more pictures; as well as An image stitching error of the detection device is determined based on an offset between grating stripes in the two-dimensional grating pattern.

Images