SAR radar transmission and reception synchronization system and control method thereof

Abstract

The present invention belongs to the field of remote sensing satellite communication technology and provides a SAR radar transceiver synchronization system and a control method thereof. The system includes: a clock source subsystem for providing three homologous clock signals; a signal timing subsystem for outputting, transmitting, and collecting synchronization pulse signals, as well as transmitting and collecting accompanying synchronization clock signals; a signal transmission subsystem for inserting a read modulated signal into a first continuous data stream and performing cross-clock domain and bit width conversion to obtain a transmitted digital signal; converting the transmitted digital signal to obtain a new modulated signal; a signal acquisition subsystem for converting an echo signal into an acquired digital signal and performing cross-clock domain and bit width conversion to obtain a second continuous data stream; and reading and intercepting the second continuous data stream to obtain an acquired signal. The system of the present invention does not require manual parameter configuration during testing, thereby improving the synchronization efficiency of the acquired and transmitted signals of the spaceborne SAR radar.

Description

Technical Field

[0001] The present invention relates to the technical field of remote sensing satellite communication, and in particular to a SAR radar transceiver synchronization system and a control method thereof. Background Art

[0002] In a spaceborne synthetic aperture radar (SAR) system, when the signal transmission subsystem uses a high-speed digital to analog converter (DAC) logic clock, or the signal acquisition subsystem uses a high-speed analog to digital converter (ADC) logic clock to sample the transmission (or sampling) synchronization pulses generated by the signal timing subsystem, metastable states may be sampled. This can lead to inconsistent delays between the DAC transmission timing and the ADC acquisition timing between different pulses. This can cause the echo signal's position within the sampling window to jump, affecting the SAR radar's imaging performance and even causing imaging failure.

[0003] In related technologies, in different environments, the clock frequency of the signal timing subsystem of the traditional SAR system is manually adjusted to set different operating parameters to prevent the sampling of the transmission (or sampling) synchronization pulse from being in a metastable state. When the operating temperature range of the SAR system is large, it is necessary to test the operating parameters at different temperatures, which is a huge workload. Moreover, the application scenarios of manually adjusting the clock phase are limited. For example, between multiple FPGAs of the same model, due to the influence of PVT (process, voltage, temperature) parameters, when producing batches of the same model, due to the differences in the clock phase relationship of different devices, the delay time between the external clock signal from the input pin to the internal trigger may be inconsistent, resulting in an inconsistent delay relationship between the DAC transmission timing and the ADC acquisition timing, which in turn causes the signal transmission and reception time of the spaceborne SAR system to be out of sync. Summary of the Invention

[0004] The present invention provides a SAR radar transceiver synchronization system and a control method thereof, which are used to solve the defects of the prior art in that, when the operating temperature range of the SAR system is large, the workload of manually adjusting the clock frequency of the signal timing subsystem is huge, and there is still a problem of inconsistent delay time between the external clock signal input pin and the internal trigger, which leads to inconsistent delay relationship between DAC transmission timing and ADC acquisition timing. The method of the present invention improves the synchronization efficiency of spaceborne SAR radar acquisition and transmission signals.

[0005] The present invention provides a SAR radar transmission and reception synchronization system and a control method thereof, comprising the following steps:

[0006] The clock source subsystem is used to provide the same source timing synchronization clock signal, transmit sampling clock signal and collect sampling clock signal;

[0007] The signal timing subsystem is used to use the timing synchronization clock signal as the working clock, output a periodic transmission synchronization pulse signal, delay the generation of the acquisition synchronization pulse signal, fan out the timing synchronization clock signal, and generate the transmission accompanying synchronization clock signal and the acquisition accompanying synchronization clock signal;

[0008] A signal transmission subsystem, configured to use a first clock signal as a working clock, write and read a modulated signal according to the transmission synchronization pulse signal, insert the read signal into a first continuous data stream, and perform cross-clock domain and bit width conversion to obtain a transmitted digital signal; convert the transmitted digital signal according to the transmission sampling clock signal to obtain a new modulated signal; wherein the data rate of the first continuous data stream is the same as the data rate of the read signal; the first clock signal includes a transmission accompanying synchronous clock signal and a DAC logic interaction clock signal, or a transmission accompanying synchronous clock signal;

[0009] A signal acquisition subsystem is used to use a second clock signal as a working clock, convert the echo signal into an acquisition digital signal according to the acquisition sampling clock signal, and perform cross-clock domain and bit width conversion on the acquisition digital signal to obtain a second continuous data stream; read and intercept the second continuous data stream according to the acquisition synchronization pulse signal to obtain an acquisition signal; wherein, the second clock signal includes an acquisition accompanying synchronization clock signal and an ADC logic interaction clock signal, or an acquisition accompanying synchronization clock signal; the data rate of the second continuous data stream is the same as the rate of reading the second continuous data stream, and the acquisition moment corresponding to the acquisition signal and the transmission moment corresponding to the new modulation signal have a fixed delay.

[0010] According to a SAR radar transceiver synchronization system provided by the present invention, the signal transmission subsystem includes:

[0011] A first clock management chip, configured to generate the DAC logic interaction clock signal according to the transmit sampling clock signal;

[0012] A first clock fan-out chip, configured to generate a DAC sampling clock signal according to the transmit sampling clock signal;

[0013] The transmitting FPGA chip is used to use the transmitting accompanying synchronous clock signal as the working clock, write and read the modulated signal according to the transmitting synchronous pulse signal, and insert the read signal into the first continuous data stream to obtain a third continuous data stream; use the transmitting accompanying synchronous clock signal and the DAC logic interactive clock signal as the working clock, perform cross-clock domain and bit width conversion on the third continuous data stream to obtain the transmitting digital signal;

[0014] The digital-to-analog conversion (DAC) module is used to convert the transmitted digital signal according to the DAC sampling clock signal to obtain the new modulation signal.

[0015] According to a SAR radar transceiver synchronization system provided by the present invention, the transmitting FPGA chip includes:

[0016] A first synchronous FIFO module is used to use the transmission accompanying synchronous clock signal as a working clock, write and read the modulated signal according to the transmission synchronization pulse signal, and output the read signal, wherein the instantaneous data write rate and the instantaneous data read rate of the first synchronous FIFO module are determined based on the DAC sampling rate, the frequency of the transmission accompanying synchronous clock signal, and the number of DAC quantization bits;

[0017] a transmission data insertion selection module, which uses the transmission accompanying synchronous clock signal as the working clock and is used to insert the read signal into the first continuous data stream to obtain a third continuous data stream;

[0018] A first asynchronous cross-clock FIFO module uses the transmitted accompanying synchronous clock signal as the working clock on the write side and the DAC logic interaction clock signal as the working clock on the read side. The first asynchronous cross-clock FIFO module is used to perform cross-clock domain and bit width conversion on the third continuous data stream to obtain the transmitted digital signal; wherein, the continuous data write rate of the first asynchronous cross-clock FIFO module is the same as the data rate of the second continuous data stream; the continuous data read rate of the first asynchronous cross-clock FIFO module is determined based on the DAC sampling rate, the frequency of the DAC logic interaction clock signal and the number of DAC quantization bits.

[0019] According to a SAR radar transmission and reception synchronization system provided by the present invention, the signal acquisition subsystem includes:

[0020] A second clock management chip, configured to generate the ADC logic interaction clock signal according to the acquisition sampling clock signal;

[0021] A second clock fan-out chip, configured to generate an ADC sampling clock signal according to the acquisition sampling clock signal;

[0022] An analog-to-digital conversion (ADC) module, configured to convert the echo signal according to the ADC sampling clock signal to obtain the collected digital signal;

[0023] An acquisition FPGA chip is used to use the ADC logic interaction clock signal and the acquisition accompanying synchronous clock signal as working clocks to perform cross-clock domain and bit width conversion on the acquired digital signal to obtain the second continuous data stream; using the acquisition accompanying synchronous clock signal as the working clock, the second continuous data stream is intercepted according to the acquisition synchronization pulse signal to obtain the acquisition signal.

[0024] According to a SAR radar transceiver synchronization system provided by the present invention, the acquisition FPGA chip includes:

[0025] A second asynchronous cross-clock FIFO module, wherein the writing side uses the ADC logic interaction clock signal as the working clock, and the reading side uses the acquisition accompanying synchronous clock signal as the working clock, and the second asynchronous cross-clock FIFO module is used to perform cross-clock domain and bit width conversion on the acquired digital signal to obtain the second continuous data stream; the continuous data write rate of the second asynchronous cross-clock FIFO module is determined based on the ADC sampling rate, the frequency of the ADC logic interaction clock signal and the number of ADC quantization bits, and the continuous data read rate is determined based on the ADC sampling rate, the frequency of the acquisition accompanying synchronous clock signal and the number of ADC quantization bits;

[0026] The second synchronous FIFO module is used to use the acquisition accompanying synchronous clock signal as the working clock, intercept the second continuous data stream according to the sampling window according to the acquisition synchronization pulse signal, and obtain the acquisition signal; the instantaneous data write rate and instantaneous data read rate of the second synchronous FIFO module are the same as the continuous data read rate of the second asynchronous cross-clock FIFO module.

[0027] According to a SAR radar transceiver synchronization system provided by the present invention, the clock source subsystem, the signal timing subsystem, the signal transmission subsystem and the signal acquisition subsystem are integrated into different boards in the same single machine or into different devices on the same board.

[0028] The present invention also provides a control method for a SAR radar transceiver synchronization system, comprising:

[0029] Based on the clock source subsystem, it provides the same source timing synchronization clock signal, transmission sampling clock signal and acquisition sampling clock signal;

[0030] Based on the signal timing subsystem, the timing synchronization clock signal is used as the working clock, the transmission synchronization pulse signal is output periodically, and the acquisition synchronization pulse signal is generated with a delay, the timing synchronization clock signal is fanned out, and the transmission accompanying synchronization clock signal and the acquisition accompanying synchronization clock signal are generated;

[0031] Based on the signal transmission subsystem using the first clock signal as the working clock, writing and reading the modulated signal according to the transmission synchronization pulse signal, inserting the read signal into the first continuous data stream and performing cross-clock domain and bit width conversion to obtain a transmitted digital signal; converting the transmitted digital signal according to the transmission sampling clock signal to obtain a new modulated signal; wherein the data rate of the first continuous data stream is the same as the data rate of the read signal; the first clock signal includes a transmission accompanying synchronous clock signal and a DAC logic interaction clock signal, or a transmission accompanying synchronous clock signal;

[0032] Based on the signal acquisition subsystem using the second clock signal as the working clock, the echo signal is converted into an acquisition digital signal according to the acquisition sampling clock signal, and the acquisition digital signal is subjected to cross-clock domain and bit width conversion to obtain a second continuous data stream; the second continuous data stream is read and intercepted according to the acquisition synchronization pulse signal to obtain an acquisition signal; wherein, the second clock signal includes an acquisition accompanying synchronization clock signal and an ADC logic interaction clock signal, or an acquisition accompanying synchronization clock signal; the data rate of the second continuous data stream is the same as the rate of reading the second continuous data stream, and the acquisition moment corresponding to the acquisition signal and the transmission moment corresponding to the new modulation signal have a fixed delay.

[0033] The present invention also provides an electronic device, comprising a memory, a programmable logic device, and a program stored in the memory and runnable on the programmable logic device. When the programmable logic device executes the program, it implements the control method of the SAR radar transceiver synchronization system as described in any one of the above.

[0034] The present invention also provides a non-transitory readable storage medium having a program stored thereon, which, when executed by a programmable logic device, implements the control method of the SAR radar transceiver synchronization system as described above.

[0035] The SAR radar transceiver synchronization system and control method provided by the present invention provide a homologous clock signal through a clock source subsystem, output a periodic transmission synchronization pulse signal through a signal timing subsystem, and delay the generation of an acquisition synchronization pulse signal. Then, the signal transmission subsystem uses a first clock signal as a working clock, writes and reads a modulated signal according to the transmission synchronization pulse signal, inserts the read signal into a first continuous data stream, and performs cross-clock domain and bit width conversion to obtain a transmission digital signal; converts the transmission digital signal according to a transmission sampling clock signal to obtain a new modulation signal; finally, the signal acquisition subsystem uses a second clock signal as a working clock, converts the echo signal into an acquisition digital signal according to the acquisition sampling clock signal, and performs cross-clock domain and bit width conversion on the acquisition digital signal to obtain a second continuous data stream; and reads and intercepts the second continuous data stream according to the acquisition synchronization pulse signal to obtain an acquisition signal. No manual parameter configuration is required during testing, thereby improving the synchronization efficiency of the acquisition signal and the transmission signal of the spaceborne SAR radar. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 This is one of the structural diagrams of the SAR radar transceiver synchronization system provided by the present invention.

[0038] Figure 2 It is a structural diagram of the signal timing subsystem provided by the present invention.

[0039] Figure 3 It is a structural diagram of the signal transmission subsystem provided by the present invention.

[0040] Figure 4 It is a flow chart of the transmission data synchronization method provided by the present invention.

[0041] Figure 5 It is a structural diagram of the signal acquisition subsystem provided by the present invention.

[0042] Figure 6 It is a flow chart of the acquisition data synchronization method provided by the present invention.

[0043] Figure 7 This is the second structural diagram of the SAR radar transceiver synchronization system provided by the present invention.

[0044] Figure 8The figure is a flow chart of a control method of a SAR radar transmitting and receiving synchronization system provided by the present invention.

[0045] Figure 9 It is a structural schematic diagram of the electronic device provided by the present invention.

[0046] Reference numerals:

[0047] 100: clock source subsystem; 200: signal timing subsystem; 300: signal transmission subsystem;

[0048] 310: first clock management chip; 320: first clock fan-out chip;

[0049] 330: transmitting FPGA chip; 331: first synchronization FIFO module;

[0050] 332: Transmitted data insertion selection module; 333: First asynchronous cross-clock FIFO module;

[0051] 340: DAC module; 400: signal acquisition subsystem;

[0052] 410: second clock management chip; 420: second clock fan-out chip;

[0053] 430: ADC module; 440: acquisition FPGA chip;

[0054] 441: a second asynchronous cross-clock FIFO module; 442: a second synchronous FIFO module. DETAILED DESCRIPTION

[0055] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0056] The following combination Figures 1-8 The SAR radar transmitting and receiving synchronization system and control method thereof of the present invention are described.

[0057] Figure 1 This is one of the structural diagrams of the SAR radar transceiver synchronization system provided by the present invention, such as Figure 1 As shown, the system includes: a clock source subsystem 100 , a signal timing subsystem 200 , a signal transmission subsystem 300 and a signal acquisition subsystem 400 .

[0058] The clock source subsystem 100 is used to provide a timing synchronous clock signal of the same source, transmit a sampling clock signal, and collect a sampling clock signal.

[0059] In this embodiment, the clock source subsystem 100 can use the same crystal oscillator as input and generate the timing synchronization clock signal required by the signal timing subsystem, the transmission sampling clock signal required by the signal transmission subsystem 300, and the acquisition sampling clock signal required by the signal acquisition subsystem 400. The above clocks are strictly of the same source, but there may be uncertainty in the phase relationship between the clocks.

[0060] For example, a highly stable oven-controlled crystal oscillator (OCXO) can be used as a reference source to output a 10MHz reference clock signal. A single clock generator chip (corresponding to the clock source subsystem 100) then receives the crystal oscillator signal and generates a timing synchronization clock signal, a transmission sampling clock signal, and an acquisition sampling clock signal through an internal phase-locked loop. The three clocks are output through the same clock tree buffer to ensure homologous characteristics.

[0061] The signal timing subsystem 200 is used to use the timing synchronization clock signal as the working clock, output a periodic transmission synchronization pulse signal, delay the generation of the acquisition synchronization pulse signal, fan out the timing synchronization clock signal, and generate the transmission path synchronization clock signal and the acquisition path synchronization clock signal.

[0062] Figure 2 This is a schematic diagram of the structure of the signal timing subsystem provided by the present invention. Figure 2 In the illustrated embodiment, the signal timing subsystem uses the timing FPGA as the main control chip, uses the timing synchronization clock signal generated by the clock source subsystem as the working clock, outputs a periodic transmission synchronization pulse signal, and after each transmission synchronization pulse signal is output, delays for a certain time to generate a collection synchronization pulse signal.

[0063] In this embodiment, the timing synchronization clock signal is fanned out (or output through the internal clock output component of the FPGA) to generate a transmission accompanying synchronization clock signal and a collection accompanying synchronization clock signal.

[0064] In this embodiment, for the transmission synchronization pulse signal, set_output_delay is used to constrain it during the timing FPGA layout and routing, and the same medium is used for transmission as the transmission accompanying synchronization clock signal, and the routing length is approximately the same, to ensure that within the entire operating temperature range of the SAR system, when the signal transmission subsystem 300 uses the transmission accompanying synchronization clock signal to sample the transmission synchronization pulse signal, the setup and hold time requirements can be met, and no metastable state will be sampled.

[0065] In this embodiment, for the acquisition synchronization pulse signal, set_output_delay is used to constrain it during the timing FPGA layout and routing, and the same medium is used for transmission as the acquisition accompanying synchronization clock signal, and the routing length is approximately the same, to ensure that within the entire operating temperature range of the SAR system, when the signal acquisition subsystem 400 uses the acquisition accompanying synchronization clock signal to sample the acquisition synchronization pulse signal, the setup and hold time requirements can be met, and no metastable state will be sampled.

[0066] The signal transmission subsystem 300 is used to use the first clock signal as the working clock, write and read the modulated signal according to the transmission synchronization pulse signal, insert the read signal into the first continuous data stream and perform cross-clock domain and bit width conversion to obtain a transmitted digital signal; convert the transmitted digital signal according to the transmission sampling clock signal to obtain a new modulated signal; wherein the data rate of the first continuous data stream is the same as the data rate of the read signal; the first clock signal includes a transmission accompanying synchronous clock signal and a DAC logic interaction clock signal, or a transmission accompanying synchronous clock signal.

[0067] In this embodiment, in the spaceborne SAR system, the signal timing subsystem generates a periodic transmission synchronization pulse signal and triggers the signal transmission subsystem 300 to transmit a modulated signal (a specific waveform generated by digital signal processing).

[0068] In this embodiment, after the signal transmission subsystem 300 writes and reads the modulated signal, it can ensure the position of the modulated signal in the transmitted digital signal through a synchronous or asynchronous cross-clock domain buffer, and maintain a certain delay relationship with the transmitted synchronization pulse signal.

[0069] In this embodiment, the first clock signal may be a transmit-link synchronous clock signal, and the signal transmitting subsystem 300 may insert the read signal into the first continuous data stream via an asynchronous cross-clock domain buffer within the transmit-link synchronous clock domain.

[0070] In this embodiment, the first clock signal may also include a DAC logic interaction clock signal and a transmission accompanying synchronous clock signal. The first clock signal is used as the working clock, and the new first continuous data stream is subjected to cross-clock domain and bit width transformation through an asynchronous cross-clock domain buffer to obtain a transmitted digital signal.

[0071] In this embodiment, continuous data streams are formed in the transmit synchronous clock domain (which includes the transmit synchronous clock signal) and the DAC logic interaction clock domain (which includes the DAC logic interaction clock signal), thereby establishing a one-to-one correspondence between each data in the transmit synchronous clock domain and each data in the DAC logic interaction clock domain. At the same time, the modulation signal is inserted into the continuous data stream in the transmit synchronous clock domain through the transmit synchronous pulse signal generated by the signal timing subsystem to obtain a new modulation signal.

[0072] The signal acquisition subsystem 400 is used to use the second clock signal as the working clock, convert the echo signal into an acquisition digital signal according to the acquisition sampling clock signal, and perform cross-clock domain and bit width conversion on the acquisition digital signal to obtain a second continuous data stream; read and intercept the second continuous data stream according to the acquisition synchronization pulse signal to obtain an acquisition signal; wherein, the second clock signal includes an acquisition accompanying synchronization clock signal and an ADC logic interaction clock signal, or an acquisition accompanying synchronization clock signal; the data rate of the second continuous data stream is the same as the rate of reading the second continuous data stream, and the acquisition moment corresponding to the acquisition signal and the transmission moment corresponding to the new modulation signal have a fixed delay.

[0073] In this embodiment, after the signal timing subsystem outputs the transmission synchronization pulse signal, it delays for a certain period of time to generate an acquisition synchronization pulse signal, and triggers the signal acquisition subsystem 400 to acquire the external echo signal to obtain the corresponding acquisition signal.

[0074] In this embodiment, after the signal acquisition subsystem 400 converts the echo signal into an acquired digital signal, it can ensure that the position of the acquired signal in the acquired digital signal maintains a certain delay relationship with the acquired synchronization pulse signal through a synchronous or asynchronous cross-clock domain buffer; that is, when the echo signal delay is constant, the echo signal generated by the new modulation signal has a fixed position in the time domain of the acquired signal.

[0075] In this embodiment, the second clock signal can be the acquisition accompanying synchronous clock signal and the ADC logic interaction clock signal. The signal acquisition subsystem 400 uses the second clock signal as the working clock, and performs cross-clock domain and bit width conversion on the acquired digital signal through an asynchronous cross-clock domain buffer to obtain a second continuous data stream.

[0076] In this embodiment, the second clock signal can be an acquisition-path synchronous clock signal. The signal acquisition subsystem 400 reads and intercepts the second continuous data stream according to the acquisition synchronization pulse signal through a synchronous cross-clock domain buffer within the acquisition-path synchronous clock domain to obtain an acquisition signal for subsequent digital signal processing procedures.

[0077] This embodiment can perform clock domain transformation on a continuous data stream so that both the transmitted digital signal and the collected digital signal form a continuous data stream in the timing synchronization clock domain, thereby establishing a temporal correspondence between each data point in the timing synchronization clock domain and each data point transmitted by the DAC and collected by the ADC. On this basis, in the timing synchronization clock domain, a frequency modulation signal is inserted into the data stream by transmitting a synchronization pulse signal, and collected data is intercepted from the data stream by collecting the synchronization pulse signal, thereby ensuring a certain delay relationship between the modulation signal and the collected data.

[0078] The SAR radar transceiver synchronization system provided by the embodiment of the present invention provides a homologous clock signal through the clock source subsystem 100, outputs a periodic transmission synchronization pulse signal through the signal timing subsystem 200, and delays the generation of an acquisition synchronization pulse signal. Then, the signal transmission subsystem 300 uses the first clock signal as the working clock, writes and reads the modulated signal according to the transmission synchronization pulse signal, inserts the read signal into the first continuous data stream, and performs cross-clock domain and bit width conversion to obtain a transmission digital signal; converts the transmission digital signal according to the transmission sampling clock signal to obtain a new modulated signal; finally, the signal acquisition subsystem 400 uses the second clock signal as the working clock, converts the echo signal into an acquisition digital signal according to the acquisition sampling clock signal, and performs cross-clock domain and bit width conversion on the acquisition digital signal to obtain a second continuous data stream; and reads and intercepts the second continuous data stream according to the acquisition synchronization pulse signal to obtain an acquisition signal. No manual parameter configuration is required during testing, thereby improving the synchronization efficiency of the acquisition signal and the transmission signal of the spaceborne SAR radar.

[0079] In some embodiments, the signal transmission subsystem 300 includes: a first clock management chip 310, which is used to generate a DAC logic interaction clock signal based on the transmission sampling clock signal; a first clock fan-out chip 320, which is used to generate a DAC sampling clock signal based on the transmission sampling clock signal; a transmission FPGA chip 330, which is used to use the transmission accompanying synchronous clock signal as the working clock, write and read the modulated signal according to the transmission synchronization pulse signal, and insert the read signal into the first continuous data stream to obtain a third continuous data stream; using the transmission accompanying synchronous clock signal and the DAC logic interaction clock signal as the working clock, the third continuous data stream is subjected to cross-clock domain and bit width conversion to obtain a transmission digital signal; a digital-to-analog conversion DAC module 340, which is used to convert the transmission digital signal according to the DAC sampling clock signal to obtain a new modulated signal.

[0080] Figure 3 It is a structural diagram of the signal transmission subsystem provided by the present invention. Figure 3In the illustrated embodiment, the first clock fan-out chip fans out the transmit sampling clock signal into multiple DAC sampling clock signals to ensure the synchronization of the multi-channel DACs, while forwarding the transmit sampling clock signal to the first clock management chip and outputting the DAC logic interaction clock signal. At this time, the transmitting FPGA chip uses the transmit accompanying synchronous clock signal as the working clock, writes and reads the modulated signal according to the transmit synchronous pulse signal, and obtains a third continuous data stream by inserting the read signal into the first continuous data stream. The DAC uses the DAC sampling clock signal as the working clock to perform digital-to-analog conversion on the transmit digital signal to obtain the corresponding modulated signal.

[0081] The first clock fan-out chip 320 can use a zero-delay buffer (such as IDT8T49N241) to generate multiple low-skew clocks. Each clock drives a single DAC chip, supporting synchronous calibration.

[0082] The first clock management chip 310 can use a phase-locked loop (PLL) or a frequency divider to divide the transmission sampling clock signal. The output DAC logic interaction clock signal has the same source as the transmission sampling clock signal but a different frequency, which can meet the jitter requirements.

[0083] The SAR radar transceiver synchronization system provided by the embodiment of the present invention generates a DAC logic interaction clock signal through the first clock management chip 310, generates a DAC sampling clock signal through the first clock fan-out chip 320, and inserts the read signal into the first continuous data stream through the transmitting FPGA chip 330 using the transmitting accompanying synchronous clock signal as the working clock to obtain a third continuous data stream; using the transmitting accompanying synchronous clock signal and the DAC logic interaction clock signal as the working clock, the third continuous data stream is subjected to cross-clock domain and bit width conversion to obtain a transmitted digital signal, and the transmitted digital signal is converted through the digital-to-analog conversion DAC module 340 to obtain a new modulated signal. The signal transmission subsystem 300 improves the automatic phase adjustment efficiency and adaptability of the SAR radar and simplifies the test process through the cross-clock domain continuous data stream, accompanying synchronous clock design and adaptive FIFO mechanism.

[0084] Furthermore, the transmitting FPGA chip 330 includes: a first synchronous FIFO module 331 , a transmitting data insertion selection module 332 and a first asynchronous cross-clock FIFO module 333 .

[0085] The first synchronous FIFO module 331 is used to use the transmitted synchronous clock signal as the working clock, write and read the modulated signal according to the transmitted synchronous pulse signal, and output the read signal. The instantaneous data write rate and instantaneous data read rate of the first synchronous FIFO module 331 are determined based on the DAC sampling rate, the frequency of the transmitted synchronous clock signal and the number of DAC quantization bits.

[0086] Figure 4 It is a flow chart of the transmission data synchronization method provided by the present invention. Figure 4 In the embodiment shown, the first synchronous FIFO module is a synchronous FIFO (corresponding to the transmit synchronous FIFO-1), which operates in the transmit synchronous clock domain. Its read enable signal is controlled by the transmit synchronous pulse signal. After receiving the transmit synchronous pulse signal, it starts to read the modulated signal and stops reading after reading empty.

[0087] In this embodiment, the instantaneous data rate written and read by the first synchronous FIFO module 331 is obtained by the following mathematical relationship: (DAC sampling rate / transmitter synchronous clock frequency) DAC quantization bits.

[0088] It should be noted that if the DAC supports quadrature up-conversion and interpolation functions, the DAC sampling rate is the total sampling rate of the IQ data before interpolation.

[0089] The transmission data insertion selection module 332 uses the transmission associated synchronous clock signal as a working clock, and is used to insert the read signal into the first continuous data stream to obtain a third continuous data stream.

[0090] exist Figure 4 In the embodiment shown, the transmission data insertion selection module operates in the transmission synchronous clock domain, and the output is a continuous data stream in the transmission synchronous clock domain. The data rate of the continuous data stream is the same as the instantaneous data rate of writing and reading the transmission synchronous FIFO-1, and the read result output by the transmission synchronous FIFO-1 is inserted into the continuous data stream.

[0091] Specifically, when the reading result of the transmit synchronization FIFO-1 is valid, the reading result of the transmit synchronization FIFO-1 is used as the output; otherwise, a constant value of 0 is used as the output.

[0092] The writing side of the first asynchronous cross-clock FIFO module 333 uses the transmitting synchronous clock signal as the working clock, and the reading side uses the DAC logic interaction clock signal as the working clock. The first asynchronous cross-clock FIFO module is used to perform cross-clock domain and bit width conversion on the third continuous data stream to obtain a transmitted digital signal; wherein, the continuous data writing rate of the first asynchronous cross-clock FIFO module 333 is the same as the data rate of the second continuous data stream; the continuous data reading rate of the first asynchronous cross-clock FIFO module 333 is determined based on the DAC sampling rate, the frequency of the DAC logic interaction clock signal and the number of DAC quantization bits.

[0093] exist Figure 4In the illustrated embodiment, the first asynchronous cross-clock FIFO module is an asynchronous cross-clock FIFO (corresponding to the transmit synchronous FIFO-2). The write side operates in the transmit accompanying synchronous clock domain, and the read side operates in the DAC logic interaction clock domain. The write and read enable signals of this module are always valid. The continuous data stream output by the transmit data insertion selection module is subjected to cross-clock domain and bit width conversion to obtain a continuous data stream in the DAC logic interaction clock domain, that is, a transmit digital signal, which is output to the DAC.

[0094] In this embodiment, the data rate on the write side of the first asynchronous cross-clock FIFO module 333 is the same as the continuous data stream output by the transmit data insertion selection module 332, and the data rate on the read side satisfies the following mathematical relationship: (DAC sampling rate / DAC logic interaction clock frequency) DAC quantization bits.

[0095] The SAR radar transceiver synchronization system provided by the embodiment of the present invention uses the transmission-associated synchronous clock signal as the working clock through the first synchronization FIFO module 331 to write and read the modulated signal and output the read signal, and uses the transmission-associated synchronous clock signal as the working clock through the transmission data insertion selection module 332 to insert the read signal into the first continuous data stream to obtain a third continuous data stream; through the first asynchronous cross-clock FIFO module 333, the writing side uses the transmission-associated synchronous clock signal as the working clock, and the reading side uses the DAC logic interaction clock signal as the working clock, and performs cross-clock domain and bit width conversion on the third continuous data stream to obtain a transmission digital signal, thereby achieving precise timing control and rate matching, eliminating the risk of metastable states, supporting multi-mode and multi-channel expansion, and ensuring high-resolution imaging.

[0096] In some embodiments, the signal acquisition subsystem 400 includes: a second clock management chip 410, which is used to generate an ADC logic interaction clock signal based on the acquisition sampling clock signal; a second clock fan-out chip 420, which is used to generate an ADC sampling clock signal based on the acquisition sampling clock signal; an analog-to-digital conversion ADC module 430, which is used to convert the echo signal according to the ADC sampling clock signal to obtain an acquired digital signal; an acquisition FPGA chip 440, which is used to use the ADC logic interaction clock signal and the acquisition accompanying synchronous clock signal as working clocks to perform cross-clock domain and bit width conversion on the acquired digital signal to obtain a second continuous data stream; using the acquisition accompanying synchronous clock signal as the working clock, the second continuous data stream is intercepted according to the acquisition synchronization pulse signal to obtain an acquisition signal.

[0097] Figure 5 This is a schematic diagram of the structure of the signal acquisition subsystem provided by the present invention. Figure 5In the illustrated embodiment, the second clock fan-out chip fans out the acquisition sampling clock signal into multiple ADC sampling clock signals to ensure the synchronization of the multi-channel ADCs, and at the same time forwards the acquisition sampling clock signal to the second clock management chip and outputs the ADC logic interaction clock signal; the ADC uses the ADC sampling clock signal as the working clock to perform analog-to-digital conversion on the echo signal to obtain the corresponding acquisition digital signal, and the acquisition FPGA chip uses the acquisition accompanying synchronous clock signal as the working clock, and obtains the corresponding acquisition signal by using the acquisition digital signal through the acquisition synchronization pulse signal and the ADC logic interaction clock signal.

[0098] The second clock fan-out chip 420 can use a zero-delay buffer (such as IDT8T49N241) to generate multiple low-skew clocks. Each clock drives a single ADC chip, supporting synchronous calibration.

[0099] The second clock management chip 410 can use a phase-locked loop (PLL) or a frequency divider to divide the acquisition sampling clock signal. The output ADC logic interaction clock signal has the same source as the transmission sampling clock signal but a different frequency, which can meet the jitter requirements.

[0100] The SAR radar transceiver synchronization system provided by the embodiment of the present invention generates an ADC logic interaction clock signal through a second clock management chip 410; generates an ADC sampling clock signal through a second clock fan-out chip 420; converts the echo signal through an analog-to-digital conversion ADC module 430 to obtain an acquired digital signal; uses the ADC logic interaction clock signal and the acquired accompanying synchronous clock signal as the working clock through an acquisition FPGA chip 440 to perform cross-clock domain and bit width conversion on the acquired digital signal to obtain a second continuous data stream; uses the acquired accompanying synchronous clock signal as the working clock, intercepts the second continuous data stream according to the acquisition synchronization pulse signal to obtain an acquired signal. The signal acquisition subsystem 400 improves the automatic phase adjustment efficiency and adaptability of the SAR radar and simplifies the test process through the cross-clock domain continuous data stream, accompanying synchronous clock design and adaptive FIFO mechanism.

[0101] In some embodiments, the acquisition FPGA chip 440 includes: a second asynchronous cross-clock FIFO module 441 and a second synchronous FIFO module 442 .

[0102] The second asynchronous cross-clock FIFO module 441 uses the ADC logic interaction clock signal as the working clock on the write side and the acquisition path synchronous clock signal as the working clock on the read side. The second asynchronous cross-clock FIFO module 441 performs cross-clock domain and bit width conversion on the acquired digital signal to obtain a second continuous data stream; the continuous data write rate of the second asynchronous cross-clock FIFO module 441 is determined based on the ADC sampling rate, the frequency of the ADC logic interaction clock signal and the number of ADC quantization bits, and the continuous data read rate is determined based on the ADC sampling rate, the frequency of the acquisition path synchronous clock signal and the number of ADC quantization bits.

[0103] Figure 6 This is a flow chart of the data acquisition synchronization method provided by the present invention. Figure 6 In the embodiment shown, the second asynchronous cross-clock FIFO module is an asynchronous cross-clock FIFO (corresponding to the acquisition synchronous FIFO-1), the write side operates in the ADC logic interaction clock domain, and the read side operates in the acquisition path synchronous clock domain. Its write and read enable signals are always valid, and the acquisition digital signal output by the ADC (the continuous data stream in the ADC logic interaction clock domain) is subjected to cross-clock domain and bit width transformation to obtain a continuous data stream in the acquisition path synchronous clock domain.

[0104] In this embodiment, the data rate at the write side of the acquisition synchronization FIFO-1 satisfies the following mathematical relationship:

[0105] (ADC sampling rate / ADC logic interaction clock frequency) ADC quantization bits;

[0106] The data rate on the read side satisfies the following mathematical relationship:

[0107] (ADC sampling rate / acquisition synchronous clock frequency) ADC quantization bits;

[0108] If the ADC supports quadrature down-conversion and filtering decimation, the ADC sampling rate is the total sampling rate of the IQ data after decimation.

[0109] The second synchronous FIFO module 442 is used to use the acquisition-path synchronous clock signal as the working clock, intercept the second continuous data stream according to the sampling window based on the acquisition synchronous pulse signal, and obtain the acquisition signal; the instantaneous data write rate and instantaneous data read rate of the second synchronous FIFO module 442 are the same as the continuous data read rate of the second asynchronous cross-clock FIFO module 441.

[0110] exist Figure 6In the embodiment shown, the second synchronous FIFO module is a synchronous FIFO (corresponding to the acquisition synchronous FIFO-2), which operates in the acquisition synchronous clock domain and is responsible for intercepting the output data of the acquisition synchronous FIFO-1 according to the sampling window. The specific method is: its write enable signal is controlled by the acquisition synchronous pulse signal, and writing starts after receiving the acquisition synchronous pulse signal, and writing stops after the number of acquisition data signals reaches the required length of the sampling window; its read enable signal is always valid, and the acquisition synchronous FIFO-2 is read immediately if it is not empty. The reading result is the interception result of the output data of the acquisition synchronous FIFO-1 according to the sampling window, and the interception result is input into the digital signal processing method for digital signal processing.

[0111] In this embodiment, the instantaneous data rate of writing and reading from the acquisition synchronization FIFO-2 is equal to the read-side data rate of the acquisition synchronization FIFO-1.

[0112] The SAR radar transceiver synchronization system provided by the embodiment of the present invention uses the ADC logic interaction clock signal as the working clock on the write side of the second asynchronous cross-clock FIFO module 441 and the acquisition path synchronization clock signal as the working clock on the reading side to perform cross-clock domain and bit width conversion on the acquired digital signal to obtain a second continuous data stream; uses the acquisition path synchronization clock signal as the working clock through the second synchronization FIFO module 442, intercepts the second continuous data stream according to the acquisition synchronization pulse signal according to the sampling window to obtain an acquisition signal; through the continuous data streams formed in both the ADC logic interaction clock domain and the acquisition path synchronization clock domain, a corresponding relationship can be established in time between each data point in the timing synchronization clock domain and each data point transmitted by the DAC and collected by the ADC, thereby ensuring a certain delay relationship between the modulated signal and the acquired data.

[0113] In some embodiments, the clock source subsystem 100 , the signal timing subsystem 200 , the signal transmission subsystem 300 , and the signal acquisition subsystem 400 are integrated into different boards in the same single machine or into different devices on the same board.

[0114] In this embodiment, the clock source subsystem 100, the signal timing subsystem 200, the signal transmission subsystem 300 and the signal acquisition subsystem 400 are logical functional subsystems. In physical implementation, each subsystem can be an independent stand-alone machine, or a different board in the same stand-alone machine, or a different device on the same board.

[0115] Specifically, the timing FPGA in the signal timing subsystem, the transmission FPGA in the signal transmission subsystem 300, and the acquisition FPGA in the signal acquisition subsystem 400 can be implemented by the same digital integrated FPGA. The corresponding functions of each FPGA are equivalent to different functional modules inside the digital integrated FPGA, and the above-mentioned transmission path synchronization clock signal and acquisition path synchronization clock signal are replaced by the timing synchronization clock signal, thereby realizing the SAR radar transmission and reception synchronization.

[0116] The SAR radar transceiver synchronization system provided by the embodiment of the present invention can adapt to changes in various external factors such as ambient temperature and chip technology by integrating a clock source subsystem, a signal timing subsystem, a signal transmission subsystem, and a signal acquisition subsystem into different boards within the same single machine or integrating different devices on the same board. When producing batches of the same model, the software status and configuration parameters of different devices do not need to be adjusted, and during ground testing, special tests for different environments are not required. This further improves the synchronization efficiency of the spaceborne SAR radar's acquisition and transmission signals and the scalability of the transceiver synchronization system.

[0117] Figure 7 This is the second structural diagram of the SAR radar receiving and transmitting synchronization system provided by the present invention. Figure 7 In the embodiment shown, a SAR radar transceiver synchronization system includes a clock source subsystem, which provides a transmission sampling clock signal for the signal transmission subsystem, a timing synchronization clock signal for the signal timing subsystem, and an acquisition sampling clock signal for the signal acquisition subsystem; the signal timing subsystem provides a transmission accompanying synchronization clock signal and a transmission synchronization pulse signal for the signal transmission subsystem, and provides an acquisition accompanying synchronization clock signal and an acquisition synchronization pulse signal for the signal acquisition subsystem. This can solve the problem of metastable state that may occur when the signal transmission subsystem samples the transmission synchronization pulse signal (or the signal acquisition subsystem samples the acquisition synchronization pulse signal), and at the same time establishes a temporal correspondence between each data point under the timing synchronization clock domain and each data point transmitted by the DAC and collected by the ADC, thereby ensuring that there is a certain fixed delay between the new modulated signal and the collected signal.

[0118] The control method of the SAR radar transceiver synchronization system provided by the present invention is described below. The control method of the SAR radar transceiver synchronization system described below and the SAR radar transceiver synchronization system described above can be referenced to each other.

[0119] Figure 8 1 is a flow chart of a control method for a SAR radar transceiver synchronization system provided by the present invention, the method comprising the following steps:

[0120] Step 810: Provide a timing synchronization clock signal, a transmission sampling clock signal, and a collection sampling clock signal of the same source based on the clock source subsystem.

[0121] In this step, the clock source subsystem can use the same crystal oscillator as input and generate the timing synchronization clock signal required by the signal timing subsystem, the transmission sampling clock signal required by the signal transmission subsystem, and the acquisition sampling clock signal required by the signal acquisition subsystem. The above clocks are strictly from the same source, but there may be uncertainty in the phase relationship between the clocks.

[0122] For example, a highly stable oven-controlled crystal oscillator (OCXO) can be used as a reference source to output a 10MHz reference clock signal. A single clock generator chip (corresponding to the clock source subsystem) then receives the crystal oscillator signal and generates a timing synchronization clock signal, a transmission sampling clock signal, and an acquisition sampling clock signal through an internal phase-locked loop. The three clocks are output through the same clock tree buffer to ensure homologous characteristics.

[0123] Step 820: Based on the signal timing subsystem, the timing synchronization clock signal is used as the working clock, and a periodic transmission synchronization pulse signal is output, and a delay is generated to generate a collection synchronization pulse signal, and the timing synchronization clock signal is fanned out to generate a transmission accompanying synchronization clock signal and a collection accompanying synchronization clock signal.

[0124] In this step, the signal timing subsystem uses the timing FPGA as the main control chip, uses the timing synchronization clock signal generated by the clock source subsystem as the working clock, outputs a periodic transmission synchronization pulse signal, and after each transmission synchronization pulse signal is output, delays for a certain time to generate a collection synchronization pulse signal.

[0125] In this embodiment, the timing synchronization clock signal is fanned out (or output through the internal clock output component of the FPGA) to generate a transmission accompanying synchronization clock signal and a collection accompanying synchronization clock signal.

[0126] In this embodiment, for the transmission synchronization pulse signal, set_output_delay is used to constrain it during the timing FPGA layout and routing, and the same medium is used for transmission as the transmission accompanying synchronization clock signal, and the routing length is approximately the same, to ensure that within the entire operating temperature range of the SAR system, when the signal transmission subsystem uses the transmission accompanying synchronization clock signal to sample the transmission synchronization pulse signal, the setup and hold time requirements can be met, and no metastable state will be sampled.

[0127] In this embodiment, for the acquisition synchronization pulse signal, set_output_delay is used to constrain it during the timing FPGA layout and routing, and the same medium is used for transmission as the acquisition accompanying synchronization clock signal, and the routing length is approximately the same, to ensure that within the entire operating temperature range of the SAR system, when the signal acquisition subsystem uses the acquisition accompanying synchronization clock signal to sample the acquisition synchronization pulse signal, the setup and hold time requirements can be met, and no metastable state will be sampled.

[0128] Step 830: Based on the signal transmission subsystem, the first clock signal is used as the working clock, and the modulated signal is written and read according to the transmission synchronization pulse signal. The read signal is inserted into the first continuous data stream and cross-clock domain and bit width conversion is performed to obtain a transmitted digital signal; the transmitted digital signal is converted according to the transmission sampling clock signal to obtain a new modulated signal; wherein, the data rate of the first continuous data stream is the same as the data rate of the read signal; the first clock signal includes a transmission accompanying synchronous clock signal and a DAC logic interaction clock signal, or a transmission accompanying synchronous clock signal.

[0129] In this step, in the spaceborne SAR system, the signal timing subsystem generates a periodic transmission synchronization pulse signal and triggers the signal transmission subsystem to transmit a modulated signal (a specific waveform generated by digital signal processing).

[0130] In this embodiment, after the signal transmission subsystem writes and reads the modulated signal, it can ensure the position of the modulated signal in the transmitted digital signal through a synchronous or asynchronous cross-clock domain buffer, and maintain a certain delay relationship with the transmitted synchronization pulse signal.

[0131] In this embodiment, the first clock signal may be a transmit-link synchronous clock signal, and the signal transmitting subsystem may insert the read signal into the first continuous data stream via an asynchronous cross-clock domain buffer within the transmit-link synchronous clock domain.

[0132] In this embodiment, the first clock signal may also include a DAC logic interaction clock signal and a transmission accompanying synchronous clock signal. The first clock signal is used as the working clock, and the new first continuous data stream is subjected to cross-clock domain and bit width transformation through an asynchronous cross-clock domain buffer to obtain a transmitted digital signal.

[0133] In this embodiment, continuous data streams are formed in the transmit synchronous clock domain and the DAC logic interaction clock domain, so that each data in the transmit synchronous clock domain establishes a one-to-one correspondence with each data in the DAC logic interaction clock domain. At the same time, the modulation signal is inserted into the continuous data stream in the transmit synchronous clock domain through the transmit synchronization pulse signal generated by the signal timing subsystem to obtain a new modulation signal.

[0134] Step 840: Based on the signal acquisition subsystem using the second clock signal as the working clock, the echo signal is converted into an acquisition digital signal according to the acquisition sampling clock signal, and the acquisition digital signal is subjected to cross-clock domain and bit width conversion to obtain a second continuous data stream; the second continuous data stream is read and intercepted according to the acquisition synchronization pulse signal to obtain an acquisition signal; wherein, the second clock signal includes an acquisition accompanying synchronization clock signal and an ADC logic interaction clock signal, or an acquisition accompanying synchronization clock signal; the data rate of the second continuous data stream is the same as the rate of reading the second continuous data stream, and the acquisition moment corresponding to the acquisition signal and the transmission moment corresponding to the new modulation signal have a fixed delay.

[0135] In this step, after the signal timing subsystem outputs the transmission synchronization pulse signal, it delays for a certain time to generate the acquisition synchronization pulse signal, and triggers the signal acquisition subsystem to acquire the external echo signal to obtain the corresponding acquisition signal.

[0136] In this embodiment, after the signal acquisition subsystem converts the echo signal into an acquired digital signal, it can ensure that the position of the acquired signal in the acquired digital signal maintains a certain delay relationship with the acquired synchronization pulse signal through a synchronous or asynchronous cross-clock domain buffer; that is, when the echo delay is constant, the echo signal generated by the new modulation signal has a fixed position in the time domain of the acquired signal.

[0137] In this embodiment, the second clock signal can be the acquisition accompanying synchronous clock signal and the ADC logic interaction clock signal. The signal acquisition subsystem uses the second clock signal as the working clock, and performs cross-clock domain and bit width conversion on the acquired digital signal through an asynchronous cross-clock domain buffer to obtain a second continuous data stream.

[0138] In this embodiment, the second clock signal can be an acquisition-path synchronous clock signal. The signal acquisition subsystem reads and intercepts the second continuous data stream according to the acquisition synchronization pulse signal through a synchronous cross-clock domain buffer within the acquisition-path synchronous clock domain to obtain an acquisition signal for subsequent digital signal processing procedures.

[0139] This embodiment can perform clock domain transformation on a continuous data stream so that both the transmitted digital signal and the collected digital signal form a continuous data stream in the timing synchronization clock domain, thereby establishing a temporal correspondence between each data point in the timing synchronization clock domain and each data point transmitted by the DAC and collected by the ADC. On this basis, in the timing synchronization clock domain, a frequency modulation signal is inserted into the data stream by transmitting a synchronization pulse signal, and collected data is intercepted from the data stream by collecting the synchronization pulse signal, thereby ensuring a certain delay relationship between the modulation signal and the collected data.

[0140] The control method of the SAR radar transceiver synchronization system provided by the embodiment of the present invention provides a homologous clock signal through a clock source subsystem, outputs a periodic transmission synchronization pulse signal through a signal timing subsystem, and delays to generate an acquisition synchronization pulse signal. Then, the signal transmission subsystem uses a first clock signal as a working clock, writes and reads a modulated signal according to the transmission synchronization pulse signal, inserts the read signal into a first continuous data stream, and performs cross-clock domain and bit width conversion to obtain a transmission digital signal; converts the transmission digital signal according to the transmission sampling clock signal to obtain a new modulated signal; finally, the signal acquisition subsystem uses a second clock signal as a working clock, converts the echo signal into an acquisition digital signal according to the acquisition sampling clock signal, and performs cross-clock domain and bit width conversion on the acquisition digital signal to obtain a second continuous data stream; and reads and intercepts the second continuous data stream according to the acquisition synchronization pulse signal to obtain an acquisition signal. No manual parameter configuration is required during testing, thereby improving the synchronization efficiency of the acquisition signal and the transmission signal of the spaceborne SAR radar.

[0141] Figure 9 An example of a physical structure diagram of an electronic device is shown below. Figure 9As shown, the electronic device may include: a programmable logic device (PLD) 910, a communication interface (CommunicationsInterface) 920 and a communication bus 930, wherein the programmable logic device 910 and the communication interface 920 communicate with each other through the communication bus 930. The programmable logic device 910 can execute a control method for a SAR radar transceiver synchronization system, which includes: providing a timing synchronization clock signal, a transmission sampling clock signal and an acquisition sampling clock signal of the same source based on a clock source subsystem; based on a signal timing subsystem, using the timing synchronization clock signal as a working clock, outputting a periodic transmission synchronization pulse signal, and delaying the generation of an acquisition synchronization pulse signal, fanning out the timing synchronization clock signal, and generating a transmission accompanying synchronization clock signal and an acquisition accompanying synchronization clock signal; based on a signal transmission subsystem, using the first clock signal as a working clock, writing and reading a modulated signal according to the transmission synchronization pulse signal, inserting the read signal into a first continuous data stream and performing cross-clock domain and bit width conversion to obtain a transmission digital signal; converting the transmission digital signal according to the transmission sampling clock signal to obtain a new modulated signal; wherein the first continuous data stream is The data rate of the continuous data stream is the same as the data rate of the read signal; the first clock signal includes a transmitting synchronous clock signal and a DAC logic interaction clock signal, or a transmitting synchronous clock signal; based on the signal acquisition subsystem, the second clock signal is used as the working clock, and the echo signal is converted into an acquired digital signal according to the acquisition sampling clock signal, and the acquired digital signal is subjected to cross-clock domain and bit width conversion to obtain a second continuous data stream; the second continuous data stream is read and intercepted according to the acquisition synchronization pulse signal to obtain an acquisition signal; wherein, the second clock signal includes an acquisition synchronous clock signal and an ADC logic interaction clock signal, or an acquisition synchronous clock signal; the data rate of the second continuous data stream is the same as the rate of reading the second continuous data stream, and the acquisition moment corresponding to the acquisition signal and the emission moment corresponding to the new modulation signal have a fixed delay.

[0142] In addition, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a programmable logic device to execute all or part of the steps of the method described in each embodiment of the present invention.

[0143] On the other hand, the present invention also provides a non-transitory readable storage medium having a program stored thereon, which, when executed by a programmable logic device, is implemented to execute the control method of the SAR radar transceiver synchronization system provided by the above-mentioned methods, the method comprising: based on the clock source subsystem, providing a timing synchronization clock signal, a transmission sampling clock signal and an acquisition sampling clock signal of the same source; based on the signal timing subsystem, using the timing synchronization clock signal as the working clock, outputting a periodic transmission synchronization pulse signal, and delaying the generation of an acquisition synchronization pulse signal, fanning out the timing synchronization clock signal, generating a transmission accompanying synchronization clock signal and an acquisition accompanying synchronization clock signal; based on the signal transmission subsystem, using the first clock signal as the working clock, writing and reading the modulated signal according to the transmission synchronization pulse signal, inserting the read signal into the first continuous data stream and performing cross-clock domain and bit width conversion to obtain a transmission digital signal; based on the transmission sampling clock signal, the transmission digital signal is converted to the transmission digital signal. The signal is converted to obtain a new modulated signal; wherein, the data rate of the first continuous data stream is the same as the data rate of the read signal; the first clock signal includes a transmitting synchronous clock signal and a DAC logic interaction clock signal, or a transmitting synchronous clock signal; based on the signal acquisition subsystem, the second clock signal is used as the working clock, and the echo signal is converted into an acquired digital signal according to the acquisition sampling clock signal, and the acquired digital signal is subjected to cross-clock domain and bit width conversion to obtain a second continuous data stream; the second continuous data stream is read and intercepted according to the acquisition synchronization pulse signal to obtain an acquisition signal; wherein, the second clock signal includes an acquisition synchronous clock signal and an ADC logic interaction clock signal, or an acquisition synchronous clock signal; the data rate of the second continuous data stream is the same as the rate of reading the second continuous data stream, and the acquisition moment corresponding to the acquisition signal and the emission moment corresponding to the new modulated signal have a fixed delay.

[0144] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0145] Through the description of the above embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the existing technology, can be embodied in the form of a software product. This software product can be stored in a readable storage medium, such as an FPGA or a SOC (System on a Chip) device with programmable logic, and includes a number of instructions for causing the programmable logic device to execute the methods described in various embodiments or certain portions of the embodiments.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A SAR radar transmission and reception synchronization system, characterized in that: include: The clock source subsystem is used to provide the same source timing synchronization clock signal, transmit sampling clock signal and collect sampling clock signal; The signal timing subsystem is used to use the timing synchronization clock signal as the working clock, output a periodic transmission synchronization pulse signal, delay the generation of the acquisition synchronization pulse signal, fan out the timing synchronization clock signal, and generate the transmission accompanying synchronization clock signal and the acquisition accompanying synchronization clock signal; A signal transmission subsystem, configured to use a first clock signal as a working clock, write and read a modulated signal according to the transmission synchronization pulse signal, insert the read signal into a first continuous data stream, and perform cross-clock domain and bit width conversion to obtain a transmitted digital signal; convert the transmitted digital signal according to the transmission sampling clock signal to obtain a new modulated signal; wherein the data rate of the first continuous data stream is the same as the data rate of the read signal; the first clock signal includes a transmission accompanying synchronous clock signal and a DAC logic interaction clock signal, or a transmission accompanying synchronous clock signal; A signal acquisition subsystem is used to use a second clock signal as a working clock, convert the echo signal into an acquisition digital signal according to the acquisition sampling clock signal, and perform cross-clock domain and bit width conversion on the acquisition digital signal to obtain a second continuous data stream; read and intercept the second continuous data stream according to the acquisition synchronization pulse signal to obtain an acquisition signal; wherein, the second clock signal includes an acquisition accompanying synchronization clock signal and an ADC logic interaction clock signal, or an acquisition accompanying synchronization clock signal; the data rate of the second continuous data stream is the same as the rate of reading the second continuous data stream, and the acquisition moment corresponding to the acquisition signal and the transmission moment corresponding to the new modulation signal have a fixed delay.

2. The SAR radar transmitting and receiving synchronization system according to claim 1, characterized in that: The signal transmission subsystem includes: A first clock management chip, configured to generate the DAC logic interaction clock signal according to the transmit sampling clock signal; A first clock fan-out chip, configured to generate a DAC sampling clock signal according to the transmit sampling clock signal; The transmitting FPGA chip is used to use the transmitting accompanying synchronous clock signal as the working clock, write and read the modulated signal according to the transmitting synchronous pulse signal, and insert the read signal into the first continuous data stream to obtain a third continuous data stream; use the transmitting accompanying synchronous clock signal and the DAC logic interactive clock signal as the working clock, perform cross-clock domain and bit width conversion on the third continuous data stream to obtain the transmitting digital signal; The digital-to-analog conversion (DAC) module is used to convert the transmitted digital signal according to the DAC sampling clock signal to obtain the new modulation signal.

3. The SAR radar transmitting and receiving synchronization system according to claim 2, characterized in that: The transmitting FPGA chip includes: A first synchronous FIFO module is used to use the transmission accompanying synchronous clock signal as a working clock, write and read the modulated signal according to the transmission synchronization pulse signal, and output the read signal, wherein the instantaneous data write rate and the instantaneous data read rate of the first synchronous FIFO module are determined based on the DAC sampling rate, the frequency of the transmission accompanying synchronous clock signal, and the number of DAC quantization bits; a transmission data insertion selection module, which uses the transmission accompanying synchronous clock signal as the working clock and is used to insert the read signal into the first continuous data stream to obtain a third continuous data stream; A first asynchronous cross-clock FIFO module uses the transmitted accompanying synchronous clock signal as the working clock on the write side and the DAC logic interaction clock signal as the working clock on the read side. The first asynchronous cross-clock FIFO module is used to perform cross-clock domain and bit width conversion on the third continuous data stream to obtain the transmitted digital signal; wherein, the continuous data write rate of the first asynchronous cross-clock FIFO module is the same as the data rate of the second continuous data stream; the continuous data read rate of the first asynchronous cross-clock FIFO module is determined based on the DAC sampling rate, the frequency of the DAC logic interaction clock signal and the number of DAC quantization bits.

4. The SAR radar transmitting and receiving synchronization system according to claim 1, characterized in that: The signal acquisition subsystem includes: A second clock management chip, configured to generate the ADC logic interaction clock signal according to the acquisition sampling clock signal; A second clock fan-out chip, configured to generate an ADC sampling clock signal according to the acquisition sampling clock signal; An analog-to-digital conversion (ADC) module, configured to convert the echo signal according to the ADC sampling clock signal to obtain the collected digital signal; An acquisition FPGA chip is used to use the ADC logic interaction clock signal and the acquisition accompanying synchronous clock signal as working clocks to perform cross-clock domain and bit width conversion on the acquired digital signal to obtain the second continuous data stream; using the acquisition accompanying synchronous clock signal as the working clock, the second continuous data stream is intercepted according to the acquisition synchronization pulse signal to obtain the acquisition signal.

5. The SAR radar transmitting and receiving synchronization system according to claim 4, characterized in that: The acquisition FPGA chip includes: A second asynchronous cross-clock FIFO module, wherein the writing side uses the ADC logic interaction clock signal as the working clock, and the reading side uses the acquisition accompanying synchronous clock signal as the working clock, and the second asynchronous cross-clock FIFO module is used to perform cross-clock domain and bit width conversion on the acquired digital signal to obtain the second continuous data stream; the continuous data write rate of the second asynchronous cross-clock FIFO module is determined based on the ADC sampling rate, the frequency of the ADC logic interaction clock signal and the number of ADC quantization bits, and the continuous data read rate is determined based on the ADC sampling rate, the frequency of the acquisition accompanying synchronous clock signal and the number of ADC quantization bits; The second synchronous FIFO module is used to use the acquisition accompanying synchronous clock signal as the working clock, intercept the second continuous data stream according to the sampling window according to the acquisition synchronization pulse signal, and obtain the acquisition signal; the instantaneous data write rate and instantaneous data read rate of the second synchronous FIFO module are the same as the continuous data read rate of the second asynchronous cross-clock FIFO module.

6. The SAR radar transmitting and receiving synchronization system according to claim 1, characterized in that: The clock source subsystem, the signal timing subsystem, the signal transmission subsystem and the signal acquisition subsystem are integrated into different boards in the same single machine or into different devices on the same board.

7. A control method for a SAR radar transceiver synchronization system, characterized in that: include: Based on the clock source subsystem, it provides the same source timing synchronization clock signal, transmission sampling clock signal and acquisition sampling clock signal; Based on the signal timing subsystem, the timing synchronization clock signal is used as the working clock, the transmission synchronization pulse signal is output periodically, and the acquisition synchronization pulse signal is generated with a delay, the timing synchronization clock signal is fanned out, and the transmission accompanying synchronization clock signal and the acquisition accompanying synchronization clock signal are generated; Based on the signal transmission subsystem using the first clock signal as the working clock, writing and reading the modulated signal according to the transmission synchronization pulse signal, inserting the read signal into the first continuous data stream and performing cross-clock domain and bit width conversion to obtain a transmitted digital signal; converting the transmitted digital signal according to the transmission sampling clock signal to obtain a new modulated signal; wherein the data rate of the first continuous data stream is the same as the data rate of the read signal; the first clock signal includes a transmission accompanying synchronous clock signal and a DAC logic interaction clock signal, or a transmission accompanying synchronous clock signal; Based on the signal acquisition subsystem using the second clock signal as the working clock, the echo signal is converted into an acquisition digital signal according to the acquisition sampling clock signal, and the acquisition digital signal is subjected to cross-clock domain and bit width conversion to obtain a second continuous data stream; the second continuous data stream is read and intercepted according to the acquisition synchronization pulse signal to obtain an acquisition signal; wherein, the second clock signal includes an acquisition accompanying synchronization clock signal and an ADC logic interaction clock signal, or an acquisition accompanying synchronization clock signal; the data rate of the second continuous data stream is the same as the rate of reading the second continuous data stream, and the acquisition moment corresponding to the acquisition signal and the transmission moment corresponding to the new modulation signal have a fixed delay.

8. An electronic device comprising a memory, a programmable logic device, and a program stored in the memory and running on the programmable logic device, characterized in that: When the programmable logic device executes the program, the control method of the SAR radar transceiver synchronization system according to claim 7 is implemented.

9. A non-transitory readable storage medium having a program stored thereon, characterized in that: When the program is executed by a programmable logic device, the control method of the SAR radar transceiver synchronization system as claimed in claim 7 is implemented.

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