Data writing method and memory controller

Abstract

The invention provides a data writing method and a memory controller, and the method comprises the steps: responding to one or more forcing unit access (FUA) writing commands, and distributing a unique command identifier for each FUA writing command; recording a plurality of stages experienced by the write-in operation corresponding to each command identifier; integrating the write-in data corresponding to one or more command identifiers and caching the write-in data to cache units corresponding to a plurality of planes; after the cache unit is fully written, writing cached write-in data of the cache unit into a memory module through a multi-plane write-in mechanism; and after all target write-in data corresponding to the target command identifier is successfully written in, transmitting a successful response to the host system to indicate that the corresponding target FUA write-in command has been completed. The circulation state of each command is recorded through various data structures, the FUA protocol requirement is met while data cache splicing is carried out, the write-in efficiency is improved, write amplification is reduced, and the service life of a memory is prolonged.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a data writing method for an FUA write command and a memory controller. Background Art

[0002] FUA (Force Unit Access) writes are a special write operation defined in the UFS (Universal Flash Storage) protocol. Generally speaking, a normal write operation will respond to the host with a successful write response after the data is written to the cache. However, FUA writes require that the data be stored on physical media (e.g., flash memory) without errors before the host receives a successful write response. This is not the case with just the data being stored in the device's cache.

[0003] Therefore, FUA write commands are typically processed in a single-command serial manner, ensuring that each FUA write command receives a corresponding response back to the host system after being written to the flash memory. However, this single-command serial approach is inefficient and fails to fully utilize the multi-plane write capability of the flash memory. Furthermore, when a FUA write command contains less data, dummy data must be added, resulting in write amplification.

[0004] If the data of multiple FUA write commands are pieced together in the buffer and then written in multiple planes using one data block, the status of each FUA write command cannot be determined, and the FUA write requirements of the UFS protocol cannot be met. Summary of the Invention

[0005] In view of this, the present disclosure provides a data writing method and a memory controller thereof, which record the flow status of FUA write commands through multiple data structures, so that even when data is pieced together in the cache, the status of each command data can still be tracked, meeting the FUA protocol requirements and improving write efficiency.

[0006] One or more embodiments of the present disclosure provide a data writing method for a storage device configured with a memory module and a buffer memory. The memory module includes a plurality of chips, and each chip has a plurality of physical blocks grouped into a plurality of planes. The method includes: in response to one or more forced unit access write commands, assigning a unique command identifier to each forced unit access write command; recording information on the multiple stages experienced by the write operation corresponding to each command identifier; integrating and caching the write data corresponding to one or more command identifiers into the cache units corresponding to the plurality of planes in the buffer memory; when the cache unit is full, writing the cached write data of the cache unit to the memory module through a multi-plane write mechanism; and when all target write data corresponding to the target command identifier are successfully written to the memory module, transmitting a success response to the host system to indicate that the target forced unit access write command corresponding to the target command identifier has been completed.

[0007] In one or more embodiments of the present disclosure, the multiple phases include a trigger phase, a cache phase, and a completion phase. After receiving a target mandatory unit access write command corresponding to the target command identifier, the target write operation of the target command identifier enters the trigger phase;

[0008] After the target write data corresponding to the target command identifier is integrated and cached in the target cache units corresponding to the multiple planes, the target write operation enters the cache phase.

[0009] After all target write data corresponding to the target command identifier are successfully written from the target cache unit to the memory module through the multi-plane write mechanism, the target write operation enters the completion stage.

[0010] In one or more embodiments of the present disclosure, the information of multiple stages of the write operation corresponding to each command identifier is recorded, including: establishing a status information table to record the general status information of each command identifier; maintaining a trigger linked list to record the command identifier corresponding to each received forced unit access write command; maintaining a wait linked list to record one or more command identifiers corresponding to each cache unit; and maintaining a completion linked list to record the command identifier corresponding to the completed forced unit access write command.

[0011] In one or more embodiments of the present disclosure, the write data corresponding to one or more command identifiers are integrated and cached into the cache units corresponding to the multiple planes in the buffer memory, including: extracting one or more first command identifiers from the trigger linked list to integrate and cache the corresponding first write data into the first cache unit, wherein the size of the first write data is equal to the size of the first cache unit, and the size of the cache unit corresponds to a Flash Super Page (FSP) of the memory module; removing the one or more first command identifiers from the trigger linked list; and updating the one or more first command identifiers to the waiting linked list and the status information table.

[0012] In one or more embodiments of the present disclosure, the status information table includes structure elements of the maximum number of command identifiers, each structure element corresponds one-to-one to one of the command identifiers, and each of the structure elements includes: a continuation pointer field, used to point to the next command identifier following the corresponding command identifier; a cache unit count field, used to record the total number of cache units storing the write data corresponding to the command identifier; a completion flag field, used to identify whether all the write data corresponding to the command identifier has been cached; and an error flag field, used to identify whether an error occurs in the write data corresponding to the command identifier during the writing process.

[0013] In one or more embodiments of the present disclosure, the trigger linked list includes: a first head pointer field, used to point to the first command identifier in the trigger linked list; a first tail pointer field, used to point to the last command identifier in the trigger linked list; and a first quantity field, used to record the total number of command identifiers contained in the trigger linked list.

[0014] In one or more embodiments of the present disclosure, after receiving the target force unit access write command, the method further includes: if the trigger linked list is empty, updating the corresponding target command identifier to the first head pointer field and the first tail pointer field of the trigger linked list, and setting the first quantity field of the trigger linked list to one; if the trigger linked list is not empty, updating the continuation pointer field of the structure element of the command identifier pointed to by the current first tail pointer field in the status information table to the target command identifier, updating the target command identifier to the first tail pointer field of the trigger linked list, and increasing the value of the first quantity field of the trigger linked list by one.

[0015] In one or more embodiments of the present disclosure, the total number of multiple wait list elements of the wait list is configured according to the number of chips in the memory module, and each wait list element corresponds to one cache unit, wherein each wait list element includes: a second head pointer field, used to point to the first command identifier associated with the corresponding cache unit; a second tail pointer field, used to point to the last command identifier associated with the corresponding cache unit; and a second quantity field, used to record the total number of all command identifiers associated with the corresponding cache unit, wherein when the target write data corresponding to the target command identifier is cached to the target cache unit, the target command identifier is updated to the target wait list element associated with the target cache unit, and the value of the cache unit count field of the corresponding structure element in the status information table is increased by one.

[0016] In one or more embodiments of the present disclosure, when the cached write data of the target cache unit is successfully written to the memory module, the method further includes: subtracting by one the value of the cache unit count field of the structure element of the status information table associated with each command identifier in the target wait list corresponding to the target cache unit; and clearing the target wait list.

[0017] In one or more embodiments of the present disclosure, the completion linked list includes: a third head pointer field, used to point to the first command identifier in the completion linked list; a third tail pointer field, used to point to the last command identifier in the completion linked list; and a third quantity field, used to record the total number of command identifiers included in the completion linked list, wherein when the value of the cache unit count field of the target structure element corresponding to the target command identifier in the status information table is reduced to zero and the completion flag field of the target structure element is a first value, the target command identifier is updated to the completion linked list, wherein after a successful response corresponding to the target command identifier is transmitted to the host system, the target command identifier is removed from the completion linked list, and the third head pointer field of the completion linked list is updated to the next command identifier of the target command identifier.

[0018] One or more embodiments of the present disclosure provide a memory controller for controlling a storage device configured with a memory module and a buffer memory, wherein the memory module includes multiple chips, each chip having multiple physical blocks grouped into multiple planes. The memory controller includes: a memory interface control circuit electrically connected to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device for electrically connecting to a host system. The processor is configured to: in response to one or more force unit access write commands, assign a unique command identifier to each force unit access write command; record information about the multiple stages of the write operation corresponding to each command identifier; consolidate and cache write data corresponding to the one or more command identifiers into cache units corresponding to the multiple planes in the buffer memory; when the cache units are full, write the cached write data in the cache units to the memory module via a multi-plane write mechanism; and when all target write data corresponding to the target command identifier is successfully written to the memory module, transmit a success response to the host system to indicate that the target force unit access write command corresponding to the target command identifier has been completed.

[0019] Based on the above, the data writing method and memory controller provided by the present disclosure achieve accurate tracking of each command by assigning a unique command identifier to each forced unit access write command and recording the status information of the multiple stages it has experienced. By integrating the data of multiple commands and caching them in a specific cache unit using a multi-plane write mechanism, the write efficiency is improved. At the same time, the method records the flow status of each command in detail through a variety of data structures to ensure that a successful response is sent to the host only after all the data of the command is successfully written to the memory module, and fully meets the protocol requirements of FUA writes. In addition to meeting the protocol requirements of FUA writes, this design can also solve the problem of low efficiency of single-command serial processing, avoid the defect that it is difficult to track the status of a single command in parallel processing of multiple commands, reduce write amplification, and effectively extend the service life of the memory module. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0021] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present disclosure;

[0022] Figure 2 is a flow chart of a data writing method according to an embodiment of the present disclosure;

[0023] Figure 3 Schematic diagram of a data transmission architecture according to an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram showing information of multiple stages experienced by a write operation corresponding to a recording command identifier according to an embodiment of the present disclosure;

[0025] Figure 5 and Figure 6 is a sequence diagram of a data writing method corresponding to a forced unit access write command according to an embodiment of the present disclosure;

[0026] Figure 7 is a detailed schematic diagram of a state information table and multiple linked lists according to an embodiment of the present disclosure;

[0027] Figures 8A to 8L The diagram is a series of schematic diagrams illustrating state changes of various data structures in multiple stages of a write operation of multiple mandatory unit access write commands according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0029] Figure 1 FIG is a block diagram of a host system and a storage device according to an embodiment of the present disclosure. Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0030] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0031] In this embodiment, the host system 10 is electrically connected to the storage device 20 via the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0032] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless method. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon), etc., based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a display, and a speaker via the system bus.

[0033] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0034] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0035] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present disclosure is not limited thereto, and the host memory 120 may also be other suitable memories.

[0036] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading, and erasing data in the memory module 220 according to instructions from the host system 10 .

[0037] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 is operating, these control instructions / program codes are executed to perform operations such as writing, reading, and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to perform specific information management operations to implement the data writing method optimized for the forced unit access write (FUA) command provided by the present disclosure. The control instructions / program codes corresponding to the data writing method can be further implemented as a circuit unit in the form of hardware to implement the data writing method provided by the present disclosure.

[0038] It is worth mentioning that in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present disclosure is not limited thereto.

[0039] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 may also be considered as operations performed by the memory controller 210.

[0040] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is configured to receive instructions from the processor 211 to transmit data. For example, the data management circuit 212 reads data from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213 (e.g., performing corresponding write operations based on various write instructions from the host system 10). For another example, the data management circuit 212 reads data from one or more physical units of the memory module 220 (the data may be read from one or more storage cells in the one or more physical units) via the memory interface control circuit 213 and writes the read data to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., performing read operations based on read instructions from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0041] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also known as programming) operation, a read operation, or an erase operation on the memory module 220 .

[0042] In addition, the data to be written to the memory module 220 will be converted into a format acceptable to the memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence instructing to write data, a read instruction sequence instructing to read data, an erase instruction sequence instructing to erase data, and corresponding instruction sequences for instructing various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, and a physical address will be included.

[0043] Furthermore, the memory controller 210 establishes a logical to physical address mapping table and a physical to logical address mapping table to record the mapping relationships between the logical addresses of the logical units (e.g., logical blocks, logical pages) configured in the memory module 220 and the physical addresses (physical addresses) of the physical units (e.g., physical erase units / physical blocks, physical pages). In other words, the memory controller 210 can use the logical to physical address mapping table (also referred to as the logical to physical mapping table) to look up the physical unit to which a logical unit is mapped (e.g., to look up the physical page to which a logical page is mapped; to look up the physical address to which a logical address is mapped). Furthermore, the memory controller 210 can use the physical to logical address mapping table (also referred to as the physical to logical mapping table) to look up the logical unit to which a physical unit is mapped (e.g., to look up the logical page to which a physical page is mapped; to look up the logical address to which a physical address is mapped).

[0044] The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the memory module 220, and various system data used to manage the storage device 20. The buffer memory 214 can be configured with a write cache area, which is dedicated to temporarily storing write data to be written to the memory module 220 via a multi-plane write mechanism. In one embodiment, the write cache area can correspond to a Flash Super Page (FSP), whose size is equal to the total capacity of one physical page in each plane of a chip in the memory module 220. For example, if each chip contains M planes and the physical page size of each plane is P, the size of the FSP is M×P. In one embodiment, each chip has 4 planes and the size of each physical page is 16KB, the total size of the FSP is 64KB. The buffer memory 214 is also used to store: (1) various address mapping tables (for example, logical to physical address mapping tables and physical to logical address mapping tables), so that the processor 211 can quickly access relevant data, instructions or system data from the buffer memory 214; and (2) various data structures related to the data writing method of the present disclosure (for example, status information table, trigger linked list, wait linked list, completion linked list, write data register, etc.), which are used to record the flow status of the forced unit access write command and realize the tracking of the write data corresponding to each command identifier.

[0045] The memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store user data sent by the host system 10. The memory module 220 supports a multi-plane write mechanism through its multi-plane structure, which is the key to improving the efficiency of forced unit access writes. Specifically, each chip of the memory module 220 has multiple planes (Plane), each plane has multiple physical blocks, and each physical block includes multiple physical pages. When the cache unit in the buffer memory 214 (such as a specific storage unit corresponding to the size of the flash memory super page FSP, called a flash memory super page unit, FSPU) is full, the memory controller 210 can use this multi-plane structure of the memory module 220 to write data to multiple different planes in parallel at the same time, thereby improving write throughput. This structure enables the data writing method disclosed in the present invention to integrate the data of multiple forced unit access write commands in the cache, and then efficiently write them to the memory module 220 through a single multi-plane write operation, without having to perform a write operation separately for each command, thereby reducing the write amplification phenomenon and extending the service life of the memory module 220.

[0046] In this embodiment, each physical page has multiple storage units (also called physical bytes or bytes), each of which corresponds to a physical address. The physical address is used to record the physical location of the data stored in the storage unit. It should be noted that the present disclosure is not limited to the size of each physical page and logical page.

[0047] Reference Figure 2 , which is a flow chart of the data writing method disclosed in the present invention, and the data writing method is applied to Figure 1 The memory device 20 shown is configured with a memory module 220 and a buffer memory 214. As mentioned above, the memory module 220 includes multiple chips, and each chip has multiple physical blocks grouped into multiple planes. The memory controller 210 can execute program codes or instructions stored in the buffer memory 214 to implement Figure 2 The data writing method shown.

[0048] In step S210, the memory controller 210 (e.g., the processor 211) responds to one or more force unit access write commands and assigns a unique command identifier to each force unit access write command. Specifically, when the host system 10 sends one or more force unit access (FUA) write commands to the storage device 20 through the data transmission interface circuit 130, the memory controller 210 (particularly the processor 211) receives these force unit access write commands and assigns a unique command identifier to each force unit access write command to facilitate subsequent tracking of the status / stage of the write operation of each force unit access write command. In this embodiment, the command identifier can be a command tag (CTAG), the upper limit of which is MAX_CTAG_NUM, indicating the upper limit of commands that the memory controller 210 can process simultaneously.

[0049] In step S220, the memory controller 210 records information about the multiple stages that the write operation corresponding to each command identifier has gone through. Specifically, in this embodiment, the multiple stages include a triggering stage, a caching stage, and a completion stage.

[0050] In one embodiment, after the memory controller 210 receives the target forced unit access write command corresponding to the target command identifier, the target write operation of the target command identifier enters the trigger phase. Specifically, when the host system 10 sends the target forced unit access write command to the memory controller 210, the memory controller 210 assigns a unique target command identifier (CTAG) to the forced unit access write command and adds the target command identifier to the trigger list (Trig_list), indicating that the command has been received and entered the trigger phase.

[0051] In one embodiment, during the triggering phase, the memory controller 210 further initializes the structure element corresponding to the target command identifier in the status information table, sets its cache unit count field (Fsp_cnt) to zero, the completion flag field (Finish) to zero, and the error flag field (Err) to zero, in preparation for subsequent data processing and status tracking.

[0052] In one embodiment, after the target write data corresponding to the target command identifier is integrated and cached into the target cache units corresponding to the multiple planes, the target write operation enters the cache stage. Specifically, the memory controller 210 extracts one or more command identifiers including the target command identifier from the trigger list, integrates and caches the corresponding write data into the selected target cache unit. At this time, the memory controller 210 removes the target command identifier from the trigger list, updates it to the corresponding wait list (Wait_list), and updates the value of the cache unit count field corresponding to the target command identifier in the status information table. When all target write data of the target command identifier have been cached, the memory controller 210 sets the corresponding completion flag field in the status information table to a first value (e.g., 1), indicating that the cache stage is complete.

[0053] In one embodiment, during the cache phase, the memory controller 210 may need to distribute the data for a command across multiple cache units based on the size of the write data and the capacity of the cache units. Whenever data is allocated to a new cache unit, the memory controller 210 increments the cache unit count field of the corresponding command identifier by one to record the number of cache units in which the command data is distributed.

[0054] In one embodiment, after all target write data corresponding to the target command identifier is successfully written from the target cache unit to the memory module 220 via the multi-plane write mechanism, the target write operation enters the completion phase. Specifically, when the target cache unit is full, the memory controller 210 writes the cached data in parallel to multiple planes of the memory module 220 via the multi-plane write mechanism. After the write operation is completed, the memory controller 210 decrements the cache unit count field in the status information table associated with each command identifier in the wait list by one, indicating that the data in the cache unit has been successfully written.

[0055] The memory controller 210 monitors the operation status during the write process. If an error occurs, it sets the error flag field of the relevant command identifier to a first value (e.g., 1) so that an error response can be sent to the host system 10 during the completion phase to allow the host system 10 to return correct status information.

[0056] In another embodiment, the memory controller 210 can be configured to implement an error handling and recovery mechanism to improve the robustness of the storage device 20 when executing a forced unit access write command. In this embodiment, the memory controller 210 can not only identify write errors but also perform corresponding error recovery operations without immediately reporting the error status to the host system 10.

[0057] Specifically, when the memory controller 210 detects an error during a multi-plane write process, the memory controller 210 first sets the error flag field of the relevant command identifier to a first value (e.g., 1), but simultaneously initiates an internal error recovery process instead of reporting the error status to the host system 10. The memory controller 210 can be configured to perform one or more of the following error recovery operations: In a first error recovery operation, the memory controller 210 can attempt to reallocate the target write data to a different physical location in the memory module 220 for writing. Specifically, the memory controller 210 can re-execute the write operation from the cached data retained in the buffer memory 214, and further select other available physical blocks in the memory module 220 as the target location. This operation allows the memory controller 210 to bypass physical areas that may have temporary or permanent failures, thereby increasing the probability of a successful write. In a second error recovery operation, the memory controller 210 can switch to a traditional forced unit access write mode, i.e., a single command serial processing mode. In this mode, the memory controller 210 removes the write data corresponding to the target command identifier from the waiting list and the completion list, and reprocesses the command according to the traditional mandatory unit access write protocol, processing one command at a time until all data for the command is successfully written to the memory module 220 or the preset retry limit is reached. The memory controller 210 can select an appropriate error recovery operation based on a preset strategy or the characteristics of the error. For example, for temporary errors, the memory controller 210 may prioritize reallocating the physical location; for persistent errors or errors caused by hardware limitations, the memory controller 210 may choose to switch to the traditional mode write strategy. Only when all configured error recovery operations fail or the preset retry limit is reached will the memory controller 210 report the error status to the host system 10. This multi-level error handling and recovery mechanism enables the storage device 20 to resolve most write errors internally, reducing the frequency of error reporting to the host system 10, thereby improving the overall system stability and user experience.

[0058] In one embodiment, the memory controller 210 is configured to implement a multi-stage command tracking method for managing the processing status of mandatory unit access write commands and their corresponding data. The method includes maintaining multiple data structures to record information about the multiple stages of the write operation corresponding to each command identifier.

[0059] In a specific implementation, the memory controller 210 first establishes a status information table to record general status information for each command identifier. The status information table is implemented as a structure element list_info[MAX_CTAG_NUM], where MAX_CTAG_NUM represents the maximum number of commands that the memory controller 210 can process simultaneously. For each command identifier, the status information table stores key status parameters, including a continuation pointer field (next) pointing to the next command identifier in the linked list, a cache unit count field (fsp_cnt) recording the command data distribution, a completion flag field (finish) indicating whether all data has been cached, and an error flag field (err) indicating whether an error occurred during the write process.

[0060] The memory controller 210 further maintains a trigger list (trig_list) specifically for recording the command identifier corresponding to each received forced unit access write command. When the host system 10 sends a forced unit access write command to the memory controller 210, the memory controller 210 assigns a unique command identifier (CTAG) to each command and adds it to the trigger list. The trigger list includes a head pointer field (head), a tail pointer field (tail), and a size field (size), which are used to indicate the first command identifier in the list, the last command identifier, and the total number of command identifiers included in the list, respectively.

[0061] When the memory controller 210 is ready to cache data into the buffer memory 214, the memory controller 210 maintains multiple wait lists (wait_list) to record one or more command identifiers corresponding to each cache unit. Each wait list element corresponds to a cache unit, specifically, to an FSPU. The number of wait list elements is typically configured to be twice the number of chips in the memory module 220 to optimize resource utilization and ensure continuous data processing flow. Each wait list element also includes a head pointer field, a tail pointer field, and a size field for managing the set of command identifiers associated with a specific cache unit.

[0062] When the memory controller 210 caches the data of a command identifier into a cache unit, it removes the command identifier from the trigger list and adds it to the corresponding wait list. Simultaneously, the memory controller 210 updates the cache unit count field of the corresponding structure element in the status information table, increasing its value to reflect the number of cache units in which the data of the command identifier is currently distributed.

[0063] The memory controller 210 also maintains a completion list (finish_list) specifically for recording the command identifiers corresponding to completed forced unit access write commands. When the data of the cache unit is successfully written to the memory module 220, the memory controller 210 decrements the cache unit count field value of the corresponding command identifier. When the cache unit count field value of a command identifier drops to zero and its completion flag field is the first value (indicating that all data has been previously cached), the memory controller 210 moves the command identifier from the waiting list to the completion list, indicating that all data for the command has been successfully written to the memory module 220.

[0064] The completion list also includes a head pointer field, a tail pointer field, and a size field to manage completed command identifiers. The memory controller 210 traverses the completion list and sends a corresponding success or error response to the host system 10 based on the value of the error flag field for each command identifier. After sending the response, the memory controller 210 removes the command identifier from the completion list and clears the corresponding structure element in the status information table.

[0065] In one embodiment, after sending the response, the memory controller removes the processed command identifier from the completion list and releases related resources to prepare for processing new write commands. This mechanism ensures that the status of each forced unit access write command can be accurately tracked and reported even when data is merged and processed in parallel.

[0066] Through this multi-linked list collaborative working mechanism, the memory controller 210 can accurately track the processing status of each mandatory unit access write command, achieve efficient command parallel processing, and meet the mandatory unit access protocol requirements for write confirmation.

[0067] In step S230, the memory controller 210 integrates and caches the write data corresponding to the one or more command identifiers into the corresponding cache units of the multiple planes in the buffer memory 214. Specifically, the memory controller 210 extracts one or more first command identifiers from the trigger linked list, integrates and caches the corresponding first write data into the first cache unit, wherein the size of the first write data is equal to the size of the first cache unit, and the size of the cache unit corresponds to a Flash Super Page (FSP) of the memory module 220; removes the one or more first command identifiers from the trigger linked list; and updates the one or more first command identifiers to the wait linked list and the status information table.

[0068] In this embodiment, each cache unit (e.g., FSPU) corresponds to the sum of write units of all planes of a chip in the memory module 220. In this way, data of multiple command identifiers can be integrated into the same cache unit, so that subsequent write operations can fully utilize the multi-plane characteristics of the memory module 220.

[0069] In step S240, when the cache unit is full, the memory controller 210 writes the cached write data in the cache unit to the memory module 220 through a multi-plane write mechanism. Specifically, when a cache unit (such as an FSPU) is full, the memory controller 210 triggers a multi-plane write operation, writing data in parallel to multiple planes of the corresponding chip in the memory module 220. This parallel write mechanism improves write efficiency and reduces write time.

[0070] In step S250, after all target write data corresponding to the target command identifier has been successfully written to the memory module 220, the memory controller 210 transmits a success response to the host system 10, indicating that the target forced unit access write command corresponding to the target command identifier has been completed. Specifically, after a FSPU write is completed, the memory controller 210 updates the cache unit count field in the status information table for all command identifiers associated with the FSPU. For command identifiers whose cache unit count field is reduced to zero and whose completion flag field is set, the memory controller 210 adds them to the completion linked list. The memory controller 210 then extracts the command identifier from the completion linked list and, based on the status of the error flag field, sends a corresponding success or error response to the host system 10.

[0071] Through the above steps, the data writing method disclosed in the present invention effectively solves the problem of inefficiency in forced unit access write commands. By assigning a unique identifier to each command and recording its status, the completion of each command can be accurately tracked while the data is merged and written. This method not only meets the requirements of the UFS protocol for FUA writing (that is, data must be successfully written to the non-volatile storage medium before it can be replied successfully), but also optimizes write performance through multi-command data integration and multi-plane parallel writing, reducing the memory loss caused by the write operation, thereby extending the service life of the memory module 220.

[0072] Figure 3 Schematic diagram of a data transmission architecture according to an embodiment of the present disclosure.

[0073] Reference Figure 3 In one embodiment, the host system 10 sends a forced unit access write command FUA to the storage device 20 , and the storage device 20 is configured to process the forced unit access write command FUA and return a corresponding response RP to the host system 10 .

[0074] The storage device 20 includes a buffer memory 214 and a memory module 220. The buffer memory 214 is configured to temporarily store data from the host system 10, wherein the buffer memory 214 is divided into a plurality of cache units, each of which corresponds to a Flash Super Page (FSP). Figure 3 As shown, the buffer memory 214 includes a plurality of cache units FSPU(1)-FSPU(N), where N is a positive integer representing the total number of cache units available in the buffer memory 214. In one embodiment, the total number of cache units may be set to twice the total number of each chip of the memory module.

[0075] During data transmission, as indicated by arrow A31, the host system 10 sends a forced unit access write command FUA to the storage device 20. Upon receiving the forced unit access write command FUA, the memory controller 210 within the storage device 20 assigns a unique command identifier to each forced unit access write command FUA. Subsequently, the memory controller 210 integrates and caches the write data corresponding to one or more command identifiers into cache units corresponding to multiple planes in the buffer memory 214, i.e., stores the write data in one or more cache units FSPU(1) to FSPU(N).

[0076] When the cache unit corresponding to a flash memory super page (such as FSPU (1)) is full, as shown by arrow A32, the memory controller 210 writes the cached write data FSPD in the cache unit to the memory module 220 through a multi-plane write mechanism. Unlike the traditional single-command serial processing method, the architecture of the present disclosure allows multiple force units to access the data of the write command FUA, integrate them in the buffer memory 214, and then write them into the memory module 220 in batches, thereby improving write efficiency and reducing write amplification.

[0077] The memory controller 210 maintains various data structures (e.g., a status information table, a trigger list, a wait list, and a completion list) to accurately track the status of write operations corresponding to each command identifier. According to the completion list, when all target write data corresponding to the target command identifier is successfully written to the memory module 220, as indicated by arrow A33, the memory controller 210 transmits a response RP to the host system 10 to indicate that the target forced unit access write command FUA corresponding to the target command identifier has been successfully completed.

[0078] Compared with traditional methods, the data transmission architecture disclosed in the present invention has the following advantages: first, by integrating the data of multiple forced unit access write commands FUA in the buffer memory 214, and then writing them in batches to the memory module 220 in units of flash memory super pages, the advantages of multi-plane parallel writing are fully utilized to improve the writing efficiency; second, by using multiple data structure structures to record the status information of each command identifier, it is ensured that even in the case of data integration, the execution status of each forced unit access write command FUA can still be accurately tracked, thereby meeting the protocol requirements of forced unit access write; finally, by reducing the write operation of a single small data block, the write amplification phenomenon is reduced and the service life of the memory module 220 is extended.

[0079] In the architecture of the present disclosure, when the amount of data accessed by multiple forced units in a write command FUA is small, they can be integrated into the same flash memory super page, avoiding the need to add supplementary data (dummy data) for each small data block in the traditional method, further reducing write amplification. At the same time, due to the use of multiple data structures to record the information of each stage of each forced unit access write command FUA, the memory controller 210 can ensure that a success response RP is sent to the host system 10 only after all the data corresponding to the command is successfully written to the memory module 220, thereby strictly complying with the protocol provisions for forced unit access writes.

[0080] Through this optimized data transmission architecture, the present disclosure achieves a dual improvement in the processing efficiency and reliability of the forced unit access write command FUA, providing effective support for applications that require high-performance and high-reliability storage solutions.

[0081] Figure 4 This is a schematic diagram showing information of multiple stages experienced by a write operation corresponding to a recording command identifier according to an embodiment of the present disclosure.

[0082] In one embodiment, referring to Figure 4 Upon receiving a forced unit access write command FUA (assuming it is assigned to CTAG1), as indicated by arrow A41, the command identifier of the command (e.g., CTAG1) is first added to the trigger chain table T420. The trigger chain table T420 is used to record the command identifiers of all received but not yet fully processed forced unit access write commands. Subsequently, as indicated by arrow A42, the memory controller 210 updates the status information table T410 and initializes the corresponding status information for the newly received command identifier, including setting the continuation pointer field, cache unit count field, completion flag field, and error flag field.

[0083] In one embodiment, the status information table T410 is implemented as a plurality of structure elements, each of which corresponds to a command identifier. After initialization is completed, the memory controller 210 starts processing the write data WD. As shown by arrow A43, the write data WD is allocated to the cache unit FSPU (1) in the buffer memory 214. The plurality of cache subunits of the cache unit FSPU (1) are divided into a plurality of plane areas (such as Figure 4 As shown, one plane area includes four cache sub-units), including Plane 1, Plane 2, Plane 3 and Plane 4, corresponding to the multiple plane structures of the chip in the memory module 220.

[0084] During the cache unit allocation process, as indicated by arrow A44, the memory controller 210 updates the waiting list T430 to record the command identifier associated with the cache unit FSPU(1) (e.g., the write data WD corresponding to the command identifier has been cached in the cache unit FSPU(1)). At the same time, as indicated by arrow A45, the memory controller 210 updates the cache unit count field of the structure element corresponding to the command identifier in the status information table T410, increasing its value by 1, indicating that the write data corresponding to the command identifier has been allocated to one cache unit. When all the write data corresponding to the command identifier has been allocated to the cache unit, the memory controller 210 sets the corresponding completion flag field in the status information table T410 to a first value (e.g., 1).

[0085] When the cache unit FSPU (1) is filled, as shown by arrow A46, the memory controller 210 writes the cached write data to multiple planes of the memory module 220 in parallel through the multi-plane write mechanism. Figure 4As shown, the cached write data WD corresponding to Plane 1 to Plane 4 in the cache unit FSPU (1) are written in parallel to the corresponding physical pages PG1, PG2, PG3 and PG4 in the memory module 220. This multi-plane parallel write mechanism improves write efficiency, especially for forced unit access write commands with small data volumes, and avoids the write amplification problem in traditional methods.

[0086] After the cached write data WD is written to the memory module 220, as indicated by arrow A47, the memory controller 210 determines whether to update the completion list T440 to add the command identifier of the completed write to the completion list T440. At the same time, as indicated by arrow A48, since the cached data of the cache unit FSPU(1) has been programmed, the memory controller 210 clears the corresponding wait list T430 and, as indicated by arrow A49, updates the cache unit count field of the structure element of the relevant command identifier (e.g., CTAG1) in the status information table T410 by reducing its value by one.

[0087] In one embodiment, when the cache unit count field corresponding to a command identifier reaches zero and its completion flag field is at the first value (indicating that all write data has been previously cached), all data for the command has been successfully written to the memory module 220, and command processing is complete. At this point, the memory controller 210 moves the command identifier from the waiting list T430 to the completion list T440, preparing to send a response to the host system 10.

[0088] Specifically, the memory controller 210 traverses the command identifiers in the completion list T440. For each completed command identifier, as shown by arrow A50, the memory controller 210 queries the status information table T410 to determine whether an error occurred during the programming process of each completed command identifier (searching the error flag field). Based on this, the memory controller 210 sends a response to the host system 10 to indicate whether the corresponding forced unit access write command has been successfully completed or failed. After sending the response, the memory controller 210 removes the command identifier from the completion list T440 and clears the corresponding structure element in the status information table T410, freeing up resources to process new FUA write commands received subsequently.

[0089] In the multi-plane write mechanism of the memory module 220, each chip generally includes multiple planes (e.g. Figure 4 Plane 1 to Plane 4 are shown. A cache unit can be considered a collection of physical pages corresponding to all planes in a chip. By distributing write data to different planes in the cache unit and then triggering multi-plane write operations for all planes simultaneously, parallel writes are achieved, improving write performance.

[0090] In the embodiment of the present disclosure, four data structures, namely the status information table T410, the trigger linked list T420, the wait linked list T430, and the completion linked list T440, work together to track the various stages of the forced unit access write command status. The trigger linked list T420 records the received FUA write commands, the wait linked list T430 records the FUA write commands being buffered, the completion linked list T440 records the completed programmed FUA write commands, and the status information table T410 records the auxiliary status information of each FUA write command during the entire processing process.

[0091] Through this multi-linked list collaborative working mechanism, the memory controller 210 can accurately track the processing status of each mandatory unit access write command, achieve efficient command parallel processing, and meet the strict requirements of the mandatory unit access protocol for write confirmation.

[0092] Figure 5 and Figure 6 FIG. 1 is a sequence diagram of a data writing method corresponding to a forced unit access write command according to an embodiment of the present disclosure.

[0093] In one embodiment, referring to Figure 5 The sequence diagram describes in detail the interaction process between the host system 10, the memory controller 210, the status information table T410, the trigger list T420, the wait list T430, the buffer memory 214 and the memory module 220, and shows the three main stages of the data writing method: stage one (initialization and command allocation), stage two (data integration and caching) and stage three (multi-plane writing).

[0094] Phase 1: Initialization and command distribution

[0095] In phase 1, first, as shown in step S511, the host system 10 sends a forced unit access (FUA) write command to the memory controller 210. After receiving the FUA write command, as shown in step S512, the memory controller 210 assigns a unique command identifier to the FUA write command. The assignment of the command identifier ensures that the memory controller 210 can uniquely identify and track each forced unit access write command throughout the entire processing process.

[0096] Subsequently, as shown in step S513, the memory controller 210 initializes the status information table T410. Specifically, the memory controller 210 creates a structure element for the newly assigned command identifier in the status information table T410 and initializes its various fields: the continuation pointer field is set to a null value, the cache unit count field is set to zero, the completion flag field is set to zero (indicating that the data has not been completely cached), and the error flag field is set to zero (indicating that no error has occurred).

[0097] Next, as shown in step S514, the memory controller 210 updates the trigger linked list T420 and adds the command identifier of the new FUA write command to the trigger linked list T420. If the trigger linked list T420 is empty, the command identifier is set as the head pointer and tail pointer of the trigger linked list T420, and the quantity field is set to one. If the trigger linked list T420 is not empty, the command identifier is added to the end of the linked list, the tail pointer is updated, and the quantity field is incremented by one.

[0098] After these initialization and command allocation operations are completed, as shown in B101 , the write operation of the corresponding command identifier may enter the triggering phase.

[0099] Phase 2: Data integration and caching

[0100] In the second phase, as shown in step S521, the memory controller 210 extracts the command identifier from the trigger list T420. When data needs to be processed, the memory controller 210 starts from the head of the trigger list T420 and sequentially obtains the command identifier to process the corresponding write data.

[0101] As shown in step S522, the memory controller 210 consolidates the write data corresponding to the command identifier and caches it in the cache units corresponding to the multiple planes. In this step, the memory controller 210 consolidates the write data from multiple commands into the cache units (e.g., flash memory super pages) of the buffer memory 214, fully utilizing the multi-plane structure to improve write efficiency. This consolidation mechanism can avoid the write amplification problem caused by writing a single small data block.

[0102] Subsequently, as shown in step S523, the memory controller 210 updates the waiting list T430 of the corresponding cache unit and adds the command identifier to the waiting list T430 associated with the cache unit. At the same time, as shown in step S524, the memory controller 210 updates the number field of the element in the waiting list T430 to record the total number of command identifiers associated with the corresponding cache unit.

[0103] When all write data for an FUA write command has been cached, as shown in step S525, the memory controller 210 sets the completion flag field and sets the completion flag field corresponding to the command identifier in the status information table T410 to the first value, indicating that all data has been cached. Furthermore, as shown in step S526, the memory controller 210 removes the fully cached command identifier from the trigger linked list T420 and completes the maintenance of the trigger linked list T420 by updating the fields.

[0104] After these operations are completed, as shown in B201 , the writing operation of the command identifier enters the cache stage, and the data has been integrated and stored in the buffer memory 214 , waiting to be written to the memory module 220 .

[0105] Phase 3: Multi-plane writing

[0106] In phase three, as shown in step S531, when a cache unit is full, the memory controller 210 executes a write operation corresponding to the cache unit, instructing the multi-plane write operation to be performed on the cached write data of the cache unit. As shown in step S532, the memory controller 210 uses the multi-plane write mechanism to simultaneously write the data in the cache unit in the buffer memory 214 to the physical pages of multiple planes of the memory module 220, achieving parallel write and improving write performance. In addition, it also ensures that the write data of the FUA write command has been successfully transferred from the buffer memory 214 to the memory module 220, and prepares for subsequent status updates.

[0107] Then, after the multi-plane write operation is completed, as shown in step S533, the memory module 220 sends a write completion notification to the memory controller 210. This notification indicates that the memory module 220 has completed the physical write operation of all specified data. After receiving this notification, the memory controller 210 checks whether an error occurred during the write process. Subsequently, based on the result of this check, as shown in step S534, if an error occurs during the write process, the memory controller 210 sets the error flag field of the relevant command identifier to a first value (e.g., 1), otherwise it remains at zero (indicating that no error occurred during the write process corresponding to the command identifier). This step ensures that the execution status of each command can be accurately tracked even in the case of data integration and multi-plane writing.

[0108] In one embodiment, referring to Figure 6 , the sequence diagram describes in detail the interaction process between the host system 10, the memory controller 210, the status information table T410, the waiting list T430, the memory module 220 and the completion list T440 in stage four (status update and list management) and stage five (response generation).

[0109] Phase 4: Status Update and Link List Management

[0110] In Phase 4, the data write operation enters the critical state update and linked list management phase. First, as shown in step S541, the memory module 220 sends a write completion notification to the memory controller 210. This notification indicates that the memory module 220 has successfully completed the physical write operation of the data, ensuring that the forced unit access (FUA) write command meets protocol requirements.

[0111] After receiving the write completion notification, as shown in step S542, the memory controller 210 extracts the relevant command identifiers from the wait list T430 corresponding to the programmed cached write data. These command identifiers point to all FUA write commands involved in the currently completed write operation. Subsequently, as shown in step S543, the memory controller 210 decrements the cache unit count field corresponding to the extracted command identifier in the status information table T410. The cache unit count field indicates the number of cache units in which the command data is distributed. Each time the data of a cache unit is successfully written to the memory module 220, the value of this field is decremented by one.

[0112] When the cache unit count field decreases to zero and the completion flag is at the first value, it indicates that all cached write data of the FUA write command has been successfully written to the memory module 220. In this case, as shown in step S544, the memory controller 210 updates the completion linked list T440 and adds the corresponding command identifier to the completion linked list T440. As shown in B401, the write operation corresponding to the command identifier now enters the completion phase and prepares to send a response to the host system 10.

[0113] Finally, as shown in step S545, the memory controller 210 removes all extracted command identifiers from the waiting list T430 and releases the empty waiting list T430 resources to subsequently process new FUA write commands (e.g., the write data of the new FUA write command is cached in the corresponding cache unit). This resource management mechanism ensures that the storage device 20 can continuously process write commands sent by the host system 10, achieving high data throughput processing.

[0114] Phase 5: Response Generation

[0115] Phase 5 primarily involves sending a command completion response to the host system 10. First, as shown in step S551, the memory controller 210 extracts command identifiers from the completion list T440. These command identifiers correspond to FUA write commands for which all data has been successfully written to the memory module 220, and the memory controller 210 awaits the sending of an operation completion response to the host system 10.

[0116] Then, as shown in step S552, the memory controller 210 obtains the value of the error flag field corresponding to the extracted command identifier in the status information table T410. This field records whether an error occurred during the write process, providing a basis for the memory controller 210 to determine what type of response to send to the host system 10.

[0117] Based on the value of the Error Flag field, the memory controller 210 performs different response operations. As shown in step S5531, when the value of the Error Flag field is a first value (indicating an error), the memory controller 210 sends an error response corresponding to the extracted command identifier to the host system 10. Conversely, as shown in step S5532, when the value of the Error Flag field is zero (indicating no error), the memory controller 210 sends a success response corresponding to the extracted command identifier to the host system 10. As shown in B501, after sending the response, the FUA write command corresponding to the extracted command identifier is executed.

[0118] After the completion response is sent, as shown in step S554, the memory controller 210 removes the command identifier that has been responded to the host system 10 from the completion list T440, and maintains the maintenance of the completion list T440. Finally, as shown in step S555, the memory controller 210 clears the structure element corresponding to the command identifier that has been responded to the host system 10 in the status information table T410, freeing up the occupied resources and preparing to process the new FUA write command.

[0119] Through the operations of phases four and five, the data writing method provided by the present disclosure implements a complete processing cycle of the forced unit access write command, ensures the safe writing of data and provides accurate operation completion feedback to the host system 10.

[0120] Figure 7 Detailed schematic diagram of a status information table and multiple linked lists according to an embodiment of the present disclosure.

[0121] In one embodiment, referring to Figure 7 ,This disclosure realizes the precise tracking and management of the mandatory unit access write commands by designing a series of special data structures.

[0122] (1) Status Information Table

[0123] like Figure 7 As shown, the status information table T410 is implemented as a structure array, including multiple structure elements E410, each structure element E410 corresponds to a command identifier. The general status information number E411 (structure element number) represents the command identifier [CTAG] corresponding to the structure element. Each structure element E410 contains the following four fields:

[0124] The continuation pointer field E412 is used to point to the next command identifier after the command identifier in the linked list;

[0125] The cache unit count field E413 is used to record the total number of cache units storing write data corresponding to the command identifier;

[0126] The completion flag field E414 is used to identify whether all write data corresponding to the command identifier has been cached;

[0127] The error flag field E415 is used to identify whether an error occurs during the writing process of the write data corresponding to the command identifier.

[0128] The size of status information table T410 is typically set to a predetermined size (MAX_CTAG_NUM), which represents the maximum number of commands that the memory controller can process simultaneously. By maintaining such an array of structures, the memory controller can efficiently access and update status information for each command identifier, providing the necessary information support for each stage of command processing.

[0129] (2) Trigger linked list

[0130] The trigger chain table T420 is used to record the command identifier of each received mandatory unit access write command. Figure 7 As shown, the trigger list T420 contains three key fields:

[0131] The head pointer field E421 (also called the first head pointer field) is used to point to the first command identifier in the trigger list T420;

[0132] The tail pointer field E422 (also called the first tail pointer field) is used to point to the last command identifier in the trigger list T420;

[0133] The quantity field E423 (also called the first quantity field) is used to record the total quantity of command identifiers included in the trigger list T420.

[0134] When a new forced unit access write command is received, the memory controller adds its command identifier to the end of the trigger list T420 and updates the relevant pointer and count value (e.g., the quantity field). When the data of a forced unit access write command is completely cached, the corresponding command identifier will be removed from the trigger list T420 (removed from the head pointer field), and the next command identifier can be found from the continuation pointer field E412 of the corresponding structure element to update the head pointer field. The trigger list T420 implements the link between command identifiers through the continuation pointer field E412 in the status information table T410, forming an efficient one-way linked list structure.

[0135] In one embodiment, the present disclosure also provides a method for efficiently managing trigger linked list T420. When the memory controller 210 receives a target forced unit access write command, it first assigns a unique target command identifier to the command and then adds the target command identifier to trigger linked list T420. The specific method for updating trigger linked list T420 has two different processing flows depending on the current state of trigger linked list T420.

[0136] When trigger list T420 is empty, memory controller 210 directly updates the corresponding target command identifier into head pointer field E421 and tail pointer field E422 of trigger list T420, so that both the head pointer and the tail pointer point to the target command identifier. It also sets quantity field E423 of trigger list T420 to 1, indicating that there is only one command identifier in trigger list T420. At this point, trigger list T420 only contains the newly added target command identifier, and there is no need to update continuation pointer field E412 in status information table T410.

[0137] When the trigger linked list T420 is not empty, the operation of adding a new command identifier is more complicated and the integrity of the linked list needs to be maintained. The memory controller 210 first obtains the current tail command identifier from the tail pointer field E422 of the trigger linked list T420, and then updates the continuation pointer field E412 of the structure element E410 corresponding to the tail command identifier in the status information table T410 to the target command identifier. Through this update, a link between the original tail command identifier and the new target command identifier is established. Subsequently, the memory controller 210 updates the target command identifier to the tail pointer field E422 of the trigger linked list T420, so that the tail pointer points to the newly added target command identifier. Finally, the memory controller 210 increases the value of the quantity field E423 of the trigger linked list T420 by one, reflecting the increase in the total number of command identifiers in the trigger linked list T420.

[0138] (3) Waiting list

[0139] The waiting list T430 is used to record one or more command identifiers corresponding to each cache unit. Figure 7 As shown, the wait list T430 includes multiple wait list elements E431, each of which corresponds to a cache unit (i.e., a flash memory super page), such as FSPU (1), FSPU (2), FSPU (3), and FSPU (4). According to a feature of the present disclosure, the total number of the multiple wait list elements E431 in the wait list T430 is configured according to the number of chips in the memory module 220 to optimize resource utilization and ensure the continuity of data processing.

[0140] Each wait list element E431 contains three key fields:

[0141] The head pointer field E432 (also called the second head pointer field) is used to point to the first command identifier associated with the corresponding cache unit;

[0142] A tail pointer field E433 (also called a second tail pointer field) is used to point to the last command identifier associated with the corresponding cache unit;

[0143] The quantity field E434 (also called the second quantity field) is used to record the total quantity of all command identifiers associated with the corresponding cache unit.

[0144] During the data processing process, when the memory controller 210 caches the target write data corresponding to the target command identifier to the target cache unit, the memory controller 210 performs two update operations: first, the target command identifier is updated to the tail pointer field E433 of the target wait list element E431 associated with the target cache unit to establish an association between the command identifier and the cache unit; second, the value of the cache unit count field E413 of the structure element E410 corresponding to the target command identifier in the status information table T410 is increased by one to record the number of cache units where the command data is currently distributed.

[0145] When data in the cache unit is successfully written to the memory module 220, the corresponding command identifier is removed from the waiting list element E431 (from the head pointer field E432). The next command identifier is then searched for using the continuation pointer field of the structure element of the removed command identifier to update the head pointer field E432 of the waiting list element E431. The associated count value (quantity field E434) is also updated accordingly. Through this precise association management mechanism, the memory controller 210 can accurately track the data distribution and processing status of each command even when processing multiple commands in parallel and integrating data.

[0146] In one embodiment, after the cached write data of the target cache unit is successfully written to the memory module 220, the memory controller 210 performs a series of status update operations to maintain the accuracy of the system state. First, the memory controller 210 iterates through each command identifier in the target wait list corresponding to the target cache unit. For each command identifier, the memory controller 210 decrements the value of the cache unit count field E413 of the structure element E410 of the associated status information table T410 by one. This operation reflects that the partial data of the corresponding command has been successfully written to the permanent storage medium and no longer occupies cache resources.

[0147] After the decrement operation on cache unit count field E413 is complete, memory controller 210 clears the target wait list, freeing up associated resources to prepare for receiving and processing new data. This clearing operation ensures that no command identifiers are associated with processed cache units, preventing resource usage and state confusion while freeing up space for subsequent data processing. This clearing process includes resetting the head pointer field E432, tail pointer field E433, and quantity field E434 of wait list element E431 to their initial state.

[0148] In some embodiments, the number of elements in the waiting list T430 can be configured to be N times the number of chips in the memory module 220 (N is a variable parameter of 2 or greater, for example), so that the system can perform write operations on one part of the cache units while another part of the cache units can receive new data, thereby achieving more efficient pipelined data processing.

[0149] (4) Complete the linked list

[0150] The completion linked list T440 is used to record the command identifiers corresponding to the completed mandatory unit access write commands. Figure 7 As shown, the completion list T440 contains three key fields:

[0151] The head pointer field E441 (also called the third head pointer field) is used to point to the first command identifier in the completion list T440;

[0152] The tail pointer field E442 (also called the third tail pointer field) is used to point to the last command identifier in the completion list T440;

[0153] The quantity field E443 (also called the third quantity field) is used to record the total number of command identifiers included in the completion list T440.

[0154] In the system disclosed herein, the migration of the command identifier to the completion list T440 is subject to strict conditional control to ensure that the migration operation is performed only after the command is completely processed. Specifically, when the value of the cache unit count field E413 of the target structure element E410 corresponding to the target command identifier in the status information table T410 is reduced to zero (indicating that all cached data has been written to the memory module 220) and the completion flag field E414 of the target structure element E410 is the first value (indicating that all data has been completely cached), the memory controller 210 updates the target command identifier to the tail pointer field E442 of the completion list T440, and adds the command identifier to the end of the completion list T440 (e.g., the tail pointer field) through appropriate pointer operations.

[0155] At the final stage of command processing, the memory controller 210 transmits a corresponding success or error response to the host system 10 based on the value of the error flag field E415 in the status information table T410 for the command identifier. After transmitting the response corresponding to the target command identifier to the host system 10, the memory controller 210 performs a linked list maintenance operation: removing the target command identifier from the completion linked list T440 and updating the head pointer field E441 of the completion linked list T440 to the command identifier next to the target command identifier. This head element removal mechanism implements a first-in-first-out (FIFO) command processing order in the completion linked list T440, ensuring the timing and integrity of command responses.

[0156] This precise completion list management mechanism ensures that the memory controller 210 can still accurately track and respond to each mandatory unit access write command in complex scenarios where multiple commands are processed in parallel, thereby achieving efficient command processing and cache resource recovery.

[0157] The present disclosure achieves efficient management of mandatory unit access write commands through the collaborative operation of these four data structures. Commands are first registered in the trigger linked list T420, and then the relevant information is recorded in the status information table T410 during data processing. When data is allocated to the cache unit, the command identifier is transferred to the wait linked list T430. Finally, after the data is successfully written, it is added to the completion linked list T440 to await response processing.

[0158] This design ensures that even when multiple commands are processed in parallel and data is consolidated, the memory controller can still accurately record information about the multiple stages of the write operation corresponding to each command identifier to track the status of each forced unit access write command, meeting the strict requirements of the forced unit access protocol. At the same time, it improves data writing efficiency, reduces write amplification, and extends the service life of the storage device.

[0159] By using a linked list structure rather than a traditional array or queue, the present disclosure implements dynamic command processing capabilities, flexibly adjusting the processing order based on the execution status of the mandatory unit access write command, greatly improving the system's responsiveness and data processing efficiency. Furthermore, the status information table T410 provides centralized status management, simplifying status query and update operations and ensuring stable operation of the entire mandatory unit access write command.

[0160] Figures 8A to 8L The diagram is a series of schematic diagrams illustrating state changes of various data structures in multiple stages of a write operation of multiple mandatory unit access write commands according to an embodiment of the present disclosure.

[0161] In one embodiment, referring to Figure 8AWhen the storage device 20 receives the first forced unit access write command FUA3 (assuming that the command identifier (CTAG) of the command is set to "3" and the data length is 8×4K (i.e., 32KB)), the memory controller 210 immediately initializes the relevant data structure and prepares for subsequent command processing.

[0162] For command identifier "3", the corresponding structure element E410 can be identified by the structure element number E411 [3]. In addition, the four fields of this structure element - the continuation pointer field E412, the cache unit count field E413, the completion flag field E414, and the error flag field E415 are all initialized to zero, indicating that the command has not yet been processed, no cache unit has been allocated, the data is not fully cached, and no error has occurred.

[0163] At the same time, the memory controller 210 updates the trigger linked list T420 and adds the command identifier "3" as the first processing object. Figure 8A As shown, the head pointer field E421 and the tail pointer field E422 of the trigger linked list T420 are both set to "3", and the quantity field E423 is also set to "1" (indicating that there is one command, which actually means that the linked list length is 1). Since there is only one command identifier in the trigger linked list T420 at this time, the head pointer and tail pointer of the trigger linked list both point to the same command identifier.

[0164] In addition, the memory controller 210 also prepares for data caching. Figure 8A As shown, the buffer memory 214 is divided into four cache units FSPU (1), FSPU (2), FSPU (3) and FSPU (4) (here, the total number of cache units is set to twice the number of chips in the memory module), and each cache unit is further divided into four plane areas corresponding to the physical pages of planes Plane 1 to Plane 4, respectively, for parallel processing of data. In this embodiment, it is assumed that each chip contains four planes and the physical page size of each plane is 16KB, so the size of each cache unit is 4×16KB=64KB. All cache sub-units in each cache unit (for the convenience of explanation, each size is assumed to be 4KB) are initialized to zero, indicating that no data has been stored.

[0165] On the other hand, each element of the waiting list T430 is also in the initial state. Figure 8A Four wait list elements E431[FSPU(1)]-E431[FSPU(4)] are shown, corresponding to the four cache units FSPU(1) to FSPU(4). The head pointer field E432, tail pointer field E433, and quantity field E434 of each wait list element E431 are initialized to zero, indicating that no command has yet been associated with any cache unit.

[0166] Likewise, the completion list T440 is also in an idle state, with its head pointer field E441, tail pointer field E442, and quantity field E443 all being zero, indicating that no command has yet been completed.

[0167] At this initial stage, command FUA3 has been recognized and recorded by the system, but its data has not yet begun to be cached or written and is in a state of waiting for processing.

[0168] Next, refer to Figure 8B When the storage device 20 receives the second forced unit access write command FUA1 (the command identifier (CTAG) of the command is set to "1" and the data length is 24×4K (ie 96KB)), the memory controller 210 performs a series of operations to update the relevant data structure.

[0169] First, the memory controller 210 initializes a corresponding structure element E410 for the command identifier "1" in the status information table T410. This element can be identified by the structure element number E411[1]. Similar to the previous processing of the FUA3 command, the four fields of this structure element—the continuation pointer field E412, the cache unit count field E413, the completion flag field E414, and the error flag field E415—are all initialized to zero, indicating that the command has not yet been processed.

[0170] Next, the memory controller 210 updates the trigger linked list T420 and adds command identifier "1" to the linked list. Since command identifier "3" already exists in the trigger linked list T420, the memory controller 210 updates the continuation pointer field E412 of the structure element corresponding to command identifier "3" in the status information table T410 to "1", establishing a link from command "3" to command "1". At the same time, the tail pointer field E422 of the trigger linked list T420 is updated to "1", indicating that command identifier "1" is now the last element in the trigger linked list T420. The head pointer field E421 remains "3", indicating that command identifier "3" is still the first element in the linked list. In addition, the quantity field E423 is updated to "2", reflecting that there are now two command identifiers in the trigger linked list T420.

[0171] At this point, cache units FSPU(1) to FSPU(4) in buffer memory 214 remain unused, and all cache subunits are zero, indicating that no data for any command has yet been stored. Similarly, the head pointer field E432, tail pointer field E433, and quantity field E434 of the four wait list elements E431[FSPU(1)]-E431[FSPU(4)] in wait list T430 all remain zero, indicating that no FUA write command has yet been associated with any cache unit.

[0172] The completion list T440 also continues to remain in an idle state, with its head pointer field E441, tail pointer field E442 and quantity field E443 all being zero, indicating that no command has yet been completed.

[0173] At this stage, the storage device 20 has received and recorded two mandatory unit access write commands (FUA3 and FUA1). These commands are linked in the trigger linked list T420 in the order they were received, awaiting subsequent processing. Command FUA3, as the first command received, will be processed first, while command FUA1 will be processed later. This linked list-based command management mechanism enables the memory controller 210 to process commands according to the first-in, first-out (FIFO) principle, ensuring orderly command processing.

[0174] Next, refer to Figure 8C , the memory controller 210 starts processing the forced unit access write command (FUA3) with the command identifier "3", caches its write data into the cache unit FSPU(1), and updates the relevant data structure to reflect this operation.

[0175] When the memory controller 210 extracts the command identifier "3" from the trigger list T420, the memory controller 210 allocates the corresponding 8×4K write data to the Plane 1 and Plane 2 areas of the cache unit FSPU(1). Figure 8C As shown, the first eight cache sub-units of the cache unit FSPU (1) are marked as "3", indicating that these locations have been occupied by data with command identifier "3".

[0176] At the same time, the memory controller 210 updates the structure element E410 corresponding to the command identifier "3" in the status information table T410 (corresponding to the structure element number E411[3]). Specifically, the cache unit count field E413 is updated to "1", indicating that the data of the command is now distributed in one cache unit; the completion flag field E414 is updated to "1", indicating that all write data corresponding to the command identifier "3" has been completely cached.

[0177] After completing the data caching operation, the memory controller 210 updates the trigger list T420. Since all data for command identifier "3" has been completely cached, the memory controller 210 removes it from the trigger list T420 and updates the head pointer field E421 to "1" by setting the value "1" in the continuation pointer field of the structure element E411[3] corresponding to command identifier "3". This indicates that command identifier "1" is now the first element in the trigger list. The tail pointer field E422 remains "1", while the quantity field E423 is updated to "1", reflecting that there is only one command identifier left in the trigger list T420.

[0178] At the same time, the memory controller 210 updates the wait list element E431 [FSPU(1)] corresponding to the cache unit FSPU(1) in the wait list T430. The head pointer field E432 and the tail pointer field E433 of this wait list element are both set to "3", indicating that the command identifier "3" is the only command associated with this cache unit; the quantity field E434 is set to "1", indicating that this cache unit is currently associated with a command identifier. The wait list elements corresponding to other cache units remain unused, and their head pointer field E432, tail pointer field E433, and quantity field E434 are all "0".

[0179] The completion list T440 remains idle at this stage, and its head pointer field E441, tail pointer field E442 and quantity field E443 are all "0", indicating that no command has yet completed the entire processing flow.

[0180] Next, refer to Figure 8D , the memory controller 210 continues to perform data processing operations, caches the partial write data corresponding to the command identifier "1" into the remaining space of the cache unit FSPU(1), and updates the status of each data structure accordingly.

[0181] In the previous stage, Plane 1 and Plane 2 of the cache unit FSPU (1) have been used to store data of command identifier "3". Now, the memory controller 210 extracts command identifier "1" from the trigger list T420 and starts processing the corresponding forced unit access write command FUA1. Since the data volume corresponding to command identifier "1" is large (24×4K), the memory controller 210 first allocates part of its data to the remaining space of the cache unit FSPU (1), namely Plane 3 and Plane 4. Figure 8D As shown, the last eight cache sub-units of the cache unit FSPU (1) are marked as "1" (bold and underlined), indicating that these locations are now occupied by part of the data of the command identifier "1".

[0182] As data allocation proceeds, the memory controller 210 updates the structure element E410 corresponding to the command identifier "1" in the status information table T410 (corresponding to the structure element number E411[1]). Specifically, the cache unit count field E413 is updated to "1" (bold and underlined), indicating that part of the data of the command is now distributed in a cache unit. Since the data of the command identifier "1" has not been fully cached (only 8 4K sub-units are used, and the total data volume is 24×4K), the completion flag field E414 remains "0". In one embodiment, the memory controller 210 can maintain a write data register for accurately recording the cache status of the write data of each forced unit access write command. For example, the write data register allocates a bitmap structure for each command identifier, in which each bit corresponds to a data block of a specific size (such as 4K). When the corresponding data block is successfully cached, the corresponding bit is set to a specific value (such as "1"). By checking the state of the write data register, the memory controller 210 can accurately calculate the difference between the amount of data cached for command identifier "1" (8×4K) and the total amount of data (24×4K), thereby determining that 16×4K of write data remains to be cached. This sophisticated data tracking mechanism enables the memory controller 210 to efficiently manage the data caching process, providing the necessary decision-making basis for subsequent cache operations, while also ensuring that all write data is correctly processed and meets the strict requirements of the mandatory unit access protocol.

[0183] At the same time, the memory controller 210 also updates the wait list element E431 [FSPU(1)] in the wait list T430 corresponding to the cache unit FSPU(1). Since data for two commands is now stored in this cache unit, the state of the wait list element needs to be updated accordingly. The head pointer field E432 remains "3", indicating that command identifier "3" is still the first command associated with this cache unit; the tail pointer field E433 is updated to "1", indicating that command identifier "1" is now the last command associated with this cache unit; and the quantity field E434 is updated to "2", reflecting that two command identifiers are currently associated with this cache unit.

[0184] It is worth noting that at this point, the cache unit FSPU (1) has been completely filled (all 16 4K cache sub-units have been used), forming a complete cache unit. In one embodiment, the memory controller 210 will prepare to perform corresponding programmed operations on the cache unit that has been filled.

[0185] The state of trigger list T420 remains unchanged. Its head pointer field E421 and tail pointer field E422 are both "1," and the quantity field E423 is "1," indicating that command identifier "1" is still in the trigger list, awaiting further processing. Because the data for command identifier "1" has not yet been fully cached, it is not removed from trigger list T420.

[0186] The completion linked list T440 remains in an idle state, and its head pointer field E441, tail pointer field E442 and quantity field E443 are all "0", indicating that no command has yet completed the entire processing flow.

[0187] Next, refer to Figure 8E The memory controller 210 continues to process the remaining write data of the forced unit access write command FUA1 corresponding to the command identifier "1", and caches these data in the cache unit FSPU (2), while completing the update of the relevant data structure.

[0188] When the cache unit FSPU (1) is completely filled, the memory controller 210 continues to extract the command identifier "1" from the trigger list T420 and starts processing the remaining write data. Figure 8E As shown, the memory controller 210 allocates the remaining write data corresponding to the command identifier "1" to the cache unit FSPU (2). Since the total data size of the command identifier "1" is 24×4K, and 8×4K data are already stored in the cache unit FSPU (1), the memory controller 210 allocates the remaining 16×4K data to the cache unit FSPU (2). All 16 cache sub-units of the cache unit FSPU (2) are marked as "1", indicating that these locations have been occupied by the remaining write data of the command identifier "1".

[0189] As the data allocation is completed, the memory controller 210 updates the structure element E410 corresponding to the command identifier "1" in the status information table T410 (corresponding to the structure element number E411[1]). Specifically, the cache unit count field E413 is updated to "2" (bold and underlined), indicating that the data for this command is now distributed across two cache units; and the completion flag field E414 is updated to "1", indicating that all write data for the command identifier "1" has been completely cached.

[0190] Since all data of command identifier "1" have been completely cached, the memory controller 210 removes it from the trigger list T420. Figure 8E As shown, the head pointer field E421, the tail pointer field E422 and the quantity field E423 of the trigger list T420 are all updated to "0", indicating that the trigger list T420 is now empty and there is no command to be processed.

[0191] At the same time, the memory controller 210 updates the wait list element E431 [FSPU(2)] corresponding to the cache unit FSPU(2) in the wait list T430. The head pointer field E432 and the tail pointer field E433 of this wait list element are both set to "1", indicating that the command identifier "1" is the only command associated with this cache unit; the quantity field E434 is set to "1", indicating that this cache unit is currently associated with one command identifier.

[0192] At this point, the memory controller 210 is ready to perform programming operations on the fully filled cache units FSPU (1) and FSPU (2). (In some embodiments, once the cache unit FSPU (1) is filled, the cached data can be written in parallel to multiple planes of the memory module 220 through a multi-plane write mechanism.) The programming operation writes the cached data in parallel to multiple planes of the memory module 220 through a multi-plane write mechanism, thereby achieving efficient data writing. This parallel write operation avoids the write amplification problem in traditional methods by integrating data.

[0193] The completion list T440 remains idle at this stage, with its head pointer field E441, tail pointer field E442 and quantity field E443 all being "0", indicating that no command has yet completed the entire processing flow because although the data has been fully cached, it has not yet been successfully written to the memory module 220.

[0194] Next, refer to Figure 8F , the memory controller 210 executes the programmed operation of the cache unit FSPU(1), writes the cached write data FSPD1 to the memory module 220, and updates each data structure accordingly to reflect the system status after the operation is completed.

[0195] When the data in the cache unit FSPU (1) is ready, the memory controller 210 triggers a programmed operation to write the write data FSPD1 containing the command identifier "3" and the command identifier "1" in FSPU (1) to the corresponding physical location of the memory module 220 through a multi-plane write mechanism. Figure 8F As shown by the arrow on the right, this programmed operation realizes the permanent storage transfer of data from the buffer memory 214 to the memory module 220.

[0196] After the programming operation is completed, the memory controller 210 updates the wait list element E431 [FSPU(1)] corresponding to the cache unit FSPU(1) in the wait list T430. Since the data of the cache unit has been successfully written to the memory module 220, the memory controller 210 clears this wait list element and resets its head pointer field E432, tail pointer field E433, and quantity field E434 to "0" (bold and underlined), indicating that the cache unit is no longer associated with any command. This operation releases cache resources, making the cache unit FSPU(1) and the corresponding wait list element E431 [FSPU(1)] available for subsequent data caching operations.

[0197] At the same time, the memory controller 210 updates the status of the command identifiers associated with the data in FSPU(1) in the status information table T410. For command identifier "3", since one of its associated cache units FSPU(1) has already performed a programming operation, the write data corresponding to command identifier "3" is programmed into the memory module 220, and the cache unit FSPU(1) will be cleared. Therefore, the memory controller 210 reduces the value of its cache unit count field E413 from "1" to "0" to indicate that there are currently 0 cache units storing the write data associated with command identifier "3". Similarly, for command identifier "1", since part of its data (8×4K) is stored in FSPU(1) and the other part (16×4K) is stored in FSPU(2), the memory controller 210 reduces the value of its cache unit count field E413 from "2" to "1", indicating that the data of this command is now distributed in only one cache unit (i.e., FSPU(2)).

[0198] Next, refer to Figure 8G After the data in the cache unit FSPU (1) is successfully written into the memory module 220, the memory controller 210 performs a command completion status check and updates the status information table and the completion linked list.

[0199] like Figure 8G As shown, when memory controller 210 detects that cache unit count field E413 of command identifier "3" has decreased to "0" and completion flag field E414 is "1," memory controller 210 performs a series of operations to update the system status. Arrow A81 indicates that memory controller 210 checks completion flag field E414 in structure element E410 corresponding to command identifier "1" and confirms that its value is "1," indicating that all data for the command has been completely cached.

[0200] Subsequently, as indicated by arrow A82, the memory controller 210 checks the cache unit count field E413 in the structure element E410 corresponding to command identifier "3" and confirms that its value is "0" (bold and underlined), indicating that all data for the command has been successfully written to the memory module 220 and no longer occupies any cache units. Simultaneously, the memory controller 210 also confirms that the completion flag field E414 of the structure element is "1," indicating that all data for the command is fully cached. In other words, at this point, the memory controller 210 can determine that all write data corresponding to command identifier "3" has been written to the memory module 220, provided that it has been fully cached.

[0201] Based on the above check results, as indicated by arrow A83, memory controller 210 adds command identifier "3" to completion list T440. Specifically, memory controller 210 updates both head pointer field E441 and tail pointer field E442 of completion list T440 to "3" (bold and underlined), indicating that command identifier "3" is the first and only element in the completion list. Memory controller 210 also sets quantity field E443 to "1" (bold and underlined), indicating that the completion list currently contains one command identifier.

[0202] In addition, the cache unit FSPU (1) is also completely cleared so that the cache unit FSPU (1) can be used for subsequent data cache operations. The cache unit FSPU (2) still holds the data of the command identifier "1" and waits for the execution of the programmed operation.

[0203] Through this series of status checks and completion list updates, the memory controller 210 tracks the processing status of the forced unit access write command. Specifically, when all command data has been successfully written to the memory module 220 and no longer occupies any cache units, the command identifier is added to the completion list T440, preparing for the subsequent transmission of a command completion response to the host system 10.

[0204] Reference Figure 8H , the memory controller 210 executes the programmed operation of the cache unit FSPU(2), writes the cached write data FSPD2 to the memory module 220, and updates the relevant data structure to reflect the system status after this operation.

[0205] like Figure 8HAs shown, the memory controller 210 triggers the programming operation of the cache unit FSPU (2), and simultaneously writes the remaining write data FSPD2 of the command identifier "1" stored therein to the corresponding physical locations of the memory module 220 through the multi-plane write mechanism. This programming operation transfers the data of all 16 cache sub-units corresponding to Plane 1 to Plane 4 in the cache unit FSPU (2) to the memory module 220, completing the transfer of all write data of the command identifier "1" from the buffer memory 214 to the memory module 220.

[0206] After the programming operation is completed, the memory controller 210 updates the wait list element E431 [FSPU(2)] corresponding to the cache unit FSPU(2) in the wait list T430. Since the data of the cache unit has been successfully written to the memory module 220, the memory controller 210 clears this wait list element and resets its head pointer field E432, tail pointer field E433, and quantity field E434 to "0" (bold and underlined), indicating that the cache unit and the corresponding wait list element E431 [FSPU(2)] are no longer associated with any command. This operation releases the cache resources.

[0207] Next, refer to Figure 8I After the data of the cache unit FSPU (2) is successfully written into the memory module 220, the memory controller 210 performs a command completion status check and updates the status information table and the completion linked list.

[0208] like Figure 8I As shown, after the data in the cache unit FSPU (2) is programmed into the memory module 220, the cache unit FSPU (2) will be cleared. At the same time, the memory controller 210 updates the status of the structure element E410 (corresponding structure element number E411 [1]) corresponding to the command identifier "1" in the status information table T410. Since the cache unit FSPU (2) associated with the command identifier "1" has performed the programming operation and programmed the corresponding write data into the memory module 220, the cache unit count field E413 is reduced from "1" to "0", indicating that there is no longer any cache unit storing the write data associated with the command identifier "1".

[0209] At this time, the memory controller 210 detects that the cache unit count field E413 of the command identifier “1” has been reduced to “0” and the completion flag field E414 is “1”, indicating that all data of the command has been completely cached and successfully written to the memory module 220 .

[0210] The memory controller 210 checks the processing status of command identifier "1". As shown by arrow A85, the memory controller 210 first checks the cache unit count field E413 of the structure element E410 corresponding to the command identifier "1" in the status information table T410, and confirms that its value is "0" (bold and with a dotted box), indicating that there are no longer any cache units storing the write data associated with the command identifier. At the same time, the memory controller 210 also confirms that the completion flag field E414 is "1", indicating that all data for the command has been completely cached. In other words, at this time, the memory controller 210 can determine that all write data corresponding to the command identifier "1" has been written to the memory module 220 if all of it has been cached. Based on the above check results, the memory controller 210 adds the command identifier "1" to the completion list T440. At this time, the completion list T440 already contains the command identifier "3". Memory controller 210 updates the structure of completion list T440, setting the tail pointer field E442 to "1" to indicate that command identifier "1" is now the last element in the list. It also updates the quantity field E443 to "2" to reflect that the completion list currently contains two command identifiers. The head pointer field E441 remains at "3" to indicate that command identifier "3" is still the first element in the list.

[0211] In addition, the cache unit FSPU(2) is indicated by a dotted box, indicating that all its internal cache sub-units are reset to "0", and the memory controller 210 updates all fields of the waiting list element E431 (FSPU(2)) to "0", indicating that the current cache unit FSPU(2) is not associated with any FUS write command.

[0212] Through this series of status checks and completion list updates, the memory controller 210 tracks the processing status of the forced unit access write command. Specifically, when all command data has been successfully written to the memory module 220 and no longer occupies any cache units, the command identifier is added to the completion list T440, preparing for the subsequent transmission of a command completion response to the host system 10.

[0213] In completion list T440, command identifiers "3" and "1" correspond to forced unit access write commands FUA3 and FUA1, respectively, and all of their data has been successfully written to memory module 220. Since command identifier "3" was added to completion list T440 before command identifier "1", memory controller 210 processes the responses to the commands in the order in which they were added.

[0214] For example, refer to Figure 8J When there is a command identifier in the completion list T440 , the memory controller 210 performs a command completion response operation and sends a processing result of the corresponding command to the host system 10 .

[0215] like Figure 8J As shown, the memory controller 210 begins processing the command identifiers in the completion list T440 and prepares to send a response to the host system 10. Specifically, the memory controller 210 first obtains the first command identifier "3" (within a dotted box) from the head pointer field E441 of the completion list T440. This command identifier corresponds to the forced unit access write command FUA3, and all data for this command has been successfully written to the memory module 220.

[0216] Before sending the response, as indicated by arrow A86, the memory controller 210 checks the error flag field E415 of the structure element E410 (corresponding to structure element number E411[3]) corresponding to the command identifier "3" in the status information table T410. This check confirms that the value of the error flag field E415 is "0", indicating that no errors occurred during command processing. Based on this check result, the memory controller 210 sends a "success" response to the host system 10, indicating that the forced unit access write command FUA3 has been successfully completed.

[0217] This completion list-based command response mechanism ensures that the memory controller 210 can send corresponding responses to the host system 10 in the order in which the commands are completed. For a forced unit access write command, a success response is sent only after all data has been written to the memory module 220, thus meeting the strict requirements of the forced unit access write protocol.

[0218] Furthermore, by checking the error flag field E415 before sending a response, the memory controller 210 can accurately reflect the actual result of command processing, ensuring that the host system 10 receives accurate operational status information. If an error occurs during command processing (e.g., a write failure), the error flag field E415 will be set to the corresponding value, and the memory controller 210 will send an "error" response to the host system 10 instead of a success response.

[0219] Next, refer to Figure 8K , the memory controller 210 continues to process the next command identifier in the completion list T440 and completes the response operation to the command FUA1.

[0220] like Figure 8KAs shown, after sending a successful response to the command FUA3 corresponding to the command identifier "3", the memory controller 210 removes the command identifier "3" from the completion list T440, updates the head pointer field E441 of the completion list T440 to the next command identifier pointed to by the continuation pointer of the command identifier "3" (i.e., the command identifier "1"), and continues to process other commands in the list. At the same time, the memory controller 210 clears the structure element E410 corresponding to the command identifier "3" in the status information table T410, and resets its continuation pointer field E412, cache unit count field E413, completion flag field E414, and error flag field E415 to "0", freeing up resources to process new commands.

[0221] Next, the memory controller 210 begins processing the current head command identifier "1" in the completion list T440. As indicated by arrow A87, the memory controller 210 checks the error flag field E415 of the structure element E410 (corresponding to structure element number E411[1]) corresponding to the command identifier "1" in the status information table T410. This check confirms that the value of the error flag field E415 is "0", indicating that no errors occurred during command processing. Based on this check result, the memory controller 210 sends a success response to the host system 10, indicating that the forced unit access write command FUA1 has been successfully completed.

[0222] After the memory controller 210 has processed all the commands in the completion list T440 , it will release the corresponding resources and be ready to receive and process a new mandatory unit access write command.

[0223] After completing the response to all FUA write commands to the host system 10, refer to Figure 8L For example, after the memory controller 210 completes processing of the command identifier “1”, it performs a system clear operation to reset the relevant data structure to an initial state to prepare for receiving and processing a new forced unit access write command.

[0224] like Figure 8L As shown, after sending a successful response to command identifier "1", the memory controller 210 performs a series of clear operations. First, the memory controller 210 removes command identifier "1" from the completion list T440 and resets the head pointer field E441, tail pointer field E442, and quantity field E443 of the completion list T440 to "0", indicating that the completion list T440 is empty and no longer contains any command identifiers.

[0225] At the same time, the memory controller 210 clears all fields of the structure element E410 (corresponding to the structure element number E411[1]) corresponding to the command identifier "1" in the status information table T410, and resets its continuation pointer field E412, cache unit count field E413, completion flag field E414, and error flag field E415 to "0". In particular, Figure 8L The completion flag field E414 is from Figure 8K The "1" in is reset to "0", indicating that the structure element has been completely cleared and can be used to process new commands.

[0226] Through this series of flush operations, the memory controller 210 resets the entire system state to its initial state, preparing it to receive and process new mandatory unit access write commands. This complete resource recovery and state reset mechanism ensures that the storage device 20 can continue to process other write requests from the host system 10, maintaining stable system operation.

[0227] This clearing step is the final stage of the forced unit access write command optimization method provided by the present disclosure, marking the end of a complete processing cycle. At this point, all data of the two forced unit access write commands FUA3 and FUA1 have been successfully written to the memory module 220, and the corresponding success response has been sent to the host system 10, meeting the requirements of the forced unit access write protocol. At the same time, all system resources used to process these commands, including data structures and cache units, have been released and reset, providing sufficient resource support for subsequent command processing.

[0228] This complete processing flow from command reception, data caching, write execution to command response and resource release embodies the forced unit access write command optimization method provided by the present invention. It can efficiently utilize the multi-plane write mechanism to meet the protocol requirements of forced unit access write, and provides an effective technical solution for storage systems that need to process a large number of forced unit access write commands.

[0229] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in a processor, the processor performs the steps of the above-mentioned storage device testing method. The computer program product can be implemented in hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK).

[0230] Based on the above, the data writing method and memory controller provided by the present disclosure can effectively optimize the processing flow of forced unit access write operations. By maintaining four types of efficient data structures, namely the status information table, the trigger linked list, the waiting linked list and the completion linked list, combined with the multi-plane parallel writing mechanism, the present method realizes the accurate tracking and processing of forced unit access write commands. This technical solution not only meets the strict requirements of the forced unit access write protocol, ensuring that the data is sent to the host system only after it is successfully written to the non-volatile storage medium. It also reduces the write amplification phenomenon through data integration technology, effectively extending the service life of the memory module. Compared with the traditional single-command serial processing method, the technical solution disclosed in the present disclosure achieves dual optimization of storage resource utilization and write efficiency through multi-command data integration and parallel processing while ensuring data security.

[0231] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A data writing method, applied to a storage device configured with a memory module and a buffer memory, wherein the memory module includes a plurality of chips, and each chip has a plurality of physical blocks grouped into a plurality of planes, characterized in that: The method comprises: responsive to the one or more force unit access write commands, assigning a unique command identifier to each force unit access write command; Recording information about multiple stages of the write operation corresponding to each command identifier; integrating and buffering the write data corresponding to one or more command identifiers into the buffer units corresponding to the plurality of planes in the buffer memory; When the cache unit is full, writing the cached write data of the cache unit to the memory module through a multi-plane write mechanism; and When all target write data corresponding to the target command identifier are successfully written to the memory module, a success response is transmitted to the host system to indicate that the target forced unit access write command corresponding to the target command identifier has been completed.

2. The data writing method according to claim 1, wherein: The multiple phases include a trigger phase, a cache phase, and a completion phase, wherein: After receiving the target forced unit access write command corresponding to the target command identifier, the target write operation of the target command identifier enters the triggering phase; After the target write data corresponding to the target command identifier is integrated and cached in the target cache units corresponding to the multiple planes, the target write operation enters the cache phase. After all target write data corresponding to the target command identifier are successfully written from the target cache unit to the memory module through the multi-plane write mechanism, the target write operation enters the completion stage.

3. The data writing method according to claim 2, wherein: The information recording the multiple stages of the write operation corresponding to each command identifier includes: Establishing a status information table to record general status information of each command identifier; Maintaining a trigger linked list to record the command identifier corresponding to each received forced unit access write command; Maintaining a waiting list to record one or more command identifiers corresponding to each cache unit; and A completion linked list is maintained to record the command identifiers corresponding to the completed mandatory unit access write commands.

4. The data writing method according to claim 3, wherein: The step of integrating and buffering the write data corresponding to one or more command identifiers into the cache unit corresponding to the plurality of planes in the buffer memory includes: Extracting one or more first command identifiers from the trigger linked list to integrate and cache corresponding first write data into a first cache unit, wherein a size of the first write data is equal to a size of the first cache unit, and the size of the cache unit corresponds to a flash memory super page of the memory module; removing the one or more first command identifiers from the trigger linked list; and The one or more first command identifiers are updated to the waiting list and the status information table.

5. The data writing method according to claim 3, wherein: The status information table includes structure elements of the maximum number of command identifiers, each structure element corresponds to one of the command identifiers, and each structure element includes: A continuation pointer field is used to point to the next command identifier following the corresponding command identifier; A cache unit count field, used to record the total number of cache units storing write data corresponding to the command identifier; A completion flag field, used to identify whether all write data corresponding to the command identifier has been cached; and The error flag field is used to identify whether an error occurs during the writing process of the write data corresponding to the command identifier.

6. The data writing method according to claim 3, wherein: The trigger chain list includes: A first head pointer field is used to point to the first command identifier in the trigger list; A first tail pointer field, used to point to the last command identifier in the trigger linked list; and The first quantity field is used to record the total number of command identifiers included in the trigger list.

7. The data writing method according to claim 6, wherein: After receiving the target forced unit access write command, the method further includes: If the trigger linked list is empty, updating the corresponding target command identifier to the first head pointer field and the first tail pointer field of the trigger linked list, and setting the first quantity field of the trigger linked list to one; If the trigger linked list is not empty, the continuation pointer field of the structure element of the command identifier pointed to by the current first tail pointer field in the status information table is updated to the target command identifier, the target command identifier is updated to the first tail pointer field of the trigger linked list, and the value of the first quantity field of the trigger linked list is increased by one.

8. The data writing method according to claim 3, wherein: The total number of the plurality of wait list elements of the wait list is configured according to the number of chips in the memory module, and each wait list element corresponds to one of the cache units, wherein each wait list element includes: A second head pointer field is used to point to a first command identifier associated with the corresponding cache unit; A second tail pointer field is used to point to the last command identifier associated with the corresponding cache unit; and The second quantity field is used to record the total number of all command identifiers associated with the corresponding cache unit. When the target write data corresponding to the target command identifier is cached to the target cache unit, the target command identifier is updated to the target wait list element associated with the target cache unit, and the value of the cache unit count field of the corresponding structure element in the status information table is increased by one.

9. The data writing method according to claim 3, wherein: When the cached write data of the target cache unit is successfully written into the memory module, the method further includes: Subtract one from the value of the cache unit count field of the structure element of the status information table associated with each command identifier in the target wait list corresponding to the target cache unit; and Clear the target waiting list.

10. The data writing method according to claim 3, wherein: The completion list includes: A third head pointer field is used to point to the first command identifier in the completion list; A third tail pointer field is used to point to the last command identifier in the completion list; and The third quantity field is used to record the total number of command identifiers included in the completion list. When the value of the cache unit count field of the target structure element corresponding to the target command identifier in the status information table is reduced to zero and the completion flag field of the target structure element is a first value, the target command identifier is updated to the completion linked list, After a successful response corresponding to the target command identifier is transmitted to the host system, the target command identifier is removed from the completion list, and the third head pointer field of the completion list is updated to be the next command identifier of the target command identifier.

11. A memory controller for controlling a storage device configured with a memory module and a buffer memory, wherein the memory module includes a plurality of chips, and each chip has a plurality of physical blocks grouped into a plurality of planes, characterized in that: The memory controller comprises: a memory interface control circuit for electrically connecting to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is also electrically connected to the connection interface circuit of the storage device to electrically connect to the host system, wherein the processor is configured to: responsive to the one or more force unit access write commands, assigning a unique command identifier to each force unit access write command; Recording information about multiple stages of the write operation corresponding to each command identifier; integrating and buffering the write data corresponding to one or more command identifiers into the buffer units corresponding to the plurality of planes in the buffer memory; When the cache unit is full, writing the cached write data of the cache unit to the memory module through a multi-plane write mechanism; and When all target write data corresponding to the target command identifier are successfully written to the memory module, a success response is transmitted to the host system to indicate that the target forced unit access write command corresponding to the target command identifier has been completed.

12. The memory controller according to claim 11, wherein: The multiple phases include a trigger phase, a cache phase, and a completion phase, wherein: After receiving the target forced unit access write command corresponding to the target command identifier, the target write operation of the target command identifier enters the triggering phase; After the target write data corresponding to the target command identifier is integrated and cached in the target cache units corresponding to the multiple planes, the target write operation enters the cache phase; After all target write data corresponding to the target command identifier are successfully written from the target cache unit to the memory module through the multi-plane write mechanism, the target write operation enters the completion stage.

13. The memory controller according to claim 12, wherein: The information recording the multiple stages experienced by the write operation corresponding to each command identifier includes: Establishing a status information table to record general status information of each command identifier; Maintaining a trigger linked list to record the command identifier corresponding to each received forced unit access write command; Maintaining a waiting list to record one or more command identifiers corresponding to each cache unit; and A completion linked list is maintained to record the command identifiers corresponding to the completed mandatory unit access write commands.

14. The memory controller according to claim 13, wherein: The step of integrating and buffering the write data corresponding to the one or more command identifiers into the cache unit corresponding to the plurality of planes in the buffer memory includes: Extracting one or more first command identifiers from the trigger linked list to integrate and cache corresponding first write data into a first cache unit, wherein a size of the first write data is equal to a size of the first cache unit, and the size of the cache unit corresponds to a flash memory super page of the memory module; removing the one or more first command identifiers from the trigger linked list; and The one or more first command identifiers are updated to the waiting list and the status information table.

15. The memory controller according to claim 13, wherein: The status information table includes structure elements of the maximum number of command identifiers, each structure element corresponds to one of the command identifiers, and each structure element includes: A continuation pointer field is used to point to the next command identifier following the corresponding command identifier; A cache unit count field, used to record the total number of cache units storing write data corresponding to the command identifier; A completion flag field, used to identify whether all write data corresponding to the command identifier has been cached; and The error flag field is used to identify whether an error occurs during the writing process of the write data corresponding to the command identifier.

16. The memory controller according to claim 13, wherein: The trigger chain list includes: A first head pointer field is used to point to the first command identifier in the trigger list; A first tail pointer field, used to point to the last command identifier in the trigger linked list; and The first quantity field is used to record the total number of command identifiers included in the trigger list.

17. The memory controller according to claim 16, wherein: Upon receiving the target forced unit access write command, the processor is further configured to: If the trigger linked list is empty, updating the corresponding target command identifier to the first head pointer field and the first tail pointer field of the trigger linked list, and setting the first quantity field of the trigger linked list to one; If the trigger linked list is not empty, the continuation pointer field of the structure element of the command identifier pointed to by the current first tail pointer field in the status information table is updated to the target command identifier, the target command identifier is updated to the first tail pointer field of the trigger linked list, and the value of the first quantity field of the trigger linked list is increased by one.

18. The memory controller according to claim 13, wherein: The total number of the plurality of wait list elements of the wait list is configured according to the number of chips in the memory module, and each wait list element corresponds to one of the cache units, wherein each wait list element includes: A second head pointer field is used to point to a first command identifier associated with the corresponding cache unit; A second tail pointer field is used to point to the last command identifier associated with the corresponding cache unit; and The second quantity field is used to record the total number of all command identifiers associated with the corresponding cache unit. When the target write data corresponding to the target command identifier is cached to the target cache unit, the processor is configured to update the target command identifier to the target wait list element associated with the target cache unit, and add one to the value of the cache unit count field of the corresponding structure element in the status information table.

19. The memory controller according to claim 13, wherein: When the cached write data of the target cache unit is successfully written into the memory module, the processor is further configured to: Subtract one from the value of the cache unit count field of the structure element of the status information table associated with each command identifier in the target wait list corresponding to the target cache unit; and Clear the target waiting list.

20. The memory controller according to claim 13, wherein: The completion list includes: A third head pointer field is used to point to the first command identifier in the completion list; A third tail pointer field is used to point to the last command identifier in the completion list; and The third quantity field is used to record the total number of command identifiers included in the completion list. When the value of the cache unit count field of the target structure element corresponding to the target command identifier in the status information table is reduced to zero and the completion flag field of the target structure element is a first value, the processor is configured to update the target command identifier to the completion linked list, After transmitting a successful response corresponding to the target command identifier to the host system, the processor is configured to remove the target command identifier from the completion list and update the third head pointer field of the completion list to the next command identifier of the target command identifier.

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