Storage device, operation method of storage device, and computing system

Abstract

The invention provides a storage device, an operation method of the storage device, and a computing system. When an unrecoverable error occurs in a storage device that receives a command from a host device, the storage device transmits a prompt requesting transmission of a hardware reset signal to the host device, and the storage device performs a reset operation by receiving a hardware reset signal corresponding to the prompt from the host device. With the quick recovery operation, delay time due to the occurrence of an error may be reduced, and operation performance of the memory device may be improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0017502 filed on February 5, 2024, in the Korean Intellectual Property Office, Korean Patent Application No. 10-2024-0066487 filed on May 22, 2024, in the Korean Intellectual Property Office, Korean Patent Application No. 10-2024-0074520 filed on June 7, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0148154 filed on October 28, 2024, which are hereby incorporated by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to a storage device, a method for operating a storage device, and a computing system. Background Art

[0004] The storage device may include at least one memory for storing data. The storage device may include a controller for controlling the operation of the at least one memory.

[0005] The controller can control the operation of the memory based on a command received from an external device or a command of the controller itself. For example, the controller can control the operation of writing data to the memory or reading data written to the memory according to a command received from the external device.

[0006] An error may occur during operation of a storage device under the control of a controller. When an error has occurred, the controller may perform error recovery and ensure normal operation of the storage device in which the error has occurred, but this may result in additional delay time, which degrades the operating performance of the storage device. Summary of the Invention

[0007] Various embodiments of the present disclosure aim to provide measures capable of reducing a delay time due to a recovery operation when an error occurs during operation of a storage device and improving the operation performance of the storage device.

[0008] In an embodiment, a storage device may include: a memory; and a controller configured to control the operation of the memory, receive a command from a host device, and send a prompt to the host device requesting a hardware reset when an unrecoverable hardware error occurs while the host device waits for a response to the command according to a timeout policy.

[0009] In an embodiment, a method for operating a storage device may include: receiving a command unit from a host device; detecting an unrecoverable hardware error before a predetermined time period elapses after receiving the command unit; sending a prompt requesting a hardware reset to the host device within the predetermined time period; and receiving a hardware reset signal from the host device in response to the prompt.

[0010] In an embodiment, a computing system may include: a storage device; and a host device configured to send a command unit to the storage device, wherein, when an unrecoverable hardware error occurs while the host device waits for a response to the command unit according to a timeout policy, the storage device sends a prompt to the host device requesting a hardware reset.

[0011] According to an embodiment of the present disclosure, the operational performance of a storage device may be improved by reducing the time required to recover the operation when an error occurs during the operation of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a schematic configuration of a storage device according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram illustrating a configuration of a memory included in a storage device according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram illustrating an example of a reset operation method of a memory device according to an embodiment of the present disclosure.

[0015] Figure 4 is a diagram illustrating another example of a reset operation method of a memory device according to an embodiment of the present disclosure.

[0016] Figures 5 to 7 It shows that according to Figure 4 A diagram illustrating an example of operations of a host device and a memory device showing a reset operation method.

[0017] Figures 8 to 12 It shows that according to Figure 4 FIG2 is a diagram illustrating an example of a method for requesting or setting a hardware reset.

[0018] Figure 13 and Figure 14 is a diagram illustrating other examples of a reset operation method of a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings in which specific examples or embodiments that may be implemented are shown by way of illustration, and in the drawings, the same reference numerals and symbols may be used to represent the same or similar components even when the same or similar components are shown in different figures. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that a detailed description of well-known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure more unclear, the description will be omitted. Terms such as "including," "having," "comprising," "consisting of," and "formed of" used herein are generally intended to allow for the addition of other components unless these terms are used with the term "only." As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0020] Terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to limit the nature, order, sequence, or quantity of the elements, but is only used to distinguish the corresponding element from other elements.

[0021] When referring to a first element being “connected or coupled to” a second element, “contacting or overlapping” the second element, etc., it should be understood that not only the first element may be “directly connected or coupled to” the second element, or “directly contacting or overlapping” the second element, but also a third element may be “interposed” between the first and second elements, or the first and second elements may be “connected or coupled to”, “contacting or overlapping” each other via a fourth element, etc. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled to”, “contacting or overlapping”, etc., each other.

[0022] When time relative terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0023] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance range or error margin that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even when no relevant description is given. In addition, the term "may" fully encompasses all meanings of the term "may".

[0024] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a diagram illustrating a schematic configuration of a storage device according to an embodiment of the present disclosure.

[0026] Reference Figure 1 , the storage device may include at least one memory 110. The storage device 100 may include a controller 120 that controls the operation of the memory 110.

[0027] For example, the memory 110 may be a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, but the embodiments of the present disclosure are not limited thereto. The memory 110 may be a non-volatile memory such as NAND flash memory, 3D NAND flash memory, and NOR flash memory. In some embodiments, a portion of the memory 110 included in the storage device 100 may be a volatile memory, and the remaining portion of the memory 110 may be a non-volatile memory.

[0028] In addition, the memory 110 may be one of various types of memories such as resistive RAM, phase change memory, magnetoresistive memory, ferroelectric memory, and spin transfer torque memory. The memory 110 may be a processing-in-memory including a computing function or a data processing function.

[0029] The memory 110 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells. Two or more memory cells may constitute a page, and a plurality of pages may constitute a memory block.

[0030] The controller 120 may receive a command from the outside and may control the operation of the memory 110 based on the received command. In addition, the controller 120 may control the operation of the memory 110 based on an internally generated command. In this specification, a command received from the outside by the controller 120 may be referred to as an external command, and a command generated internally by the controller 120 may be referred to as an internal command.

[0031] The controller 120 may control the operation of the memory 110 based on an external command or an internal command. For example, the controller 120 may control the operation of writing data to the memory 110. The controller 120 may also control the operation of reading data written to the memory 110. Data may be transmitted and received between the controller 120 and the memory 110.

[0032] According to the type of the memory 110 , the controller 120 may control a data saving operation (eg, a refresh operation or a patrol scrub operation) or an erase operation of data written to the memory 110 .

[0033] To maintain and improve the operational performance of the storage device 100, the controller 120 may perform background operations associated with the memory 110 based on external commands received from the external host device 200 or based on internal commands. The background operations may include, for example, at least one of garbage collection operations, wear leveling operations, read reclamation operations, and bad block management operations. By controlling the background operations, the controller 120 may improve the operational performance of the storage device 100 or prevent degradation of the operational performance of the storage device 100.

[0034] The controller 120 may control the operation of the memory 110 based on a command received from the host device 200. The controller 120 may provide a processing result according to the operation corresponding to the command to the host device 200. The controller 120 may transmit data or a response signal to the host device 200.

[0035] For example, host device 200 may be a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a storage device configured in a data center, one of various electronic devices configured in a home network, one of various electronic devices configured in a telematics network, an RFID (radio frequency identification) device, a mobile device capable of human control or autonomous driving (e.g., a vehicle, robot, or drone), etc. Alternatively, host device 200 may be a virtual / augmented reality device that provides 2D or 3D virtual reality images or augmented reality images. Furthermore, host device 200 may be any of a variety of electronic devices, each of which requires a storage device 100 capable of storing data.

[0036] The host device 200 may include at least one operating system. The operating system may manage and control all functions and operations of the host device 200 and may control the interoperation between the host device 200 and the storage device 100. Depending on the mobility of the host device 200, the operating system may be classified into a general-purpose operating system and a mobile operating system.

[0037] The controller 120 and the host device 200 may be separate devices or may be integrated into one device, or some components or functions of the controller 120 may be implemented by being included in the host device 200. Hereinafter, for ease of explanation, the controller 120 and the host device 200 are described as separate devices as an example.

[0038] Figure 2is a diagram illustrating a configuration of a memory included in a storage device according to an embodiment of the present disclosure.

[0039] Reference Figure 2 , the memory 110 according to an embodiment of the present disclosure may include a memory cell array 111 , an address decoder 112 , a read and write circuit 113 , a control logic 114 , and a voltage generation circuit 115 .

[0040] The memory cell array 111 may include a plurality of memory blocks BLK1 to BLKz (where z is a natural number of 2 or greater).

[0041] In the plurality of memory blocks BLK, a plurality of word lines WL and a plurality of bit lines BL may be provided, and a plurality of memory cells may be arranged.

[0042] The plurality of memory blocks BLK may be connected to the address decoder 112 through a plurality of word lines WL. The plurality of memory blocks BLK may be connected to the read and write circuit 113 through a plurality of bit lines BL.

[0043] Each of the plurality of memory blocks BLK may include a plurality of memory cells. The plurality of memory cells may be nonvolatile memory cells and may be configured using nonvolatile memory cells having a vertical channel structure.

[0044] The memory cell array 111 may be configured as a memory cell array having a two-dimensional structure, and according to circumstances, may be configured as a memory cell array having a three-dimensional structure.

[0045] Each of the plurality of memory cells included in the memory cell array 111 can store at least 1 bit of data. For example, each of the plurality of memory cells included in the memory cell array 111 can be a single-level cell (SLC) storing 1 bit of data. In another example, each of the plurality of memory cells included in the memory cell array 111 can be a multi-level cell (MLC) storing 2 bits of data, a triple-level cell (TLC) storing 3 bits of data, a quad-level cell (QLC) storing 4 bits of data, or a memory cell storing at least 5 bits of data.

[0046] The number of bits of data stored in each of the plurality of memory cells can be dynamically determined. For example, a single-level cell storing 1 bit of data can be changed to a triple-level cell storing 3 bits of data.

[0047] The address decoder 112 , the read and write circuit 113 , the control logic 114 , and the voltage generation circuit 115 may operate as peripheral circuits that drive the memory cell array 111 .

[0048] The address decoder 112 may be connected to the memory cell array 111 through a plurality of word lines WL. The address decoder 112 may be configured to operate in response to control of the control logic 114.

[0049] The address decoder 112 may receive an address through an input / output buffer in the memory 110. The address decoder 112 may be configured to decode a block address in the received address and may select at least one memory block BLK according to the decoded block address.

[0050] The address decoder 112 may receive a read voltage Vread and a pass voltage Vpass from the voltage generation circuit 115 .

[0051] In an operation of applying a read voltage Vread during a read operation, the address decoder 112 may apply the read voltage Vread to a selected word line WL in a selected memory block BLK and may apply a pass voltage Vpass to the remaining unselected word lines WL.

[0052] In a program verification operation, the address decoder 112 may apply the verification voltage generated in the voltage generation circuit 115 to a selected word line WL in a selected memory block BLK, and may apply the pass voltage Vpass to the remaining unselected word lines WL.

[0053] The address decoder 112 may be configured to decode a column address from the received address and may send the decoded column address to the read and write circuit 113 .

[0054] The read operation and the program operation of the memory 110 may be performed in units of pages. An address received when each of the read operation and the program operation is requested may include at least one of a block address, a row address, and a column address.

[0055] The address decoder 112 may select a memory block BLK and a word line WL according to the block address and the row address. The column address may be decoded by the address decoder 112 and the decoded column address may be provided to the read and write circuit 113.

[0056] The address decoder 112 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0057] The read and write circuit 113 may include a plurality of page buffers PB. The read and write circuit 113 may operate as a read circuit in a read operation of the memory cell array 111 and may operate as a write circuit in a write operation of the memory cell array 111.

[0058] The read and write circuit 113 may also be referred to as a page buffer circuit or a data register circuit including a plurality of page buffers PB. The read and write circuit 113 may include a data buffer responsible for data processing functions, and may further include a cache buffer responsible for a cache function as appropriate.

[0059] A plurality of page buffers PB may be connected to the memory cell array 111 through a plurality of bit lines BL. In order to sense the threshold voltage (Vth) of the memory cells in a read operation and a program verification operation, the plurality of page buffers PB may continuously supply a sensing current to the bit lines BL connected to the memory cells, and may latch sensing data by sensing a change in the amount of current flowing according to a program state of the corresponding memory cell through a sensing node.

[0060] The read and write circuit 113 may operate in response to a page buffer control signal output from the control logic 114 .

[0061] In a read operation, the read and write circuit 113 may temporarily store the read data by sensing the data of the memory cell, and then may output the data DATA to the input / output buffer of the memory 110. As an exemplary embodiment, the read and write circuit 113 may further include a column selection circuit, etc., in addition to the page buffer PB or the page register.

[0062] The control logic 114 may be connected to the address decoder 112, the read and write circuit 113, and the voltage generation circuit 115. The control logic 114 may receive a command CMD and a control signal CTRL through an input / output buffer of the memory 110.

[0063] The control logic 114 may be configured to control the overall operation of the memory 110 in response to the control signal CTRL. The control logic 114 may output a control signal for adjusting a precharge potential level of a sensing node of the plurality of page buffers PB.

[0064] The control logic 114 may control the read and write circuit 113 to perform a read operation of the memory cell array 111. The voltage generation circuit 115 may generate a read voltage Vread and a pass voltage Vpass used in the read operation in response to a voltage generation circuit control signal output from the control logic 114.

[0065] Each of the memory blocks BLK of the above-described memory 110 may be composed of a plurality of pages corresponding to a plurality of word lines WL and a plurality of strings corresponding to a plurality of bit lines BL.

[0066] In a memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged to intersect each other. A memory cell connected to one of the plurality of word lines WL and one of the plurality of bit lines BL may be defined. A transistor may be provided in each memory cell.

[0067] The transistor in a memory cell may include a drain, a source, and a gate. The drain (or source) of the transistor may be connected to the corresponding bit line BL directly or through another transistor. The source (or drain) of the transistor may be connected to a source line (which may be ground) directly or through another transistor. The gate of the transistor may include a floating gate surrounded by a dielectric and a control gate to which a gate voltage is applied from a word line WL.

[0068] In each memory block BLK, a first selection line (also called a source selection line or a drain selection line) can be additionally set outside the first outermost word line WL between the two outermost word lines WL, closer to the read and write circuit 113, and a second selection line (also called a drain selection line or a source selection line) can be additionally set outside the second outermost word line WL between the two outermost word lines WL.

[0069] At least one dummy word line may be further provided between the first outermost word line and the first selection line. At least one dummy word line may be further provided between the second outermost word line and the second selection line.

[0070] The read operation and the program operation (write operation) of the above-described memory block BLK may be performed in units of pages, and the erase operation may be performed in units of the memory block BLK of the memory 110 .

[0071] An error may occur during an operation such as a write operation, a read operation, or an erase operation on a memory block BLK of the memory 110. An error may also occur in the operation of the controller 120 that controls the memory 110. Control of an operation for recovering from the error may be performed by the controller 120, but the controller 120 may not be able to perform error recovery or error recovery by the controller 120 may cause a delay.

[0072] Embodiments of the present disclosure may provide measures capable of controlling a reset operation of the memory device 100 when an error occurs in the operation of the memory device 100 to prevent or minimize degradation of operational performance of the memory device 100 due to error correction or recovery operations.

[0073] Figure 3 is a diagram illustrating an example of a reset operation method of a memory device according to an embodiment of the present disclosure.

[0074] Figure 3It is shown that during the period in which the memory device 100 operates according to a command of the host device 200 , the host device 200 performs a reset operation of the memory device 100 .

[0075] For example, the host device 200 may send a command to the storage device 100. The storage device 100 may perform an operation based on the command received from the host device 200. Various errors may occur during the operation of the storage device 100. When an error occurs during the operation of the storage device 100, processing of the command received from the host device 200 may not be performed.

[0076] When there is no response to the command transmitted to the memory device 100 , the host device 200 may transmit a reset signal to the memory device 100 .

[0077] When a reception response to a command transmitted to the memory device 100 is not received or when an operation completion response according to the command is not received, the host device 200 may transmit a reset signal to the memory device 100 .

[0078] For example, the host device 200 may first send a first reset signal. The first reset signal may be a signal requesting or instructing a reset of the operation of the command sent from the host device 200 to the storage device 100. Alternatively, the first reset signal may be a signal requesting or instructing a reset of the operation of a task associated with the command sent from the host device 200 to the storage device 100. Alternatively, the first reset signal may be a signal requesting or instructing a reset of a logical unit associated with the task including the command sent from the host device 200 to the storage device 100. Alternatively, the first reset signal may be a hardware reset signal requesting a reset of the storage device 100.

[0079] The host device 200 may wait for a response from the memory device 100 after transmitting the first reset signal. When no response is received from the memory device 100 after transmitting the first reset signal, the host device 200 may transmit a second reset signal to the memory device 100.

[0080] The second reset signal may be a signal requesting a reset of a unit larger than the unit requested by the first reset signal. For example, when the first reset signal is a signal requesting a task reset, the second reset signal may be a signal requesting a reset of a logic unit or hardware. In another example, when the first reset signal is a signal requesting a reset of a logic unit, the second reset signal may be a signal requesting a reset of hardware.

[0081] When there is no response to the command from the memory device 100, the host device 200 may sequentially transmit a first reset signal and a second reset signal. Although the host device 200 transmits two types of reset signals in this example, the host device 200 may sequentially transmit at least three types of reset signals or may repeatedly transmit the same type of reset signal.

[0082] After sending the command, the host device 200 may send a reset signal according to a preset condition. For example, when no response is received from the storage device 100 within a predetermined period of time after sending the command, the host device 200 may send a reset signal to the storage device 100.

[0083] The predetermined time period may be a time period that is fixed for all commands, or may be a time period determined according to the type of command that the host device 200 transmits to the storage device 100 .

[0084] When the host device 200 transmits a plurality of commands to the memory device 100 , the predetermined period may start at a time point when the first command is transmitted, or may start at a time point when the last command is transmitted.

[0085] When no response is generated from the storage device 100 within a predetermined period of time after a command is sent to the storage device 100, the host device 200 may send a reset signal to the storage device 100 to perform control of recovery of the storage device 100. As a result of the reset signal from the host device 200, the storage device 100 may enter a normal operating state again.

[0086] Embodiments of the present disclosure may provide a measure for performing a faster recovery operation when an error occurs by requesting the host device 200 to transmit a reset signal when the storage device 100 does not process an operation according to a command of the host device 200 .

[0087] Figure 4 is a diagram illustrating another example of a reset operation method of a memory device according to an embodiment of the present disclosure.

[0088] Reference Figure 4 , the host device 200 may send a command to the storage device 100 requesting an operation of the storage device 100 .

[0089] The storage device 100 that receives the command from the host device 200 may perform an operation according to the command. The storage device 100 may monitor the operating state of the storage device 100 and may check whether an unrecoverable error of the storage device 100 has occurred. Such control of the storage device 100 may be performed by the controller 120 of the storage device 100.

[0090] The situations in which an unrecoverable error occurs in the storage device 100 may vary. For example, there may be a situation in which the storage device 100 stops due to an unusual abnormal situation, a situation in which the storage device 100 is determined to be unable to operate due to a hardware failure such as a bit flip of a cache memory or buffer memory included in the storage device 100, a situation in which it is determined that another command cannot be processed due to a timeout occurring in the internal operation of the storage device 100, or a situation in which a task management unit receives a command from the host device 200. However, in addition to the above examples, as unrecoverable error situations according to embodiments of the present disclosure, a situation in which the storage device 100 cannot operate normally or cannot process a command from the host device 200 may also be included.

[0091] When an unrecoverable error condition occurs, the memory device 100 may send a signal to the host device 200 requesting a reset signal for faster recovery operations.

[0092] For example, the storage device 100 may transmit a signal requesting transmission of a reset signal for a task or a logical unit to the host device 200. The storage device 100 may transmit a signal requesting transmission of a hardware reset signal to the host device 200. The type of reset signal that the storage device 100 requests from the host device 200 is not limited and may include at least one of various reset signals that the storage device 100 may receive from the host device 200 when an unrecoverable error condition occurs.

[0093] The memory device 100 may transmit a signal requesting transmission of a reset signal to the host device 200 once or repeatedly. The memory device 100 may also transmit a signal requesting transmission of a reset signal to the host device 200 at regular time intervals.

[0094] The memory device 100 may transmit a request for transmission of a reset signal to the host device 200 using various types of signals.

[0095] For example, the memory device 100 may request transmission of the reset signal through a response signal transmitted to the host device 200 according to a command of the host device 200 .

[0096] Alternatively, the storage device 100 may request the host device 200 to send a reset signal through a separately defined signal.

[0097] Alternatively, the memory device 100 may request the host device 200 to send a reset signal using a signal of a type that can be sent through an interface for communicating with the host device 200 or using at least one of signal lines between the memory device 100 and the host device 200 .

[0098] The method in which the memory device 100 requests the host device 200 to transmit a reset signal is not limited to the above-described example and may vary in the embodiments of the present disclosure.

[0099] Embodiments of the present disclosure may include a memory device 100 that uses at least one of various types of signals that may be transmitted to a host device 200 before the memory device 100 receives a reset signal from the host device 200 when an unrecoverable error of the memory device 100 occurs.

[0100] When an unrecoverable error occurs after receiving a command from the host device 200 , if the memory device 100 requests the host device 200 to transmit a reset signal before receiving the reset signal, a delay in the operation of the memory device 100 may be reduced.

[0101] For example, when there is no response from the memory device 100 after sending a command, the host device 200 may send a reset signal to the memory device 100, or when there is no request to send a reset signal, the host device 200 may send a reset signal to the memory device 100. Therefore, even if the memory device 100 does not generate a reset signal sending request, the memory device 100 can still resolve an unrecoverable error condition.

[0102] When an unrecoverable error of the memory device 100 occurs, the memory device 100 and the host device 200 may perform control of a normal operation of the memory device 100 by requesting transmission of a reset signal or transmitting a reset signal.

[0103] In this case, for example, operations of the memory device 100 and the host device 200 may be performed based on a time elapsed after the host device 200 transmits a command to the memory device 100 .

[0104] Figures 5 to 7 It shows that according to Figure 4 A diagram illustrating an example of operations of a host device and a memory device showing a reset operation method.

[0105] Reference Figure 5 , the host device 200 may send a command unit (①) to the storage device 100. The command unit may be, for example, a command requesting that data be written to the storage device 100 or a command requesting that data written to the storage device 100 be read. Alternatively, the command unit may be a command requesting that a calculation be performed in the storage device 100 using the data stored in the storage device 100. In this case, the storage device 100 may perform the calculation according to the command of the host device 200 and return the result value of the calculation to the host device 200.

[0106] After the memory device 100 receives the command unit from the host device 200, an unrecoverable error may occur in the memory device 100. The unrecoverable error may include at least one of the above-mentioned errors.

[0107] The storage device 100 may monitor whether an unrecoverable error occurs before a predetermined period of time elapses after receiving the command unit from the host device 200. The predetermined period of time may be, for example, 30 seconds, but the embodiment is not limited thereto.

[0108] When an unrecoverable error is detected before a predetermined period of time has passed after receiving the command unit, the storage device 100 may send a prompt (②) requesting a reset signal to the host device 200. The prompt may refer to a signal or method for requesting a reset signal to be sent from the host device 200.

[0109] The storage device 100 may request, through a prompt, to send a signal indicating a reset of a command unit, a task associated with a command unit, or a logic unit including a task. Alternatively, through a prompt, the storage device 100 may request to send a signal indicating a reset of hardware.

[0110] When an unrecoverable error occurs in the storage device 100, it may be difficult to control the normal state of the storage device 100 using a signal from the host device 200 that instructs the reset of a task or logic unit. Therefore, when an unrecoverable error is detected within a predetermined period of time after receiving a command unit, the storage device 100 may send a prompt to the host device 200 requesting a signal to instruct a hardware reset, thereby enabling rapid recovery of the storage device 100.

[0111] The storage device 100 may, for example, utilize any one of the fields included in the response signal to be transmitted to the host device 200 to transmit a prompt requesting the transmission of a reset signal. The response signal may be a signal in response to a command unit received from the host device 200. The response signal may be generated in a state where an operation according to the command unit is being executed or not being executed. For example, the storage device 100 may utilize at least a portion of the device information field included in the response unit to transmit a prompt requesting the transmission of a reset signal. Alternatively, the storage device 100 may utilize at least one of the abnormal event control attribute and the abnormal event status attribute constituting the abnormal event to request the host device 200 to transmit a reset signal.

[0112] Alternatively, the storage device 100 may request to send a hardware reset signal by sending a signal requesting to initialize the communication interface between the host device 200 and the storage device 100. The signal requesting to initialize the communication interface may be one of the above prompts.

[0113] Alternatively, the storage device 100 may request to send a hardware reset signal by changing a signal level of at least one of signal lines physically connecting the host device 200 and the storage device 100. Changing the signal level of at least one of the signal lines may be one of the above prompts.

[0114] When receiving a prompt requesting to send a reset signal within a predetermined period of time after sending a command unit to the storage device 100 , the host device 200 may send a reset signal to the storage device 100 (③).

[0115] Even if the host device 200 does not receive a response signal corresponding to the command unit from the storage device 100, it can receive a prompt requesting to send a reset signal. In response to the request from the storage device 100, the host device 200 can send a signal to the storage device 100 instructing to reset the hardware.

[0116] Based on the request of the storage device 100 and the reset signal sent by the host device 200, control of an unrecoverable error that occurs in the storage device 100 within a predetermined time period after sending the command unit can be performed with less delay. The delay in processing the command from the host device 200 and the operation of the storage device 100 caused by the error of the storage device 100 can be reduced. The storage device 100 does not have to wait for the reset signal from the host device 200 during the predetermined time period. If the host device 200 operates according to the timeout policy, the host device 200 can send a reset signal or other signal for controlling the storage device 100 after the predetermined time period. The predetermined time period can be configured according to the timeout policy. In this case, the time period required to receive the reset signal from the host device 200 may be longer than the above case. By quickly recovering according to the reset request of the storage device 100, the delay and operating performance of the storage device 100 can be improved.

[0117] In other embodiments, the storage device 100 does not send a prompt requesting the host device 200 to send a reset signal within a predetermined period of time after receiving the command unit from the host device 200. For example, the host device 200 may send a control signal for recovery of the storage device 100 to the storage device 100 after the predetermined period of time has passed.

[0118] For example, refer to Figure 6 , the host device 200 may transmit a command unit (①) to the storage device 100 . The command unit may include at least one of commands instructing various operations of the storage device 100 .

[0119] An unrecoverable error may occur in the storage device 100 that receives the command unit. Due to the unrecoverable error, the storage device 100 may not send a response signal to the command unit of the host device 200. A predetermined time period may elapse during which the storage device 100 does not send a response signal to the command unit.

[0120] When no response signal corresponding to the command unit or prompt requesting to send a reset signal is received within a predetermined period of time after sending the command unit to the storage device 100 , the host device 200 may send a signal indicating a reset to the storage device 100 .

[0121] For example, when a predetermined period of time has passed after sending a command unit, the host device 200 may send a task management unit (②) to the storage device 100. For example, the task management unit may instruct the storage device 100 not to process the command unit sent from the host device 200. The task management unit may instruct the storage device 100 to operate without processing the command unit previously received at (①).

[0122] In response to the task management unit from the host device 200 , when the storage device 100 does not perform processing on the previously received command unit, the storage device 100 may transmit a response signal to the task management unit to the host device 200 (③).

[0123] When receiving a response signal corresponding to the task management unit at (③), the host device 200 may send a new command unit and request the storage device 100 to process the new command unit.

[0124] However, when an unrecoverable error occurs, the storage device 100 may not transmit a response signal to the task management unit of the host device 200 .

[0125] Therefore, when a response signal to the task management unit is not received from the storage device 100 , the host device 200 may transmit a signal instructing reset of a logic unit including a plurality of tasks to the storage device 100 (④).

[0126] The signal indicating the reset of the logical unit instructs the storage device 100 not to process a command unit previously sent by the host device 200 and related to the logical unit. The command unit may be a signal sent by the host device 200 to process a specific operation (e.g., programming, reading, etc.). The host device 200 may repeatedly send the signal indicating the reset of the logical unit.

[0127] When the host device 200 does not receive a response signal from the memory device 100 in response to the signal indicating the reset of the logic unit, the host device 200 may transmit a signal indicating a hardware reset of the memory device 100 to the memory device 100 (⑤).

[0128] The storage device 100 may be reset by a hardware reset signal from the host device 200. When an unrecoverable error occurs in the storage device 100, the storage device 100 may be reset to normal operation by the hardware reset of the storage device 100 at (⑤) and may enter a state where the storage device 100 can process a command unit from the host device 200.

[0129] Even when the storage device 100 does not send a reset request signal to the host device 200 due to an unrecoverable error within a predetermined time period after receiving the command unit, the storage device 100 can be restored by the reset signal sent by the host device 200 after the predetermined time period. The host device 200 can send the task management unit, the logic unit reset signal, and the hardware reset signal sequentially as in the above example, or can send the logic unit reset signal or the hardware reset signal in a different order. For example, the host device 200 can send the task management unit first. Alternatively, the host device 200 can send the logic unit reset signal or the hardware reset signal first. The object reset by the hardware reset can be larger than the object reset by the logic unit reset signal. Furthermore, the object reset by the logic unit reset signal can be larger than the object reset by the task management unit.

[0130] In other embodiments, even when the host device 200 receives a prompt requesting to send a reset signal from the storage device 100, the host device 200 may control the operation of the storage device 100 by sending various reset signals to the storage device 100 before or after the predetermined time period expires.

[0131] For example, refer to Figure 7 , the host device 200 can send a command unit (①) to the storage device 100.

[0132] An unrecoverable error may occur in the storage device 100. The storage device 100 may send a prompt (②) requesting the host device 200 to send a reset signal within a predetermined period of time after receiving the command unit.

[0133] Upon receiving the prompt requesting to send a reset signal, the host device 200 may send a task management unit to the storage device 100 (③). The host device 200 may receive a response signal corresponding to the task management unit from the storage device 100 (④).

[0134] When the host device 200 does not receive a response signal corresponding to the task management unit, the host device 200 may transmit a signal (⑤) instructing reset of the logic unit to the storage device 100. The host device 200 may repeatedly transmit the signal instructing reset of the logic unit.

[0135] If the host device 200 does not receive a response signal from the storage device 100, the host device 200 may transmit a signal (⑥) instructing a hardware reset to the storage device 100. If the host device 200 operates according to a timeout policy, the host device 200 may transmit the signal instructing a hardware reset after a predetermined period of time has elapsed. Alternatively, the host device 200 may transmit this signal after a predetermined period of time has elapsed and after transmitting another type of reset signal a predetermined number of times.

[0136] In various embodiments, when receiving a prompt requesting to send a reset signal from the storage device 100, the host device 200 may immediately send a hardware reset signal, or may sequentially send a task management unit, a logic unit reset signal, and a hardware reset signal, or the host device 200 may send a signal indicating the reset of the storage device 100 within a predetermined time period after sending the command unit or after a predetermined time period has passed.

[0137] Therefore, when the storage device 100 sends a prompt requesting transmission of a reset signal due to occurrence of an unrecoverable error within a predetermined period of time after receiving a command unit, the operation of the host device 200 may be changed to achieve faster recovery.

[0138] If the storage device 100 does not send a prompt within a predetermined period of time, the host device 200 may perform a reset signal sending process. Therefore, even when the storage device 100 does not generate a request within a predetermined period of time, the host device 200 may perform a recovery process.

[0139] The prompt requesting the reset signal from the storage device 100 can be sent in various ways. For example, the reset signal can be requested using a response signal sent from the storage device 100 to the host device 200, but the reset signal can also be sent using an unused bit of the exception event.

[0140] Figures 8 to 12 It shows that according to Figure 4 FIG2 is a diagram illustrating an example of a method for requesting or setting a hardware reset.

[0141] Figure 8 A prompt requesting transmission of a reset signal is shown, which is transmitted to the host device 200 using a device information field included in a response unit to be transmitted from the storage device 100 to the host device 200 .

[0142] The storage device 100 may send a hint using a response unit to be sent to the host device 200. The response unit may be sent in response to a command unit previously received from the host device 200. Alternatively, the storage device 100 may generate a response unit for sending a hint and may send the hint to the host device 200 using the response unit.

[0143] The Device Information field can provide device-level information and is not necessarily associated with the logic unit executing the command. For example, the information provided by the Device Information field may be information about events that change more slowly than typical commands or information where the response delay of the host device 200 is unimportant or irrelevant. Using the Device Information field can avoid continuous polling for some UFS attributes.

[0144] Bit 0 and bits [2:5] of the Device Information field may be defined. Bit 1 of the Device Information field may be reserved for the Host Performance Booster (HPB) extension standard. The other bits of the Device Information field may be reserved and set to 0.

[0145] Bits [2:5] of the device information field included in the response unit may be used to indicate whether a fast recovery operation is required.

[0146] For example, when the value of bits [2:5] of the device information field is 0x0, this value may indicate that the memory device 100 does not need to be reset. Therefore, when the value of bits [2:5] of the device information field included in the response unit sent from the memory device 100 to the host device 200 is 0x0, the host device 200 may recognize that the memory device 100 has not sent a hardware reset request signal.

[0147] When the value of bits [2:5] of the device information field is not 0x0, the value may indicate that the storage device 100 requests a hardware reset signal. In addition to whether a hardware reset signal is requested, the value of bits [2:5] of the device information field may also indicate a waiting time before sending a hardware reset signal.

[0148] For example, when the value of bits [2:5] of the device information field is 0x1, the value may indicate that the memory device 100 needs to be reset. The host device 200 may recognize the value as a hint requesting a hardware reset signal upon receiving the hint from the memory device 100.

[0149] When the value of bits [2:5] of the device information field is 0x1, the host device 200 can recognize that no waiting time is required before generating a hardware reset signal. When the value of bits [2:5] of the device information field included in the response unit received from the storage device 100 is 0x1, the host device 200 can recognize that the storage device 100 generates a request for a hardware reset signal and can transmit the hardware reset signal to the storage device 100 without waiting time.

[0150] When the value of bits [2:5] of the device information field is other than 0x0 and 0x1, the value may indicate that there is a waiting time before the host device 200 generates a hardware reset signal.

[0151] For example, when the value of bits [2:5] of the device information field is 0x2, the value may indicate that the memory device 100 requests a reset and the waiting time before the host device 200 generates a hardware reset signal is 1 second.

[0152] When the value of bits [2:5] of the device information field included in the response unit received from the storage device 100 is 0x2, the host device 200 may send a hardware reset signal to the storage device 100 after 1 second. Alternatively, the host device 200 may send a hardware reset signal to the storage device 100 within 1 second after receiving the response unit including the device information field from the storage device 100.

[0153] Similarly, according to the value of bits [2:5] of the device information field, the waiting time required by the host device 200 before generating a hardware reset signal may be set differently.

[0154] When receiving information requesting a reset from the storage device 100 as in the above example, the host device 200 may send a hardware reset signal to the storage device 100 after a waiting time set according to the value of bits [2:5] of the device information field. Alternatively, the host device 200 may send a hardware reset signal to the storage device 100 within the set waiting time.

[0155] When the value of bits [2:5] of the device information field is 0xF, the waiting time before the host device 200 generates a hardware reset signal may be set to 14 seconds. 14 seconds may be the maximum waiting time, but embodiments of the present disclosure are not limited thereto.

[0156] Before a predetermined period of time elapses after the host device 200 transmits a command, the storage device 100 may request the host device 200 to transmit a hardware reset signal for a quick recovery operation through the device information field.

[0157] The storage device 100 can set a wait time for the host device 200. Even when the wait time is set, a reset operation of the storage device 100 by a hardware reset signal from the host device 200 can be performed within a time period shorter than the predetermined time period. For example, the wait time can be shorter than the predetermined time period. The host device 200 can send a hardware reset signal to the storage device 100 after the wait time has elapsed and before the predetermined time period has elapsed. Furthermore, the storage device 100 can perform certain operations during the wait time. For example, after sending a response unit including a device information field, the storage device 100 can perform an operation during an idle period, such as a background operation, during the wait time of the host device 200.

[0158] In the above example, the value of bits [2:5] of the device information field sets the waiting time of the host device 200 before generating a hardware reset signal in units of 1 second, but in other embodiments, the waiting time can be set in different units such as 0.1 seconds, 0.5 seconds, 2 seconds, etc.

[0159] In addition, although the above example utilizes bits [2:5] of the device information field to indicate whether a hardware reset signal and a wait time are requested, at least some of the other bits from the device information field that are not set for other purposes can be utilized to send information requesting that a hardware reset signal be sent after a wait time.

[0160] In other embodiments, the prompt requesting the hardware reset signal may be sent using another format other than the device information field.

[0161] Figure 9 This illustrates an example in which the storage device 100 utilizes an abnormal event to send a prompt requesting the host device 200 to send a reset signal.

[0162] The storage device 100 may request to send a reset signal, for example, by utilizing at least one of an abnormal event control attribute and an abnormal event status attribute included in an abnormal event. An abnormal event may be composed of, for example, an event alarm bit, an abnormal event control attribute, and an abnormal event status attribute.

[0163] The abnormal event control attribute may be composed of, for example, 2 bytes. Various information or requests may be sent to the host device 200 using the 2 bytes of the abnormal event control attribute.

[0164] The abnormal event status attribute may be composed of, for example, 2 bytes. Various information or requests may be sent to the host device 200 using the 2 bytes of the abnormal event status attribute.

[0165] For example, bit 0 of the abnormal event control attribute or abnormal event status attribute may be used for the storage device 100 to request a dynamic capacity operation. When bit 0 of the abnormal event control attribute or abnormal event status attribute is set, this may indicate that the storage device 100 requests a dynamic capacity operation.

[0166] Bit 1 of the abnormal event control attribute or the abnormal event status attribute may indicate that all resources for processing the data of the host device 200 as system data are consumed. When the memory area managed by the host device 200 as the system data area is changed to the non-system data area, bit 1 of the abnormal event control attribute or the abnormal event status attribute may be cleared.

[0167] Bit 2 of the exception event control attribute or the exception event status attribute may indicate that the storage device 100 requests the host device 200 to pay attention to the required level of background operation. When the status of the background operation returns to 00h or 01h, bit 2 of the exception event control attribute or the exception event status attribute may be cleared.

[0168] Bit 3 of the abnormal event control attribute or abnormal event status attribute can be used by the storage device 100 to request the host device 200 to lower the temperature of the storage device 100. Bit 4 of the abnormal event control attribute or abnormal event status attribute can be used by the storage device 100 to request the host device 200 to increase the temperature of the storage device 100.

[0169] Bit 5 of the exception event control attribute or the exception event status attribute may indicate that a buffer of a write enhancer in the storage device 100 needs to be flushed.

[0170] Bit 6 of the exception event control attribute or the exception event status attribute may indicate that the storage device 100 is operating at reduced performance for throttling.

[0171] Bit 7 of the exception event control attribute or the exception event status attribute may indicate that an exception has occurred in the level of the storage device 100 .

[0172] The memory device 100 may request transmission of a signal indicating a reset of the memory device 100 using at least one bit other than bits 0 to 7 in the abnormal event control attribute or the abnormal event status attribute.

[0173] For example, the storage device 100 may send a request for a reset signal to the host device 200 by setting bit 8 of the abnormal event control attribute or the abnormal event status attribute to reset the storage device 100 .

[0174] When an unrecoverable error occurs within a predetermined period of time after receiving a command unit from the host device 200, the storage device 100 may set the value of bit 8 of the abnormal event control attribute or the abnormal event status attribute. The storage device 100 may send the abnormal event control attribute or the abnormal event status attribute with bit 8 changed to the host device 200.

[0175] When the host device 200 receives the attributes from the storage device 100, the host device can recognize that a hardware reset of the storage device 100 is required by checking the setting value of bit 8 of the exception event control attribute or the exception event status attribute. The host device 200 can then send a signal indicating a hardware reset to the storage device 100. When the signal indicating a hardware reset is sent to the storage device 100, bit 8 of the exception event control attribute or the exception event status attribute can be cleared.

[0176] The modes of operation of the memory device 100 and the host device 200 in a state where an unrecoverable error occurs may be set by separate properties.

[0177] For example, refer to Figure 10 You can set options for fast recovery mode operations through the fast recovery method property.

[0178] The quick recovery method attribute may consist of, for example, 1 byte. When the quick recovery method attribute is set to 00h, a hardware reset signal may be sent in response to a prompt from the storage device 100. When the quick recovery method attribute is set to 01h, a task management unit may be sent in response to a prompt from the storage device 100. When the quick recovery method attribute is set to 10h, a retry may be performed in response to a prompt from the storage device 100. The above is merely an example, and depending on the setting value of the quick recovery method attribute, the signal to be sent to the storage device 100 or the operation of the host device 200 may vary in response to a prompt from the storage device 100.

[0179] In addition, the fast resume mode wait time can be set using the fast resume wait time attribute. This attribute can define the wait time before the host device 200 performs operations related to the fast resume operation. The fast resume wait time attribute can be expressed in units of 1ms. The wait time before the host device 200 performs operations such as hardware reset, task management unit, and retry can be determined by the set value of the fast resume wait time.

[0180] Whether such a quick recovery mode is supported may be indicated by the extended UFS feature support of the storage device 100 .

[0181] For example, refer to Figure 11, whether the quick resume mode is supported can be indicated by the device descriptor. For example, whether the storage device 100 supports the quick resume mode can be indicated by setting bit 19 of the extended UFS feature support of the device descriptor. Alternatively, at least one bit other than bits 0 to 18 of the extended UFS feature support can be used to indicate whether the quick resume mode is supported.

[0182] When the storage device 100 supports the fast recovery mode, it sends a prompt to the host device 200 within a predetermined period of time requesting a reset signal according to the setting value of the fast recovery mode wait time. The host device 200 receiving the prompt can send a reset signal to the storage device 100 according to the fast recovery method attribute.

[0183] The storage device 100 may send a prompt through attributes constituting an abnormal event, and in some embodiments, may send a prompt through other signals.

[0184] For example, refer to Figure 12 The storage device 100 may request the transmission of a reset signal through a response signal. The storage device 100 may request the transmission of a reset signal using a sensing key included in a response unit transmitted in response to a command unit. Information regarding the occurrence of a hardware error may be transmitted to the host device 200 through the sensing key.

[0185] When an unrecoverable error occurs in the storage device 100 within a predetermined period of time, it may be impossible to send a response unit to a command unit received from the host device 200. Therefore, a prompt may be sent to the host device 200 using a response unit corresponding to another different command unit. The another command unit may be a command unit received before receiving the command unit corresponding to the unrecoverable error, or may be a command unit received after receiving the command unit corresponding to the unrecoverable error.

[0186] In this way, the storage device 100 can provide a request to send a reset signal to the host device 200 through the sensing key or abnormal event attribute included in the response unit when an unrecoverable error occurs within a predetermined time period after receiving the command unit of the host device 200, and can receive the reset signal of the host device 200 to perform a reset of the storage device 100, thereby making the operation faster.

[0187] In some embodiments, in addition to the above signals, a reset signal may be requested to be sent via a communication interface or a physical signal line between the host device 200 and the storage device 100 .

[0188] Figure 13 and 14 is a diagram illustrating other examples of a reset operation method of a memory device according to an embodiment of the present disclosure.

[0189] Reference Figure 13 , the host device 200 and the storage device 100 can send and receive signals through the communication interface. For example, communication can be performed between a first interface of the host device 200 and a second interface of the storage device 100.

[0190] The memory device 100 may receive a command from the host device 200 through the interface. When an unrecoverable error occurs within a predetermined period of time after receiving the command, the memory device 100 may transmit a signal requesting initialization of the interface to the host device 200.

[0191] When the host device 200 receives a signal requesting initialization of an interface from the storage device 100 within a predetermined period and the host device 200 has not received a response signal corresponding to a command unit sent to the storage device 100 , the host device 200 may determine that a hardware reset is required.

[0192] The host device 200 may transmit a hardware reset signal to the memory device 100 in response to the initialization request signal. A quick recovery of the memory device 100 may be performed by the reset signal.

[0193] Alternatively, information on the necessity of resetting the memory device 100 may be provided to the host device 200 through at least one of physical signal lines between the host device 200 and the memory device 100 .

[0194] For example, refer to Figure 14 , the storage device 100 may include a storage pin 130. The host device 200 may include a host pin 210. The storage pin 130 and the host pin 210 may be connected via a physical signal line. The signal line connecting the storage pin 130 and the host pin 210 may maintain a constant voltage level.

[0195] The host device 200 may transmit a command to the memory device 100 , and an unrecoverable error of the memory device 100 may occur.

[0196] When an unrecoverable error occurs, the memory device 100 may change the level of a signal line connecting the memory pin 130 of the memory device 100 and the host pin 210 of the host device 200 from an existing level.

[0197] For example, the signal line connecting the storage pin 130 and the host pin 210 can maintain a first level (e.g., a high level), and when the storage device 100 discovers an unrecoverable error, the level of the corresponding signal line can be changed to a second level (e.g., a low level).

[0198] When the level of the signal line connecting the host pin 210 and the storage pin 130 changes within a predetermined time period after sending a command, the host device 200 can recognize that a hardware reset of the storage device 100 is required, and since the host device 200 uses the signal line to send a hardware reset signal to the storage device 100, the recovery of the storage device 100 can be made faster.

[0199] According to the embodiments of the present disclosure described above, the storage device 100 can send a prompt to the host device 200 requesting a hardware reset based on an unrecoverable error occurring within a predetermined period of time after receiving a command from the host device 200. The storage device 100 can perform a quick recovery based on the hardware reset signal sent from the host device 200 in response to the prompt.

[0200] Therefore, it is possible to reduce a delay time due to an unrecoverable error occurring in the memory device 100 and improve the operation performance of the memory device 100 .

[0201] Although various embodiments of the present disclosure have been described with specific details and variations for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible based on the contents disclosed or described in the present disclosure without departing from the spirit and scope of the present disclosure as defined in the claims.

Claims

1. A storage device comprising: Memory; as well as A controller controls the operation of the memory, receives a command from a host device, and sends a prompt requesting a hardware reset to the host device when an unrecoverable hardware error occurs while the host device waits for a response to the command according to a timeout policy.

2. The storage device according to claim 1, wherein The timeout policy includes a predetermined time period that elapses after the command is sent, the unrecoverable hardware error occurs before the predetermined time period elapses, and the controller sends the prompt to the host device within the predetermined time period.

3. The storage device according to claim 1, wherein When the controller does not send the prompt to the host device within a predetermined period of time, the controller receives at least one of a task management unit, a logic unit reset signal, and a hardware reset signal from the host device after the predetermined period of time has elapsed. The storage device according to claim 1 , wherein: The controller receives a hardware reset signal from the host device in response to the prompt. The storage device according to claim 1 , wherein: The controller sends the prompt using a device information field included in a response unit sent to the host device. The storage device according to claim 5 , wherein: The controller sends the prompt using at least a portion of bit 2 to bit 5 of the device information field.

7. The storage device according to claim 5, wherein: The device information field includes information about a waiting time before a hardware reset signal is sent from the host device.

8. The storage device according to claim 1, wherein The controller sends the prompt to the host device using at least one of an abnormal event control attribute and an abnormal event status attribute for configuring an abnormal event.

9. The storage device according to claim 8, wherein: The controller sends the prompt to the host device using at least one bit except bits 0 to 7 of the abnormal event control attribute.

10. The storage device according to claim 8, wherein The controller sends the prompt to the host device using bit 8 of the exception event control attribute.

11. The storage device according to claim 8, wherein The controller sends the prompt to the host device using at least one bit except bits 0 to 7 of the abnormal event status attribute.

12. The storage device according to claim 8, wherein The controller sends the prompt to the host device using bit 8 of the abnormal event status attribute.

13. The storage device according to claim 8, wherein The controller clears the bit indicating the prompt in the abnormal event status attribute after receiving a hardware reset signal from the host device.

14. A method for operating a storage device, comprising: receiving a command unit from a host device; detecting an unrecoverable hardware error before a predetermined period of time has elapsed after receiving the command unit; sending a prompt requesting a hardware reset to the host device within the predetermined time period; as well as A hardware reset signal is received from the host device in response to the prompt.

15. The method according to claim 14, wherein The prompt is sent to the host device using at least a portion of a device information field included in a response element.

16. The method according to claim 15, wherein The prompt is sent to the host device using at least a portion of bits 2 through 5 of the device information field.

17. The method according to claim 15, wherein: The prompt includes information about a waiting time before the host device can send the hardware reset signal.

18. A computing system comprising: storage device; as well as A host device sends a command unit to the storage device, Wherein, when the host device waits for a response to the command unit according to a timeout policy, when an unrecoverable hardware error occurs, the storage device sends a prompt requesting a hardware reset to the host device.

19. The computing system of claim 18, wherein: When the unrecoverable hardware error occurs before a predetermined period of time elapses after receiving the command unit, the storage device sends the prompt to the host device within the predetermined period of time.

20. The computing system of claim 18, wherein: When the storage device does not send the prompt to the host device within a predetermined period of time, the storage device receives at least one of a task management unit, a logic unit reset signal, and a hardware reset signal from the host device after the predetermined period of time has elapsed.

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