System manager, error data processing method, device and program product

Abstract

The present application discloses a system manager, an error data processing method, a device and a program product, and relates to the technical field of data processing. Since the processor is used to write the error data corresponding to the system error into an error information storage area when a system error is detected, the controller is used to read the error data stored in the error information storage area and generate an alarm message when the error data meets a preset condition. Therefore, the transmission of error data and efficient asynchronous communication are achieved through the error information storage area and the interrupt register, and a preset condition is added. When the preset condition is met, the alarm message is triggered, thereby avoiding the processor from entering the system management mode, and at the same time reducing the performance jitter of the operating system caused by frequent system management interrupts, thereby improving the efficiency of the system in processing error data.

Description

Technical Field

[0001] The present application relates to the technical field of data processing, and in particular to a system manager, a method for processing erroneous data, a device, and a program product. Background Art

[0002] High-performance computing devices place extremely high demands on reliability, availability, and serviceability (RAS). For example, in server systems, RAS can be implemented through a collaborative approach of hardware and software. When a hardware error is detected, it can be categorized as a correctable error (CE), an uncorrectable but recoverable error (UCE), or an uncorrectable fatal error (FATAL). Different error handling paths are triggered based on the error type.

[0003] When handling different errors, CE and UCE frequently cause the central processing unit (CPU) to enter a special operating mode, blocking operating system services. After a fatal error is triggered, it takes too long to read CPU register data, resulting in low system efficiency in handling error data. Summary of the Invention

[0004] The present application provides a system manager, an error data processing method, a device, and a program product to at least solve the problem of low efficiency of error data processing in the system in the related art.

[0005] The present application provides a system manager, the system manager including a processor and a controller, the processor being connected to the controller;

[0006] The controller includes an error information storage area and an interrupt register. The error information storage area is a register area reserved in the controller;

[0007] a processor, configured to, upon detecting a system error, write error data corresponding to the system error into an error information storage area and send an error notification signal to the controller, the error notification signal including a first error notification signal and / or a second interrupt signal, the first error notification signal being configured to trigger an interrupt register to generate a first interrupt signal, and the second interrupt signal being an interrupt signal generated by the processor via a preset pin;

[0008] The controller is configured to read error data stored in the error information storage area in response to the received first interrupt signal and / or second interrupt signal, and generate alarm information when the error data meets a preset condition.

[0009] This application also provides a method for processing erroneous data, including:

[0010] Performing detection and processing on the system to determine whether there is a system error in the system, and if so, determining the error data corresponding to the system error;

[0011] Writing the error data into an error information storage area of ​​the controller and sending an error notification signal to the controller, where the error information storage area is a register area reserved in the controller, and the error notification signal includes a first error notification signal and / or a second interrupt signal, where the first error notification signal is used to trigger an interrupt register of the controller to generate a first interrupt signal;

[0012] Reading at least one error data in an error information storage area according to the first interrupt signal and / or the second interrupt signal, and storing the at least one error data in an error log;

[0013] Generate alarm information according to at least one error data in the error log.

[0014] The present application also provides a device for processing erroneous data, comprising:

[0015] The detection module is used to detect and process the system to determine whether there is a system error in the system. If so, it determines the error data corresponding to the system error;

[0016] a writing module, configured to write error data into an error information storage area of ​​the controller and send an error notification signal to the controller, wherein the error information storage area is a register area reserved in the controller, and the error notification signal includes a first error notification signal and / or a second interrupt signal, wherein the first error notification signal is configured to trigger an interrupt register of the controller to generate a first interrupt signal;

[0017] a reading module, configured to read at least one error data from the error information storage area according to the first interrupt signal and / or the second interrupt signal, and store the at least one error data in an error log;

[0018] The sending module is used to generate alarm information according to at least one error data in the error log.

[0019] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned methods for processing erroneous data when executing the computer program.

[0020] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for processing erroneous data are implemented.

[0021] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned error data processing methods when the computer program is executed by a processor.

[0022] Through the present application, since the processor is used to write the error data corresponding to the system error into the error information storage area when a system error is detected, the controller is used to read the error data stored in the error information storage area and generate an alarm message when the error data meets the preset conditions. Therefore, the transmission of error data and efficient asynchronous communication are realized through the error information storage area and the interrupt register, and the preset conditions are added. When the preset conditions are met, the alarm information is triggered, thereby avoiding the processor from entering the system management mode, and at the same time reducing the performance jitter of the operating system caused by frequent system management interrupts, and improving the efficiency of the system in processing error data. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 A schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of the structure of a system manager provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of the structure of another system manager provided in an embodiment of the present application;

[0027] Figure 4 A flowchart of a method for processing erroneous data provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of the structure of an erroneous data processing device provided in an embodiment of the present application;

[0029] Figure 6 This is a schematic diagram of the structure of the electronic device provided in this application. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0031] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0032] High-performance computing equipment places extremely high demands on reliability, availability, and serviceability (RAS). For example, in server systems based on , RAS can be implemented through a collaborative approach of hardware and software. When a hardware error is detected, it can be categorized as a correctable error (CE), an uncorrectable but recoverable error (UCE), or an uncorrectable fatal error (FATAL). Different error handling paths are triggered based on the error.

[0033] RAS can be the core technology to ensure high reliability, high availability and serviceability in computer systems, and can be applied to key infrastructure such as servers and data centers.

[0034] The core objectives of RAS include:

[0035] Reliability: Reduces system failures caused by hardware errors.

[0036] Availability: Maximize system uptime.

[0037] Serviceability: Quickly locate and repair faults.

[0038] For example, RAS is typically implemented through the following hardware / software collaboration:

[0039] The hardware layer can include the CPU's Machine Check Architecture (MCA), memory's Error-Correcting Code (ECC), and PCI Express Advanced Error Reporting (PCIe AER).

[0040] The software layer may include the operating system's Machine Check Exception (MCE) handler and the Baseboard Management Controller (BMC)'s System Event Log (SEL).

[0041] Next, combine Figure 1 , explaining the processing paths for various hardware errors.

[0042] Figure 1 This is a schematic diagram of the structure of a computer system provided in an embodiment of the present application. Figure 1 , Figure 1 It can include main memory, central processing unit (CPU), basic input / output system (BIOS), baseboard management controller (BMC) and operating system (OS).

[0043] For correctable errors (CE), when a System Management Interrupt (SMI) is triggered, the BIOS prioritizes SMI processing. The SMI handler in the BIOS reads and parses the error log from the Model-Specific Registers (MSR) of the CPU's Machine Check Architecture (MCA). The SMI handler reports the error log as a system event log event to the BMC through the Intelligent Platform Management Interface (IPMI). Once the report is complete, a Corrected Machine Check Interrupt (CMCI) is triggered to notify the OS. The OS's CMCI handler handles the correctable error accordingly.

[0044] For uncorrectable error recoverable (UCE), when a system management interrupt (SMI) is triggered, the BIOS prioritizes SMI processing. The BIOS's SMI handler reads and parses the error log from the model-specific registers of the CPU's MCA. The SMI handler reports the error log as a system event log event to the BMC via IPMI. Once the report is complete, an interrupt signal is triggered to notify the OS. The OS's MCA handler handles the uncorrectable error accordingly.

[0045] For uncorrectable fatal errors, a dedicated hardware interrupt signal is triggered to notify the BMC.

[0046] For CE and UCE, system management interrupts cause the CPU to enter System Management Mode (SMM), monopolizing CPU resources and blocking normal OS operations. If the SMI handler takes too long to process, it may cause the OS kernel watchdog to time out. Frequent SMI triggering can significantly degrade OS performance.

[0047] Fatal errors trigger a preset hardware interrupt to notify the BMC, which then reads the model-specific registers of the CPU's MCA through the Processor Environment Control Interface (PECI). PECI is a single-bus interface with a low data transfer rate. However, the model-specific registers in the CPU's MCA contain large amounts of data. Reading all model-specific registers typically takes about two minutes, which is quite time-consuming.

[0048] In summary, when handling different errors, CE and UCE will cause the CPU to frequently enter a special operating mode, blocking the operating system services. After Fatal is triggered, it takes too long to read the register data in the CPU, resulting in low efficiency in the system's handling of error data.

[0049] In order to solve the above technical problems, an embodiment of the present application provides a system manager, including a processor and a controller, the controller including an error information storage area and an interrupt register, the error information storage area being a register area reserved in the controller, the processor being used to write error data corresponding to the system error into the error information storage area when a system error is detected, and to send an error notification signal to the controller, the error notification signal including a first error notification signal and / or a second interrupt signal, the first error notification signal being used to trigger the interrupt register to generate a first interrupt signal, the controller being used to read the error data stored in the error information storage area in response to the received first interrupt signal and / or second interrupt signal, and to generate an alarm message when the error data meets a preset condition. In this way, the transmission of error data and efficient asynchronous communication are achieved through the error information storage area and the interrupt register, and a preset condition is added. When the preset condition is met, the alarm message is triggered, thereby avoiding the processor from entering the system management mode, while reducing the performance jitter of the operating system caused by frequent system management interrupts, and improving the efficiency of the system in processing error data.

[0050] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0051] Figure 2 This is a schematic diagram of the structure of a system manager provided in an embodiment of the present application. Figure 2 , Figure 2 At least the system manager.

[0052] The system manager includes a processor and a controller, and the processor is connected to the controller;

[0053] The controller includes an error information storage area and an interrupt register;

[0054] a processor, configured to, upon detecting a system error, write error data corresponding to the system error into an error information storage area and send an error notification signal to the controller, the error notification signal including a first error notification signal and / or a second interrupt signal, the first error notification signal being configured to trigger an interrupt register to generate a first interrupt signal, and the second interrupt signal being an interrupt signal generated by the processor via a preset pin;

[0055] The controller is configured to read error data stored in the error information storage area in response to the received first interrupt signal and / or second interrupt signal, and generate alarm information when the error data meets a preset condition.

[0056] The processor may be a central processing unit.

[0057] The processor can be used to execute instructions and process data.

[0058] The controller may be a baseboard management controller or other similar management controller.

[0059] The controller can be used to monitor and manage the hardware status of the computer system.

[0060] The processor may include a PCIe controller, which may be used to manage devices on the PCIe link.

[0061] The processor can establish a connection with the controller through the internally integrated PCIe controller.

[0062] The processor may be configured with functional modules corresponding to a Machine Check Architecture (MCA).

[0063] A machine check architecture may be a mechanism within a processor for detecting and reporting hardware errors.

[0064] The error information storage area is the register area reserved in the controller.

[0065] The register area may be a storage area in a base address register.

[0066] The error information storage area may be used to store a base address of error data transmitted from the processor to the controller.

[0067] There is a mapping relationship between the base address of the error information storage area and the memory address of the processor.

[0068] The interrupt register may be used to generate a first interrupt signal to notify the controller of reading error data.

[0069] When a system error is detected, the processor can be used to write error data corresponding to the system error into the error information storage area in a predefined format through the machine check architecture, and send an error notification signal to the controller.

[0070] The error notification signal includes a first error notification signal and / or a second interrupt signal.

[0071] The first error notification signal is used to trigger the interrupt register to generate a first interrupt signal.

[0072] The second interrupt signal is an interrupt signal generated by the processor through a preset pin.

[0073] The preset pin may be a processor error pin.

[0074] A hardware interrupt signal can be generated by pulling the preset pin high.

[0075] In this way, the controller is directly notified through the hardware interrupt signal, which serves as a redundant backup signal of the interrupt register. When the error is serious, the controller can also be notified through the hardware interrupt signal.

[0076] The alarm information can be used to notify the operating system to perform corresponding processing on the system error.

[0077] The controller can be configured with the Intelligent Platform Management Interface (IPMI).

[0078] The intelligent platform management interface may be a standardized hardware management interface that is independent of the operating system and the processor.

[0079] Alarm information can be sent through the intelligent platform management interface. The driver corresponding to the IPMI of the operating system receives the alarm information and can generate system logs or perform corresponding processing based on the alarm information, such as isolating the device, issuing an alarm to notify the operation and maintenance department to replace the device, etc.

[0080] In one possible implementation, the processor is further configured to configure a first register with an address type of memory mapped I / O for the error information storage area in a register set corresponding to a peripheral component interconnect express bus PCIe;

[0081] The processor is also used to perform PCIe enumeration operations during the system initialization phase through the BIOS firmware, determine the second register corresponding to the error information storage area on the controller, and map the base address of the error information storage area to the memory address corresponding to the first register, where the second register is an existing register in the controller or a newly added register.

[0082] The processor configures a first register for an error information storage area in a register set corresponding to the PCIe controller (usually a PCIe configuration space), and sets the address type of the error information storage area to memory mapped I / O.

[0083] The first register may be a model specific register configured in the processor.

[0084] The processor may be communicatively connected with the BIOS firmware.

[0085] The BIOS firmware can also communicate with the operating system.

[0086] PCIe enumeration is the process by which the BIOS identifies and configures PCIe devices.

[0087] The second register may be a PCIe device on the PCIe link, and the second register may be an original register of the controller or a newly added register.

[0088] The original register may be a base address register of the controller in the PCIe configuration space, which is used to implement communication from the processor to the controller.

[0089] A non-cache memory may be reserved in a compatible area of ​​the video graphics array of the BMC for use by the base address register.

[0090] The newly added register can be an independent base address register.

[0091] For example, a register area may be reserved in the original register VGA Bar0 of the controller as an error information storage area.

[0092] For example, a new register may be added to the controller, and a register area in the register may be used as an error information storage area.

[0093] The BIOS may map the base address of the second register corresponding to the error information storage area to the memory address of the first register in the processor, and allocate a memory address range to the error information storage area of ​​the controller, so that the processor can access the register of the controller through this address range.

[0094] In a possible implementation, the first register is used to store multiple base addresses and multiple enable flag bits of the error information storage area;

[0095] The plurality of enable flag bits include an enable error transmission flag bit and a disable error transmission flag bit;

[0096] The processor is specifically configured to write multiple base addresses of the error information storage area into the memory address corresponding to the first register, and trigger a target enable flag bit among multiple enable flag bits.

[0097] The enable error transfer flag may be used to indicate that the system adopts the error data handling mode performed by the system manager.

[0098] The disable error propagation flag may be used to indicate to the system that the system manager is not to use the error data handling performed.

[0099] For example, each bit segment in the first register is described as follows:

[0100] Bits [63:32] are used to store the upper 32 bits of the physical address of the error information storage area;

[0101] Bits [31:1] are reserved bits;

[0102] Bit [0] is used to enable or disable the control of error propagation.

[0103] The processor can calculate the physical address of the error information storage area through the BIOS and ensure that the physical address is 4KB aligned; write the upper 32 bits of the physical address of the error information storage area into Bits [63:32] of the first register through the BIOS; set Bit [0] as needed through the BIOS to enable or disable the error transmission mechanism; execute the preset instruction through the BIOS to write the configured value into the first register.

[0104] In a possible implementation, the interrupt register includes an interrupt flag bit, and the interrupt flag bit is used to instruct the interrupt register to generate the first interrupt signal;

[0105] The processor is specifically used to: determine the error type corresponding to the error data, the error types including the first error type, the second error type and the third error type; when the error type is the first error type, send a first error notification signal to the interrupt register of the controller; when the error type is the second error type, send a first error notification signal to the interrupt register of the controller, and send a machine check interrupt signal to the operating system, so that the operating system calls a preset error handler according to the machine check interrupt signal; when the error type is the third error type, send the first error notification signal and the second interrupt signal to the controller.

[0106] In a possible implementation, the interrupt register includes a clear flag bit, and the clear flag bit is used to indicate a clear operation of error data in the error information storage area;

[0107] The controller is also used to trigger a clear flag bit of the interrupt register after reading erroneous data.

[0108] Among them, the interrupt register can be a 32-bit register, defined as follows:

[0109] Bits [31:2] are reserved.

[0110] Bit [1] is the clear flag, which is used to instruct the controller to clear the error data in the error information storage area.

[0111] The controller can clear the error data in the error information storage area by writing 1 to this bit, indicating that the controller confirms that the relevant error data has been processed and resets the value of this bit to 0.

[0112] Bit [0] is the interrupt flag bit, which is used to instruct the interrupt register to generate the first interrupt signal to notify the controller to read the error data in the error information storage area.

[0113] The processor can trigger an interrupt by writing 1 to this bit to notify the controller to read the error data in the error information storage area.

[0114] The error types include a first error type, a second error type, and a third error type.

[0115] The first error type may be used to indicate an error type corresponding to a correctable error.

[0116] The second error type may be used to indicate an error type corresponding to an uncorrectable but recoverable error.

[0117] The third error type may be used to indicate an error type corresponding to an uncorrectable fatal error.

[0118] The machine check interrupt signal can be used by the processor to directly notify the operating system, so that the operating system calls a preset error handling program according to the machine check interrupt signal.

[0119] In a possible implementation, the preset conditions include:

[0120] If error data corresponding to the first error type exists, determining an error attribute corresponding to the error data of the first error type, updating a counter corresponding to the error attribute according to the error attribute, and generating an alarm message when a current count value of at least one counter is greater than a preset threshold;

[0121] If there is error data corresponding to the second error type and / or error data corresponding to the third error type, an alarm message is generated.

[0122] The controller may include multiple counters, each counter being used to record the number of reads corresponding to error data of the same error attribute.

[0123] When the current count value of at least one counter is greater than a preset threshold, an alarm message is generated; when error data corresponding to the second error type and / or error data corresponding to the third error type exist, an alarm message is generated.

[0124] In this way, for the error types corresponding to correctable errors, the performance jitter of the operating system caused by frequent alarm information can be reduced according to the threshold strategy. For the error types corresponding to uncorrectable but recoverable errors, and the error types corresponding to uncorrectable fatal errors, alarm information can be sent to the operating system in a timely manner, thereby improving the efficiency of the system in processing error data.

[0125] In this way, through the error information storage area and interrupt register, efficient and low-latency error data notification and reporting can be achieved, avoiding the CPU from entering the system management mode, eliminating the risk of operating system business blocking, achieving high-speed data transmission and efficient asynchronous communication, reducing the performance jitter of the operating system caused by frequent system management interrupts, and improving the efficiency of the system in processing error data.

[0126] Next, combine Figure 3 , giving examples to illustrate the specific implementation of the system manager.

[0127] Figure 3 This is a structural diagram of another system manager provided in an embodiment of the present application. Figure 3 , Figure 3 At least includes a system manager, which may include a processor, controller, operating system, BIOS firmware, and platform controller hub (PCH).

[0128] The processor may include:

[0129] PCIe root complex (represented by PCIe RC in the figure): used to manage devices on the PCIe link.

[0130] MCA processor (represented by MCA in the figure): used to detect and report hardware errors.

[0131] When a system error is detected, the MCA processor can write the error data corresponding to the system error into the error information storage area through the machine check architecture, and send an error notification signal to the controller. The error notification signal includes a first error notification signal and / or a second interrupt signal. The first error notification signal is used to trigger the interrupt register to generate a first interrupt signal, and the second interrupt signal is an interrupt signal generated by the processor through a preset pin.

[0132] The MCA processor can communicate with the controller through a PCIe link (represented by PCIe in the figure).

[0133] The MCA processor can also communicate with the operating system.

[0134] The controller may include an error information storage area and an interrupt register.

[0135] The controller is used to read the error data stored in the error information storage area in response to the received first interrupt signal and / or second interrupt signal, and generate alarm information when the error data meets the preset conditions, and send the alarm information to the operating system through the intelligent platform management interface.

[0136] The controller can communicate with the operating system through the Intelligent Platform Management Interface (IPMI in the figure).

[0137] The platform controller hub can be used to manage multiple low-level hardware functions and communicate with the processor through the direct media interface (DMI in the figure).

[0138] BIOS firmware can be used to initialize the hardware.

[0139] The BIOS firmware can communicate with the platform controller center through the Serial Peripheral Interface (SPI) (represented by SPI in the figure) and interact with the operating system through the Advanced Configuration and Power Interface (ACPI) (represented by ACPI in the figure).

[0140] Figure 3 The multiple components in the embodiment can refer to the description of the above embodiment, and repeated contents will not be repeated.

[0141] Next, combine Figure 4 , explaining the method of processing error data applied to the system manager.

[0142] Figure 4 This is a flow chart of a method for processing erroneous data provided by an embodiment of the present application. The execution subject of the embodiment of the present application may be a system manager. Figure 4 , the method comprising:

[0143] S401: Detect and process the system to determine whether there is a system error. If so, determine error data corresponding to the system error.

[0144] System testing can refer to monitoring the operating status of a computer system through a machine check architecture to identify any possible anomalies or failures.

[0145] During the detection process, the system can analyze the collected data to determine whether there are any errors.

[0146] System errors can include hardware failures, software defects, resource conflicts, etc.

[0147] The error data may include at least one of the following parameters:

[0148] Error Location: Indicates the specific hardware component where the error occurred.

[0149] Error severity: Describes the severity of the error and whether it requires immediate action.

[0150] Error code: A specific code that identifies the error type for easier diagnosis and repair.

[0151] Error status: describes the system status when the error occurs, which may include register values, memory addresses, and other information.

[0152] Check code: can be used by the controller to determine whether the error data is complete.

[0153] The processor can detect and process the system through the machine check architecture to determine whether there is a system error in the system. If so, the system error is analyzed and processed to determine the error data corresponding to the system error.

[0154] S402: Write the error data into the error information storage area of ​​the controller, and send an error notification signal to the controller.

[0155] The error information storage area is the register area reserved in the controller.

[0156] The error notification signal includes a first error notification signal and / or a second interrupt signal.

[0157] The first error notification signal is used to trigger an interrupt register of the controller to generate a first interrupt signal.

[0158] The base address of the error information storage area is mapped to the memory address of the processor.

[0159] The processor can write the error data into the error information storage area of ​​the controller through the PCIe link, determine the error type of the error data, generate an error notification signal corresponding to the error type according to the error type, and send the error notification signal to the controller through the PCIe link.

[0160] Optionally, the error data can be written into the error information storage area of ​​the controller in the following manner: determine the base address of the error information storage area; encapsulate the error data according to a predefined format to obtain multiple error data blocks; for any error data block, determine the block identifier of the error data block, and determine the offset address of the error data block based on the block identifier and the number of bytes of the error data block; determine the target address of the error data block based on the base address and the offset address; and write the error data into the error information storage area of ​​the controller according to the target addresses corresponding to the multiple error data blocks.

[0161] The base address may be a starting position of the error information storage area in the memory address space.

[0162] The encapsulation process may include adding an error type identifier, a timestamp, an error type and other information, and encapsulating the error data into multiple error data blocks according to a predefined format, which is not limited here.

[0163] For example, the offset address may be a product value of the block identifier and the number of bytes 64 of the error data block.

[0164] The target address can be obtained by adding the base address to the offset address.

[0165] The error notification signal is used to instruct the controller to read the error data in the error information storage area.

[0166] Optionally, an error notification signal may be sent to the controller in the following manner:

[0167] Determine error types corresponding to the error data respectively, where the error types include a first error type, a second error type, and a third error type;

[0168] In a case where the error type is a first error type, a first error notification signal is sent to the interrupt register.

[0169] The first error notification signal is used to trigger the interrupt register to generate a first interrupt signal to notify the controller to read at least one error data in the error information storage area.

[0170] In the case that the error type is the second error type, a first error notification signal is sent to the interrupt register, and a machine check interrupt signal is sent to the operating system, so that the operating system calls a preset error handling program.

[0171] Among them, the machine check interrupt signal is a special interrupt signal issued by the processor when a serious hardware error is detected.

[0172] When the operating system receives the machine check signal, the operating system may call a preset error handling program to handle the machine check error.

[0173] In a case where the error type is the third error type, a first error notification signal and a second interrupt signal are sent to the controller.

[0174] The second interrupt signal is an interrupt signal generated by the processor through a preset pin.

[0175] Optionally, the first error notification signal can be sent to the interrupt register in the following manner: generating a transaction layer data packet; encapsulating the transaction layer data packet to obtain an encapsulated transaction layer data packet; sending the encapsulated transaction layer data packet to the interrupt register through the peripheral component interconnect high-speed bus PCIe link, so that the interrupt register parses the transaction layer data packet to obtain the first error notification signal, and triggers the interrupt flag according to the first error notification signal.

[0176] The interrupt flag is used to instruct the interrupt register to generate a first interrupt signal to notify the controller to read the error data in the error information storage area.

[0177] The transaction layer data packet includes a first error notification signal, and the first error notification signal is used to trigger the interrupt register to generate a first interrupt signal to notify the controller to read the error data in the error information storage area.

[0178] S403 : Read at least one error data in the error information storage area according to the first interrupt signal and / or the second interrupt signal, and store the at least one error data in an error log.

[0179] In response to the first interrupt signal and / or the second interrupt signal, the controller may read error data corresponding to the interrupt signals in the error information storage area according to the priority of the interrupt signals, and store at least one error data in the error log.

[0180] Optionally, at least one error data can be read in the following manner: determine the priority corresponding to at least one interrupt signal, at least one interrupt signal including a first interrupt signal and / or a second interrupt signal; in the order of priority of at least one interrupt signal from high to low, and the order of timestamps corresponding to at least one interrupt signal from early to late, read the error data corresponding to the interrupt signal in the error information storage area in sequence, and determine the error type of the error data, and store the error data in the error log according to the error type; trigger the clear flag of the interrupt register.

[0181] The clear flag is used to indicate a clearing operation on the error data in the error information storage area.

[0182] For example, the second interrupt signal has a higher priority than the first interrupt signal.

[0183] The timestamp may be used to indicate the time corresponding to when the interrupt signal is received, or the time when the interrupt signal is generated.

[0184] Optionally, at least one error data can be read in the following manner: at preset time intervals, the error data corresponding to the interrupt signal can be read in the error information storage area of ​​the controller, and the error type of the error data can be determined. According to the error type, the error data can be stored in the error log; and the clear flag of the interrupt register can be triggered.

[0185] The error types include a first error type, a second error type, and a third error type.

[0186] Optionally, the error data may be stored in the error log in the following manner: if the error data is of the first error type, determining the error attribute corresponding to the error data, updating the counter corresponding to the error attribute according to the error attribute, and storing the error data in the error log.

[0187] The counter is used to count error data with the same error attribute.

[0188] The controller may include multiple counters, each counter being used to record the number of reads corresponding to error data of the same error attribute.

[0189] The error attribute may be determined by performing hash processing on the error data.

[0190] Hash processing can also determine the error identifier and offset address of erroneous data, which is not limited here.

[0191] The error data may be hashed to generate an error identifier, which may include an error attribute, an error identifier, and an offset address.

[0192] Optionally, independent thresholds can be set in the controller for each error attribute counter, and the thresholds can be configured through IPMI commands or a preset interface.

[0193] If the error data is of the second error type or the third error type, the error data is stored in the error log.

[0194] Optionally, before reading the at least one piece of erroneous data, an integrity check may be performed on the erroneous data.

[0195] Optionally, in the case where the controller supports the Network Time Protocol, the rationality of the occurrence of the error data may be checked before reading the at least one error data.

[0196] S404: Generate alarm information according to at least one error data in the error log.

[0197] Alarm information can be used to notify the operating system to handle system errors.

[0198] Optionally, if error data corresponding to the second error type and / or error data corresponding to the third error type exists in the error log, alarm information is generated according to the error data corresponding to the second error type and / or error data corresponding to the third error type.

[0199] If the current count value of at least one counter is greater than a preset threshold, an alarm message is generated according to the error data respectively corresponding to the at least one counter.

[0200] The preset threshold value can be configured through instructions or operation controls.

[0201] Optionally, after the alarm information is generated, the alarm information may be sent to the operating system through the intelligent platform management interface.

[0202] Optionally, alarm information can be sent to the operation and maintenance system through Redfish API and SNMP traps.

[0203] In this way, when the error data of the first error type accumulates to a certain threshold, an alarm message is triggered to notify the operating system to process the error data, thereby reducing performance jitter of the operating system caused by frequent interruptions.

[0204] The implementation content of each step in the embodiment of the present application can refer to the description of the above embodiment 1, and the repeated content will not be repeated.

[0205] The present embodiment provides a method for processing error data, which detects and processes the system to determine whether there is a system error, and if so, determines the error data corresponding to the system error; writes the error data into the error information storage area of ​​the controller, and sends an error notification signal to the controller, the error information storage area is a register area reserved in the controller, the error notification signal includes a first error notification signal and / or a second interrupt signal, and the first error notification signal is used to trigger the interrupt register of the controller to generate a first interrupt signal; based on the first interrupt signal and / or the second interrupt signal, reads at least one error data in the error information storage area, and stores at least one error data in the error log; generates an alarm message based on at least one error data in the error log. In this way, the transmission of error data and efficient asynchronous communication are achieved through the error information storage area and the interrupt register, and preset conditions are added. When the preset conditions are met, the alarm message is triggered, thereby avoiding the processor from entering the system management mode, while reducing the performance jitter of the operating system caused by frequent system management interrupts, and improving the efficiency of the system in processing error data.

[0206] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0207] Figure 5 This is a schematic diagram of the structure of a device for processing error data provided by an embodiment of the present application. Figure 5 The error data processing device 500 includes a detection module 501 , a writing module 502 , a reading module 503 and a sending module 504 .

[0208] The detection module 501 is used to detect and process the system to determine whether there is a system error in the system, and if so, determine the error data corresponding to the system error;

[0209] A writing module 502 is configured to write error data into an error information storage area of ​​the controller and send an error notification signal to the controller. The error information storage area is a register area reserved in the controller. The error notification signal includes a first error notification signal and / or a second interrupt signal. The first error notification signal is configured to trigger an interrupt register of the controller to generate a first interrupt signal.

[0210] A reading module 503 is configured to read at least one error data from the error information storage area according to the first interrupt signal and / or the second interrupt signal, and store the at least one error data in an error log;

[0211] The sending module 504 is configured to generate an alarm message according to at least one error data in the error log.

[0212] In a possible implementation, the writing module 502 is specifically configured to:

[0213] Determine error types corresponding to the error data respectively, where the error types include a first error type, a second error type, and a third error type;

[0214] When the error type is a first error type, sending a first error notification signal to the interrupt register, where the first error notification signal is used to trigger the interrupt register to generate a first interrupt signal to notify the controller to read at least one error data in the error information storage area;

[0215] If the error type is the second error type, sending a first error notification signal to the interrupt register and sending a machine check interrupt signal to the operating system so that the operating system calls a preset error handling program;

[0216] In the case that the error type is the third error type, a first error notification signal and a second interrupt signal are sent to the controller, where the second interrupt signal is an interrupt signal generated by the processor through a preset pin.

[0217] In a possible implementation, the writing module 502 is specifically configured to:

[0218] generating a transaction layer data packet, wherein the transaction layer data packet includes a first error notification signal;

[0219] Encapsulating the transaction layer data packet to obtain an encapsulated transaction layer data packet;

[0220] Sending an encapsulated transaction layer data packet to an interrupt register via a peripheral component interconnect express bus (PCIe) link, so that the interrupt register parses the transaction layer data packet to obtain a first error notification signal, and triggering an interrupt flag bit according to the first error notification signal;

[0221] The interrupt flag is used to instruct the interrupt register to generate a first interrupt signal to notify the controller to read the error data in the error information storage area.

[0222] In a possible implementation, the writing module 502 is specifically configured to:

[0223] Determine the base address of the error information storage area;

[0224] Encapsulate the error data according to a predefined format to obtain multiple error data blocks;

[0225] For any erroneous data block, determine the block identifier of the erroneous data block, and determine the offset address of the erroneous data block according to the block identifier and the number of bytes of the erroneous data block;

[0226] Determine the target address of the error data block based on the base address and the offset address;

[0227] The error data is written into the error information storage area of ​​the controller according to the target addresses respectively corresponding to the plurality of error data blocks.

[0228] In a possible implementation, the reading module 503 is specifically configured to:

[0229] Determining a priority level corresponding to at least one interrupt signal, wherein the at least one interrupt signal includes a first interrupt signal and / or a second interrupt signal;

[0230] Reading error data corresponding to the interrupt signals in the error information storage area in descending order of priority of the at least one interrupt signal and in descending order of time stamps corresponding to the at least one interrupt signal, determining error types of the error data, and storing the error data in an error log according to the error type;

[0231] The clear flag of the interrupt register is triggered. The clear flag is used to indicate the clearing operation of the error data in the error information storage area.

[0232] In a possible implementation manner, the error type includes a first error type, a second error type, and a third error type, and the reading module 503 is specifically configured to:

[0233] If the error type of the error data is the first error type, determining an error attribute corresponding to the error data, updating a counter corresponding to the error attribute according to the error attribute, and storing the error data in an error log, where the counter is used to count error data with the same error attribute;

[0234] If the error type of the error data is the second error type or the third error type, the error data is stored in an error log.

[0235] In a possible implementation, the sending module 504 is specifically configured to:

[0236] If error data corresponding to the second error type and / or error data corresponding to the third error type exists in the error log, generating an alarm message according to the error data corresponding to the second error type and / or the error data corresponding to the third error type;

[0237] If the current count value of at least one counter is greater than a preset threshold, an alarm message is generated according to the error data respectively corresponding to the at least one counter.

[0238] For the description of the features in the embodiment corresponding to the device for processing error data, reference can be made to the relevant description of the embodiment corresponding to the method for processing error data, which will not be described in detail here.

[0239] Figure 6 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 6 As shown, the electronic device 60 provided in this embodiment includes: at least one processor 601 and a memory 602. Optionally, the electronic device 60 further includes a communication component 603. The processor 601, the memory 602 and the communication component 603 are connected via a bus.

[0240] During the specific implementation process, at least one processor 601 executes the computer-executable instructions stored in the memory 602, so that the at least one processor 601 executes the above-mentioned embodiment of the method for processing erroneous data.

[0241] The specific implementation process of the processor 601 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0242] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0243] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0244] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0245] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned embodiments of the method for processing erroneous data when running.

[0246] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0247] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned embodiments of the method for processing erroneous data are implemented.

[0248] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned erroneous data processing method embodiments are implemented.

[0249] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0250] The above describes in detail a system manager and a method for processing erroneous data provided by this application. This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only intended to help understand the method and core concept of this application. It should be noted that for those skilled in the art, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A system manager, characterized in that: The system manager includes a processor and a controller, wherein the processor is connected to the controller; The controller includes an error information storage area and an interrupt register, wherein the error information storage area is a register area reserved in the controller for storing error data written by the processor; The processor is configured to, upon detecting a system error, write error data corresponding to the system error into the error information storage area and send an error notification signal to the controller, wherein the error notification signal includes a first error notification signal and / or a second interrupt signal, wherein the first error notification signal is configured to trigger the interrupt register to generate a first interrupt signal, and the second interrupt signal is an interrupt signal generated by the processor via a preset pin; the interrupt register includes an interrupt flag bit, and the interrupt flag bit is configured to instruct the interrupt register to generate the first interrupt signal; The controller is configured to read error data stored in the error information storage area in response to the received first interrupt signal and / or the received second interrupt signal, and generate alarm information when the error data meets a preset condition; The error type corresponding to the error data includes a first error type and a second error type; The first error type is used to indicate the error type corresponding to a correctable error, and the second error type is used to indicate the error type corresponding to an uncorrectable but recoverable error; the processor is specifically used to: when the error type is the first error type, send the first error notification signal to the interrupt register of the controller; when the error type is the second error type, send the first error notification signal to the interrupt register of the controller, and send a machine check interrupt signal to the operating system, so that the operating system calls a preset error handler according to the machine check interrupt signal.

2. The system manager according to claim 1, wherein: The processor is further configured to configure a first register with a memory-mapped I / O address type for the error information storage area in a register set corresponding to a peripheral component interconnect express bus PCIe; The processor is also used to perform PCIe enumeration operations during the system initialization phase through the BIOS firmware, determine the second register corresponding to the error information storage area on the controller, and map the base address of the error information storage area to the memory address corresponding to the first register. The second register is an original register in the controller, or a newly added register.

3. The system manager according to claim 2, wherein: The first register is used to store multiple base addresses and multiple enable flag bits of the error information storage area; The plurality of enable flag bits include an enable error transmission flag bit and a disable error transmission flag bit; The processor is specifically configured to write multiple base addresses of the error information storage area into the memory address corresponding to the first register, and trigger a target enable flag bit among the multiple enable flag bits.

4. The system manager according to any one of claims 1 to 3, characterized in that: The processor is further specifically configured to: determining an error type corresponding to the error data, where the error type further includes a third error type; In a case where the error type is the third error type, the first error notification signal and the second interrupt signal are sent to the controller.

5. The system manager according to claim 4, wherein: The preset conditions include: If error data corresponding to the first error type exists, determining an error attribute corresponding to the error data of the first error type, updating a counter corresponding to the error attribute according to the error attribute, and generating an alarm message when a current count value of at least one counter is greater than a preset threshold; If error data corresponding to the second error type and / or error data corresponding to the third error type exist, alarm information is generated.

6. The system manager according to any one of claims 1 to 3, characterized in that: The interrupt register includes a clear flag bit, and the clear flag bit is used to indicate a clear operation of the error data in the error information storage area; The controller is further configured to trigger a clear flag bit of the interrupt register after reading the erroneous data.

7. A method for processing error data, wherein the method is applied to the system manager according to any one of claims 1 to 6, characterized in that: include: Performing detection processing on the system to determine whether the system has a system error, and if so, determining error data corresponding to the system error; Writing the error data into an error information storage area of ​​a controller, and sending an error notification signal to the controller, wherein the error information storage area is a register area reserved in the controller, and the error notification signal includes a first error notification signal and / or a second interrupt signal, wherein the first error notification signal is used to trigger an interrupt register of the controller to generate a first interrupt signal; Reading at least one error data in the error information storage area according to the first interrupt signal and / or the second interrupt signal, and storing the at least one error data in an error log; Generate alarm information according to at least one error data in the error log.

8. The method for processing erroneous data according to claim 7, characterized in that: Sending an error notification signal to the controller, comprising: Determining error types corresponding to the error data respectively, where the error types include a first error type, a second error type, and a third error type; When the error type is the first error type, sending a first error notification signal to the interrupt register, wherein the first error notification signal is used to trigger the interrupt register to generate the first interrupt signal to notify the controller to read at least one error data in the error information storage area; When the error type is the second error type, sending the first error notification signal to the interrupt register and sending a machine check interrupt signal to the operating system, so that the operating system calls a preset error handling program; In a case where the error type is the third error type, the first error notification signal and a second interrupt signal are sent to the controller, where the second interrupt signal is an interrupt signal generated by a processor through a preset pin.

9. The method for processing erroneous data according to claim 8, characterized in that: Sending a first error notification signal to the interrupt register includes: generating a transaction layer data packet, wherein the transaction layer data packet includes the first error notification signal; Encapsulating the transaction layer data packet to obtain an encapsulated transaction layer data packet; sending the encapsulated transaction layer data packet to the interrupt register via a peripheral component interconnect express bus (PCIe) link, so that the interrupt register parses the transaction layer data packet to obtain the first error notification signal, and triggering an interrupt flag bit according to the first error notification signal; The interrupt flag is used to instruct the interrupt register to generate the first interrupt signal to notify the controller to read the error data in the error information storage area.

10. The method for processing erroneous data according to any one of claims 7 to 9, characterized in that: Writing the error data into the error information storage area of ​​the controller includes: Determining a base address of the error information storage area; Encapsulating the error data according to a predefined format to obtain multiple error data blocks; For any erroneous data block, determining a block identifier of the erroneous data block, and determining an offset address of the erroneous data block according to the block identifier and the number of bytes of the erroneous data block; Determining a target address of the error data block according to the base address and the offset address; The error data is written into an error information storage area of ​​the controller according to target addresses corresponding to the multiple error data blocks.

11. The method for processing erroneous data according to any one of claims 7 to 9, characterized in that: Reading at least one error data in the error information storage area according to the first interrupt signal and / or the second interrupt signal, and storing the at least one error data in an error log, includes: determining a priority corresponding to at least one interrupt signal, wherein the at least one interrupt signal includes the first interrupt signal and / or the second interrupt signal; Reading error data corresponding to the interrupt signals in the error information storage area in descending order of priority of the at least one interrupt signal and in descending order of timestamps corresponding to the at least one interrupt signal, determining an error type of the error data, and storing the error data in an error log according to the error type; A clear flag of the interrupt register is triggered, where the clear flag is used to indicate a clearing operation of the error data in the error information storage area.

12. The method for processing erroneous data according to claim 11, characterized in that: The error types include a first error type, a second error type, and a third error type. According to the error types, storing the error data in an error log includes: If the error type of the error data is the first error type, determining an error attribute corresponding to the error data, updating a counter corresponding to the error attribute according to the error attribute, and storing the error data in the error log, where the counter is used to count error data with the same error attribute; If the error type of the error data is the second error type or the third error type, the error data is stored in the error log.

13. The method for processing erroneous data according to claim 12, characterized in that: Generating alarm information according to at least one error data in the error log includes: If error data corresponding to the second error type and / or error data corresponding to the third error type exists in the error log, generating an alarm message according to the error data corresponding to the second error type and / or the error data corresponding to the third error type; If the current count value of at least one counter is greater than a preset threshold, an alarm message is generated according to the error data respectively corresponding to the at least one counter.

14. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the method for processing erroneous data according to any one of claims 7 to 13 when executing the computer program.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for processing erroneous data according to any one of claims 7 to 13 are implemented.

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