GPU resource aware matrix multiplication parallel performance analysis model construction method

Abstract

The invention discloses a GPU resource aware matrix multiplication parallel performance analysis model construction method, which relates to the technical field of high-performance calculation, depends on the Roofline principle, combines a bandwidth model, a resource load model and an instruction dependence model to construct a performance analysis model, and is successfully applied to a matrix multiplication scene. And the parallel performance quantification under the matrix multiplication application of resource awareness is realized. The method is not limited by a platform, resource awareness can be achieved, maximized resource use and parameter setting of optimized performance can be distinguished through a performance analysis model in a matrix multiplication scene, and a foundation is laid for follow-up parallel program optimization work; the hardware parameters used in the method are completely based on the GPU hardware parameters which can be obtained publicly, so that non-GPU professionals can also use the model to evaluate the performance of the program.

Description

Technical Field

[0001] The present invention relates to the technical field of high-performance computing, and in particular to a method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model. Background Art

[0002] With the rapid development of information technology, global demand for computing power is growing exponentially, and the field of high-performance computing is undergoing unprecedented development and transformation. Modern technology has imposed higher computing power requirements, posing a more severe challenge to traditional CPU architectures. Consequently, current research and industry are focusing on how to effectively improve computing performance and resource utilization. Modern image processing units (GPUs) integrate extensive parallel hardware to form thousands of lightweight context switches, enabling higher performance in high-throughput and high-latency applications and spawning numerous emerging fields. The most notable change is the extension of artificial intelligence (AI) to larger-scale learning. The essence of GPU-accelerated AI computing can be largely attributed to GPU-accelerated matrix operations. In the high-performance domain, general matrix multiplication is the core task for efficient matrix operations. Its optimization not only fully exploits the parallel computing potential of GPUs but also plays a significant role in improving model training speed and inference efficiency.

[0003] The emergence of parallel programming languages has greatly reduced the development difficulty of GPU programming, but GPU programming is still considered a specialized field. Parallel programs are primarily concerned with post-port performance optimization. Changing the kernel launch parameters of a parallel program is a direct and easy performance optimization method. These parameters determine the operation mapping between software and hardware, determine the utilization of resources such as registers and shared memory, and limit the number of active thread blocks in the GPU's multiprocessor, thus affecting the actual granularity of task parallelism. Therefore, while these parameters are logically independent of the program itself, they serve as the foundation for all subsequent optimization efforts. Incorrect or unreasonable launch parameters often lead to poor resource utilization, especially in matrix multiplication scenarios, where irregularities further complicate parameter tuning. Therefore, the selection of launch parameters must not only consider the hardware characteristics of the GPU architecture but also adapt to specific characteristics such as the shape of the matrix. Achieving optimal launch parameter configuration under multiple constraints has become a major challenge in GPU programming and performance optimization.

[0004] Determining the optimal performance of a parallel program often requires relying on experience and conducting numerous repeated validation experiments and tests to adjust parameters, a time-consuming and labor-intensive process. In particular, changes in GPU architectures make parameter optimization a moving target. Minor differences between platforms can render the original optimal parameters and optimized performance meaningless, impacting the portability and reproducibility of parallel programs. To address these challenges, automatic tuning methods based on performance prediction have become an important tool for addressing the generalization problem of GPU parameter optimization. Summary of the Invention

[0005] In response to the above technical problems in related technologies, the present invention provides a GPU resource-aware matrix multiplication parallel performance analysis model construction method, which can solve the above problems.

[0006] To achieve the above technical objectives, the technical solution of the present invention is implemented as follows: A GPU resource-aware matrix multiplication parallel performance analysis model construction method includes the following steps: S100, building a resource awareness model, including obtaining the total number of theoretical thread blocks that can be executed in parallel by the GPU under the current settings through a classic occupancy model, and obtaining the total number of thread blocks of the current parallel task partition based on the startup parameters, thereby obtaining the impact rate of the tail effect, and building a load occupancy model to achieve resource awareness of load imbalance; S200, establishing a memory access pattern that conforms to application characteristics based on a memory access address mapping method of a matrix multiplication application, and constructing a bandwidth model, including obtaining an average memory access data redundancy by combining the memory access address mapping method of matrix multiplication in global memory and shared memory, and then constructing a concept of thread warp reuse distance, expanding a temporal access method to generate an average thread warp cache line reuse distance with spatiotemporal locality SM, and obtaining memory access data locality with current application characteristics; S300: Based on the Roofline principle, a performance analysis model combining memory access model and computational intensity is constructed. This includes obtaining the computational intensity of the corresponding computation-memory access instructions by counting the computations and memory access operation instructions under the current matrix multiplication application. This is combined with the bandwidth model in S200 to implement a performance analysis model per floating-point calculation count. S400: Establishing instruction dependencies under computing intensity, combining the computing intensity calculation method of computing-memory access instructions, constructing a simple instruction dependency chain using computing instructions as the medium, simulating the GPU instruction issuance process to estimate the overall running time, obtaining the computing instruction change rate under the influence of instruction dependency, achieving quantification of instruction dependency, and then optimizing the performance analysis model; S500: Build a scale-aware parallel comprehensive performance analysis model. This includes dividing the performance analysis model optimized in S400 according to the impact of task scale, building emphasis factors, and achieving a more complete comprehensive performance analysis model and improving scale perception capabilities.

[0007] Furthermore, the tail effect in S100 refers to the phenomenon that the GPU cannot fully start all SMs to complete parallel computing, resulting in some SMs waiting idle during the computing process, resulting in resource waste and reduced computing efficiency.

[0008] Furthermore, in the construction of the resource-aware model of S100, the theoretical awareness model is obtained through the programming interface cudaOccupancyMaxPotentialBlockSize() to calculate the theoretical load occupancy; the number of thread blocks divided into parallel tasks is obtained through the startup parameter setting; the tail effect is estimated by quantifying the load by evenly distributing the actual tasks to the load ratio of each SM.

[0009] Furthermore, the warp reuse distance in S200 is the number of non-duplicate cache lines generated by active warps in the same SM within a time interval before a cache line accessed by a warp is accessed again.

[0010] Furthermore, the specific steps of S100 are as follows: S101. Use cudaOccupancyMaxPotentialBlockSize() to obtain the number of thread blocks that can be executed in parallel on each SM, and then obtain the total number of thread blocks that can be processed in parallel on the GPU based on the limit on the number of SMs on the GPU. S102 uses the parameters of the BlockDim part in the startup parameters to obtain the task partition size, and obtains the total number of task partition thread blocks according to the task scale; S103: Dividing the number of task thread blocks divided by the startup parameters by the number of thread blocks that can be processed in parallel by the GPU to obtain a parallel execution ratio of the full-load operation, and then dividing by the upper limit of the ratio to obtain a tail effect load ratio; S104 Multiplying the load ratio obtained in S103 by the theoretical load occupancy rate can obtain the load occupancy rate under the influence of the tail effect, which is further expressed as a load-aware resource model.

[0011] Furthermore, the specific steps of S200 are as follows: S201, by mapping the program global memory access address with the memory block in units of 128 bytes, estimate the number of memory blocks corresponding to each thread warp, also known as the number of cache lines; S202: The number of warps executed in parallel by each SM is obtained based on the resource-aware model, and the loop portion of the memory access process is expanded to find the corresponding cache line mapping using the method of S201. S203: After obtaining the cache line mapping for each warp, a cache stack is constructed. The cache line of each warp is pushed sequentially to update the top of the stack. The number of cache lines passed during the stacking process is counted to obtain the corresponding reuse distance. The sum of the reuse distances of all warps is averaged to obtain the number of cache lines corresponding to each warp. S204, normalize the average number of cache lines obtained in S203 by the number of cache lines corresponding to the data blocks accessed by the thread warp, take the reciprocal, and obtain a final reuse distance parameter; S205 , combining the reuse distance parameter with the load occupancy rate obtained in S104 to obtain a bandwidth impact parameter, and combining the parameter with the peak bandwidth corresponding to the GPU platform to obtain a bandwidth estimate.

[0012] Furthermore, the specific steps of S300 are as follows: S301, obtaining the corresponding theoretical number of multiplications and additions according to the matrix multiplication algorithm, and combining the block parameters set by the startup parameters to obtain the number of global memory accesses after the shared memory is introduced; S302, using a computing intensity calculation method, dividing the theoretical number of multiplications and additions by the amount of access data of the corresponding global memory access number to obtain the corresponding computing intensity of the global memory; S303 : Combine the computation intensity obtained in S302 and multiply it by the bandwidth estimate obtained in S205 to obtain the corresponding number of unit floating-point computations.

[0013] Furthermore, the specific steps of S400 are as follows: S401, obtaining the number of instructions under different instructions, and constructing a simple dependency relationship between instructions using calculation instructions as a medium; S402, establishing an instruction issuance pipeline model between instructions according to the instruction issuance method in the GPU, and estimating the overall running time; S403, dividing the total execution time estimated in S402 by the number of executed computing instructions to obtain an average unit computing instruction execution time, and comparing it with the theoretical unit computing instruction execution time to obtain an instruction dependency impact factor; S404 : Divide the performance analysis model obtained in S300 by the instruction dependency factor to optimize the performance analysis model.

[0014] Furthermore, the specific steps of S500 are as follows: S501. Based on the performance analysis model optimized in S400, obtain the corresponding computing intensity division threshold according to the Roofline principle, calculate the theoretical computing intensity of the current computing application, and divide the two to obtain the task scale division ratio; S502, using a nonlinear function to change the division ratio to obtain an emphasis factor; S503: Use emphasis factors to emphasize the computation-global memory computation intensity obtained in step S302 and the bandwidth impact parameter in step S205, respectively, to obtain a final comprehensive performance analysis model.

[0015] The beneficial effects of the present invention are as follows: the present invention is not restricted by the platform and can realize resource perception, and in the matrix multiplication scenario, it can identify the parameter settings that maximize resource utilization and optimize performance through the performance analysis model, laying the foundation for subsequent parallel program optimization work, and is an important step in the portability of parallel program performance; the hardware parameters used in the present invention are completely based on publicly available GPU hardware parameters, so that non-GPU professionals can also use the model to evaluate the performance of the program; the present invention fully considers the influencing factors of hardware resources, captures the task characteristics of matrix multiplication applications, can realize resource perception and task characteristic perception, has strong applicability, and can effectively alleviate performance bottlenecks in the field of high-performance computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] The present invention will be described in further detail below with reference to the accompanying drawings.

[0018] Figure 1 Schematic diagram of a method for calculating data redundancy in a description of a global memory access pattern used in constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to an embodiment of the present invention; Figure 2 2 is a schematic diagram of a method for calculating the reuse distance of thread warps used in constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to an embodiment of the present invention; Figure 3 Schematic diagram of a method for calculating the total GPU running time under the matrix multiplication instruction dependency relationship used in constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to an embodiment of the present invention; Figure 4Schematic diagram of the Roofline model used in constructing the GPU resource-aware matrix multiplication parallel performance analysis model according to an embodiment of the present invention; Figure 5 This is an experimental diagram based on the use of emphasis factors in constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to an embodiment of the present invention; Figure 6 It is a GPU resource-aware matrix multiplication parallel performance analysis model described in an embodiment of the present invention, based on a quantization table of the fitting relationship between the proposed model, the traditional occupancy model and time under two different GPU platforms, V100 and A100. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention are within the scope of protection of the present invention.

[0020] According to the present invention, a method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model is disclosed. The method relies on the Roofline principle and combines the bandwidth model, resource load model, and instruction dependency model to construct a performance analysis model. The model is successfully applied to the matrix multiplication scenario to achieve parallel performance quantification under resource-aware matrix multiplication applications. The main principles are as follows: (1) Tracking global and shared memory access patterns: Taking the global and shared memory access logic as input, the average number of memory access transactions per thread warp during global memory access and the average number of storage bank conflicts per thread warp during shared memory access are counted to achieve the calculation of data redundancy rate in the current application scenario. (2) Constructing a thread warp-level reuse distance theory: Sequentially estimate the average number of thread warps per SM and expand the access loop, implement a cache line replacement strategy with the hardware cache size as the limit, and count the average number of cache lines per thread warp in each SM to achieve quantitative characterization of data locality. (3) Capturing resource changes under uneven load: Calculating the corresponding number of thread blocks based on the parallel task size and the block partitioning strategy, combined with the theoretical number of thread blocks that can be executed in parallel under the occupancy model, obtains a new occupancy model under uneven load, and realizes resource perception under uneven load. (4) Establishing instruction dependency under computing intensity: Counting the number of computations and memory access instructions of parallel computing tasks and each storage unit to obtain the corresponding computing intensity relationship, using computation instructions as the medium to construct the dependency relationship between memory access instructions, realize a simple dependency chain between computation and each storage unit, and then combine the GPU instruction emission method to realize the quantification of instruction dependency. (5) Realizing a comprehensive performance analysis model combining memory access and computing characteristics: Build a memory access and computing model by combining the bandwidth and resource quantification indicators obtained from (1) to (4), and then build a comprehensive performance analysis model based on Roofline theory, and build an intensity factor, and finally realize a comprehensive performance analysis model with task scale perception.

[0021] In a specific embodiment of the present invention, Figure 1 The figure below shows the data redundancy calculation method used in the global memory access pattern description. This method counts the mapping between access addresses and memory addresses in thread warps, determines whether thread access locations are continuous, and determines the number of aligned and contiguous 128-byte memory blocks that data addresses fall into. This method then calculates the number of 128-byte memory blocks corresponding to the number of threads. This is then compared with the actual valid data to determine changes in data efficiency, indirectly reflecting the data redundancy characteristics of the application's memory access pattern. This method can also be expressed as a count of cache lines per thread, preparing for subsequent data reuse distances.

[0022] The warp reuse distance is the number of unique cache lines generated between the next access of a cache line accessed by a warp and the next access of that cache line within the same warp, for active warps in the same SM. This warp-level reuse distance theory not only reflects data locality between warps, but also reflects data locality within a warp by counting cache lines accessed within the warp. The specific formula for calculating the reuse distance RD is as follows: ; RD stands for reuse distance, which is the abbreviation of Reuse Distance. ave Represents the average reuse distance of each thread warp during the entire memory access process; RD Wi It represents the reuse distance corresponding to the thread bundle including the time series expansion; Nloop represents the sequence length of the time series; Nact_warp represents the number of active warps in the SM (Streaming Multiprocessor) under the current resource constraints; Ncl_per_sm represents the number of non-duplicate cache lines corresponding to the data that the current SM needs to access.

[0023] In cache reuse distance calculation, a cache stack structure with timing-aware characteristics is designed to accurately characterize the warp-level memory access pattern. The core mechanism is to build a virtual cache stack that conforms to the hardware execution characteristics. Its concept can be divided into three key points: building a cache stack, building temporal locality, and building spatial locality.

[0024] In terms of cache stack construction, the system constructs a dynamic memory access sequence based on the thread bundle scheduling order. The cache line request initiated by the first thread of each thread bundle will trigger a push operation, and the corresponding cache line will be pushed into the virtual cache stack and arranged in the stack order. At the same time, in terms of the stacking strategy, this application uses a timing preservation strategy-the cache line accessed for the first time will be placed at the bottom of the stack instead of the top of the stack. This anti-stack order design effectively maintains the timing of thread bundle execution, avoiding the reuse distance calculated at the top of the stack being too small and ignoring the disordered nature of thread bundle access. It is worth noting that the calculation of the reuse distance needs to maintain the capacity constraint characteristics of the physical cache stack to ensure that storage hardware limitations are taken into account.

[0025] In terms of temporal locality, this application converts cyclic accesses within the same warp into virtual warps, breaking the cyclic timing into multiple logical warp entities for computation. This virtual warp processing method not only preserves the temporal characteristics of the original memory access pattern but also enables cross-cycle memory access correlation analysis.

[0026] In terms of spatial locality, this application adopts a top-of-stack update strategy. When a new warp requests access to a non-duplicate cache line, the corresponding data block is pushed onto the stack in order according to the bottom-of-stack strategy and moved to the top of the stack after distance calculation. If the access request is to an existing cache line, it is directly moved to the top of the stack.

[0027] Finally, the reuse distance calculation requires a normalization factor: the cumulative reuse distance is divided by the number of data cache lines that the SM actually needs to access. This is to avoid dimensional errors caused by task size. Furthermore, the normalized reuse distance calculation needs to be divided by the number of active warps actually resident in the SM to better estimate the actual locality characteristics of each access request. Using actual warps eliminates cardinality bias caused by virtual warp expansion, ensuring that the calculation results strictly correspond to the hardware execution characteristics.

[0028] like Figure 2 The figure below shows an example of reuse distance. In this example, each thread block in the program design accesses global memory according to the warp layout template. Under resource allocation constraints, each SM can support one active thread block, with the threads set to (8,8). This means that two active warps can execute in parallel within the SM, each with accesses in the (8,4) pattern. The program design includes two loops, so virtual expansion generates four warp accesses within the SM. In this case, Nwarp = 2 and Nloop = 2.

[0029] First, in the first loop Loop-0, the first threads T0, T8, T 16 、T 24 、T 32 、T 40 、T 48 、T 56The data cache lines that need to be accessed will be placed in the cache. Taking the first thread warp Warp0 as an example, cache lines C3, C2, C1, and C0 are placed in the cache lines. The first thread T0 in the first row accesses the top element C0, resulting in a reuse distance of 0, and keeps C0 at the top of the stack; T8 accesses C1 and updates the top element of the stack, resulting in a reuse distance of 1, and so on for other threads. Therefore, the reuse distance of thread warp Warp0 in this example is RDw0=0+1+2+3=6. Since Warp0 and Warp1 are two parallel thread warps, they will initiate write requests to the cache at the same time, but the service of the write requests will be implemented in a certain order. In order to preserve the order characteristics, the new cache line of Warp1 will be placed at the bottom of the stack. At this time, the order of cache lines in the cache stack is C7, C6, C5, C4, C0, C1, C2, and C3. When a cache line is read, the corresponding cache line is updated to the top of the stack. Specifically, T32 accesses C4 with a reuse distance of 4 and updates C4 to the top of the stack. T40 accesses C5 with a reuse distance of 5 and updates C5 to the top of the stack, and so on. Finally, the reuse distance of Warp 1 is RDw1 = 4 + 5 + 6 + 7 = 22.

[0030] Regarding the calculation of the temporal reuse distance, after the first loop completes, the second round of Loop-1 virtual warps will begin parallel access, using the same access method as Loop-0. Since the cache line at the top of the current cache stack coincides with the access of Warp1 in Loop-1, Warp1 will prioritize access based on locality. At this point, cache lines C7, C6, C5, and C4 are accessed sequentially, generating a new reuse distance RDw2 = 0 + 1 + 2 + 3 = 6, and updating the cache distribution at the top of the stack to C0, C1, C2, C3, C7, C6, C5, and C4. Warp0 will then continue sequentially accessing C3, C2, C1, and C0, generating a reuse distance RDw3 = 4 + 5 + 6 + 7 = 22, updating and generating a new cache distribution of C7, C6, C5, C4, C3, C2, C1, and C0.

[0031] Finally, the total reuse distance corresponding to this access pattern is RDw0+RDw1+RDw2+RDw3=6+22+6+22=56, and the final reuse distance is RD=56 / 8 / 2=3.5.

[0032] In a specific embodiment of the present invention, Figure 3 The overall time estimation model after considering the computational intensity is presented. The time consumed by the entire computational execution process is the sum of the execution time of a single thread bundle under parallel execution and the redundant time consumed during the scheduling process, as shown in Formulas 2 to 4: ; Among them, tcmp represents the GPU hardware unit operation time; tshm represents the GPU hardware shared memory unit access time; Nscheduler represents the current number of hardware thread warp schedulers; Nops represents the number of hardware units corresponding to the current operation; NLS / ST represents the number of load and storage units under the current hardware conditions; Nconflict represents the number of storage conflicts that occur in shared memory under the current access mode; Nwarp represents the current number of active thread warps; Nthd_per_warp represents the number of threads in each thread warp; Nops_per_warp represents the number of computing operations in each thread warp; AI represents computing intensity, and AIglb_shm and AIshm_cmp represent the computing intensity between global memory access and computing operations, and shared memory access and computing operations, respectively.

[0033] By constructing an instruction-level SIMT model, we can obtain a simple estimate of the overall runtime T. Combined with the known number of computations, we can determine the change in the unit time of operation under the influence of instruction dependencies and shared memory access conflicts. Then, by comparing the changed unit time of operation with the unaffected unit time of operation, we can obtain the quantified impact factor, as shown in Formulas 5 and 6 below: ; ; Where T represents the overall running time estimated by the proposed SIMT model method; AIglb_cmp represents the computational intensity between global memory access and computational instructions in the current application; Tcmp represents the unit computational time estimated by the proposed SIMT model method; tcmp represents the unit operation time of GPU hardware, and the calculation method is shown in Formula (3); Rcmp represents the quantitative impact factor of instruction dependency on computational operations.

[0034] In a specific embodiment of the present invention, Figure 4 The Roofline principle model is presented. This model is a commonly used performance analysis indicator in the high-performance field. Based on the principle of Roofline, this paper innovatively implements a priori performance analysis model by constructing a bandwidth model and a computational intensity model. The specific calculation method is shown in formulas 7 to 9: ; ; Among them, AIglb_cmp is the computational intensity between global memory access and computing operations; BW refers to the actual bandwidth estimate after considering load balancing and reuse distance; BWtheo is the theoretical peak bandwidth of GPU global memory; Occbl represents the occupancy after considering load balancing; Occtheo represents the theoretical occupancy, which can be obtained through the interface cudaOccupancyMaxPotentialBlockSize(); Nact_wave represents the number of times the GPU SM runs at full load under the current task; FLOPS represents the number of floating-point calculations per unit; Rcmp represents the quantitative impact factor of instruction dependency on computing operations, and the specific calculation method is shown in Formula (5).

[0035] In a specific embodiment of the present invention, Figure 5 The experimental diagram shows the use of the emphasis factor. Figure 5 As shown in the figure, different factors in the proposed performance indicators show a two-tier differentiation in compute-intensive applications, that is, computing intensity, reuse distance, and occupancy rate show different degrees of sensitivity. To this end, based on the sensitivity change phenomenon and the analysis function of the Roofline model, this paper combines the analysis theory of the Roofline model with the standard computing intensity to divide parallel computing tasks, and sets an emphasis index to highlight the role of indicators in different tasks, as shown in formulas 10 to 12: ; ; Among them, p is the emphasis index, which is used to control the fluctuation of the corresponding parameters to achieve the effect of emphasizing the role of different parameters in different task scenarios; β is used to control the changing speed of the emphasis index p; α is used to control the changing range of the emphasis index; AIbase represents the basic computing intensity of the current application, that is, the computing amount of the application divided by the corresponding data amount; AIthres is expressed as the computing intensity threshold under the Roofline indicator, that is, the ratio of the peak computing intensity FLOPSpeak of the GPU under the corresponding computing type to the peak bandwidth BWpeak of the global memory.

[0036] By combining thresholds, the new computing intensity in the performance model can distinguish changes before and after the threshold and eliminate the deviation caused by dimensional differences. At the same time, due to the different influencing factors in memory-limited and compute-limited scenarios, the use of logical functions combined with thresholds can accurately capture the dynamic changes in memory-limited and compute-limited scenarios. The reason for using logical functions is that they can show the fast and slow patterns of changes in performance bottleneck scenarios, which is something that linear functions cannot achieve.

[0037] like Figure 6As shown, it can be seen that the indicators proposed in this application show strong correlation under different scales and GPU models, and the absolute value of this correlation coefficient exceeds 0.8, indicating that it has strong performance capture capabilities in matrix multiplication scenarios. At the same time, for the occupancy index, it shows a certain inverse proportional performance capture capability in the scenario of small-scale matrices, and this correlation further decreases in the scenario of large-scale matrices. The performance analysis model proposed in this application effectively introduces a description of computing intensity on the basis of the occupancy model, which can achieve more accurate capture of changes in performance influencing factors. Matrix multiplication experiments of different scales further verify the effectiveness of the proposed performance analysis indicators in GPU performance evaluation. Experimental results show that the proposed indicators show a high correlation under matrices of different scales and GPU models, which is better than the traditional occupancy model. At the same time, the correlation analysis also reveals the advantages of performance indicators in capturing computing intensity, memory reuse, etc.

[0038] In summary, leveraging the above-mentioned technical solutions, this paper conducts research focused on heterogeneous hardware resource and task characteristic awareness, innovatively constructing a hierarchical performance analysis model and achieving breakthroughs in multi-dimensional optimization. Approaching the research from the dual perspectives of GPU hardware and task characteristics, at the memory access level, based on the global and shared memory storage hierarchies, analyzes memory access transactions and bank conflicts, and proposes a warp-level reuse distance theory. At the compute level, this paper extends traditional pipeline logic to address instruction dependencies, proposes a computationally-intensive instruction dependency identification method, and constructs an instruction-level SIMT pipeline model. Furthermore, this paper constructs a unified parallel performance analysis model based on Roofline theory, breaking through the application boundaries of traditional models and making it applicable to memory- and compute-intensive tasks. After experimental fine-tuning, prediction accuracy is enhanced. This paper fully considers multiple influencing factors and constructs a performance analysis model based on authoritative principles. This model achieves high temporal accuracy, captures performance variations, and achieves resource awareness. Its applicability and usability are strong, making it suitable for application in various heterogeneous computing systems.

[0039] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A GPU resource-aware matrix multiplication parallel performance analysis model construction method, characterized by: The steps include: S100, building a resource awareness model, including obtaining the total number of theoretical thread blocks that can be executed in parallel by the GPU under the current settings through a classic occupancy model, and obtaining the total number of thread blocks of the current parallel task partition based on the startup parameters, thereby obtaining the impact rate of the tail effect, and building a load occupancy model to achieve resource awareness of load imbalance; S200, establishing a memory access pattern that conforms to application characteristics based on a memory access address mapping method of a matrix multiplication application, and constructing a bandwidth model, including obtaining an average memory access data redundancy by combining the memory access address mapping method of matrix multiplication in global memory and shared memory, and then constructing a concept of thread warp reuse distance, expanding a temporal access method to generate an average thread warp cache line reuse distance with spatiotemporal locality SM, and obtaining memory access data locality with current application characteristics; S300: Based on the Roofline principle, a performance analysis model combining memory access model and computational intensity is constructed. This includes obtaining the computational intensity of the corresponding computation-memory access instructions by counting the computations and memory access operation instructions under the current matrix multiplication application. This is combined with the bandwidth model in S200 to implement a performance analysis model per floating-point calculation count. S400: Establishing instruction dependencies under computing intensity, combining the computing intensity calculation method of computing-memory access instructions, constructing a simple instruction dependency chain using computing instructions as the medium, simulating the GPU instruction issuance process to estimate the overall running time, obtaining the computing instruction change rate under the influence of instruction dependency, achieving quantification of instruction dependency, and then optimizing the performance analysis model; S500: Build a scale-aware parallel comprehensive performance analysis model. This includes dividing the performance analysis model optimized in S400 according to the impact of task scale, building emphasis factors, and achieving a more complete comprehensive performance analysis model and improving scale perception capabilities.

2. The method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to claim 1, characterized in that: The tail effect in S100 refers to the phenomenon that the GPU cannot fully start all SMs to complete parallel computing, resulting in some SMs waiting idle during the computing process, resulting in resource waste and reduced computing efficiency.

3. The method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to claim 1, wherein: In constructing the resource-aware model of S100, the theoretical awareness model is obtained through the programming interface cudaOccupancyMaxPotentialBlockSize() to calculate the theoretical load occupancy; the number of thread blocks divided into parallel tasks is obtained through the startup parameter setting; the tail effect is estimated by quantifying the load by evenly distributing the actual tasks to the load ratio of each SM.

4. The method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to claim 1, wherein: The warp reuse distance in S200 is the number of non-duplicate cache lines generated by active warps in the same SM within a time interval before a cache line accessed by a warp is accessed again.

5. The method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to claim 3, wherein: The specific steps of S100 are as follows: S101. Use cudaOccupancyMaxPotentialBlockSize() to obtain the number of thread blocks that can be executed in parallel on each SM, and then obtain the total number of thread blocks that can be processed in parallel on the GPU based on the limit on the number of SMs on the GPU. S102 uses the parameters of the BlockDim part in the startup parameters to obtain the task partition size, and obtains the total number of task partition thread blocks according to the task scale; S103: Dividing the number of task thread blocks divided by the startup parameters by the number of thread blocks that can be processed in parallel by the GPU to obtain a parallel execution ratio of the full-load operation, and then dividing by the upper limit of the ratio to obtain a tail effect load ratio; S104 Multiplying the load ratio obtained in S103 by the theoretical load occupancy rate can obtain the load occupancy rate under the influence of the tail effect, which is further expressed as a load-aware resource model.

6. The method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to claim 5, characterized in that: The specific steps of S200 are as follows: S201, by mapping the program global memory access address with the memory block in units of 128 bytes, estimate the number of memory blocks corresponding to each thread warp, also known as the number of cache lines; S202: The number of warps executed in parallel by each SM is obtained based on the resource-aware model, and the loop portion of the memory access process is expanded to find the corresponding cache line mapping using the method of S201. S203: After obtaining the cache line mapping for each warp, a cache stack is constructed. The cache line of each warp is pushed sequentially to update the top of the stack. The number of cache lines passed during the stacking process is counted to obtain the corresponding reuse distance. The sum of the reuse distances of all warps is averaged to obtain the number of cache lines corresponding to each warp. S204, normalize the average number of cache lines obtained in S203 by the number of cache lines corresponding to the data blocks accessed by the thread warp, take the reciprocal, and obtain a final reuse distance parameter; S205 , combining the reuse distance parameter with the load occupancy rate obtained in S104 to obtain a bandwidth impact parameter, and combining the parameter with the peak bandwidth corresponding to the GPU platform to obtain a bandwidth estimate.

7. The method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to claim 6, characterized in that: The specific steps of S300 are as follows: S301, obtaining the corresponding theoretical number of multiplications and additions according to the matrix multiplication algorithm, and combining the block parameters set by the startup parameters to obtain the number of global memory accesses after the shared memory is introduced; S302, using a computing intensity calculation method, dividing the theoretical number of multiplications and additions by the amount of access data of the corresponding global memory access number to obtain the corresponding computing intensity of the global memory; S303 : Combine the computation intensity obtained in S302 and multiply it by the bandwidth estimate obtained in S205 to obtain the corresponding number of unit floating-point computations.

8. The method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to claim 1, characterized in that: The specific steps of S400 are as follows: S401, obtaining the number of instructions under different instructions, and constructing a simple dependency relationship between instructions using calculation instructions as a medium; S402, establishing an instruction issuance pipeline model between instructions according to the instruction issuance method in the GPU, and estimating the overall running time; S403, dividing the total execution time estimated in S402 by the number of executed computing instructions to obtain an average unit computing instruction execution time, and comparing it with the theoretical unit computing instruction execution time to obtain an instruction dependency impact factor; S404 : Divide the performance analysis model obtained in S300 by the instruction dependency factor to optimize the performance analysis model.

9. The method for constructing a GPU resource-aware matrix multiplication parallel performance analysis model according to claim 7, wherein: The specific steps of S500 are as follows: S501. Based on the performance analysis model optimized in S400, obtain the corresponding computing intensity division threshold according to the Roofline principle, calculate the theoretical computing intensity of the current computing application, and divide the two to obtain the task scale division ratio; S502, using a nonlinear function to change the division ratio to obtain an emphasis factor; S503 , using emphasis factors to respectively emphasize the computation-global memory computation intensity obtained in step S302 and the bandwidth impact parameter in S205 , to obtain a final comprehensive performance analysis model.

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