A circuit diagram-based fault diagnosis method, terminal device and storage medium

Abstract

The application relates to the technical field of circuit diagnosis, and discloses a fault diagnosis method based on a circuit diagram, a terminal device and a storage medium, which comprises the following steps: acquiring component information and wire connection relationships in a preprocessed to-be-tested circuit diagram; constructing a topological relationship graph based on the component information and the wire connection relationships of the to-be-tested circuit diagram, generating a circuit digital model; acquiring fault information, and performing circuit logic analysis on the fault information based on the circuit digital model to generate a fault list; and matching all fault types in the fault list with a maintenance database to acquire maintenance recommendation information. The application realizes automatic processing of the to-be-tested circuit diagram, greatly improves the recognition and fault diagnosis efficiency, generates detailed maintenance suggestions and steps, guides users to quickly repair faults, and is suitable for to-be-tested circuit diagram analysis in different design stages.

Description

Technical Field

[0001] This application relates to the field of circuit diagnostic technology, and in particular to a fault diagnosis method, terminal device and storage medium based on circuit diagrams. Background Technology

[0002] The analysis and fault diagnosis of circuit diagrams under test (DUTs) mainly rely on manual operation, such as engineers manually checking paper DUTs to locate problems. This method has the following drawbacks: digitizing paper DUTs is time-consuming, labor-intensive, and prone to errors; fault diagnosis often depends on the engineer's experience and lacks a systematic and standardized process; potential design flaws cannot be detected in time during the circuit design phase. Even if the fault point is found, repair suggestions are often not specific enough, resulting in a complex and time-consuming repair process. Summary of the Invention

[0003] In view of this, embodiments of this application provide a circuit diagram-based fault diagnosis method, terminal device, and storage medium, which can effectively solve the problems of time-consuming traditional circuit diagnosis and lack of real-time analysis.

[0004] In a first aspect, embodiments of this application provide a fault diagnosis method based on circuit diagrams, comprising:

[0005] Obtain component information and wire connection relationships from the pre-processed image of the circuit diagram under test;

[0006] Based on the component information and wire connection relationships of the circuit diagram under test, a topology diagram is constructed to generate a digital circuit model;

[0007] Obtain fault information described by the user, and perform circuit logic analysis on the fault information based on the circuit digital model to generate a fault list;

[0008] Match all fault types in the fault list with the maintenance database to obtain maintenance recommendation information.

[0009] In a first possible embodiment of the first aspect, the circuit diagram-based fault diagnosis method further includes:

[0010] A circuit logic model is constructed based on the component information of the circuit diagram under test;

[0011] Based on the topology diagram and circuit logic model of the circuit under test, analyze the signal flow and the interaction between the components of the circuit under test;

[0012] Design flaws in the circuit under test are detected using a rule engine and topology analysis, and a defect report is generated.

[0013] In a second possible embodiment of the first aspect, the component information includes component type and component parameters, and the acquisition of component information and wire connection relationships in the preprocessed image diagram of the circuit under test includes:

[0014] The circuit diagram under test is input into a pre-trained component recognition model to identify the component types in the circuit diagram under test.

[0015] Text recognition is performed on the text area of ​​the circuit diagram under test to obtain the component parameters;

[0016] The wires in the circuit diagram under test are used as detection targets to identify the wire connection relationships in the circuit diagram under test.

[0017] In a third possible embodiment of the first aspect, constructing a topology diagram based on the component information and the wire connection relationships of the circuit diagram under test includes:

[0018] A topology diagram is constructed based on the component type and the wire connection relationship, and the component parameters are labeled to the corresponding components in the topology diagram.

[0019] The topology diagram after parameter annotation is used as the digital model of the circuit.

[0020] In a fourth possible embodiment of the first aspect, the fault information includes faulty components and fault phenomena, and the step of performing circuit logic analysis on the fault information based on the circuit digital model to generate a fault list includes:

[0021] Starting with the faulty component, search and identify some circuit elements related to the fault information in the topology diagram;

[0022] Logical reasoning is performed on the found circuit components to determine the fault point;

[0023] Determine the fault type corresponding to the fault point based on the fault database;

[0024] The fault types are sorted according to their fault probabilities to generate the fault list.

[0025] In a fifth possible embodiment of the first aspect, the repair recommendation information includes repair suggestions, repair procedures, and repair time, and obtaining the repair recommendation information includes:

[0026] Based on the maintenance database, obtain the maintenance suggestions and maintenance procedures corresponding to the fault type;

[0027] The total operation time of the maintenance process is determined based on a time weight library, and the total operation time is adjusted based on preset constraints to determine the maintenance time.

[0028] In a sixth possible embodiment of the first aspect, the analysis of the signal flow and inter-component relationships of the circuit under test based on the topology diagram and circuit logic model of the circuit under test includes:

[0029] Starting with the analog signal at the input terminal of the circuit under test, the level changes of each circuit node in the circuit under test are determined sequentially.

[0030] Starting from the target circuit node, determine the upstream signal source that affects the target circuit node.

[0031] In a seventh possible embodiment of the first aspect, the step of detecting design defects in the circuit under test and generating a defect report through a rule engine and topology analysis includes:

[0032] The circuit under test is tested for short circuits and overloads using predefined circuit testing rules.

[0033] The signal loop path of the circuit under test is determined by topology analysis, and loop detection is performed on the circuit under test.

[0034] The isolation nodes of the circuit under test are determined by topology analysis, and the circuit under test is then isolated for inspection.

[0035] Secondly, embodiments of this application provide a terminal device, the terminal device including a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the above-described circuit diagram-based fault diagnosis method.

[0036] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed on a processor, implements the circuit diagram-based fault diagnosis method described above.

[0037] The embodiments of this application have the following beneficial effects:

[0038] This embodiment of a circuit diagram-based fault diagnosis method includes: acquiring component information and wire connection relationships in the pre-processed circuit diagram under test; constructing a topology diagram based on the component information and wire connection relationships in the circuit diagram under test to generate a circuit digital model; acquiring fault information, and performing circuit logic analysis on the fault information based on the circuit digital model to generate a fault list; matching all fault types in the fault list with a maintenance database to obtain maintenance recommendation information. This application automates the processing of circuit diagrams under test, significantly improving identification and diagnosis efficiency. By utilizing the circuit digital model and logical reasoning, it ensures the accuracy of fault point inference, generates detailed maintenance suggestions and steps, guides users to quickly repair faults, and is applicable to the analysis of circuit diagrams under test at different design stages. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This paper illustrates a first flowchart of a fault diagnosis method based on a circuit diagram according to an embodiment of this application.

[0041] Figure 2 A second flowchart of a fault diagnosis method based on a circuit diagram according to an embodiment of this application is shown;

[0042] Figure 3 The diagram illustrates a third flowchart of a fault diagnosis method based on a circuit diagram according to an embodiment of this application. Detailed Implementation

[0043] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0044] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0045] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0046] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in a generally used dictionary) shall be interpreted as having the same meaning as in the context of the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0047] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0048] The following examples illustrate the circuit diagram-based fault diagnosis method.

[0049] Figure 1 A flowchart of a circuit diagram-based fault diagnosis method according to an embodiment of this application is shown. Exemplarily, this circuit diagram-based fault diagnosis method includes the following steps:

[0050] S110: Obtain component information and wire connection relationships from the circuit diagram under test after image preprocessing.

[0051] In this embodiment, the application imports the circuit diagram to be tested through a scanner or image file, performs image preprocessing on the circuit diagram to be tested, and exemplaryly improves the clarity and reduces noise interference through image enhancement processing, and then identifies areas with significant brightness changes in the image through edge detection algorithm. In this application, such areas usually correspond to the boundaries or contours of the circuit diagram to be tested, which helps to locate components such as resistors and capacitors.

[0052] In one embodiment, the image enhancement process includes grayscale conversion, binarization, and denoising. Grayscale conversion converts a color image to a grayscale image, reducing redundant information while preserving key features. Binarization further simplifies the grayscale image into a black-and-white image, facilitating subsequent contour extraction or region segmentation. Denoising eliminates random noise in the image while retaining useful signals; for example, it uses a Gaussian filter to perform a convolution operation on the image to reduce the impact of high-frequency noise.

[0053] In another embodiment, this application uses the Canny edge detection algorithm to perform edge detection on the circuit diagram under test. The Canny edge detection algorithm is based on computer vision technology and is used to extract clear and accurate edges from images. In this application, the circuit diagram under test is input after image enhancement processing, and the edge detection of the circuit diagram under test is performed using the Canny edge detection algorithm to output an edge map containing the outlines of circuit elements.

[0054] In one embodiment, the component information includes component type and component parameters. This application inputs the circuit diagram under test (DUT) into a pre-trained component recognition model to identify the component types in the DUT. The component recognition model is a deep learning-based object detection algorithm used to automatically identify and classify various electronic components (such as power supplies, motors, sensors, resistors, capacitors, etc.) from the DUT. By training the model, it learns the feature representations of different components in the DUT, and the model can output the position and category label of each component with high accuracy.

[0055] In one embodiment, the component recognition model pre-training process includes: In the data preparation stage, collecting images of the circuit diagram to be tested, containing components such as power supplies, motors, sensors, resistors, and capacitors, and labeling them, such as using the LabelImg tool to mark component categories and bounding boxes. In the model selection stage, training the component recognition model based on YOLO or Faster R-CNN, and performing transfer learning using pre-trained weights. In the training optimization stage, inputting pre-processed images, defining a loss function (classification loss + bounding box regression loss), and optimizing the model parameters through backpropagation until the validation set accuracy converges.

[0056] In another embodiment, the component recognition model's recognition mechanism is as follows: An edge map containing the outline of circuit components is input into the component recognition model. The model extracts image features using a convolutional neural network, generating candidate regions (using the RPN network of Faster R-CNN or the grid partitioning of YOLO). Each candidate region is then classified to identify components such as power supplies, motors, sensors, resistors, and capacitors. Simultaneously, the model precisely locates the components by adjusting the bounding box coordinates (x, y, width, height) to ensure the detected component range is as accurate as possible. The final output of the component recognition model is a structured list, including component category, confidence level, and location coordinates. The confidence level represents the model's confidence in the component recognition result, typically expressed as a value from 0 to 1 (1 indicating complete confidence). The location coordinates are the specific position of the component in the circuit diagram under test, represented by the bounding box coordinates (x, y, width, height).

[0057] In one embodiment, this application further refines the component type through template matching or feature extraction algorithms. The feature matching algorithm can be a local feature description algorithm or an algorithm for local image shape features. Template matching involves comparing a known component template with the detected component contour to determine the specific type. The feature extraction algorithm is used to extract SIFT (Scale-Invariant Feature Transform) or HOG (Histogram of Oriented Gradients) features from each bounding box region output by the deep learning model. The extracted features are then matched with a predefined feature library to determine the specific type of the component.

[0058] Understandably, while deep learning models can provide preliminary classification results, more precise feature descriptions may be needed for certain subcategories (such as different models of resistors or capacitors). In such cases, traditional computer vision algorithms, such as template matching or feature extraction algorithms, can be introduced for further refinement.

[0059] In one embodiment, this application performs text recognition on the text area of ​​the circuit diagram under test to obtain component parameters, wherein the component parameters include, but are not limited to, the resistance value, capacitance value, model number, etc. of the component. In this embodiment, this application extracts component parameters from the circuit diagram under test using an OCR (Optical Character Recognition) engine. The OCR engine is used to convert the text content in the image into editable and searchable data. In this application, the OCR engine can be used to read the annotation information on the component (such as "1kΩ", "10uF", "BC547", etc.), thereby realizing automated recognition and classification.

[0060] In one implementation, the OCR engine can be Tesseract, an open-source optical character recognition (OCR) engine used to extract text information from images.

[0061] In another embodiment, this application uses the wires in the circuit diagram under test as the detection target to identify the wire connection relationships in the circuit diagram under test. In this embodiment, this application uses Hough transform or deep learning segmentation models (such as U-Net) to extract the wire connection relationships in the circuit.

[0062] The Hough transform is used to detect specific shapes (such as lines and circles) from an image. In this application, the Hough transform can be used to detect the geometric properties of wires (such as orientation and position), thereby identifying the connection relationships of the wires. Deep learning segmentation models are image segmentation techniques based on Convolutional Neural Networks (CNNs), capable of identifying target regions in an image with pixel-level accuracy. In this application, the deep learning segmentation model is used to accurately extract the pixel distribution of wires and further identify their connection relationships. It can be understood that this application, given a determination of the element type, further determines the wires connecting them, thereby determining the wire connection relationships between the elements.

[0063] S120 constructs a topology diagram based on the component information and wire connection relationships of the circuit diagram under test, and generates a digital model of the circuit.

[0064] In one embodiment, this application constructs a topology diagram based on component types and wire connection relationships, and labels component parameters to the corresponding components in the topology diagram; the topology diagram after parameter labeling is used as the circuit digital model. A topology diagram is a mathematical model used to represent the electrical connection relationships between components in a circuit. This application automatically labels component functions and parameters in the topology diagram using a component database (containing standard component parameters), and uses the labeled topology diagram as the circuit digital model.

[0065] Optionally, the circuit digital model of this application is stored as structured data. The format of the structured data includes, but is not limited to, JSON and XML formats, etc., and is not limited here. The circuit digital model can be displayed in the form of a visual circuit diagram under test. The visual circuit diagram under test can be in SVG, PNG, etc., for easy viewing by users.

[0066] In this embodiment, the topology graph includes nodes and edges. Nodes represent components, and their attributes include component type, parameters, and location coordinates. Edges represent wire connections, and their attributes include line width and signal type (power / ground / signal). The topology graph structure can be stored using an adjacency list or a Neo4j graph database, supporting fast path lookup (such as finding the shortest path from power source to load).

[0067] S130: Obtain the fault information described by the user, and perform circuit logic analysis on the fault information based on the circuit digital model to generate a fault list.

[0068] In this embodiment, the application obtains fault information described by the user, such as "the car window cannot be raised or lowered," and uses Natural Language Processing (NLP) to parse the fault description input by the user and extract fault information, which includes the faulty component and the fault phenomenon. Natural Language Processing focuses on the interaction between computers and human language, and its core goal is to enable computers to understand, interpret, generate, and respond to natural language. In this application, NLP is used to parse the fault description input by the user, and its role is to transform the user's unstructured language input into a structured data format for subsequent fault diagnosis.

[0069] In one embodiment, such as Figure 2 As shown, this application performs circuit logic analysis on fault information, including the following steps:

[0070] S131, starting from the faulty component, searches and identifies some circuit elements related to the fault information in the topology diagram.

[0071] In one embodiment, this application identifies certain circuit elements related to fault information based on a digital circuit model. These circuit elements may include, but are not limited to, control units, motors, and power paths. Starting with the faulty component, this application queries the topological relationship graph in the graph database using a breadth-first search (BFS) approach.

[0072] In one embodiment, this application uses a breadth-first search to trace upstream from the faulty component to find the control unit and power path. By initializing the queue, the faulty component is added to the queue, and nodes in the queue are sequentially retrieved. The predecessor node (i.e., all nodes pointing to the current node) is checked and added to the queue. The traversal continues until the power or control unit is reached. For example, the faulty component is a car window, the upstream path includes relays, switches, and batteries, and the control unit is the control pin of a microcontroller.

[0073] In another embodiment, this application uses a breadth-first search to expand downstream from the faulty component to find the controlled load. A queue is initialized, the faulty component is added to the queue, nodes in the queue are sequentially removed, their successor nodes (i.e., all nodes pointed to by the current node) are checked, and the successor nodes are added to the queue. The traversal continues until the terminal load is reached. For example, the faulty component is a car window, and the downstream controlled loads include motors.

[0074] S132, perform logical reasoning on the searched circuit components to determine the fault point.

[0075] In this embodiment, the present application establishes a Boolean logic model, represents the searched circuit element nodes as Boolean variables (such as relay status, motor running status, etc.), and establishes Boolean expressions to describe the logical relationships between the nodes.

[0076] In one embodiment, the circuit element nodes searched in this application are represented as Boolean variables (True / False or 1 / 0). Input signals include MCU_GPIO output (1 represents high level, 0 represents low level); intermediate nodes include relay states (1 represents closed, 0 represents open); and output loads include motor running states (1 represents running, 0 represents stopped). Boolean expressions are established to describe the logical relationships between the nodes. For example, relay state: R = (MCU_GPIO AND Switch), motor running state: M = R. Here, R represents the relay state, MCU_GPIO represents the output pin level state of the controller, Switch represents the switching state of the external input, and M represents the motor running state.

[0077] Assuming the states of some nodes are known (e.g., MCU_GPIO outputs a high level, switch is closed), the states of other nodes can be deduced using Boolean algebra. For example, given the input conditions: MCU_GPIO = 1, Switch = 1, the relay state can be deduced from the logical relationship: R = 1 AND 1 = 1; the motor running state can be deduced as: M = R = 1.

[0078] If the actual measurement data does not match the derivation results, a fault may exist. Based on the logical reasoning results, list all possible candidate points that could lead to the fault. For example, if the relay is not working properly (R = 0), but MCU_GPIO = 1 and Switch = 1, the relay itself may be faulty; if the motor does not start (M = 0), but R = 1, the motor may have an internal problem.

[0079] S133, determine the fault type corresponding to the fault point based on the fault database.

[0080] S134, sort the fault types according to their fault probabilities to generate a fault list.

[0081] In this embodiment, the fault database contains various components (such as relays, motors, transistors, etc.) and their fault types. Based on logical reasoning analysis results, this application determines the fault type corresponding to each fault point by combining the fault database, and labels each fault point with its corresponding fault type. For example, when judging the fault of the relay itself, the corresponding fault types include open circuit faults, short circuit faults, and parameter drift. Based on the common fault types of components and historical data statistics, this application can sort the possible fault types by probability and provide priority suggestions, prioritizing the investigation of high-probability fault points to improve diagnostic efficiency.

[0082] S140: Match all fault types in the fault list with the maintenance database to obtain maintenance recommendation information.

[0083] In one embodiment, the maintenance recommendation information includes maintenance suggestions, maintenance procedures, and maintenance time. This application obtains the maintenance procedures corresponding to the fault type based on a maintenance database. In this embodiment, the database should include, but is not limited to, the following information: recommended maintenance methods corresponding to different fault types (e.g., "replace relay model XYZ"), and recommended procedures corresponding to the maintenance methods. This application determines the maintenance method corresponding to the fault type based on the maintenance database, and generates a maintenance procedure by combining the circuit diagram under test and the maintenance database. For example, the maintenance procedure may be: disconnect the power supply, remove the relay, install a new relay, and test the circuit.

[0084] In another embodiment, this application further determines the total operation time of the maintenance process based on a time weight library, adjusts the total operation time based on preset constraints, and determines the maintenance time. In this embodiment, the maintenance process is decomposed: the maintenance process is broken down into multiple atomic operations, for example, disassembling 4 M3 screws and soldering 2 pins. Here, the maintenance process refers to the overall process of completing a maintenance task from start to finish. An atomic operation refers to a basic operation unit in the maintenance process that cannot be further subdivided.

[0085] In one embodiment, this application establishes a time-weighted library containing atomic operations and their basic time consumption. The total operation time of the maintenance process is determined based on the atomic operation time in the time-weighted library. For example, disassembling each screw takes 0.5 minutes; soldering each pin takes 1 minute. This application introduces various preset constraints to reflect the additional difficulty in actual operation. This application introduces a spatial constraint correction: when the operating area is narrow, the basic time consumption is increased by 20%. A narrow operating area refers to the inability of operators to conveniently and efficiently complete certain atomic operations due to physical space limitations during maintenance tasks. If disassembling a screw involves a narrow operating area, the corrected operation time is... minute.

[0086] This application introduces a tool-dependent correction condition. If a specialized tool is unavailable, the base time is increased by 30%. For example, if the base time for removing one screw is 0.5 minutes, without a specialized tool, the corrected time is 0.5 (1 + 30%) = 0.65 minutes. In this application, a specialized tool refers to a high-efficiency tool designed for a specific repair task (such as an electric screwdriver, a specialized wrench, etc.). If a specialized tool is unavailable, a general-purpose tool (such as a regular screwdriver, pliers) may be required.

[0087] This application also introduces historical calibration correction conditions, dynamically adjusting the time taken for atomic operations in the maintenance process by analyzing past maintenance log records (e.g., the average time for the past 100 "relay replacements" is 28 minutes). Historical calibration correction refers to dynamically adjusting the parameter values ​​in the time weight library by analyzing the actual time data in past maintenance log records, making the estimation closer to the actual situation. For example, if historical data shows that the average time for a certain maintenance process in the past 100 times is 28 minutes, this application adjusts the time taken for atomic operations accordingly, so that the final output estimated time is close to 28 minutes.

[0088] In one embodiment, this application can also perform analytical analysis on the circuit under test to determine whether there are potential design defects in the circuit design, such as short-circuit risk or component overload. Figure 3 As shown, the analytical method may include the following steps:

[0089] S141, Construct a circuit logic model based on the component information of the circuit diagram under test.

[0090] In this embodiment, the circuit diagram under test can be input as a circuit design file in CAD format (such as Altium Designer or Eagle). This application uses a CAD file parsing library (such as DXF or Gerber parser) to extract the circuit design information, which includes, but is not limited to, component layout and wire connections. Similarly, the topology diagram of the circuit under test is obtained by establishing the circuit topology diagram as described above.

[0091] In one embodiment, this application also classifies and models the components based on component information to construct a circuit logic model, dividing the circuit components into passive components and active components. Passive components may include resistors and capacitors. The circuit logic model of a passive component refers to describing the behavioral characteristics of an active component in the circuit through mathematical or logical means. For example, the resistance R = V / I, and the resistance value is determined by the voltage V and the current I.

[0092] An active element is a component in a circuit whose operating state can be controlled by external signals, possessing gain or switching functions. Active elements can include, but are not limited to, transistors, diodes, and operational amplifiers. The circuit logic model of an active element describes its behavioral characteristics in a circuit using mathematical, physical, or logical methods.

[0093] In one implementation, active element modeling can be achieved using two main methods: establishing a SPICE model and a state machine. A SPICE (Simulation Program with Integrated Circuit Emphasis) model is a mathematical model based on physical characteristics, reproducing the actual electrical characteristics of the active element through a set of parameterized equations, including non-ideal effects (such as parasitic capacitance and temperature dependence). For MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), the SPICE model can accurately simulate their on, off, and saturation states.

[0094] State machine models are a modeling method based on logical functions, primarily used to describe the switching behavior or logical states of active components. In this application, the state machine model abstracts the operating states of a transistor into discrete states (such as "on" and "off"), and defines the state switching relationships through input conditions. For example, a transistor's state machine model can be represented by two states: on (ON) and off (OFF).

[0095] In this embodiment, the circuit logic model of the passive component is used to analyze the signal flow and the interaction between components in the circuit under test. When there is resistance in the signal path, an impedance effect is introduced, which affects voltage transmission. When there is both voltage and capacitance in the signal path, an RC time constant is established. The RC time constant (τ) is a core parameter in a resistor-capacitor (RC) circuit used to measure the charging and discharging speed of a capacitor, and its value is equal to the product of the resistance and capacitance values ​​(τ = R × C). The circuit logic model of the active component is used to analyze the signal flow and the interaction between components in the circuit under test, and to determine whether the device is in an active state (e.g., a transistor forming a circuit after being turned on).

[0096] S142, based on the topology diagram and circuit logic model of the circuit under test, analyze the signal flow and the interaction between the components of the circuit under test.

[0097] In one embodiment, this application converts the topology graph into a Directed Acyclic Graph (DAG), where nodes represent signal states (high / low level) and edges represent logic gates (AND / OR / NOT). In this embodiment, based on the circuit topology graph, a DAG is constructed according to the signal transmission order, with input signals as starting nodes, output signals as ending nodes, and intermediate nodes representing the operation results of logic gates.

[0098] In one embodiment, this application performs forward tracing analysis on the circuit under test, starting with the analog signal at the input terminal of the circuit under test and sequentially determining the level changes of each circuit node in the circuit under test. In this embodiment, starting from the input terminal of the circuit (e.g., power supply, control switch, sensor signal), the process of how the analog signal propagates to the output terminal through each component is simulated step by step according to the circuit connection relationship.

[0099] In another embodiment, this application performs reverse sourcing analysis on the circuit under test, starting from the target circuit node to determine the upstream signal sources affecting the target circuit node. Reverse sourcing involves tracing all possible upstream signal sources that may affect the state of the target node backwards. The target node to be analyzed is identified, and a directed acyclic graph (DAG) similar to that used in forward sourcing is used, but in the opposite direction. Starting from the target node, all upstream nodes are traversed backwards until all possible signal sources are found, determining the degree of influence of each upstream signal on the target node.

[0100] This application uses an LED blinking circuit as an example, combining forward tracing and reverse sourcing for signal analysis. The circuit components include: switch S, controlling the circuit's on / off state; resistor R1, a current-limiting resistor; transistor Q1, serving as a switching element; and an LED (light-emitting diode). Circuit working principle: When switch S1 is closed, current flows through R1 into the base of Q1, triggering Q1 to conduct. After Q1 conducts, current flows through the LED, illuminating it.

[0101] Forward tracing analysis assumes that switch S1 is initially open (low level) and then closed (high level). Node 1 represents the output of S1, initially low (switch open). When the switch closes, the output becomes high. Node 2 represents the base voltage of Q1. Initially, due to the open switch, the base is low; when the switch closes, current flows into the base through R1, and the base voltage gradually increases. Logic model verification: Check if the base voltage reaches the threshold. If it does, Q1 conducts, current flows through the LED, and it lights up; if it does not reach the threshold, the LED is off.

[0102] Reverse sourcing analysis, assuming the target node is the state of the LED (on / off), traces back all upstream signal sources that might affect its state: Node 1 is the LED state, determined by the on / off state of Q1. Node 2 is the base voltage of Q1, whose on / off state depends on whether the base voltage reaches a threshold. Node 3 is the initial output state of S1, whose base voltage is determined by the output state of S1. If the LED is off, the base voltage has not reached the threshold, and the initial output state of S1 is low; if the LED is on, the base voltage has reached the threshold, and the initial output state of S1 is high.

[0103] S143 detects design defects in the circuit under test through a rule engine and topology analysis, and generates a defect report.

[0104] In one embodiment, the rule engine performs short-circuit and overload detection on the circuit under test using predefined circuit detection rules. In this embodiment, the short-circuit detection rule checks for a direct connection between the power supply and ground (except for explicitly designed 0Ω resistors). For example, detecting an unmarked wire between power supply VCC and GND triggers a "potential short-circuit risk" alarm. The overload detection rule calculates whether the actual power consumption of a component exceeds its rated value. For example, it finds that resistor R1 (10Ω) consumes 2.5W under 5V power, far exceeding its 0.25W rated value.

[0105] In another embodiment, this application determines the signal loop path of the circuit under test (DUT) through topology analysis. In this embodiment, topology analysis converts the topology of the DUT into a directed graph, where nodes represent key points in the circuit (such as logic gates, amplifiers, capacitors, etc.), and edges represent signal transmission paths and their directions. Feedback loop detection is performed on the DUT, automatically identifying all feedback loops in the circuit. For each loop, the following checks are performed: whether an amplifier (gain unit) exists; whether energy storage elements (capacitors, inductors) exist; and whether the loop constitutes positive feedback. If the above conditions are met, it is determined whether there is a resonant frequency matching the load time constant; if there is a risk of parasitic oscillation, a visual annotation is generated.

[0106] This application also uses topology analysis to determine the isolation nodes of the circuit under test (DUT) and performs isolation checks. Topology analysis converts the DUT's topology into an undirected graph, where nodes represent key points in the circuit (such as digital ground, analog ground, ferrite beads, etc.), and edges represent physical connections and their impedance characteristics. This application performs isolation checks on multiple connection paths in the undirected graph, automatically identifying multi-point connections or non-isolated connections between digital ground and analog ground, and determining whether they conform to single-point connection specifications. For example, it checks if digital ground and analog ground are connected only at a single point via a ferrite bead.

[0107] In one embodiment, this application performs analytical analysis on the circuit under test, generates a defect analysis report based on the analysis results, and searches a defect modification scheme database to obtain relevant modification schemes. This application visually marks defective areas on the circuit diagram under test, for example, by highlighting different types of problem areas with different colors. In this embodiment, the defect modification scheme database is a structured storage system used to store modification diagrams and reference cases related to circuit design defects. For example, if there are multiple connection paths between analog and digital grounds, the database responds by recommending the addition of ferrite beads for single-point isolation and providing suggestions on ferrite bead models.

[0108] This application also provides a terminal device, exemplary of which includes a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer program to enable the terminal device to perform the circuit diagram-based fault diagnosis method described above.

[0109] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Network Processor (NP), Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0110] Memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM). Memory is used to store computer programs, and the processor can execute these programs upon receiving execution instructions.

[0111] This application also provides a computer-readable storage medium for storing computer programs used in the aforementioned terminal devices. For example, the computer-readable storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0112] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0113] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0114] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0115] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A fault diagnosis method based on circuit diagrams, characterized in that, include: Obtain component information and wire connection relationships from the pre-processed image of the circuit diagram under test; Based on the component information and wire connection relationships of the circuit diagram under test, a topology diagram is constructed to generate a digital circuit model; Obtain fault information described by the user, and perform circuit logic analysis on the fault information based on the circuit digital model to generate a fault list; The fault information includes faulty components and fault phenomena. The step of performing circuit logic analysis on the fault information based on the circuit digital model to generate a fault list includes: Starting with the faulty component, search and identify some circuit elements related to the fault information in the topology diagram; Logical reasoning is performed on the searched circuit components to determine the fault point. The fault type corresponding to the fault point is determined according to the fault database. The fault types are sorted according to the fault probability to generate the fault list. Match all fault types in the fault list with the maintenance database to obtain maintenance recommendation information.

2. The fault diagnosis method based on circuit diagrams according to claim 1, characterized in that, Also includes: A circuit logic model is constructed based on the component information of the circuit diagram under test; Based on the topology diagram and circuit logic model of the circuit under test, analyze the signal flow and the interaction between the components of the circuit under test; Design flaws in the circuit under test are detected using a rule engine and topology analysis, and a defect report is generated.

3. The fault diagnosis method based on circuit diagrams according to claim 1, characterized in that, The component information includes component type and component parameters. The acquisition of component information and wire connection relationships in the preprocessed image diagram of the circuit under test includes: The circuit diagram under test is input into a pre-trained component recognition model to identify the component types in the circuit diagram under test. Text recognition is performed on the text area of ​​the circuit diagram under test to obtain the component parameters; The wires in the circuit diagram under test are used as detection targets to identify the wire connection relationships in the circuit diagram under test.

4. The fault diagnosis method based on circuit diagrams according to claim 3, characterized in that, The construction of a topology diagram based on the component information and wire connection relationships of the circuit under test includes: A topology diagram is constructed based on the component type and the wire connection relationship, and the component parameters are labeled to the corresponding components in the topology diagram. The topology diagram after parameter annotation is used as the digital model of the circuit.

5. The fault diagnosis method based on circuit diagrams according to claim 1, characterized in that, The repair recommendation information includes repair suggestions, repair procedures, and repair time. Obtaining the repair recommendation information includes: Based on the maintenance database, obtain the maintenance suggestions and maintenance procedures corresponding to the fault type; The total operation time of the maintenance process is determined based on a time weight library, and the total operation time is adjusted based on preset constraints to determine the maintenance time.

6. The fault diagnosis method based on circuit diagrams according to claim 2, characterized in that, The analysis of signal flow and inter-component relationships in the circuit under test based on the topology diagram and circuit logic model includes: Starting with the analog signal at the input terminal of the circuit under test, the level changes of each circuit node in the circuit under test are determined sequentially. Starting from the target circuit node, determine the upstream signal source that affects the target circuit node.

7. The fault diagnosis method based on circuit diagrams according to claim 2, characterized in that, The process of detecting design defects in the circuit under test using a rule engine and topology analysis, and generating a defect report, includes: The circuit under test is tested for short circuits and overloads using predefined circuit testing rules. The signal loop path of the circuit under test is determined by topology analysis, and loop detection is performed on the circuit under test. The isolation nodes of the circuit under test are determined by topology analysis, and the circuit under test is then isolated for inspection.

8. A terminal device, characterized in that, The terminal device includes a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the circuit diagram-based fault diagnosis method according to any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed on a processor, implements the circuit diagram-based fault diagnosis method according to any one of claims 1-7.

Images