Method for preparing a passive heat dissipation device for an integrated circuit chip

Abstract

The present invention provides a method for preparing a passive heat dissipation device for an integrated circuit chip, comprising: providing a substrate, forming adjacent P-type and N-type layers in the substrate, with the P-type layer located above the N-type layer; forming multiple isolation trenches in the substrate, each isolation trench extending through the P-type layer and into the N-type layer; depositing an isolation material on a first surface of the substrate to fill the isolation trenches, and performing a flattening process down to the surface of the P-type layer; forming a thermoelectric conversion layer on the surface of the P-type layer; forming a heat conductive layer on the surface of the thermoelectric conversion layer; and forming a ground pin connected to the N-type layer on a second surface of the substrate. This method can be used to prepare a passive heat dissipation device that achieves efficient heat dissipation without relying on external power supply, and can dissipate heat simultaneously in both thermal and electrical dimensions, resulting in a better heat dissipation effect than existing technologies. This method is highly compatible with existing semiconductor process technologies and easily achieves efficient chip-level heat dissipation.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a passive heat dissipation device for an integrated circuit chip. Background Art

[0002] With the advancement of chip manufacturing technology, high-computing chips have become a key development direction for the semiconductor industry. Similarly, in the field of power devices, high-voltage devices such as high-voltage fast charging have become a hot topic. Both high-computing chips and high-voltage chips generate more heat than traditional chips, and chip heat dissipation technology has become a key factor restricting chip development.

[0003] In the prior art, integrated circuit (IC) chips are usually cooled by fans, heat sinks, liquid cooling or thermoelectric chips. Heat dissipation devices such as air cooling and liquid cooling are usually large in size, and thermoelectric chips need to provide power and are limited by the thermoelectric arm preparation process, making it difficult to meet today's chip-level heat dissipation requirements. Recently, the American company Frore, xmems launched a piezoelectric material heat dissipation solution. Its principle is to dig some heat dissipation holes in the silicon-based chip, and use the piezoelectric material to generate high-frequency vibrations to activate and remove the heat source of the heat dissipation holes. Cooling air is introduced on one side and the heat source is discharged from the other side, thereby reducing the chip temperature. However, the technical route of this solution is not yet mature.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to provide a method for preparing a passive heat dissipation device for an integrated circuit chip, so as to solve the heat dissipation problem of the chip.

[0006] In order to solve the above problems, a method for preparing a passive heat dissipation device for an integrated circuit chip is provided below, comprising:

[0007] S1. Providing a substrate, forming adjacent P-type and N-type layers in the substrate, wherein the P-type layer is located above the N-type layer;

[0008] S2. forming a plurality of isolation trenches in the substrate, each of the isolation trenches extending through the P-type layer and extending into the N-type layer;

[0009] S3, depositing an isolation material on the first surface of the substrate to fill the isolation trench, and performing a planarization process until the surface of the P-type layer;

[0010] S4, forming a thermoelectric conversion layer on the surface of the P-type layer;

[0011] S5, forming a heat-conducting layer on the surface of the thermoelectric conversion layer;

[0012] S6. Form a ground pin connected to the N-type layer on the second surface of the substrate.

[0013] This method can be used to prepare a passive heat dissipation device that can achieve efficient heat dissipation without relying on external energy supply, and can dissipate heat simultaneously in both thermal and electrical dimensions, with a heat dissipation effect superior to existing technologies. This preparation is highly compatible with existing semiconductor process technologies and can easily achieve efficient chip-level heat dissipation.

[0014] In step S1, the process of forming the P-type layer and the N-type layer includes: providing a substrate, performing N-type ion implantation to form the N-type layer in a first region of the substrate; performing P-type ion implantation to form the P-type layer in a second region of the substrate, the second region being located above the first region; and annealing the substrate. Ion implantation can precisely control the implantation energy and dopant dosage to produce a high-performance PN junction structure, which better meets the miniaturization requirements of chip-level heat dissipation devices.

[0015] In step S2, the isolation trench formation process includes: forming a photoresist layer on the first surface of the substrate; patterning the photoresist layer to form a photoresist mask; using the photoresist mask as an etching mask, etching the P-type layer and the N-type layer in sequence, and stopping at the N-type layer to form the isolation trench.

[0016] In step S3 , the isolation material is deposited on the first surface of the substrate by a plasma enhanced vapor deposition process. The isolation material fills the isolation trench and forms an isolation material layer on the first surface of the substrate.

[0017] In step S3 , a chemical mechanical polishing process is performed on the first surface of the substrate to remove the isolation material until the surface of the P-type layer is reached.

[0018] In step S4, a thermoelectric material is deposited on the surface of the P-type layer by a magnetron sputtering process to form the thermoelectric conversion layer; the thermoelectric material is a P-type thermoelectric material or an N-type thermoelectric material.

[0019] In step S5, a thermally conductive material is deposited on the surface of the thermoelectric conversion layer by chemical vapor deposition to form the thermally conductive layer. The thermally conductive material can be a wide bandgap semiconductor material such as gallium nitride or silicon carbide. Wide bandgap semiconductor materials are selected because they have high thermal conductivity, can quickly dissipate heat, and can also suppress leakage current of the chip to be dissipated.

[0020] After step S5 is completed, the chip to be cooled is bonded, including: providing the chip to be cooled; and bonding the back surface of the chip to be cooled to the surface of the heat-conducting layer. The bonding process can improve the adhesion between the chip and the heat dissipation device, thereby improving the final heat dissipation effect.

[0021] In step S6, the process of forming the ground pin includes: flipping the substrate, forming an outlet groove on the second surface of the substrate using photolithography and etching processes, and the bottom of the outlet groove is located in the N-type layer; filling the outlet groove with metal material to form the ground pin.

[0022] The ground pin is a copper metal wire, and the formation process of the ground pin includes: depositing a barrier layer and a copper seed layer on the second surface of the substrate in sequence; depositing copper metal on the second surface of the substrate through an electrochemical plating process to fill the outlet groove; and removing excess copper material, copper seed layer and barrier layer on the second surface of the substrate through chemical mechanical polishing.

[0023] Compared with the existing technology, the beneficial effects of the present invention mainly include the following: this method can be used to prepare a passive heat dissipation device, which can achieve efficient heat dissipation without relying on external power supply, and can dissipate heat simultaneously in both thermal and electrical dimensions, with a heat dissipation effect better than the existing technology; this preparation is highly compatible with existing semiconductor process technology and can easily achieve efficient chip-level heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 This is a flow chart for preparing a passive heat dissipation device provided by the present invention.

[0026] Figure 2 A schematic diagram of a method for preparing a passive heat dissipation device provided by the present invention. DETAILED DESCRIPTION

[0027] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0028] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0029] The steps in the following embodiments do not correspond one-to-one to the steps in the summary of the invention.

[0030] The invention provides a method for preparing a passive heat dissipation device for an integrated circuit chip. Figure 1 This is a flow chart for preparing a passive heat dissipation device provided by the present invention. Figure 2 A schematic diagram of a method for preparing a passive heat dissipation device provided by the present invention.

[0031] refer to Figure 1-2 The structure of the passive heat dissipation device prepared by the method of the present invention is as follows Figure 2 As shown in Figure 1, the passive heat dissipation device mainly includes three parts, namely, a heat conducting layer 9 bonded to the chip 10 to be cooled, a thermoelectric conversion layer 8, and a PN junction array layer; the PN junction array layer includes multiple PN junction structures 7, and an isolation structure 6 is provided between adjacent PN junction structures 7; the anode (i.e., the P-type end) of each PN junction structure 7 is respectively connected to the thermoelectric conversion layer 8, and the cathode (i.e., the N-type end) of each PN junction structure 7 is short-circuited and grounded through a ground pin 12.

[0032] Example 1

[0033] like Figure 1 As shown, in this embodiment, a method for preparing a passive heat dissipation device for an integrated circuit chip is provided, comprising:

[0034] S1. Providing a substrate, forming adjacent P-type and N-type layers in the substrate, wherein the P-type layer is located above the N-type layer;

[0035] S2. forming a plurality of isolation trenches in the substrate, each of the isolation trenches extending through the P-type layer and extending into the N-type layer;

[0036] S3, depositing an isolation material on the first surface of the substrate to fill the isolation trench, and performing a planarization process until the surface of the P-type layer;

[0037] S4, forming a thermoelectric conversion layer on the surface of the P-type layer;

[0038] S5, forming a heat-conducting layer on the surface of the thermoelectric conversion layer;

[0039] S6. Form a ground pin connected to the N-type layer on the second surface of the substrate.

[0040] Specifically, refer to Figure 1 and Figure 2 As shown, a method for preparing a passive heat dissipation device for an integrated circuit chip includes the following steps:

[0041] Step 1: providing a substrate 1;

[0042] like Figure 2 As shown in a in FIG, a substrate 1 is first provided for device fabrication. In this embodiment, a P-type germanium substrate is provided; in other embodiments, an N-type germanium substrate, an undoped single crystal germanium substrate, or a doped / undoped silicon substrate may also be provided.

[0043] In this embodiment, a germanium (Ge) substrate is used because the turn-on voltage of the Ge PN junction formed can be modulated to be very low when the PN junction structure 7 is subsequently prepared. A low turn-on voltage is beneficial to improving the heat dissipation effect of the heat dissipation device.

[0044] It should be understood that the substrate 1 includes two opposite surfaces, which can be referred to as a first surface and a second surface respectively; in this embodiment, the first surface is Figure 2 The upper surface (or front surface) of the structure shown in a, the second surface is Figure 2 The lower surface (or back surface) of the structure shown in a.

[0045] Step 2: preparing a PN junction array structure in the substrate 1 to form a PN junction array layer;

[0046] In this embodiment, the preparation process of the PN junction array structure includes the following steps:

[0047] Step 201: forming adjacent P-type layer 3 and N-type layer 2 in substrate 1;

[0048] In this embodiment, the P-type layer 3 and the N-type layer 2 are formed by an ion implantation process; however, this application does not limit the method for forming the P-type layer 3 and the N-type layer 2. In other embodiments, adjacent P-type layers 3 and N-type layers 2 may be formed by, for example, a diffusion process or an epitaxial process.

[0049] The ion implantation process is to bombard the semiconductor material with a high energy ion beam to implant impurity atoms (such as B + 、P + In this embodiment, an ion implantation process is used because the ion implantation process can precisely control the implantation energy and doping dose, conveniently regulating the penetration depth and doping concentration of the impurity ions, thereby producing a high-performance PN junction structure 7, which is more in line with the miniaturization requirements of chip-level heat dissipation devices.

[0050] Specifically, refer to Figure 2 As shown in b and c in FIG, the substrate 1 is first subjected to N-type ion implantation to form an N-type layer 2 in the first region of the substrate 1. The result is shown in FIG. Figure 2 Then, a P-type ion implantation process is performed to form a P-type layer 3 in the second region of the substrate 1. The second region is located above the first region. The result is as shown in FIG. Figure 2 Finally, the substrate 1 is annealed to repair lattice damage and activate impurity atoms. The annealing process can be rapid thermal annealing or furnace high-temperature annealing.

[0051] It should be understood that the first area and the second area are respectively Figure 2 The depth range of the N-type layer 2 and the P-type layer 3 in the substrate 1 is shown in FIG. ; the second region refers to the region from the first surface of the substrate 1 to the first depth; the first region refers to the region from the lower surface of the P-type layer 3 to the second depth.

[0052] Step 202: forming an isolation structure 6 in the substrate 1 to obtain a PN junction array structure;

[0053] The specific formation process of the isolation structure 6 is shown in FIG. Figure 2 As shown in d to g.

[0054] First, if Figure 2 As shown in d and e in FIG, a plurality of isolation trenches 5 are formed in the substrate 1 through photolithography and etching processes, and each isolation trench 5 penetrates the P-type layer 3 and extends into the N-type layer 2.

[0055] The above-mentioned photolithography and etching process includes: forming a photoresist layer on the first surface of the substrate 1 through a spin coating process; then patterning the photoresist layer (including exposure, development, etc.) to form a photoresist mask 4. The result is as follows: Figure 2 Then, using the photoresist mask 4 as an etching mask, the P-type layer 3 and the N-type layer 2 are sequentially etched through the etching process, and the etching stops at the N-type layer 2 to form an isolation trench 5. The result is as shown in FIG. Figure 2 As shown in e.

[0056] The etching process of this step can generally adopt a dry etching process. After the isolation groove 5 is formed, the substrate 1 is subjected to a stripping process to remove the residual photoresist mask 4 on the surface, and then a cleaning process is performed.

[0057] Then, if Figure 2 As shown in f and g in FIG, an isolation material is deposited on the first surface of the substrate 1 through a deposition process to fill the isolation groove 5, and then a planarization process is performed until the upper surface of the P-type layer 3.

[0058] Specifically, an isolation material is first deposited on the first surface of the substrate 1 by a plasma enhanced vapor deposition process, the isolation material fills the isolation groove 5 and forms an isolation material layer 61 on the first surface of the substrate 1. Figure 2 Then, a chemical mechanical polishing (CMP) process is performed on the first surface of the substrate 1 to remove excess isolation material until the surface of the P-type layer 3 is reached, as shown in FIG. Figure 2 In this way, a PN junction array structure consisting of a plurality of PN junction structures 7 is prepared in the substrate 1, forming a PN junction array layer.

[0059] In this embodiment, the isolation material is silicon oxide. In other embodiments, the isolation material may also be silicon nitride. In other embodiments, other deposition processes may be used to form the isolation material layer 61, such as chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy.

[0060] Step 3: forming a thermoelectric conversion layer 8 on the surface of the PN junction array layer;

[0061] refer to Figure 2 As shown in h, in this embodiment, a thermoelectric material is deposited on the surface of the P-type layer 3 via a magnetron sputtering process to form a thermoelectric conversion layer 8. The thermoelectric material can be either a P-type or an N-type thermoelectric material, which is not limited in this application. Specifically, for example, it can be a P-type Sb2Te3 thermoelectric material or an N-type Bi2Te3 thermoelectric material. Of course, other thermoelectric materials can also be used, such as bismuth-antimony (Bi-Sb) alloys, silicon-germanium (SiGe) alloys, and tellurium-lead alloys. It should be understood that to improve thermoelectric conversion efficiency and accelerate heat dissipation, materials with high thermoelectric coefficients should be selected.

[0062] In order to make the formation process of the passive heat dissipation device compatible with the integrated circuit process, in this embodiment, a magnetron sputtering process is used to form the thermoelectric conversion layer 8; in other embodiments, other physical deposition processes can also be selected according to actual conditions.

[0063] Step 4: forming a heat conducting layer 9 on the surface of the thermoelectric conversion layer 8;

[0064] refer to Figure 2As shown in Figure 1, in this embodiment, a thermally conductive material is deposited on the surface of the thermoelectric conversion layer 8 via a chemical vapor deposition process to form a thermally conductive layer 9. Thermally conductive layer 9 is used to contact the heat dissipation chip 10. Therefore, to achieve good thermal conductivity, thermally conductive layer 9 must be made of a material with high thermal conductivity while also ensuring certain leakage protection. In this embodiment, thermally conductive layer 9 can be made of gallium nitride (GaN) or silicon carbide (SiC). GaN / SiC is a wide bandgap semiconductor. On the one hand, it can prevent leakage from the heat dissipation chip 10 above, acting like an insulating substrate. On the other hand, GaN / SiC has a high thermal conductivity, which can quickly transfer heat to the thermoelectric conversion layer 8 below.

[0065] Step 5: forming a ground pin 12 connected to the N-type layer 2 on the second surface of the substrate 1 .

[0066] The main structure of the heat sink has been formed above. A grounding pin 12 needs to be formed on the back of substrate 1. It should be understood that the grounding pin 12 can be formed first, and then the heat sink and the chip 10 to be cooled can be attached after the heat sink is formed. Alternatively, the structure obtained after step 4 can be attached to the chip 10 to be cooled, and then the grounding pin 12 on the back can be prepared.

[0067] In the first embodiment, the process of first bonding the heat dissipation chip 10 and then preparing the ground pin 12 is described in detail. The specific process can be referred to Figure 2 As shown in j to l.

[0068] Step 501: providing a chip 10 to be cooled;

[0069] It should be understood that in practical applications, the chips 10 to be cooled usually refer to those chips or devices that generate a large amount of heat and require efficient cooling, such as certain high-voltage power devices or high-temperature devices such as CPUs, GPUs, and TPUs. In this embodiment, a CPU chip is taken as an example.

[0070] Step 502: Bonding the back surface of the chip 10 to be cooled to the surface of the heat conducting layer 9;

[0071] In order to better conduct the heat of the chip 10 to be cooled, it is necessary to ensure that the chip 10 to be cooled and the surface of the passive heat dissipation device, that is, the surface of the heat conducting layer 9, are well bonded. This can be achieved by, for example, soldering or bonding. If necessary, the chip 10 to be cooled can also be thinned to accelerate heat dissipation. In this embodiment, the bonding of the chip 10 to be cooled and the heat dissipation device is achieved by a thermal compression bonding process. The result is shown in FIG. Figure 2 As shown in j.

[0072] Step 503: forming an outlet groove 11 on the second surface of the substrate 1;

[0073] like Figure 2 As shown in k in FIG, the substrate 1 is flipped over, and a photolithography and etching process is used to form an outlet groove 11 on the second surface (i.e., the back surface) of the substrate 1. The bottom of the outlet groove 11 is located in the N-type layer 2. The specific process for forming the outlet groove 11 here can be referred to the process for forming the isolation trench 5 in step 202.

[0074] Step 504 : Fill the outlet groove 11 with metal material to form the ground pin 12 .

[0075] In this embodiment, the ground pin 12 is a copper metal wire, and its formation process includes:

[0076] A barrier layer and a copper seed layer are sequentially deposited on the second surface of the substrate 1; copper metal is then deposited on the second surface of the substrate 1 through an electrochemical plating process to fill the outlet groove 11; and finally, excess copper material, the copper seed layer, and the barrier layer are removed from the second surface of the substrate 1 through a chemical mechanical polishing process to obtain a ground pin 12. Figure 2 As shown in l.

[0077] Example 2

[0078] This second embodiment provides a method for preparing a passive heat sink for an integrated circuit chip. The method is substantially the same as that described in the first embodiment, except that in step 5, the backside ground pins 12 are prepared directly without first bonding the chip 10 to be cooled.

[0079] Steps 1 to 4 of the second embodiment can refer to those described in the first embodiment, and the second embodiment will be described starting from step 5.

[0080] Step 5: forming a ground pin 12 connected to the N-type layer 2 on the second surface of the substrate 1 .

[0081] The main structure of the heat sink has been formed above, and a grounding pin needs to be formed on the back of the substrate 1. In this embodiment, the grounding pin 12 is first formed on the back of the substrate 1 to form a complete heat sink, and then the heat sink is combined with the chip 10 to be cooled.

[0082] Specifically, first, a lead-out groove 11 is formed on the second surface of the substrate 1; Figure 2 As shown by k in FIG. 1 (at this point, there is no chip 10 to be dissipated in the actual device), the substrate 1 is flipped over, and a photolithography and etching process is used to form an outlet groove 11 on the second surface (i.e., the back surface) of the substrate 1. The bottom of the outlet groove 11 is located in the N-type layer 2. The specific process for forming the outlet groove 11 here can refer to the process for forming the isolation trench 5 in step 202 of the first embodiment.

[0083] Then, metal material is filled in the outlet groove 11 to form the ground pin 12. Specifically, in this embodiment, the ground pin 12 is a copper metal wire, and its formation process includes: depositing a barrier layer and a copper seed layer on the second surface of the substrate 1 in sequence; then depositing copper metal on the second surface of the substrate 1 through an electrochemical plating process to fill the outlet groove 11; finally, removing the excess copper material, copper seed layer and barrier layer on the second surface of the substrate 1 through chemical mechanical polishing to obtain the ground pin 12. The results can be referred to Figure 2 As shown in Figure 1 (at this time, there is no chip 10 to be cooled in the actual device).

[0084] After the heat dissipation device is prepared, the heat dissipation device and the chip 10 to be cooled may be attached to each other by, for example, soldering or bonding processes.

[0085] The present invention provides a method for fabricating a passive heat sink for integrated circuit chips. The passive heat sink produced by this method achieves efficient heat dissipation without relying on external power. Furthermore, the passive heat sink dissipates heat simultaneously through both thermal and electrical processes, resulting in superior heat dissipation performance compared to existing technologies. Specifically, the device rapidly dissipates heat through the high thermal conductivity of the heat-conducting layer 9, thereby utilizing heat conduction throughout the entire passive heat sink. More importantly, the device further enhances heat dissipation efficiency through the movement of electrons, converting a portion of the heat into electrical energy through the thermoelectric conversion layer 8, which is then transmitted through the PN junction array layer. This further enhances the heat dissipation efficiency of the passive heat sink.

[0086] In order to facilitate the description of the present invention, some common English nouns or letters are used for illustrative reference only and are not intended to be restrictive or specific. The scope of protection of the present invention should not be limited by their possible Chinese translations or specific letters.

[0087] It should also be noted that, in this article, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A method for preparing a passive heat dissipation device for an integrated circuit chip, characterized in that: include: S1. Providing a substrate, forming adjacent P-type and N-type layers in the substrate, wherein the P-type layer is located above the N-type layer; S2. forming a plurality of isolation trenches in the substrate, each of the isolation trenches extending through the P-type layer and extending into the N-type layer; S3, depositing an isolation material on the first surface of the substrate to fill the isolation trench, and performing a planarization process until the surface of the P-type layer; S4, forming a thermoelectric conversion layer on the surface of the P-type layer; S5, forming a heat-conducting layer on the surface of the thermoelectric conversion layer; S6. Form a ground pin connected to the N-type layer on the second surface of the substrate.

2. The method for preparing a passive heat dissipation device for an integrated circuit chip according to claim 1, wherein: In step S1, the process of forming the P-type layer and the N-type layer includes: Providing a substrate, performing an N-type ion implantation process, and forming the N-type layer in a first region of the substrate; Performing a P-type ion implantation process to form the P-type layer in a second region of the substrate, where the second region is located above the first region; The substrate is subjected to an annealing process.

3. The method for preparing a passive heat dissipation device for an integrated circuit chip according to claim 1, wherein: In step S2, the process of forming the isolation trench includes: forming a photoresist layer on the first surface of the substrate; performing patterning on the photoresist layer to form a photoresist mask; The P-type layer and the N-type layer are sequentially etched using the photoresist mask as an etching mask, and the etching stops at the N-type layer to form the isolation trench.

4. The method for preparing a passive heat dissipation device for an integrated circuit chip according to claim 3, wherein: In step S3 , the isolation material is deposited on the first surface of the substrate by a plasma enhanced vapor deposition process. The isolation material fills the isolation trench and forms an isolation material layer on the first surface of the substrate.

5. The method for preparing a passive heat dissipation device for an integrated circuit chip according to claim 4, wherein: In step S3 , a chemical mechanical polishing process is performed on the first surface of the substrate to remove the isolation material until the surface of the P-type layer is reached.

6. The method for preparing a passive heat dissipation device for an integrated circuit chip according to claim 1, wherein: In step S4, a thermoelectric material is deposited on the surface of the P-type layer by a magnetron sputtering process to form the thermoelectric conversion layer; the thermoelectric material is a P-type thermoelectric material or an N-type thermoelectric material.

7. The method for preparing a passive heat dissipation device for an integrated circuit chip according to claim 1, wherein: In step S5 , a heat-conducting material is deposited on the surface of the thermoelectric conversion layer by a chemical vapor deposition process to form the heat-conducting layer.

8. The method for preparing a passive heat dissipation device for an integrated circuit chip according to claim 1, wherein: After step S5 is completed, the bonding process of the chip to be cooled is performed, including: Provide chips to be cooled; The back surface of the chip to be cooled and the surface of the heat conducting layer are bonded together.

9. The method for preparing a passive heat dissipation device for an integrated circuit chip according to claim 8, wherein: In step S6, the process of forming the ground pin includes: Turning over the substrate, and forming an outlet groove on the second surface of the substrate by photolithography and etching processes, wherein the bottom of the outlet groove is located in the N-type layer; The outlet groove is filled with metal material to form the ground pin.

10. The method for preparing a passive heat dissipation device for an integrated circuit chip according to claim 9, wherein: The ground pin is a copper metal wire, and the formation process of the ground pin includes: Depositing a barrier layer and a copper seed layer in sequence on the second surface of the substrate; depositing copper metal on the second surface of the substrate by an electrochemical plating process to fill the outlet groove; The excess copper material, the copper seed layer and the barrier layer on the second surface of the substrate are removed by chemical mechanical polishing.

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