A multi-type MOSFET chip packaging structure

Abstract

The present invention provides a multi-type MOSFET chip packaging structure, comprising base islands arranged in a line, each base island having a corresponding source pin, gate pin, and drain pin on one side of the line connecting the base islands, the gate pin and drain pin being placed on either side of the base island, and the gate pins being alternately arranged on either side of the line connecting the base islands; the corresponding source pins of two adjacent base islands being electrically connected to each other; and the solder windows of the MOSFETs fixed on the base islands being electrically connected to the corresponding source pin, gate pin, or drain pin. The present invention utilizes base islands arranged in a predetermined order and the corresponding pin types of the base islands, so that the packaged device can accommodate more MOSFETs in a smaller area, ensures effective spacing between the gate pins, and thus prevents the magnetic induction generated during rapid current changes in the gate from affecting the operation of adjacent MOSFETs, thereby enabling the package to cope with a wider range of circuit control conditions.

Description

Technical Field

[0001] The invention belongs to the field of chip packaging, and in particular relates to a multi-type MOSFET chip packaging structure. Background Art

[0002] In the chip packaging process, a single electronic device is typically mounted within a package. However, with technological advancements, designers need to add more current paths within the circuit and control them through corresponding switches. This often requires mounting numerous packaged components on a circuit board and ensuring they coordinate with each other to achieve the desired functionality. This, however, increases the size of the circuit board and, consequently, the product itself. To meet the demands of miniaturization in electronic products, circuit board circuits need to be simplified as much as possible, allowing a single packaged component to perform more functions.

[0003] Currently, some packaging structures can encapsulate multiple devices. However, the spacing between devices fixed on the frame in such packaging structures is usually small. During the circuit control process, some circuit switches change frequently, and the current of the corresponding devices changes greatly. If the spacing between devices is too small, the inductance generated by the current can easily affect other surrounding devices, which is not conducive to the product to achieve the corresponding function. Summary of the Invention

[0004] In view of this, the present invention aims to propose a multi-type MOSFET chip packaging structure to combine multiple different types of MOSFETs to reduce the chip footprint while using the same number of chips.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0006] A multi-type MOSFET chip packaging structure includes multiple base islands arranged in a line. Each base island has a corresponding source pin on one side of the base island connection and a corresponding drain pin on the other side. Each base island also has a corresponding gate pin on one side, and multiple gate pins are alternately arranged on both sides of the base island connection. The source pins corresponding to two adjacent base islands are electrically connected to each other.

[0007] A MOSFET is fixedly arranged on each base island, and the solder window of each MOSFET is electrically connected to the corresponding source pin, gate pin or drain pin;

[0008] Furthermore, the MOSFETs fixed on the two base islands whose source pins are electrically connected to each other are MOSFETs with the same channel.

[0009] Furthermore, the number of the base islands is three, and the drain pins of the two outermost base islands are respectively placed on the sides of the two outermost base islands that are away from each other.

[0010] Furthermore, among the two source pins electrically connected to each other, the area of ​​the source pin corresponding to one base island is smaller than that of the other source pin, and the source pin of the base island and the source pin of the adjacent base island are connected as a whole through the first connecting piece.

[0011] Furthermore, each base island is connected to its corresponding drain pin via a second connecting piece.

[0012] Furthermore, the drain solder window of each MOSFET is respectively placed close to the drain side of the base island to which the MOSFET is fixed.

[0013] Furthermore, connecting strips extend outward from the outer sides of the base islands at both ends.

[0014] Furthermore, the width of the second connecting piece between the base island in the middle and its corresponding drain pin is greater than the width of the second connecting piece between the base islands in other positions and their corresponding drain pins.

[0015] Furthermore, the peripheral sides of each base island are respectively half-etched to form a packaging edge.

[0016] Furthermore, the thickness of the first connecting piece is smaller than the thickness of the source pin.

[0017] Compared with the prior art, the multi-type MOSFET chip packaging structure described in the present invention has the following advantages:

[0018] The present invention adopts base islands and corresponding pin types arranged in a predetermined order, so that the package device can accommodate more MOSFETs in a smaller area while ensuring the effective spacing between the gate pins, thereby preventing the magnetic induction generated during the rapid change of gate current from affecting the operation of adjacent MOSFETs, thereby enabling the package to cope with more circuit control conditions.

[0019] The drain pins of the base islands on both sides are arranged on the outside and connected through the second connecting pieces to cooperate with the connecting strips to improve the stability of the base island fixation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which constitute part of the present invention, are provided to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are provided to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0021] Figure 1 Schematic diagram of the package structure in this embodiment;

[0022] Figure 2 This is a schematic diagram of the packaging structure circuit.

[0023] Description of reference numerals:

[0024] 1-base island; 11-package edge; 12-connecting bar; 2-MOSFET; 3-source pin; 4-drain pin; 5-gate pin; 6-first connecting piece; 7-second connecting piece. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0026] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0027] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0028] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0029] The multi-type MOSFET chip packaging structure described in the present invention includes a plurality of base islands 1 arranged in a line, and a gap is left between each two adjacent base islands 1, and each base island 1 is provided with a source pin 3 corresponding to itself on one side, and a drain pin 4 corresponding to itself on the other side, and the source pins 3 are all placed on the same side of the line connected to the base island 1, and the drain pins 4 are all placed on the other side of the line connected to the base island 1; each base island 1 also has a gate pin corresponding to itself, and a plurality of gate pins 5 are alternately distributed on both sides of the line connected to the base island 1, so that a sufficiently large gap is maintained between the gate pins 5 to reduce the influence of the rapid change of current in the gate pin 5 on the current of other gate pins 5 caused by the large change of magnetic induction, so that the product has a better functional completion effect when in use. A MOSFET 2 is fixedly provided on each base island 1, and the gate welding window of each MOSFET 2 is respectively placed on a side of the base island 1 to which it is fixed, close to the corresponding gate pin 5, and the source welding window of each MOSFET 2 is electrically connected to the source pin 3 of the base island 1 to which it is fixed by means of wire bonding, and the drain welding window of each MOSFET 2 is electrically connected to the drain pin 4 of the base island 1 to which it is fixed; the gate welding window of each MOSFET 2 is electrically connected to the gate pin 5 of the base island 1 to which it is fixed by means of wire bonding, while avoiding the gate connection line being too long and crossing with other wires, which increases the production difficulty, and at the same time avoiding the rapid change of current in the gate from affecting the current in the adjacent wires. In this embodiment, the number of base islands 1 is three, and the source pins 3 corresponding to two adjacent base islands 1 are electrically connected to each other, and the mosfet2 fixed on the base islands 1 corresponding to the two source pins 3 electrically connected to each other are mosfet2 of the same channel. More specifically, the two mosfet2 are N-channel mosfet2, so that the currents in the two mosfet2 are the same. The mosfet2 fixed on the other base island 1 can be matched with the mosfet2 of the corresponding channel as needed. In this embodiment, combined with Figure 2 As shown, the MOSFET 2 fixed on the base island 1 is a MOSFET 2 with a channel different from that of other MOSFETs 2 , that is, the MOSFET 2 fixed on the base island 1 is a P-channel MOSFET 2 .

[0030] In this embodiment, the drain pins 4 of the two outermost base islands 1 are respectively placed on the side of the two outermost base islands 1 that are away from each other, and connecting strips 12 are respectively extended outward from the outer edges of the two outermost base islands 1, so that the drain pin 4 and the connecting strips 12 are close to each other, so that the base islands 1 at both ends are more secure during the process of fixing the MOSFET 2 and bonding. At the same time, each base island 1 is connected to its corresponding drain pin 4 through a second connecting piece 7, and during the processing, the base island 1, the second connecting piece 7 and the drain pin 4 are integrally formed from the same copper sheet, so no additional bonding connection is required between the base island 1 and the drain pin 4. Through the above arrangement, the gate pins 5 at both ends are closer to the center of the package, thereby reducing the bonding range.

[0031] In this embodiment, two electrically connected source pins 3 are connected via a first connecting piece 6. Specifically, the area of ​​the source pin 3 corresponding to one base island 1 is smaller than that of the other source pins 3, and the source pin 3 of this base island 1 and the source pin 3 of the adjacent base island 1 are connected as a whole via the first connecting piece 6. Therefore, by providing a gate pin 5 on one side of the two integrally connected source pins 3, sufficient area is provided for connection between the MOSFET 2 fixed to the middle base island 1 and the source pin 3, thereby ensuring a reliable connection between the MOSFET 2 fixed to the middle base island 1 and the source pin 3. At the same time, the gate pins 5 can be arranged in a staggered manner on both sides of the connection line of the base island 1, thereby increasing the spacing between the gate pins 5. The width of the second connecting piece 7 between the base island 1 in the middle and the drain pin 4 corresponding to it is greater than the width of the second connecting piece 7 between the base island 1 in other positions and the drain pin 4 corresponding to itself, thereby improving the reliability of its connection with the external frame and other structures, and improving the stability of the base island 1 during the process of fixing MOSFET 2 and bonding.

[0032] The packaging edge 11 is formed on each side of the base island 1 by half etching, and the thickness of the first connecting piece 6 is made smaller than the thickness of the source pin 3 by half etching, so as to facilitate the packaging reliability of the epoxy resin and the base island 1, each pin and other structures after packaging.

[0033] The multi-type MOSFET2 chip packaging structure described in the present invention encapsulates multiple MOSFETs in one package during use, reducing the footprint of the device during use. At the same time, after the packaged device is installed on a circuit board, through corresponding circuit connections, the device can control multiple line switches through the internal MOSFETs, thereby meeting more needs.

[0034] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A multi-type MOSFET chip packaging structure, characterized by: The device comprises a plurality of base islands arranged in a line, wherein a source pin corresponding to the base island is provided on one side of the base island connection line, and a drain pin corresponding to the base island is provided on the other side. Each base island also has a gate pin corresponding to the base island on one side, and the gate pins are alternately provided on both sides of the base island connection line; wherein the source pins corresponding to two adjacent base islands are electrically connected to each other; A MOSFET is fixedly arranged on each base island, and a welding window of each MOSFET is electrically connected to a corresponding source pin, gate pin or drain pin.

2. The multi-type MOSFET chip packaging structure according to claim 1, characterized in that: There are three base islands, and the drain pins of the two outermost base islands are respectively placed on the sides of the two outermost base islands that are away from each other.

3. The multi-type MOSFET chip packaging structure according to claim 2, characterized in that: The area of ​​the source pin corresponding to one of the base islands is smaller than that of the other source pins, and the source pin of the base island and the source pin of the adjacent base island are connected as a whole through a first connecting piece.

4. The multi-type MOSFET chip packaging structure according to claim 1, characterized in that: Each base island is connected to its corresponding drain pin via a second connecting piece.

5. The multi-type MOSFET chip packaging structure according to claim 1, characterized in that: The drain solder window of each MOSFET is respectively placed on the drain side close to the base island to which it is fixed.

6. The multi-type MOSFET chip packaging structure according to claim 1, characterized in that: Connecting strips extend outward from the outer sides of the base islands at both ends.

7. The multi-type MOSFET chip packaging structure according to claim 6, characterized in that: The width of the second connecting piece between the base island in the middle and the drain pin corresponding to the base island is greater than the width of the second connecting piece between the base islands in other positions and the drain pins corresponding to the base islands.

8. The multi-type MOSFET chip packaging structure according to claim 1, characterized in that: The peripheral sides of each base island are respectively formed into packaging edges by half etching.

9. The multi-type MOSFET chip packaging structure according to claim 3, characterized in that: The thickness of the first connecting piece is smaller than the thickness of the source pin.

10. The multi-type MOSFET chip packaging structure according to claim 1, wherein the MOSFETs fixed to the two base islands whose source pins are electrically connected to each other are MOSFETs of the same channel.

Images