COT converter and driving control system used therein

Abstract

Disclosed are a COT converter and a drive control system used therein. The driving control system used in the COT converter comprises a compensation ripple wave module used for generating a compensation ripple wave signal based on a switch node voltage and generating a valley value signal corresponding to the minimum value of the compensation ripple wave signal, and the switch node voltage is the voltage of a switch node between a high side power tube and a low side power tube in the COT converter; and the driving control module is used for generating a pulse width modulation (PWM) control signal corresponding to the target conduction time based on the compensation ripple signal and the valley value signal, and the PWM control signal is used for controlling the on-off state of the high-side power tube and the low-side power tube.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to a COT converter and a drive control system used therein. Background Art

[0002] Compared to traditional current-mode or voltage-mode step-down converters, COT (Constant-On-Time) step-down converters offer advantages such as fast load transient response, simple control schemes, and low power consumption at no-load. They are widely used in scenarios with rapidly varying load currents. High-performance COT step-down converters typically use on-chip PWM to generate a constant compensation ripple that is independent of switching frequency, duty cycle, and output voltage. These converters are low-cost, easy to implement, and stable and reliable. However, this solution requires time to establish the DC voltage operating point when transitioning from no-load to full-load, which can affect dynamic performance. Summary of the Invention

[0003] According to an embodiment of the present invention, a drive control system used in a constant on-time (COT) converter includes: a ripple compensation module for generating a compensation ripple signal based on a switch node voltage, and generating a valley signal corresponding to the minimum value of the compensation ripple signal, wherein the switch node voltage is the voltage of the switch node between the high-side power tube and the low-side power tube in the COT converter; and a drive control module for generating a pulse width modulation (PWM) control signal corresponding to a target on-time based on the compensation ripple signal and the valley signal, wherein the PWM control signal is used to control the on and off states of the high-side power tube and the low-side power tube.

[0004] A COT converter according to an embodiment of the present invention includes: a drive circuit; a power circuit including a high-side power transistor and a low-side power transistor; and the above-mentioned drive control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0006] Figure 1 A schematic block diagram showing the system architecture of a COT converter according to an embodiment of the present invention is shown.

[0007] Figure 2 Shown in Figure 1 The figure shows a schematic block diagram of an example structure of a ripple compensation module in a drive control system.

[0008] Figure 3 Shown in Figure 1 The figure shows a schematic block diagram of an example structure of a logic pulse generating unit in a drive control system.

[0009] Figure 4 Shown in Figure 1 FIG. 1 is a schematic block diagram of an example structure of a bias current source in a drive control system shown in FIG.

[0010] Figure 5 Shown Figure 1 Example waveform diagrams of multiple signals in the drive control system are shown. DETAILED DESCRIPTION

[0011] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed in order to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, components and algorithms without departing from the spirit of the present invention. In the accompanying drawings and the following description, well-known structures and technologies are not shown in order to avoid unnecessary ambiguity in the present invention. In addition, it should be noted that the term "A is connected to B" used herein can mean "A is directly connected to B" or "A is indirectly connected to B via one or more other elements."

[0012] In view of the problems existing in traditional on-chip PWM when generating constant compensation ripple, a drive control system used in a COT converter is proposed as an example according to the present invention, wherein the compensation ripple module generates a compensation ripple signal based on the switch node voltage, and the DC voltage operating point of the compensation ripple signal is determined based on the output voltage of the high-side power tube and the low-side power tube. The DC voltage operating point can be established quickly when switching from no-load to full-load, and the dynamic performance is better.

[0013] Figure 1 FIG. 1 is a schematic block diagram showing the system architecture of a COT converter according to an embodiment of the present invention. Figure 1 As shown, the COT converter 100 includes a drive control system 110, a drive circuit 120, and a power circuit 130, wherein the drive control system 110 includes a ripple compensation module 111 and a drive control module, and the power circuit 130 includes a high-side power transistor MH, a low-side power transistor ML, and an inductor L. The high-side power transistor MH and the low-side power transistor ML are connected in series between the input voltage source VIN and the ground terminal GND. One end of the inductor L is connected to the switch node SW of the high-side power transistor MH and the low-side power transistor ML, and the other end generates the output voltage VOUT. The load of the COT converter 100 can be Figure 1 Example load resistance RL and load capacitance CL.

[0014] like Figure 1 As shown, the drive control system 110 outputs a PWM control signal to the drive circuit 120. The drive circuit 120 sends drive signals to the gates of the high-side power tube MH and the low-side power tube ML based on the PWM control signal. The high-side power tube MH and the low-side power tube ML are turned on or off accordingly to adjust the switch node voltage V-SW and the output voltage VOUT.

[0015] like Figure 1 As shown, in the drive control system 110, the compensation ripple module 111 is used to generate a compensation ripple signal CSP based on the switch node voltage V-SW, and generate a valley signal CSN corresponding to the minimum value of the compensation ripple signal CSP. The switch node voltage V-SW is the voltage of the switch node SW between the high-side power tube and the low-side power tube in the COT converter; the drive control module is used to generate a pulse width modulation (PWM) control signal (PWM in the figure) corresponding to the target on-time based on the compensation ripple signal CSP and the valley signal CSN. The PWM control signal is used to control the on-off state of the high-side power tube and the low-side power tube.

[0016] Figure 2 Shown in Figure 1 The schematic block diagram of the exemplary structure of the ripple compensation module in the drive control system is shown in FIG. Figure 2 As shown, in some embodiments, the compensation ripple module 111 may include: a ripple generating unit 210, configured to filter the switch node voltage V-SW to generate a compensation ripple signal CSP; and a valley sampling unit 220, configured to perform valley sampling on the compensation ripple signal CSP to generate a valley signal CSN.

[0017] like Figure 2 As shown, in some embodiments, the ripple generating unit 210 may include a first voltage dividing resistor R SW1 , the second voltage divider resistor R SW2 , the first resistor R1 and the first capacitor C1, the first voltage divider resistor R SW1 The first end of the first voltage dividing resistor R SW1 The second end of the second voltage divider resistor R SW2 The first end of the first resistor R1 is connected to the first end of the first capacitor C1 and outputs the compensation ripple signal CSP. The second end of the first capacitor C1 is connected to the second voltage divider resistor R SW2 The second end is grounded.

[0018] like Figure 2As shown, in some embodiments, the ripple generating unit 210 may further include a first inverter INV1 and a first switch tube M1, the input end of the first inverter INV1 receives a PWM control signal, the output end of the first inverter INV1 is connected to the control end of the first switch tube M1, the first end of the first switch tube M1 receives a first bias current Ion1 inversely proportional to the target on-time ton, and the second end of the first switch tube M1 is connected to the first end of the first capacitor C1.

[0019] like Figure 2 As shown, in some embodiments, the valley sampling unit 220 may include a sampling pulse generating circuit 221, a sampling switch K, a sampling capacitor Csh, and a filtering circuit 222. The sampling pulse generating circuit 221 is configured to generate a sampling pulse signal φ1 triggered by the rising edge of the PWM control signal. The sampling pulse signal φ1 is used to control the on and off of the sampling switch K. The first end of the sampling switch K receives the compensation ripple signal CSP, and the second end is connected to the first end of the sampling capacitor Csh and the input end of the filtering circuit 222. The second end of the sampling capacitor Csh is grounded. The filtering circuit 222 is configured to output the valley signal CSN. The filtering circuit 222 may include a filtering resistor R3 and a filtering capacitor C3.

[0020] like Figure 1 As shown, in some embodiments, the drive control module includes: a comparator unit 112, which is used to generate a turn-on trigger signal COMP0 based on the compensation ripple signal CSP, the valley signal CSN and the output voltage VOUT of the COT converter; a logic pulse generating unit 113, which is used to be triggered by the transition edge of the turn-on trigger signal COMP0 to generate a logic pulse signal P0 corresponding to the target turn-on time; and a logic control unit 114, which is used to generate a PWM control signal based on the logic pulse signal P0.

[0021] In some embodiments, the first pair of input terminals of the comparator unit 112 respectively receive the compensation ripple signal CSP and the valley signal CSN, and the second pair of input terminals of the comparator unit 112 respectively receive the first preset voltage V ref1 , the feedback voltage V corresponding to the output voltage VOUT FB .For example Figure 1 As shown, the comparator unit 112 has a first pair of input terminals, a positive input terminal receiving the compensation ripple signal CSP, an inverting input terminal receiving the valley signal CSN, and a second pair of input terminals, a positive input terminal receiving the first preset voltage V ref1 , the inverting input receives the feedback voltage V FB .exist Figure 1 In the example, the comparator unit 112 compares the voltages of the four input signals. CSP -V CSN +V FB -V ref1>0, the conduction trigger signal COMP0 output by the comparator unit 112 is low level. CSP -V CSN +V FB -V ref1 When ≤0, the conduction trigger signal COMP0 is high level.

[0022] like Figure 1 As shown, in some embodiments, the drive control module further includes voltage divider resistors RF1 and RF2 connected in series between the second end of the inductor L and the ground terminal, and the feedback voltage V FB The voltage at the middle connection point of RF1 and RF2, that is, the feedback voltage V FB It is obtained by dividing the output voltage VOUT by resistors.

[0023] Figure 3 Shown in Figure 1 Schematic block diagram of an example structure of a logic pulse generating unit in a drive control system shown in FIG. Figure 3 As shown, in some embodiments, the logic pulse generating unit 113 includes a charging capacitor C0, a second switch tube M2, a comparator U1, an RS trigger U2, and a second inverter INV2, and wherein: a first end of the charging capacitor C0 is connected to a first end of the second switch tube M2 and a first input end (e.g., a non-inverting input end) of the comparator U1, and receives a second bias current Ion2 inversely proportional to the target on-time ton; a second end of the charging capacitor C0 and a second end of the second switch tube M2 are grounded; a second input end (e.g., an inverting input end) of the comparator U1 receives a second preset voltage V ref2 , the output end is connected to the reset end R of the RS trigger U2; the set end S of the RS trigger U2 receives the conduction trigger signal COMP0, and the output end (for example, the in-phase output end Q) outputs the logic pulse signal P0; the input end of the second inverter INV2 receives the logic pulse signal P0, and the output end is connected to the control end of the second switch tube M2.

[0024] In some embodiments, the driving control system further includes a bias current source for providing at least one of the first bias current Ion1 and the second bias current Ion2 . Figure 4 Shown in Figure 1 Schematic block diagram of an example structure of a bias current source in a drive control system shown in FIG. Figure 4As shown, in some embodiments, the bias current source 400 includes a third voltage-dividing resistor RD1, a fourth voltage-dividing resistor RD2, an operational amplifier unit OP, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, and a second resistor R2, wherein: a first end of the third voltage-dividing resistor RD1 is connected to the input voltage source VIN of the COT converter; a second end of the third voltage-dividing resistor RD1 is connected to the first end of the fourth voltage-dividing resistor RD4 and the non-inverting input terminal of the operational amplifier unit OP; a control end of the third switch tube M3 is connected to the output terminal of the operational amplifier unit OP, and a first end is connected to the inverting input terminal of the operational amplifier unit OP and the first end of the second resistor R2; a second end of the fourth voltage-dividing resistor RD2 is grounded; a first end of the fourth switch tube M4 and a first end of the fifth switch tube M5 are connected to a preset voltage source AVDD; a second end of the third switch tube M3 is connected to the second end and the control end of the fourth switch tube M4 and the control end of the fifth switch tube M5; and a second end of the fifth switch tube M5 outputs the first bias current Ion1 or the second bias current Ion2.

[0025] like Figure 4 As shown, the size ratio of the fourth switch tube M4 to the fifth switch tube M5 is N:1, where N is a positive number. Therefore, the drain current of the fifth switch tube M5 can be expressed as:

[0026]

[0027] Where β is the voltage divider ratio of the third and fourth voltage divider resistors RD1 and RD2 to the input voltage source VIN. The drain current of the fifth switch M5 can be selected to provide either the first bias current Ion1 or the second bias current Ion2 by selecting different sizes. If two switches M51 and M52 are configured in the bias current source and both are connected as the fifth switch M5, the switches M51 and M52 can output the first bias current Ion1 and the second bias current Ion2, respectively.

[0028] like Figure 3 As shown, the initial state of the conduction trigger signal COMP0 is low, the initial state of P0 is low, the second inverter INV2 outputs a high level, the second switch tube M2 is turned on, so that the first end of the charging capacitor C0 is reset to an initial voltage of 0, the comparator U1 outputs a low level, and the output of the RS trigger U2 is also reset to a low level; when the conduction trigger signal COMP0 becomes high, the non-inverting output terminal Q of the RS trigger U2 is set to a high level, that is, P0 becomes high. At this time, the reset state of the charging capacitor C0 is released, and the second bias current Ion2 charges the charging capacitor C0, so that the voltage of the first end of the charging capacitor C0 increases until it reaches the second preset voltage V ref2, the output of comparator U1 becomes high level, so that the in-phase output terminal Q of RS trigger U2 is reset to low level, that is, P0 changes from high level to low level, so the pulse width of P0 is increased by the voltage of the first terminal of charging capacitor C0 from 0 to V ref2 The time is determined by the dynamic relationship of capacitance:

[0029]

[0030] According to formula (1), we can know that:

[0031]

[0032] Where k2 is a positive number, which is the current between the fourth switch tube and the second bias current I on2 The corresponding size ratio of the fifth switch tube. Substituting formula (3) into formula (2), the conduction time can be expressed as:

[0033]

[0034] It can be seen from formula (2) that the pulse width of the logic pulse signal P0 output by the logic pulse generating unit 113 is the target on-time ton, which is inversely proportional to the second bias current Ion2.

[0035] In some embodiments, if the ripple generating unit 210 does not include the first inverter INV1 and the first switch tube M1, the first voltage dividing resistor R SW1 and the second voltage divider resistor R SW2 The function of the resistor is to divide the switch node voltage V-SW. Since the SW node is a high voltage node, the resistor is used to divide the voltage to meet the voltage domain requirements of the low voltage control voltage. The first voltage divider resistor R SW1 , the second voltage divider resistor R SW2 The resistance of is much smaller than that of the first resistor R1. The voltage divider ratio here can be expressed as:

[0036]

[0037] In the steady state, the DC component V of V-SW DC_SW It can be expressed as:

[0038] V DC_SW =DV IN =V OUT ; (6)

[0039] Where D is the duty cycle of the COT converter, V OUT The first resistor R1 and the first capacitor C1 form a low-pass filter, which divides the voltage of SW by the voltage node (R SW1 and R SW2The voltage at the connection point of the compensation ripple signal CSP is filtered, so the DC component of the compensation ripple signal CSP can be expressed as:

[0040] V DC_CSP =αV DC_SW =αDV IN =αV OUT ; (7)

[0041] Now consider the AC component of CSP. When the voltage at the SW node is high, the current charging the first capacitor C1 can be expressed as:

[0042]

[0043] Since the target on-time t on =DT s , where D is the duty cycle, T s is the switching period, so based on the dynamic relationship of the first capacitor C1, the compensation ripple of CSP generated by the SW node filtering can be expressed as:

[0044]

[0045] When the ripple generating unit 210 does not include the first inverter INV1 and the first switch tube M1, the DC voltage operating point of CSP is as shown in formula (7): DC_CSP , the compensation ripple is shown in formula (9) as ΔV CSP From formula (7), we can see that the DC voltage operating point of CSP is only related to the output voltage V OUT It is related to the internal voltage divider ratio α of the ripple generating unit 210. At this time, the ripple generating unit 210 has the advantage of a stable DC voltage operating point. As can be seen from formula (9), the compensation ripple at this time is related to the resistor voltage divider ratio α, the output voltage V OUT , switching period T s It is related to the duty cycle D. If the amplitude of the compensation ripple is too small, the system loop will be unstable. Therefore, the corresponding parameters can be selected based on formula (9) to ensure that the amplitude of the compensation ripple is not too small.

[0046] like Figure 2 As shown, in some embodiments, if the ripple generating unit 210 includes a first inverter INV1 and a first switch tube M1, when the PWM control signal is at a high level, the first switch tube M1 is turned on, and the first bias current Ion1 charges the first capacitor C1. The compensation ripple variation generated by the charging can be expressed as:

[0047]

[0048] Where k1 is a positive number, which is the current between the fourth switch tube and the first bias current I on1The size ratio of the corresponding fifth switch tube. From formula (10), it can be seen that the amplitude of the compensation ripple change is only related to the charging capacitor C0, the first capacitor C1, and the second preset voltage V ref2 And k1, the above parameters are determined during circuit design to obtain a constant compensation ripple variation ΔV CSP-i , the compensation ripple change ΔV CSP-i It is independent of system parameters such as switching frequency and duty cycle.

[0049] When the ripple generating unit 210 includes the first inverter INV1 and the first switch M1, and the first bias current Ion1 is added, the DC voltage operating point of the CSP will change. Since the charging current and the discharging current are equal in one cycle, it can be expressed as:

[0050]

[0051] Where V DC_CSP′ is the DC component of CSP in the current ripple generating unit 210, the left side of the equal sign is the discharge current, and the right side of the equal sign is the charging current. From this, it can be solved that the DC component of CSP caused by the addition of the first bias current Ion1 can be expressed as:

[0052]

[0053] From formula (12), it can be seen that due to the addition of the first bias current Ion1, the first inverter INV1 and the first switch tube M1, an increment of the DC operating point of CSP can be expressed as:

[0054]

[0055] From equations (9) and (10), it can be seen that the compensation ripple of CSP caused by the addition of the first bias current Ion1, the first inverter INV1 and the first switch tube M1 can be expressed as:

[0056]

[0057] When the ripple generating unit 210 includes the first inverter INV1 and the first switch tube M1, and the first bias current Ion1 is added, the DC voltage operating point of CSP is as shown in formula (12): DC_CSP’ , the compensation ripple is shown in formula (14) as ΔV CSP’ , CSP is the sum of two ripple components: the first ripple component is the voltage on the switch node passing through the first voltage divider resistor R SW1 , the second voltage divider resistor R SW2 , the first resistor R1 and the first capacitor C1 generate the ripple amplitude as shown in formula (9). s, duty cycle D, and other external parameters change, while its DC operating point is relatively stable as shown in equation (7); the second ripple component is generated by the first bias current Ion1 through the first switch tube M1 and the first capacitor C1. The ripple amplitude is shown in equation (10) and does not change with external parameters. The DC operating point component is shown in equation (13) and is inversely proportional to (1-D). This means that when the duty cycle D is close to 1, the DC operating point of CSP will reach the power rail limit. Through reasonable design, these two ripple components can be used to achieve the complementarity of the compensation ripple signal CSP: select a suitable k1 value. Specifically, the range of k1 values is determined based on the principle that the ripple amplitude of the second ripple component meets the minimum ripple amplitude requirement of the COT architecture. The largest k1 value is selected to minimize the impact of the second ripple component on the CSP DC operating point. Then, the appropriate first ripple component can be set according to the requirements of operating frequency, comparator speed, signal-to-noise ratio, etc., thereby improving the stability and anti-interference ability of the system.

[0058] The existence of the first ripple component can improve the dynamic performance of the COT converter under no-load to full-load conditions, because when the COT converter is in no-load condition, the high-side power tube MH and the low-side power tube ML are in the off state, and the voltage of the SW node is equal to V OUT , so the DC operating point of CSP is maintained at αV OUT , when no-load turns to full-load, the DC operating point of CSP will become V DC_CSP’ , the change is Since the maximum k1 value is selected, the change is small and the DC operating point of the CSP can be established quickly, thereby improving the dynamic performance of the COT converter from no-load to full-load.

[0059] Figure 5 Shown Figure 1 The example waveforms of multiple signals in the drive control system are shown in FIG. Figure 5 As shown, when the drive control system 110 follows Figure 1 When the compensation ripple signal CSP generated by the compensation ripple module 111 in the control system 110 is running and includes a first ripple component and a second ripple component, the phase mismatch between the two ripple components causes the CSP to exhibit significant segmentation after superposition. First, when the PWM control signal transitions from a low level to a high level, the first bias current Ion1 immediately charges the first capacitor C1, and the second ripple component begins to rise from its valley value. After PWM transitions to a high level, the switch node voltage V-SW rises. There is a transmission delay between the PWM and V-SW changes. When V-SW rises, the first ripple component begins to rise, resulting in an increased slope of CSP at the rising edge of V-SW. CSP must reach the comparator unit's flip threshold within the minimum on-time; otherwise, the minimum on-time and maximum operating frequency will be limited. Therefore, the target on-time value cannot be too small.

[0060] like Figure 2 As shown, in the valley sampling unit 220, when PWM changes from low level to high level, the sampling pulse generating circuit 221 generates a sampling pulse signal φ1 with a fixed pulse width. Figure 5 As shown, when PWM becomes high, CSP starts to rise. Therefore, CSP is at the valley position at the rising edge of PWM. The sampling pulse signal φ1 becomes high to control the sampling switch K to be turned on. The sampling pulse signal φ1 waits for a fixed pulse width time and then becomes low to control the sampling switch K to be turned off, thereby sampling the valley value of CSP and holding it on the sampling capacitor Csh. After being low-pass filtered by the filter circuit 222, a stable valley signal CSN corresponding to the valley voltage of CSP can be obtained.

[0061] like Figure 5 As shown, the voltage Vsh at the first terminal of the sampling capacitor Csh changes in accordance with the sampling pulse signal φ1. The filter circuit 222 performs low-pass filtering on Vsh to obtain a stable voltage signal as the valley signal CSN, whose voltage is a stable VCSN. The conduction trigger signal COMP0 output by the comparator unit 112 flips at the valley bottom of CSP, and the flipping moment satisfies the following relationship:

[0062] V CSP -V CSN +V FB -V ref1 =0 (15)

[0063] Always meet V at the bottom CSP -V CSN =0, so from formula (16), V FB -V ref1 =0, that is, V FB =V ref1 , so the output voltage can be expressed as: This eliminates DC errors in the output voltage.

[0064] The present invention may be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the present invention. Therefore, the present embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention is defined by the appended claims rather than the foregoing description, and all modifications coming within the meaning and scope of equivalents of the claims are intended to be included within the scope of the present invention.

Claims

1. A drive control system for a constant on-time (COT) converter, comprising: a ripple compensation module, configured to generate a compensation ripple signal based on a switch node voltage, and to generate a valley signal corresponding to a minimum value of the compensation ripple signal, wherein the switch node voltage is a voltage of a switch node between a high-side power transistor and a low-side power transistor in a COT converter; as well as A drive control module is used to generate a pulse width modulation (PWM) control signal corresponding to the target conduction time based on the compensated ripple signal and the valley signal, and the PWM control signal is used to control the on and off states of the high-side power tube and the low-side power tube.

2. The driving control system according to claim 1, wherein: The ripple compensation module includes: a ripple generating unit, configured to filter the switch node voltage to generate the compensation ripple signal; and The valley sampling unit is configured to perform valley sampling on the compensation ripple signal to generate the valley signal.

3. The driving control system according to claim 2, wherein: The ripple generating unit includes a first voltage-dividing resistor, a second voltage-dividing resistor, a first resistor and a first capacitor, wherein the first end of the first voltage-dividing resistor is connected to the switch node, the second end of the first voltage-dividing resistor is connected to the first end of the second voltage-dividing resistor and the first end of the first resistor, the second end of the first resistor is connected to the first end of the first capacitor and outputs the compensation ripple signal, and the second end of the first capacitor and the second end of the second voltage-dividing resistor are grounded.

4. The driving control system according to claim 3, wherein: The ripple generating unit further includes a first inverter and a first switching tube, wherein an input end of the first inverter receives the PWM control signal, an output end of the first inverter is connected to a control end of the first switching tube, a first end of the first switching tube receives a first bias current inversely proportional to the target on-time, and a second end of the first switching tube is connected to a first end of the first capacitor.

5. The driving control system according to claim 2, wherein: The valley sampling unit includes a sampling pulse generating circuit, a sampling switch, a sampling capacitor, and a filtering circuit, and wherein: The sampling pulse generating circuit is used to generate a sampling pulse signal triggered by the rising edge of the PWM control signal, and the sampling pulse signal is used to control the on and off of the sampling switch; The first end of the sampling switch receives the compensation ripple signal, the second end is connected to the first end of the sampling capacitor and the input end of the filter circuit, and the second end of the sampling capacitor is grounded; and The filtering circuit is used to output the valley signal.

6. The driving control system according to claim 1, wherein: The drive control module includes: a comparator unit, configured to generate a turn-on trigger signal based on the compensated ripple signal, the valley signal, and an output voltage of the COT converter; a logic pulse generating unit, configured to be triggered by a transition edge of the conduction trigger signal to generate a logic pulse signal corresponding to the target conduction time; and A logic control unit is used to generate the PWM control signal based on the logic pulse signal.

7. The driving control system according to claim 6, wherein: The first pair of input terminals of the comparator unit respectively receives the compensation ripple signal and the valley signal, and the second pair of input terminals of the comparator unit respectively receives a first preset voltage and a feedback voltage corresponding to the output voltage.

8. The driving control system according to claim 6, wherein: The logic pulse generating unit includes a charging capacitor, a second switch tube, a comparator, an RS trigger, and a second inverter, and wherein: The first end of the charging capacitor is connected to the first end of the second switch tube and the first input end of the comparator, and receives a second bias current inversely proportional to the target on-time; The second end of the charging capacitor and the second end of the second switch tube are grounded; The second input terminal of the comparator receives a second preset voltage, and the output terminal is connected to the reset terminal of the RS trigger; The set terminal of the RS trigger receives the conduction trigger signal, and the output terminal outputs the logic pulse signal; The input end of the second inverter receives the logic pulse signal, and the output end is connected to the control end of the second switch tube.

9. The drive control system according to claim 4 or 8, further comprising a bias current source, wherein: The bias current source includes a third voltage-dividing resistor, a fourth voltage-dividing resistor, an operational amplifier unit, a third switching tube, a fourth switching tube, a fifth switching tube, and a second resistor, and wherein: A first end of the third voltage-dividing resistor is connected to an input voltage source of the COT converter; The second end of the third voltage-dividing resistor is connected to the first end of the fourth voltage-dividing resistor and the non-inverting input end of the operational amplifier unit; The control end of the third switch tube is connected to the output end of the operational amplifier unit, and the first end is connected to the inverting input end of the operational amplifier unit and the first end of the second resistor; The second end of the fourth voltage-dividing resistor and the second end of the second resistor are grounded; The first end of the fourth switch tube and the first end of the fifth switch tube are connected to a preset voltage source; The second end of the third switch tube is connected to the second end and the control end of the fourth switch tube and the control end of the fifth switch tube; The second end of the fifth switch tube outputs a first bias current or a second bias current.

10. A COT converter, comprising: Drive circuit; A power circuit including a high-side power tube and a low-side power tube; as well as A drive control system according to any one of claims 1 to 9.

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