Level shift circuit

Abstract

The invention provides a level shift circuit. The circuit comprises a voltage conversion module, a first noise elimination module, a second noise elimination module and an output module, the first input end of the voltage conversion module is connected with a first pulse signal, the second input end is connected with a second pulse signal, and the first output end is connected with the first input end of the first noise elimination module and the first input end of the second noise elimination module. The second output end is connected with the second input end of the first noise elimination module and the second input end of the second noise elimination module; four output ends of the first noise elimination module are respectively connected with four input ends of the second noise elimination module; two output ends of the second noise elimination module are respectively connected with two input ends of the output module, and the two output ends of the output module alternately output a floating voltage source and a floating ground; the first noise elimination module eliminates common-mode current through cross coupling, and the second noise elimination module inhibits common-mode net current and reduces transmission time delay.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a level shift circuit. Background Art

[0002] To drive power insulated-gate bipolar transistors (IGBTs), a driver circuit must be designed between the signal control circuit and the IGBT to switch the IGBT on and off. This driver circuit primarily uses a high-voltage level shifter circuit to convert the power supply and ground voltages to the high-side floating supply and ground voltages. However, during operation, the high-voltage level shifter circuit is susceptible to interference caused by the rapid voltage changes at the IGBT's switch node, known as dV / dt transients.

[0003] Currently, resistor-capacitor filters are primarily used to suppress dV / dt transient interference. However, these filters suffer from complex structures, low noise immunity, and significant transmission delay. Therefore, there is an urgent need for a voltage level shifting circuit that can suppress transient interference and reduce transmission delay. Summary of the Invention

[0004] The purpose of this application is to provide a level shift circuit to address the deficiencies in the above-mentioned prior art, so as to solve the practical problems of the prior art in which a resistor-capacitor filter is used to suppress dV / dt transient interference, such as complex structure, low noise immunity and large transmission delay.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows: In a first aspect, an embodiment of the present application provides a level shift circuit, the circuit comprising: a voltage conversion module, a first noise elimination module, a second noise elimination module, and an output module; A first input terminal of the voltage conversion module is connected to a first pulse signal, a second input terminal of the voltage conversion module is connected to a second pulse signal that is in phase with the first pulse signal, a first output terminal of the voltage conversion module is connected to a first input terminal of the first noise elimination module and a first input terminal of the second noise elimination module, and a second output terminal of the voltage conversion module is connected to a second input terminal of the first noise elimination module and a second input terminal of the second noise elimination module; The first output terminal of the first noise cancellation module is connected to the third input terminal of the second noise cancellation module, the second output terminal of the first noise cancellation module is connected to the fourth input terminal of the second noise cancellation module, the third output terminal of the first noise cancellation module is connected to the fifth input terminal of the second noise cancellation module, and the fourth output terminal of the first noise cancellation module is connected to the sixth input terminal of the second noise cancellation module; The first output terminal of the second noise elimination module is connected to the first input terminal of the output module, and the second output terminal of the second noise elimination module is connected to the second input terminal of the output module; the first output terminal and the second output terminal of the output module are used to alternately output a floating voltage source and a floating ground; The first noise elimination module is used to eliminate the common-mode current generated by the voltage conversion module through cross-coupling, and the second noise elimination module is used to suppress the common-mode net current from the first noise elimination module.

[0006] As an optional implementation, the first noise elimination module includes: a first current mirror, a second current mirror, a third current mirror, and a fourth current mirror; An input end of the first current mirror is connected to a first output end of the voltage conversion module and a first input end of the second noise elimination module, a first output end of the first current mirror is connected to an input end of the third current mirror and a third input end of the second noise elimination module, and a second output end of the first current mirror is connected to an output end of the fourth current mirror and a fifth input end of the second noise elimination module; The input end of the second current mirror is connected to the second output end of the voltage conversion module and the second input end of the second noise elimination module, the first output end of the second current mirror is connected to the first input end of the fourth current mirror and the fourth input end of the second noise elimination module, and the second output end of the second current mirror is connected to the output end of the third current mirror and the sixth input end of the second noise elimination module.

[0007] As an optional implementation, the second noise elimination module includes: a first transmission gate and a second transmission gate; The first input terminal of the first transmission gate is connected to the second output terminal of the voltage conversion module and the second input terminal of the first noise elimination module, the second input terminal of the first transmission gate is connected to the first output terminal of the first noise elimination module, the third input terminal of the first transmission gate is connected to the third output terminal of the first noise elimination module, and the output terminal of the first transmission gate is connected to the first input terminal of the output module; A first input terminal of the second transmission gate is connected to the first output terminal of the voltage conversion module and the first input terminal of the first noise elimination module, a second input terminal of the second transmission gate is connected to the second output terminal of the first noise elimination module, a third input terminal of the second transmission gate is connected to the fourth output terminal of the first noise elimination module, and an output terminal of the second transmission gate is connected to the second output terminal of the output module.

[0008] As an optional implementation, the output module includes: a fifth current mirror, a sixth current mirror, a latch, a first inverter, and a second inverter; an input end of the fifth current mirror connected to the first output end of the second noise elimination module, a first output end of the fifth current mirror connected to the second output end of the sixth current mirror, the first end of the latch, and the input end of the first inverter, and a second output end of the fifth current mirror connected to the first output end of the sixth current mirror, the second end of the latch, and the input end of the second inverter; The input end of the sixth current mirror is connected to the second output end of the second noise elimination module; The output end of the first inverter is connected to the first output port, and the first inverter is used to output the floating voltage source when the second inverter does not output the floating ground. The output end of the second inverter is connected to the second output port, and the second inverter is used to output the floating ground when the first inverter does not output the floating voltage source.

[0009] As an optional implementation, the voltage conversion module includes: a first laterally diffused metal oxide semiconductor field effect transistor LDMOS and a second LDMOS; The gate of the first LDMOS is connected to the first pulse signal, the drain of the first LDMOS is connected to the first input terminal of the first noise elimination module and the first input terminal of the second noise elimination module, and the source of the first LDMOS and the source of the second LDMOS are both connected to a common ground; The gate of the second LDMOS is connected to the second pulse signal which is in phase opposite to the first pulse signal, and the drain of the second LDMOS is connected to the second input end of the first noise elimination module and the second input end of the second noise elimination module.

[0010] As an optional implementation, the first current mirror includes: a first P-channel metal oxide semiconductor field effect transistor (PMOS), a third PMOS, and a fourth PMOS; the second current mirror includes: a second PMOS, a fifth PMOS, and a sixth PMOS; The gate and drain of the first PMOS are short-circuited and connected to the first output terminal of the voltage conversion module, the first input terminal of the second noise elimination module, the gate of the third PMOS, and the gate of the fourth PMOS. The source of the first PMOS and the source of the second PMOS are both connected to the floating voltage source. The gate and drain of the second PMOS are short-circuited and connected to the second output terminal of the voltage conversion module, the second input terminal of the second noise elimination module, the gate of the fifth PMOS and the gate of the sixth PMOS; The drain of the third PMOS is connected to the input terminal of the third current mirror and the third input terminal of the second noise elimination module, the drain of the fourth PMOS is connected to the output terminal of the fourth current mirror and the fifth input terminal of the second noise elimination module, the drain of the sixth PMOS is connected to the first input terminal of the fourth current mirror and the fourth input terminal of the second noise elimination module, and the drain of the fifth PMOS is connected to the output terminal of the third current mirror and the sixth input terminal of the second noise elimination module; The source of the third PMOS, the source of the fourth PMOS, the source of the fifth PMOS, and the source of the sixth PMOS are all connected to the floating voltage source.

[0011] As an optional implementation, the third current mirror includes: a first N-channel metal oxide semiconductor field effect transistor (NMOS), a second NMOS, a third NMOS, and a fourth NMOS; the fourth current mirror includes: a fifth NMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS; The gate and drain of the first NMOS are short-circuited and connected to the gate of the second NMOS, the first output terminal of the first current mirror, and the third input terminal of the second noise elimination module; the source of the first NMOS is connected to the drain of the third NMOS, the gate of the third NMOS, and the gate of the fourth NMOS; The drain of the second NMOS is connected to the second output terminal of the second current mirror and the sixth input terminal of the second noise elimination module respectively, the source of the second NMOS is connected to the drain of the fourth NMOS, and the source of the third NMOS and the source of the fourth NMOS are both connected to the floating ground; The gate and drain of the sixth NMOS are short-circuited and connected to the gate of the fifth NMOS, the first output terminal of the second current mirror, and the fourth input terminal of the second noise elimination module; the source of the sixth NMOS is connected to the drain of the eighth NMOS, the gate of the eighth NMOS, and the gate of the seventh NMOS; The drain of the fifth NMOS is respectively connected to the second output terminal of the first current mirror and the fifth input terminal of the second noise elimination module, the source of the fifth NMOS is connected to the drain of the seventh NMOS, and the source of the seventh NMOS and the source of the eighth NMOS are both connected to the floating ground.

[0012] As an optional implementation, the first transmission gate includes: a fifteenth PMOS and a seventeenth NMOS; the second transmission gate includes: a sixteenth PMOS and an eighteenth NMOS; The gate of the fifteenth PMOS is connected to the first output terminal of the first noise elimination module, the drain of the fifteenth PMOS is connected to the drain of the seventeenth NMOS and the third output terminal of the first noise elimination module, the source of the fifteenth PMOS and the source of the seventeenth NMOS are both connected to the first input terminal of the output module, and the gate of the seventeenth NMOS is connected to the second output terminal of the voltage conversion module and the second input terminal of the first noise elimination module; The gate of the sixteenth PMOS is connected to the second output terminal of the first noise elimination module, the drain of the sixteenth PMOS is connected to the drain of the eighteenth NMOS and the fourth output terminal of the first noise elimination module, the source of the sixteenth PMOS and the source of the eighteenth NMOS are both connected to the second input terminal of the output module, and the gate of the eighteenth NMOS is connected to the first output terminal of the voltage conversion module and the first input terminal of the first noise elimination module.

[0013] As an optional implementation, the fifth current mirror includes: a seventh PMOS, an eighth PMOS, a ninth NMOS, and a tenth NMOS; the sixth current mirror includes: a ninth PMOS, a tenth PMOS, an eleventh NMOS, and a twelfth NMOS; The gate and drain of the seventh PMOS are short-circuited and connected to the gate of the eighth PMOS and the drain of the ninth NMOS. The source of the seventh PMOS and the source of the eighth PMOS are both connected to the floating voltage source. The drain of the eighth PMOS is respectively connected to the drain of the eleventh NMOS, the first terminal of the latch, and the input terminal of the first inverter. The gate of the ninth NMOS is connected to the first output terminal of the second noise elimination module and the gate of the tenth NMOS respectively, the source of the ninth NMOS and the source of the tenth NMOS are both connected to the floating ground, and the drain of the tenth NMOS is connected to the drain of the ninth PMOS, the second terminal of the latch, and the input terminal of the second inverter respectively; The gate and drain of the tenth PMOS are short-circuited and connected to the gate of the ninth PMOS and the drain of the twelfth NMOS, and the source of the tenth PMOS and the source of the ninth PMOS are both connected to the floating voltage source; The gate of the twelfth NMOS is connected to the second output terminal of the second noise elimination module and the gate of the eleventh NMOS respectively, and the source of the eleventh NMOS and the source of the twelfth NMOS are both connected to the floating ground.

[0014] As an optional implementation, the latch includes: an eleventh PMOS, a twelfth PMOS, a thirteenth NMOS, and a fourteenth NMOS; the first inverter includes: a thirteenth PMOS and a fifteenth NMOS; the second inverter includes: a fourteenth PMOS and a sixteenth NMOS; The gate of the eleventh PMOS is respectively connected to the gate of the thirteenth NMOS, the drain of the twelfth PMOS, the drain of the fourteenth NMOS, the second output terminal of the fifth current mirror, the gate of the fourteenth PMOS, and the gate of the sixteenth NMOS; the drain of the eleventh PMOS is respectively connected to the drain of the thirteenth NMOS, the gate of the twelfth PMOS, the gate of the fourteenth NMOS, the second output terminal of the sixth current mirror, the gate of the thirteenth PMOS, and the gate of the fifteenth NMOS; The source of the eleventh PMOS transistor, the source of the twelfth PMOS transistor, the source of the thirteenth PMOS transistor, and the source of the fourteenth PMOS transistor are all connected to the floating voltage source; the source of the thirteenth NMOS transistor, the source of the fourteenth NMOS transistor, the source of the fifteenth NMOS transistor, and the source of the sixteenth NMOS transistor are all connected to the floating ground; The drain of the thirteenth PMOS is connected to the drain of the fifteenth NMOS and the first output port respectively, and the drain of the fourteenth PMOS is connected to the drain of the sixteenth NMOS and the second output port respectively.

[0015] The beneficial effects of this application are: The present application provides a level shift circuit, which includes a voltage conversion module, a first noise elimination module, a second noise elimination module and an output module. The voltage conversion module is connected to the first noise elimination module and the second noise elimination module respectively, and the second noise elimination module is connected to the output module. The two input ends of the voltage conversion module are respectively connected to a first pulse signal and a second pulse signal that is inverted to the first pulse signal. The voltage conversion module performs voltage domain conversion based on the alternately input pulse signals and generates a differential mode current. The differential mode current is correctly transmitted to the output module through the first noise elimination module and the second noise elimination module. The output module changes the output state based on the correctly transmitted differential mode current and outputs a floating voltage source or floating ground in the high voltage domain after the voltage conversion module converts it. The first noise elimination module cross-couples the two common mode currents generated by the voltage conversion module so that the two common mode currents cancel each other. The second noise elimination module blocks the common mode net current output by the first noise elimination module, suppresses the interference of the common mode net current on the output module, and ensures that the output module alternately outputs a floating voltage source and a floating ground. The first noise elimination module and the second noise elimination module suppress the influence of the common mode current generated by the voltage conversion module during the rapid floating ground conversion on the output voltage of the output module, thereby improving the anti-noise performance of the level shift circuit and reducing the transmission delay of the level shift circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic diagram of the structure of a level shift circuit provided in an embodiment of the present application; Figure 2 Another structural diagram of the level shift circuit provided in an embodiment of the present application; Figure 3 This is another structural diagram of the level shift circuit provided in an embodiment of the present application.

[0018] Voltage conversion module: 1; first noise elimination module: 2; second noise elimination module: 3; output module: 4; first current mirror: 21; second current mirror: 22; third current mirror: 23; fourth current mirror: 24; first transmission gate: TG1; second transmission gate: TG2; fifth current mirror: 41; sixth current mirror: 42; latch: L1; first inverter: Inv1; second inverter: Inv2; first LDMOS transistor: LDMOS1; second LDMOS transistor: LDMOS2; first PMOS transistor: PM1; second PMOS transistor: PM2; third PMOS transistor: PM3; fourth PMOS transistor: PM4; fifth PMOS transistor: PM5; sixth PMOS transistor: PM6; seventh PMOS transistor: PM7; eighth PMOS transistor: PM8; ninth PMOS transistor: PM9; tenth PMOS transistor: PM10; eleventh PMOS transistor: PM11; twelfth PMOS transistor: PM12; thirteenth PMOS transistor : PM13; 14th PMOS transistor: PM14; 15th PMOS transistor: PM15; 16th PMOS transistor: PM16; 1st NMOS transistor: NM1; 2nd NMOS transistor: NM2; 3rd NMOS transistor: NM3; 4th NMOS transistor: NM4; 5th NMOS transistor: NM5; 6th NMOS transistor: NM6; 7th NMOS transistor: NM7; 8th NMOS transistor: NM8; 9th NMOS transistor: NM9; 10th NMOS transistor: N M10; eleventh NMOS transistor: NM11; twelfth NMOS transistor: NM12; thirteenth NMOS transistor: NM13; fourteenth NMOS transistor: NM14; fifteenth NMOS transistor: NM15; sixteenth NMOS transistor: NM16; seventeenth NMOS transistor: NM17; eighteenth NMOS transistor: NM18; first resistor: R1; second resistor: R2; first capacitor: C1; second capacitor: C2; first diode: D1; second diode: D2. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0020] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0021] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0022] In the semiconductor field, high-voltage level shifters in driver circuits are susceptible to dV / dt transient interference caused by the rapid voltage changes at the switching nodes of power IGBTs when driving power LGBTs. Currently, resistor-capacitor filters are the primary method for suppressing dV / dt transient interference. However, these filters suffer from complex structures, low noise immunity, and significant transmission delays. Consequently, existing high-voltage level shifters have limitations.

[0023] To address the above-mentioned issues, embodiments of the present application provide a level shifting circuit comprising a voltage conversion module, a first noise cancellation module, a second noise cancellation module, and an output module. The first noise cancellation module eliminates the common-mode current generated by the voltage conversion module through cross-coupling of multiple current mirrors. The second noise cancellation module suppresses the net common-mode current from the first noise cancellation module through two transmission gates to ensure correct output from the output module. This eliminates transient common-mode noise, improves noise immunity, and reduces the transmission delay of the level shifting circuit.

[0024] Figure 1 A schematic diagram of the structure of the level shift circuit provided in the embodiment of the present application is shown in FIG. Figure 1 As shown, the level shift circuit includes a voltage conversion module 1 , a first noise elimination module 2 , a second noise elimination module 3 and an output module 4 .

[0025] Optionally, refer to Figure 1In the level shifting circuit, voltage conversion module 1 is connected to first noise cancellation module 2 and second noise cancellation module 3, respectively. Second noise cancellation module 3 is also connected to output module 4. Voltage conversion module 1 is used to perform voltage domain conversion based on the input pulse signal and generate a differential-mode current. This differential-mode current is correctly transmitted to output module 4 through first noise cancellation module 2 and second noise cancellation module 3, ensuring that output module 4 changes its output state based on the correctly transmitted differential-mode current and outputs the converted floating voltage source VB or floating ground VS. First noise cancellation module 2 and second noise cancellation module 3 are used to suppress the impact of common-mode current generated by voltage conversion module 1 on the output voltage of output module 4 when floating ground VS changes rapidly.

[0026] The first input end of the voltage conversion module 1 is connected to the first pulse signal, the second input end of the voltage conversion module 1 is connected to the second pulse signal which is inversely proportional to the first pulse signal, the first output end of the voltage conversion module 1 is connected to the first input end of the first noise elimination module 2 and the first input end of the second noise elimination module 3, and the second output end of the voltage conversion module 1 is connected to the second input end of the first noise elimination module 2 and the second input end of the second noise elimination module 3.

[0027] Optionally, continue with reference to Figure 1 The voltage conversion module 1 includes two input terminals, two output terminals, and a ground terminal. The first input terminal of the voltage conversion module 1 can be the rising edge (RE) input terminal of the pulse width modulation (PWM) signal, which receives the first pulse signal Vre. The second input terminal of the voltage conversion module 1 can be the falling edge (FE) input terminal of the PWM signal, which receives the second pulse signal Vfe. The ground terminal of the voltage conversion module 1 is connected to the common ground COM.

[0028] The rising-edge first pulse signal Vre and the falling-edge second pulse signal Vfe are in opposite phases and are alternately input to the first input terminal and the second input terminal of the voltage conversion module 1. In differential mode, the voltage conversion module 1 performs voltage domain conversion based on the alternately input first pulse signal Vre and second pulse signal Vfe, converting the low-voltage domain from the power supply VDD to the common ground COM into the high-voltage domain from the floating voltage source VB to the common ground COM, and generating a differential-mode current.

[0029] In common-mode mode, voltage conversion module 1 generates common-mode current, which is transient common-mode noise current. The first output of voltage conversion module 1 is connected to the first input of first noise cancellation module 2 and the first input of second noise cancellation module 3. The second output of voltage conversion module 1 is connected to the second input of first noise cancellation module 2 and the second input of second noise cancellation module 3. This ensures that differential-mode current is properly transmitted to first and second noise cancellation modules 2 and 3, suppressing common-mode current.

[0030] The first output end of the first noise elimination module 2 is connected to the third input end of the second noise elimination module 3, the second output end of the first noise elimination module 2 is connected to the fourth input end of the second noise elimination module 3, the third output end of the first noise elimination module 2 is connected to the fifth input end of the second noise elimination module 3, and the fourth output end of the first noise elimination module 2 is connected to the sixth input end of the second noise elimination module 3.

[0031] Optionally, continue with reference to Figure 1 The first noise cancellation module 2 includes two inputs, four outputs, a power supply, and a reference ground. The second noise cancellation module 3 includes six inputs and two outputs. The first, second, third, and fourth outputs of the first noise cancellation module 2 are connected to the third, fourth, fifth, and sixth inputs of the second noise cancellation module 3, respectively. This connection provides multiple reference potentials for the second noise cancellation module 3, enabling the first and second noise cancellation modules 2 and 3 to work together to correctly transmit differential-mode current and suppress common-mode current.

[0032] The power supply terminal of the first noise cancellation module 2 is connected to a floating voltage source VB, which serves as the power supply node for the high-voltage domain and provides a bias voltage for the first noise cancellation module 2. The reference ground terminal of the first noise module 2 is connected to a floating ground VB, which serves as the reference ground for the level shifting circuit and provides a potential reference for the first noise module 2. The floating ground VB and the floating voltage source VB form a potential difference in the high-voltage domain. The potential of the floating ground VB fluctuates with the switching node voltage of the power IGBT device. When the potential of the floating ground VB changes rapidly, the resulting dV / dt transient interference causes the voltage conversion module 1 to enter common-mode mode, generating common-mode current.

[0033] The first output end of the second noise elimination module 3 is connected to the first input end of the output module 4, and the second output end of the second noise elimination module 3 is connected to the second input end of the output module 4; the first output end and the second output end of the output module 4 are used to alternately output a floating voltage source and a floating ground.

[0034] Optionally, continue with reference to Figure 1The output module 4 includes two input terminals, two output terminals, a power supply terminal, and a reference ground terminal. The first and second input terminals of the output module 4 are respectively connected to the first and second output terminals of the second noise cancellation module 3 to receive the alternating differential-mode current transmitted by the second noise cancellation module 3. Under the influence of the alternating differential-mode current, the output module 4 alternately outputs a floating voltage source VB and a floating ground VS through the first and second output terminals of the output module 4, thereby driving the power IGBT device.

[0035] The first noise elimination module 2 is used to eliminate the common-mode current generated by the voltage conversion module 1 through cross-coupling, and the second noise elimination module 3 is used to suppress the common-mode net current from the first noise elimination module 2 .

[0036] Optionally, continue with reference to Figure 1 The first noise cancellation module 2 cross-couples the two common-mode currents generated by the voltage conversion module 1, causing the two common-mode currents to cancel each other out. However, when the transient common-mode noise current, i.e., the common-mode current, is too large, the first noise cancellation module 2 may output a common-mode net current with a non-zero current value. At this time, the second noise cancellation module 3 blocks the common-mode net current output by the first noise cancellation module 2, preventing the common-mode net current from passing through the second noise cancellation module 3 and entering the output module 4. This suppresses the interference of the common-mode net current on the output module 4, ensuring that the output module 4 is not interfered with by the common-mode current and correctly outputs the voltage, i.e., alternately outputting the floating voltage source VB and the floating ground VS. Furthermore, since there is no need to design a resistor-capacitor filter circuit to filter out transient common-mode noise current, the transmission delay of the level shifting circuit is greatly reduced.

[0037] In this embodiment, the level shifting circuit includes a voltage conversion module, a first noise cancellation module, a second noise cancellation module, and an output module. The voltage conversion module is connected to the first and second noise cancellation modules, respectively, and the second noise cancellation module is connected to the output module. The two input terminals of the voltage conversion module are respectively connected to a first pulse signal and a second pulse signal that is in phase with the first pulse signal. The voltage conversion module performs voltage domain conversion based on the alternately input pulse signals and generates a differential-mode current. The differential-mode current is correctly transmitted to the output module through the first and second noise cancellation modules. The output module changes its output state based on the correctly transmitted differential-mode current and outputs a floating voltage source or floating ground in the high-voltage domain after conversion by the voltage conversion module. The first noise cancellation module cross-couples the two common-mode currents generated by the voltage conversion module, causing the two common-mode currents to cancel each other out. The second noise cancellation module blocks the net common-mode current output by the first noise cancellation module, suppressing interference of the net common-mode current on the output module and ensuring that the output module alternately outputs a floating voltage source and a floating ground. The first noise elimination module and the second noise elimination module suppress the influence of the common mode current generated by the voltage conversion module during the rapid floating ground conversion on the output voltage of the output module, thereby improving the anti-noise performance of the level shift circuit and reducing the transmission delay of the level shift circuit.

[0038] Figure 2 Another structural diagram of the level shift circuit provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, the first noise elimination module 2 includes a first current mirror 21 , a second current mirror 22 , a third current mirror 23 and a fourth current mirror 24 .

[0039] Optionally, refer to Figure 2 The first noise cancellation module 2 includes four current mirrors: a first current mirror 21, a second current mirror 22, a third current mirror 23, and a fourth current mirror 24. The first current mirror 21 and the second current mirror 22 are used to replicate the two common-mode currents generated simultaneously by the voltage conversion module 1 in common-mode mode, as well as the two differential-mode currents generated alternately by the voltage conversion module 1 in differential-mode mode. The third current mirror 23 and the fourth current mirror 24 are both cascode current mirrors. They are used to replicate and cross-couple the two common-mode currents in common-mode mode, outputting the cross-coupled common-mode static current to the second noise cancellation module 3, and to replicate the two alternately generated differential-mode currents in differential-mode mode, outputting the differential-mode currents to the second noise cancellation module 3.

[0040] The input end of the first current mirror 21 is connected to the first output end of the voltage conversion module 1 and the first input end of the second noise elimination module 3, the first output end of the first current mirror 21 is connected to the input end of the third current mirror 23 and the third input end of the second noise elimination module 3, and the second output end of the first current mirror 21 is connected to the output end of the fourth current mirror 24 and the fifth input end of the second noise elimination module 3.

[0041] Optionally, continue with reference to Figure 2 The first current mirror 21 and the second current mirror 22 each include an input terminal, two output terminals and a power supply terminal, and the third current mirror 23 and the fourth current mirror 24 each include an input terminal, an output terminal and a reference ground terminal.

[0042] The input of the first current mirror 21 is connected to the first output of the voltage conversion module 1 and the first input of the second noise elimination module 3 via the A1 node to provide a first reference potential to the second noise elimination module 3. In common mode, the first current mirror 21 receives the transient common-mode noise voltage generated by the first output of the voltage conversion module 1. The first current mirror 21 converts the received transient common-mode noise voltage into a first common-mode current Icom1, i.e., obtains the first common-mode current Icom1 based on the first noise current Inoise1 generated by the voltage conversion module 1. In differential mode, the first current mirror 21 also copies the first differential-mode current Isd1 from the voltage conversion module 1.

[0043] The first output terminal of the first current mirror 21 is connected to the input terminal of the third current mirror 23 and the third input terminal of the second noise cancellation module 3 via the B1 node, so as to transmit the first common-mode current Icom1 or the first differential-mode current Isd1 to the third current mirror 23 and provide a third reference potential for the second noise cancellation module 3. The second output terminal of the first current mirror 21 is connected to the output terminal of the fourth current mirror 24 and the fifth input terminal of the second noise cancellation module 3 via the E1 node, so as to transmit the first common-mode current Icom1 or the first differential-mode current Isd1 to the fourth current mirror 24 and provide a fifth reference potential for the second noise cancellation module 3.

[0044] The input end of the second current mirror 22 is connected to the second output end of the voltage conversion module 1 and the second input end of the second noise elimination module 3, the first output end of the second current mirror 22 is connected to the first input end of the fourth current mirror 24 and the fourth input end of the second noise elimination module 3, and the second output end of the second current mirror 22 is connected to the output end of the third current mirror 23 and the sixth input end of the second noise elimination module 3.

[0045] Optionally, continue with reference to Figure 2The input of the second current mirror 22 is connected to the second output of the voltage conversion module 1 and the second input of the second noise cancellation module 3 via node A2 to provide a second reference potential to the second noise cancellation module 3. In common-mode mode, the second current mirror 22 receives the transient common-mode noise voltage generated by the second output of the voltage conversion module 1. The second current mirror 22 converts the received transient common-mode noise voltage into a second common-mode current Icom2, i.e., based on the second noise current Inoise2 generated by the voltage conversion module 1, to obtain the second common-mode current Icom2. In differential-mode mode, the second current mirror 22 also copies the second differential-mode current Isd2 from the voltage conversion module 1.

[0046] The first output terminal of the second current mirror 22 is connected to the first input terminal of the fourth current mirror 24 and the fourth input terminal of the second noise cancellation module 3 via the B2 node, so as to transmit the second common-mode current Icom2 or the second differential-mode current Isd2 to the fourth current mirror 24 and provide a fourth reference potential for the second noise cancellation module 3. The second output terminal of the second current mirror 22 is connected to the output terminal of the third current mirror 23 and the sixth input terminal of the second noise cancellation module 3 via the E2 node, so as to transmit the second common-mode current Icom2 or the second differential-mode current Isd2 to the third current mirror 23 and provide a sixth reference potential for the second noise cancellation module 3.

[0047] Based on this, the third current mirror 23 replicates the first differential-mode current Isd1 in the differential-mode mode to obtain a third differential-mode current Isd3 equal to the first differential-mode current Isd1, and outputs the third differential-mode current Isd3 to the second noise elimination module 3 through the E2 node. The fourth current mirror 24 replicates the second differential-mode current Isd2 in the differential-mode mode to obtain a fourth differential-mode current Isd4 equal to the second differential-mode current Isd2, and outputs the fourth differential-mode current Isd4 to the second noise elimination module 3 through the E1 node.

[0048] In common-mode mode, the third current mirror 23 replicates the first common-mode current Icom1 to obtain a third common-mode current Icom3 equal to the first common-mode current Icom1. The fourth current mirror 24 replicates the second common-mode current Icom2 to obtain a fourth common-mode current Icom4 equal to the second common-mode current Icom2. In common-mode mode, the third current mirror 23 and the fourth current mirror 24 both act as cascode current mirrors. Through cross-coupling, the third common-mode current Icom3 and the fourth common-mode current Icom4 cancel each other out. The net common-mode current after cancellation is output to the second noise cancellation module 3 via nodes E1 and E2, so that the second noise cancellation module 3 blocks and suppresses the net common-mode current.

[0049] In this embodiment, a first current mirror, a second current mirror, a third current mirror, and a fourth current mirror are provided in the first noise cancellation module. The first current mirror transmits a common-mode current or a differential-mode current to the third and fourth current mirrors, and provides a third reference potential and a fifth reference potential for the second noise cancellation module. The second current mirror transmits another common-mode current or another differential-mode current to the third and fourth current mirrors, and provides a fourth reference potential and a sixth reference potential for the second noise cancellation module. In common-mode mode, two common-mode currents are generated by the first and second current mirrors. These two common-mode currents are replicated and cross-coupled by the third and fourth current mirrors to offset each other. The cross-coupled common-mode static current is then output to the second noise cancellation module to improve noise immunity.

[0050] As an optional implementation, the second noise elimination module 3 includes: a first transmission gate TG1 and a second transmission gate TG2.

[0051] Optionally, continue with reference to Figure 2 The second noise cancellation module 3 includes two transmission gates: a first transmission gate TG1 and a second transmission gate TG2. In differential mode, the first transmission gate TG1 and the second transmission gate TG2 are alternately turned on to transmit a differential-mode current to the output module 4 through the turned-on first transmission gate TG1 or the turned-on second transmission gate TG2. In common mode, both the first transmission gate TG1 and the second transmission gate TG2 are turned off to prevent the net common-mode current, after cross-coupling and cancellation between the third current mirror 23 and the fourth current mirror 24, from entering the output module 4.

[0052] A first input terminal of the first transmission gate TG1 is connected to the second output terminal of the voltage conversion module 1 and the second input terminal of the first noise elimination module 2, a second input terminal of the first transmission gate TG1 is connected to the first output terminal of the first noise elimination module 2, a third input terminal of the first transmission gate TG1 is connected to the third output terminal of the first noise elimination module 2, and an output terminal of the first transmission gate TG1 is connected to the first input terminal of the output module 4.

[0053] Optionally, continue with reference to Figure 2The first transmission gate TG1 includes three input terminals and one output terminal. The first input terminal of the first transmission gate TG1 serves as the second input terminal of the second noise cancellation module 3 and is connected to the second output terminal of the voltage conversion module 1 and the second input terminal of the first noise cancellation module 2 through node A2, respectively, to access the first reference potential of the first transmission gate TG1, i.e., the second reference potential of the second noise cancellation module 3. The second input terminal of the first transmission gate TG1 serves as the third input terminal of the second noise cancellation module 3 and is connected to the first output terminal of the first noise cancellation module 2 through node B1, to access the second reference potential of the first transmission gate TG1, i.e., the third reference potential of the second noise cancellation module 3. The third input terminal of the first transmission gate TG1 serves as the fifth input terminal of the second noise cancellation module 3 and is connected to the third output terminal of the first noise cancellation module 2 through node E1, to access the third reference potential of the first transmission gate TG1, i.e., the fifth reference potential of the second noise cancellation module 3. The output terminal of the first transmission gate TG1 serves as the first output terminal of the second noise cancellation module 3 and is connected to the first input terminal of the output module 4, thereby transmitting a differential-mode current to the output module 4 in differential mode.

[0054] A first input terminal of the second transmission gate TG2 is connected to the first output terminal of the voltage conversion module 1 and the first input terminal of the first noise elimination module 2, a second input terminal of the second transmission gate TG2 is connected to the second output terminal of the first noise elimination module 2, a third input terminal of the second transmission gate TG2 is connected to the fourth output terminal of the first noise elimination module 2, and an output terminal of the second transmission gate TG2 is connected to the second output terminal of the output module 4.

[0055] Optionally, continue with reference to Figure 2 The second transmission gate TG2 also includes three input terminals and one output terminal. The first input terminal of the second transmission gate TG2 serves as the first input terminal of the second noise cancellation module 3 and is connected to the first output terminal of the voltage conversion module 1 and the first input terminal of the first noise cancellation module 2 through node A1, respectively, to access the first reference potential of the second transmission gate TG2, i.e., the first reference potential of the second noise cancellation module 3. The second input terminal of the second transmission gate TG2 serves as the fourth input terminal of the second noise cancellation module 3 and is connected to the second output terminal of the first noise cancellation module 2 through node B2, to access the second reference potential of the second transmission gate TG2, i.e., the fourth reference potential of the second noise cancellation module 3. The third input terminal of the second transmission gate TG2 serves as the sixth input terminal of the second noise cancellation module 3 and is connected to the fourth output terminal of the first noise cancellation module 2 through node E2, to access the third reference potential of the second transmission gate TG2, i.e., the sixth reference potential of the second noise cancellation module 3. The output terminal of the second transmission gate TG2 serves as the second output terminal of the second noise cancellation module 3 and is connected to the second input terminal of the output module 4, thereby transmitting another differential-mode current to the output module 4 in differential-mode mode.

[0056] In this embodiment, a first transmission gate and a second transmission gate are provided in the second noise cancellation module. The first transmission gate is connected to three reference potentials through its three input terminals, and the second transmission gate is connected to another three reference potentials through its three input terminals. Based on the six reference potentials, in differential mode, the first and second transmission gates are alternately turned on to transmit a differential-mode current to the output module through the first or second transmission gate that is turned on. In common mode, both the first and second transmission gates are turned off to block the net common-mode current from entering the output module. The first and second transmission gates in the second noise cancellation module ensure the correct transmission of the differential-mode current and suppress interference with the output module caused by the net common-mode current.

[0057] As an optional implementation, the output module 4 includes: a fifth current mirror 41 , a sixth current mirror 42 , a latch L1 , a first inverter Inv1 , and a second inverter Inv2 .

[0058] Optionally, continue with reference to Figure 2 Output module 4 includes two current mirrors, two inverters, and a latch: a fifth current mirror 41, a sixth current mirror 42, a latch L1, a first inverter Inv1, and a second inverter Inv2. The fifth current mirror 41 and the sixth current mirror 42 are used to control the latch state of latch L1 based on the differential-mode current alternately output by the second noise cancellation module 3, thereby controlling the alternating on and off states of the first inverter Inv1 and the second inverter Inv2. The first inverter Inv1 and the second inverter Inv2 are used to alternately output a floating voltage source VB and a floating ground VS when on.

[0059] The input terminal of the fifth current mirror 41 is connected to the first output terminal of the second noise cancellation module 3. The first output terminal of the fifth current mirror 41 is respectively connected to the second output terminal of the sixth current mirror 42, the first terminal of the latch L1, and the input terminal of the first inverter Inv1. The second output terminal of the fifth current mirror 41 is respectively connected to the first output terminal of the sixth current mirror 42, the second terminal of the latch L1, and the input terminal of the second inverter Inv2. The input terminal of the sixth current mirror 42 is connected to the second output terminal of the second noise cancellation module 3.

[0060] Optionally, continue with reference to Figure 2 The fifth current mirror 41 and the sixth current mirror 42 each include an input terminal, two output terminals, a power supply terminal, and a reference ground terminal. The latch L1 includes two input terminals, and the first inverter Inv1 and the second inverter Inv2 each include an input terminal, an output terminal, a power supply terminal, and a reference ground terminal.

[0061] The input end of the fifth current mirror 41 serves as the first input end of the output module 4 and is connected to the first output end of the second noise cancellation module 3 via the D1 node. The input end of the sixth current mirror 42 serves as the second input end of the output module 4 and is connected to the second output end of the second noise cancellation module 3 via the D2 node. In differential mode, the two differential-mode currents output by the second noise cancellation module 3 charge and discharge the D1 and D2 nodes.

[0062] The first output terminal of the fifth current mirror 41 is connected to the second output terminal of the sixth current mirror 42, and is connected to the first terminal of the latch L1 and the input terminal of the first inverter Inv1 through the F2 node. The second output terminal of the fifth current mirror 41 is connected to the first output terminal of the sixth current mirror 42, and is connected to the second terminal of the latch L1 and the input terminal of the second inverter Inv2 through the F1 node. When charging and discharging nodes D1 and D2 in the differential mode, the fifth current mirror 41 or the sixth current mirror 42 generates current, charges and discharges nodes F1 and F2, and triggers the latch L1.

[0063] The output end of the first inverter Inv1 is connected to the first output port, and the first inverter Inv1 is used to output a floating voltage source when the second inverter Inv2 does not output a floating ground. The output end of the second inverter Inv2 is connected to the second output port, and the second inverter Inv2 is used to output a floating ground when the first inverter Inv1 does not output a floating voltage source.

[0064] Optionally, continue with reference to Figure 2 The output of the first inverter Inv1 serves as the first output of the output module 4 and is connected to the first output port VOUT1. The output of the second inverter Inv2 serves as the second output of the output module 4 and is connected to the second output port VOUT2. In differential mode, nodes F1 and F2 are charged and discharged. After latch L1 is triggered, the first inverter Inv1 or the second inverter Inv2 is alternately turned on. When the first inverter Inv1 is turned on, the second inverter Inv2 is turned off, and the first inverter Inv1 outputs the floating voltage source VB. When the second inverter Inv2 is turned on, the first inverter Inv1 is turned off, and the second inverter Inv2 outputs the floating ground VS. This enables the output module 4 to alternately output the floating voltage source VB and the floating ground VS.

[0065] It is worth noting that in common-mode mode, the net common-mode current cannot pass through the second noise cancellation module 3 and enter the fifth current mirror 41 and the sixth current mirror 42. This means that it cannot charge or discharge nodes D1 and D2, and thus cannot trigger latch L1. The latch state of latch L1 remains unchanged, keeping the on / off states of the first inverter Inv1 and the second inverter Inv2 unchanged, and thus the output state. In other words, the net common-mode current cannot interfere with the output states of the first inverter Inv1 and the second inverter Inv2, thus ensuring the correct output of the output module 4.

[0066] In this embodiment, the output module includes a fifth current mirror, a sixth current mirror, a latch, a first inverter, and a second inverter. The fifth and sixth current mirrors receive the two differential-mode currents alternately output by the second noise cancellation module. Based on the differential-mode currents, they control the latching state of the latch, thereby alternating the on and off states of the first and second inverters. This ensures that the first and second inverters alternately output a floating voltage source and a floating ground when on, ensuring correct output from the output module in both differential and common-mode modes.

[0067] Figure 3 Another structural diagram of the level shift circuit provided in the embodiment of the present application is shown in FIG. Figure 3 As shown, the voltage conversion module 1 includes: a first laterally diffused metal oxide semiconductor field effect transistor LDMOS tube LDMOS1 and a second LDMOS tube LDMOS2.

[0068] Optionally, refer to Figure 3 Voltage conversion module 1 includes two laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOS), namely a first LDMOS 1 and a second LDMOS 2. Both LDMOS 1 and LDMOS 2 have high-voltage resistance. They are used for voltage domain conversion and generate two differential-mode currents.

[0069] The gate of the first LDMOS transistor LDMOS1 is connected to the first pulse signal, the drain of the first LDMOS transistor LDMOS1 is connected to the first input end of the first noise elimination module 2 and the first input end of the second noise elimination module 3, and the source of the first LDMOS transistor LDMOS1 and the source of the second LDMOS transistor LDMOS2 are both connected to the common ground.

[0070] Optionally, continue with reference to Figure 3The gate of the first LDMOS transistor LDMOS1 serves as the first input terminal of the voltage conversion module 1 and receives the first pulse signal Vre. The drain of the first LDMOS transistor LDMOS1 serves as the first output terminal of the voltage conversion module 1 and is connected to the first input terminal of the first noise elimination module 2 and the first input terminal of the second noise elimination module 3 via node A1. The source terminals of the first LDMOS transistor LDMOS1 and the second LDMOS transistor LDMOS2 both serve as the ground terminals of the voltage conversion module 1 and are connected to the common ground COM. The first LDMOS transistor LDMOS1 performs voltage domain conversion based on the first pulse signal Vre and generates a differential mode current.

[0071] The gate of the second LDMOS transistor LDMOS2 receives a second pulse signal in phase opposite to the first pulse signal, and the drain of the second LDMOS transistor LDMOS2 is connected to the second input end of the first noise elimination module 2 and the second input end of the second noise elimination module 3 .

[0072] Optionally, continue with reference to Figure 3 The gate of the second LDMOS transistor LDMOS2 serves as the second input terminal of the voltage conversion module 1, receiving a second pulse signal Vfe that is in phase with the first pulse signal. The drain of the second LDMOS transistor LDMOS2 serves as the second output terminal of the voltage conversion module 1 and is connected to the second input terminal of the first noise elimination module 2 and the second input terminal of the second noise elimination module 3 via node A2. The second LDMOS transistor LDMOS2 performs voltage domain conversion based on the second pulse signal Vfe and generates another differential mode current.

[0073] In differential mode, when the first LDMOS transistor LDMOS1 is turned on and the second LDMOS transistor LDMOS2 is turned off, the voltage at node A1 is pulled down to the floating ground VS. Alternatively, when the first LDMOS transistor LDMOS1 is turned off and the second LDMOS transistor LDMOS2 is turned on, the voltage at node A2 is pulled down to the floating ground VS. In common mode, when both the first LDMOS transistor LDMOS1 and the second LDMOS transistor LDMOS2 are turned off, the voltages at nodes A1 and A2 are pulled down to the floating ground VS.

[0074] The first LDMOS tube LDMOS1 has a first drain-source parasitic capacitor , the second LDMOS tube LDMOS2 has a second drain-source parasitic capacitance In the common mode of VS fast conversion, there is a first drain-source parasitic capacitance on the drain of the first LDMOS tube LDMOS1 and the drain of the second LDMOS tube LDMOS2. and the second drain-source parasitic capacitance The introduced first noise current Inoise1, the second noise current Inoise2 and the transient common-mode noise voltage.

[0075] Specifically, the first drain-source parasitic capacitance in the first LDMOS transistor LDMOS1 is The first noise current Inoise1 introduced and the second drain-source parasitic capacitance in the second LDMOS tube LDMOS2 The expression of the introduced second noise current Inoise2 is as follows:

[0076]

[0077] Among them, among them, is the first noise current, is the first drain-source parasitic capacitance, is the second noise current, is the second drain-source parasitic capacitance, is a floating voltage source and VS is a floating ground.

[0078] In this embodiment, a first LDMOS transistor and a second LDMOS transistor are provided in the voltage conversion module. Voltage domain conversion is performed by the first and second LDMOS transistors, and two differential-mode currents are alternately generated in differential-mode mode. Two noise currents are simultaneously generated in common-mode mode. The drains of the first and second LDMOS transistors are both connected to the first and second noise cancellation modules, so that the first and second noise cancellation modules correctly transmit the differential-mode currents and cancel the two noise currents.

[0079] As an optional implementation, the first current mirror 21 includes: a first P-channel metal oxide semiconductor field effect transistor PMOS tube PMOS1, a third PMOS tube PMOS3 and a fourth PMOS tube PMOS4; the second current mirror 22 includes: a second PMOS tube PMOS2, a fifth PMOS tube PMOS5 and a sixth PMOS tube PMOS6.

[0080] Optionally, continue with reference to Figure 3 The first current mirror 21 includes three P-channel metal oxide semiconductor field-effect transistors (MOS), namely a first PMOS transistor PMOS1, a third PMOS transistor PMOS3, and a fourth PMOS transistor PMOS4. The second current mirror 22 also includes three PMOS transistors, namely a second PMOS transistor PMOS2, a fifth PMOS transistor PMOS5, and a sixth PMOS transistor PMOS6.

[0081] The gate and drain of the first PMOS transistor PMOS1 are short-circuited and connected to the first output terminal of the voltage conversion module 1, the first input terminal of the second noise elimination module 3, the gate of the third PMOS transistor PMOS3, and the gate of the fourth PMOS transistor PMOS4. The source of the first PMOS transistor PMOS1 and the source of the second PMOS transistor PMOS2 are both connected to a floating voltage source.

[0082] Optionally, continue with reference to Figure 3 The gate and drain of the first PMOS transistor PMOS1 are short-circuited, and are connected to the gate of the third PMOS transistor PMOS3 and the gate of the fourth PMOS transistor PMOS4, and serve as the input end of the first current mirror 21 and the first input end of the first noise elimination module 2, and are connected to the first output end of the voltage conversion module 1 and the first input end of the second noise elimination module 3 through the A1 node.

[0083] The gate and drain of the second PMOS transistor PMOS2 are short-circuited and connected to the second output terminal of the voltage conversion module 1, the second input terminal of the second noise elimination module 3, the gate of the fifth PMOS transistor PMOS5 and the gate of the sixth PMOS transistor PMOS6.

[0084] Optionally, continue with reference to Figure 3 The gate and drain of the second PMOS transistor PMOS2 are short-circuited and connected to the gate of the fifth PMOS transistor PMOS5 and the gate of the sixth PMOS transistor PMOS6, and serve as the input end of the second current mirror 22 and the second input end of the first noise elimination module 2, and are connected to the second output end of the voltage conversion module 1 and the second input end of the second noise elimination module 3 through the A2 node.

[0085] The drain of the third PMOS transistor PMOS3 is connected to the input end of the third current mirror 23 and the third input end of the second noise elimination module 3, the drain of the fourth PMOS transistor PMOS4 is connected to the output end of the fourth current mirror 24 and the fifth input end of the second noise elimination module 3, the drain of the sixth PMOS transistor PMOS6 is connected to the first input end of the fourth current mirror 24 and the fourth input end of the second noise elimination module 3, and the drain of the fifth PMOS transistor PMOS5 is connected to the output end of the third current mirror 23 and the sixth input end of the second noise elimination module 3.

[0086] Optionally, continue with reference to Figure 3The drain of the third PMOS transistor PMOS3 serves as the first output terminal of the first current mirror 21 and the third output terminal of the first noise cancellation module 2, and is connected to the input terminal of the third current mirror 23 and the third input terminal of the second noise cancellation module 3 through node B1. The drain of the fourth PMOS transistor PMOS4 serves as the first output terminal of the second current mirror 22 and the fifth output terminal of the first noise cancellation module 2, and is connected to the first input terminal of the fourth current mirror 24 and the fourth input terminal of the second noise cancellation module 3 through node E1. The drain of the sixth PMOS transistor PMOS6 serves as the first output terminal of the second current mirror 22 and the fourth output terminal of the first noise cancellation module 2, and is connected to the first input terminal of the fourth current mirror 24 and the fifth input terminal of the second noise cancellation module 3 through node B2. The drain of the fifth PMOS transistor PMOS5 serves as the second output terminal of the first current mirror 21 and the fourth output terminal of the first noise cancellation module 2, and is connected to the output terminal of the third current mirror 23 and the sixth input terminal of the second noise cancellation module 3 through node E2.

[0087] The source of the third PMOS transistor PMOS3 , the source of the fourth PMOS transistor PMOS4 , the source of the fifth PMOS transistor PMOS5 , and the source of the sixth PMOS transistor PMOS6 are all connected to the floating voltage source.

[0088] Optionally, continue with reference to Figure 3 The source of the third PMOS transistor PMOS3, the source of the fourth PMOS transistor PMOS4, and the source of the fifth PMOS transistor PMOS5 all serve as the power supply end of the first current mirror 21 and the power supply end of the first noise elimination module 2, and are connected to the floating voltage source VB to obtain the bias voltage when the MOS transistors are turned on.

[0089] The first current mirror 21, which is composed of the first PMOS transistor PMOS1, the third PMOS transistor PMOS3, and the fourth PMOS transistor PMOS4, converts the transient common-mode noise voltage generated at the first output terminal of the connected voltage conversion module 1 into a first common-mode current Icom1. The first common-mode current Icom1 flows through the third PMOS transistor PMOS3 and the fourth PMOS transistor PMOS4. Specifically, the expression of the first common-mode current Icom1 flowing through the third PMOS transistor PMOS3 is as follows:

[0090] in, is the first common mode current, is the hole mobility of the third PMOS tube PMOS3, is the gate oxide capacitance of the third PMOS tube PMOS3, is the width-to-length ratio of the third PMOS tube PMOS3, is the gate-source voltage of the third PMOS tube PMOS3, is the threshold voltage of the third PMOS transistor PMOS3.

[0091] The second current mirror 22, which is composed of the second PMOS transistor PMOS2, the fifth PMOS transistor PMOS5, and the sixth PMOS transistor PMOS6, converts the transient common-mode noise voltage generated at the second output terminal of the connected voltage conversion module 1 into a second common-mode current Icom2. The second common-mode current Icom2 flows through the fifth PMOS transistor PMOS5 and the sixth PMOS transistor PMOS6. Specifically, the expression of the second common-mode current Icom2 flowing through the fifth PMOS transistor PMOS5 is as follows:

[0092] in, is the second common-mode current, is the hole mobility of the fifth PMOS transistor PMOS5, is the gate oxide capacitance of the fifth PMOS transistor PMOS5, is the width-to-length ratio of the fifth PMOS transistor PMOS5, is the gate-source voltage of the fifth PMOS transistor PMOS5, is the threshold voltage of the fifth PMOS transistor PMOS5.

[0093] In this embodiment, the first, third, and fourth PMOS transistors share a gate to form a first current mirror. The first current mirror converts the transient common-mode noise voltage generated at the first output terminal of the connected voltage conversion module into a first common-mode current. The second, fifth, and sixth PMOS transistors share a gate to form a second current mirror. The second current mirror converts the transient common-mode noise voltage generated at the second output terminal of the connected voltage conversion module into a second common-mode current. The first common-mode current flows through the third and fourth PMOS transistors and is transmitted to the third and fourth current mirrors, while the second common-mode current flows through the fifth and sixth PMOS transistors and is transmitted to the third and fourth current mirrors. This allows the third and fourth current mirrors to cancel cross-coupling between the two common-mode currents.

[0094] As an optional implementation, the third current mirror 23 includes: a first N-channel metal oxide semiconductor field effect transistor NMOS tube NMOS1, a second NMOS tube NMOS2, a third NMOS tube NMOS3 and a fourth NMOS tube NMOS4; the fourth current mirror 24 includes: a fifth NMOS tube NMOS5, a sixth NMOS tube NMOS6, a seventh NMOS tube NMOS7 and an eighth NMOS tube NMOS8.

[0095] Optionally, continue with reference to Figure 3 The third current mirror 23 includes four NMOS transistors, namely a first NMOS transistor NMOS1, a second NMOS transistor NMOS2, a third NMOS transistor NMOS3, and a fourth NMOS transistor NMOS4. The fourth current mirror 24 also includes four NMOS transistors, namely a fifth NMOS transistor NMOS5, a sixth NMOS transistor NMOS6, a seventh NMOS transistor NMOS7, and an eighth NMOS transistor NMOS8.

[0096] The gate and drain of the first NMOS transistor NMOS1 are short-circuited and connected to the gate of the second NMOS transistor NMOS2, the first output terminal of the first current mirror 21, and the third input terminal of the second noise elimination module 3. The source of the first NMOS transistor NMOS1 is connected to the drain of the third NMOS transistor NMOS3, the gate of the third NMOS transistor NMOS3, and the gate of the fourth NMOS transistor NMOS4.

[0097] Optionally, continue with reference to Figure 3 The gate and drain of the first NMOS transistor NMOS1 are short-circuited and connected to the gate of the second NMOS transistor NMOS2. The gate and drain serve as the input of the third current mirror 23 and are connected to the first output of the first current mirror 21 and the third input of the second noise elimination module 3 through the B1 node. The source of the first NMOS transistor NMOS1 is connected to the drain of the third NMOS transistor NMOS3, the gate of the third NMOS transistor NMOS3, and the gate of the fourth NMOS transistor NMOS4.

[0098] The drain of the second NMOS transistor NMOS2 is respectively connected to the second output terminal of the second current mirror 22 and the sixth input terminal of the second noise elimination module 3, the source of the second NMOS transistor NMOS2 is connected to the drain of the fourth NMOS transistor NMOS4, and the source of the third NMOS transistor NMOS3 and the source of the fourth NMOS transistor NMOS4 are both connected to the floating ground.

[0099] Optionally, continue with reference to Figure 3 The drain of the second NMOS transistor NMOS2 serves as the output terminal of the third current mirror 23 and the fourth output terminal of the first noise cancellation module 2, and is connected to the second output terminal of the second current mirror 22 and the sixth input terminal of the second noise cancellation module 3 through node E2. The source of the second NMOS transistor NMOS2 is connected to the drain of the fourth NMOS transistor NMOS4. The sources of the third NMOS transistor NMOS3 and the fourth NMOS transistor NMOS4 both serve as the reference ground terminal of the third current mirror 23 and are connected to the floating ground VS.

[0100] The gate and drain of the sixth NMOS transistor NMOS6 are short-circuited and connected to the gate of the fifth NMOS transistor NMOS5, the first output terminal of the second current mirror 22, and the fourth input terminal of the second noise elimination module 3. The source of the sixth NMOS transistor NMOS6 is connected to the drain of the eighth NMOS transistor NMOS8, the gate of the eighth NMOS transistor NMOS8, and the gate of the seventh NMOS transistor NMOS7.

[0101] Optionally, continue with reference to Figure 3 The gate and drain of the sixth NMOS transistor NMOS6 are short-circuited and connected to the gate of the fifth NMOS transistor NMOS5. The sixth NMOS transistor NMOS6 serves as the input of the fourth current mirror 24 and is connected to the first output of the second current mirror 22 and the fourth input of the second noise elimination module 3 through the B2 node. The source of the sixth NMOS transistor NMOS6 is connected to the drain of the eighth NMOS transistor NMOS8, the gate of the eighth NMOS transistor NMOS8, and the gate of the seventh NMOS transistor NMOS7.

[0102] The drain of the fifth NMOS transistor NMOS5 is respectively connected to the second output terminal of the first current mirror 21 and the fifth input terminal of the second noise elimination module 3, the source of the fifth NMOS transistor NMOS5 is connected to the drain of the seventh NMOS transistor NMOS7, and the source of the seventh NMOS transistor NMOS7 and the source of the eighth NMOS transistor NMOS8 are both connected to the floating ground.

[0103] Optionally, continue with reference to Figure 3 The drain of the fifth NMOS transistor NMOS5 serves as the output terminal of the fourth current mirror 24 and the third output terminal of the first noise cancellation module 2, and is connected to the second output terminal of the first current mirror 21 and the fifth input terminal of the second noise cancellation module 3 through the E1 node, respectively. The source of the fifth NMOS transistor NMOS5 is connected to the drain of the seventh NMOS transistor NMOS7. The source of the seventh NMOS transistor NMOS7 and the source of the eighth NMOS transistor NMOS8 both serve as the reference ground terminal of the fourth current mirror 24 and are connected to the floating ground VS.

[0104] The third current mirror 23 composed of the first NMOS transistor NMOS1, the second NMOS transistor NMOS2, the third NMOS transistor NMOS3 and the fourth NMOS transistor NMOS4 is used to control the first common mode current output by the first current mirror 21. Copy and get the common mode current of the first channel Equal third common-mode current ,Right now In order to accurately replicate the current and ensure the current proportional relationship, the width-to-length ratio relationship between the first NMOS transistor NMOS1, the second NMOS transistor NMOS2, the third NMOS transistor NMOS3 and the fourth NMOS transistor NMOS4 is as follows:

[0105] in, is the width-to-length ratio of the first NMOS tube NMOS1, is the width-to-length ratio of the second NMOS transistor NMOS2, is the width-to-length ratio of the third NMOS transistor NMOS3, is the width-to-length ratio of the fourth NMOS transistor NMOS4.

[0106] Accordingly, the fourth current mirror 24 composed of the fifth NMOS transistor NMOS5, the sixth NMOS transistor NMOS6, the seventh NMOS transistor NMOS7 and the eighth NMOS transistor NMOS8 controls the second common-mode current output by the second current mirror 22. Copy and get the common mode current of the second channel Equal fourth common-mode current ,Right now In order to accurately replicate the current and ensure the current proportional relationship, the width-to-length ratio relationship between the fifth NMOS transistor NMOS5, the sixth NMOS transistor NMOS6, the seventh NMOS transistor NMOS7 and the eighth NMOS transistor NMOS8 is as follows:

[0107] in, is the width-to-length ratio of the fifth NMOS transistor NMOS5, is the width-to-length ratio of the sixth NMOS transistor NMOS6, is the width-to-length ratio of the seventh NMOS transistor NMOS7, is the width-to-length ratio of the eighth NMOS transistor NMOS8.

[0108] The third current mirror 23 and the fourth current mirror 24 are both cascode current mirrors. And the fourth common mode circuit Cross-coupling is performed to cancel out the two common-mode currents.

[0109] In this embodiment, the first, second, third, and fourth NMOS transistors form a third cascode current mirror, which replicates the first common-mode current output by the first current mirror. The fifth, sixth, seventh, and eighth NMOS transistors form a fourth cascode current mirror, which replicates the second common-mode current output by the second current mirror. The third and fourth current mirrors cross-couple the two common-mode circuits, causing them to cancel each other out and output a net common-mode current to the second noise cancellation module.

[0110] As an optional implementation, the first transmission gate TG1 includes: a fifteenth PMOS transistor PMOS15 and a seventeenth NMOS transistor NMOS17 ; the second transmission gate TG2 includes: a sixteenth PMOS transistor PMOS16 and an eighteenth NMOS transistor NMOS18 .

[0111] Optionally, continue with reference to Figure 3 The first transmission gate TG1 includes a PMOS transistor and an NMOS transistor, namely the fifteenth PMOS transistor PMOS15 and the seventeenth NMOS transistor NMOS17. The second transmission gate TG2 also includes a PMOS transistor and an NMOS transistor, namely the sixteenth PMOS transistor PMOS16 and the eighteenth NMOS transistor NMOS18.

[0112] The gate of the fifteenth PMOS transistor PMOS15 is connected to the first output terminal of the first noise elimination module 2, the drain of the fifteenth PMOS transistor PMOS15 is connected to the drain of the seventeenth NMOS transistor NMOS17 and the third output terminal of the first noise elimination module 2, the source of the fifteenth PMOS transistor PMOS15 and the source of the seventeenth NMOS transistor NMOS17 are both connected to the first input terminal of the output module 4, and the gate of the seventeenth NMOS transistor NMOS17 is connected to the second output terminal of the voltage conversion module 1 and the second input terminal of the first noise elimination module 2.

[0113] Optionally, continue with reference to Figure 3The gate of the fifteenth PMOS transistor PMOS15 serves as the second input of the first transmission gate TG1 and the third input of the second noise cancellation module 3, and is connected to the first output of the first noise cancellation module 2 via the B1 node. The drain of the fifteenth PMOS transistor PMOS15 and the drain of the seventeenth NMOS transistor NMOS17 both serve as the third input of the first transmission gate TG1 and the fifth input of the second noise cancellation module 3, and are connected to the third output of the first noise cancellation module 2 via the E1 node. The source of the fifteenth PMOS transistor PMOS15 and the source of the seventeenth NMOS transistor NMOS17 both serve as the output of the first transmission gate TG1 and the first output of the second noise cancellation module 3, and are connected to the first input of the output module 4 via the D1 node. The gate of the seventeenth NMOS transistor NMOS17 serves as the first input of the first transmission gate TG1 and the second input of the second noise cancellation module 3, and is connected to the second output of the voltage conversion module 1 and the second input of the first noise cancellation module 2 via the A2 node.

[0114] The gate of the sixteenth PMOS transistor PMOS16 is connected to the second output terminal of the first noise elimination module 2, the drain of the sixteenth PMOS transistor PMOS16 is connected to the drain of the eighteenth NMOS transistor NMOS18 and the fourth output terminal of the first noise elimination module 2, the source of the sixteenth PMOS transistor PMOS16 and the source of the eighteenth NMOS transistor NMOS18 are both connected to the second input terminal of the output module 4, and the gate of the eighteenth NMOS transistor NMOS18 is connected to the first output terminal of the voltage conversion module 1 and the first input terminal of the first noise elimination module 2.

[0115] Optionally, continue with reference to Figure 3 The gate of the sixteenth PMOS transistor PMOS16 serves as the second input of the second transmission gate TG2 and the fourth input of the second noise cancellation module 3, and is connected to the second output of the first noise cancellation module 2 via the B2 node. The drain of the sixteenth PMOS transistor PMOS16 and the drain of the eighteenth NMOS transistor NMOS18 both serve as the third input of the second transmission gate TG2 and the sixth input of the second noise cancellation module 3, and are connected to the fourth output of the first noise cancellation module 2 via the E2 node. The source of the sixteenth PMOS transistor PMOS16 and the source of the eighteenth NMOS transistor NMOS18 both serve as the output of the second transmission gate TG2 and the second output of the second noise cancellation module 3, and are connected to the second input of the output module 4 via the D2 node. The gate of the eighteenth NMOS transistor NMOS18 serves as the first input of the second transmission gate TG2 and the first input of the second noise cancellation module 3, and is connected to the first output of the voltage conversion module 1 and the first input of the first noise cancellation module 2 via the A1 node.

[0116] Based on the above connection relationship, in differential mode, the voltage at either node A1 or node A2 is always at the floating voltage source VB, and the voltage at either node B1 or node B2 is always at the floating ground VS. This ensures that one of the first transmission gate TG1 and the second transmission gate TG2 is always in the on state, allowing one of the two differential-mode currents to enter the output module 4 through the on transmission gate. In common mode, the voltages at both nodes A1 and A2 are at the floating ground V, and the voltages at both nodes B1 and B2 are at the floating voltage source VB. This ensures that both the first transmission gate TG1 and the second transmission gate TG2 are in the off state, preventing common-mode static current from entering the output module 4 through the first transmission gate TG1 and the second transmission gate TG2.

[0117] In this embodiment, the fifteenth PMOS transistor and the seventeenth NMOS transistor form a first transmission gate, and the sixteenth PMOS transistor and the eighteenth NMOS transistor form a second transmission gate. In differential mode, the first and second transmission gates alternately conduct, transmitting a differential-mode current through the conducting transmission gates to the output module. In common mode, both the first and second transmission gates are disconnected, blocking the net common-mode current from entering the output module. This ensures the transmission of differential-mode current while suppressing the transmission of common-mode current.

[0118] As an optional implementation, the fifth current mirror 41 includes: a seventh PMOS tube PMOS7, an eighth PMOS tube PMOS8, a ninth NMOS tube NMOS9 and a tenth NMOS tube NMOS10; the sixth current mirror 42 includes: a ninth PMOS tube PMOS9, a tenth PMOS tube PMOS10, an eleventh NMOS tube NMOS11 and a twelfth NMOS tube NMOS12.

[0119] Optionally, continue with reference to Figure 3 The fifth current mirror 41 includes two PMOS transistors and two NMOS transistors, namely, a seventh PMOS transistor PMOS7, an eighth PMOS transistor PMOS8, a ninth NMOS transistor NMOS9, and a tenth NMOS transistor NMOS10. The sixth current mirror 42 also includes two PMOS transistors and two NMOS transistors, namely, a ninth PMOS transistor PMOS9, a tenth PMOS transistor PMOS10, an eleventh NMOS transistor NMOS11, and a twelfth NMOS transistor NMOS12.

[0120] The gate and drain of the seventh PMOS transistor PMOS7 are short-circuited and connected to the gate of the eighth PMOS transistor PMOS8 and the drain of the ninth NMOS transistor NMOS9. The source of the seventh PMOS transistor PMOS7 and the source of the eighth PMOS transistor PMOS8 are both connected to a floating voltage source. The drain of the eighth PMOS transistor PMOS8 is respectively connected to the drain of the eleventh NMOS transistor NMOS11, the first end of the latch L1, and the input end of the first inverter Inv1.

[0121] Optionally, continue with reference to Figure 3 The gate and drain of the seventh PMOS transistor PMOS7 are short-circuited and connected to the gate of the eighth PMOS transistor PMOS8 and the drain of the ninth NMOS transistor NMOS9, respectively. The source of the seventh PMOS transistor PMOS7 and the source of the eighth PMOS transistor PMOS8 are both connected to the floating voltage source VB as the power supply terminal of the fifth current mirror 41. The drain of the eighth PMOS transistor PMOS8 serves as the first output terminal of the fifth current mirror 41 and is connected to the drain of the eleventh NMOS transistor NMOS11. Furthermore, the drain of the eighth PMOS transistor PMOS8 is connected to the first terminal of the latch L1 and the input terminal of the first inverter Inv1 via the F2 node, thereby charging and discharging the F2 node in differential mode.

[0122] The gate of the ninth NMOS transistor NMOS9 is respectively connected to the first output terminal of the second noise elimination module 3 and the gate of the tenth NMOS transistor NMOS10, the source of the ninth NMOS transistor NMOS9 and the source of the tenth NMOS transistor NMOS10 are both connected to the floating ground, and the drain of the tenth NMOS transistor NMOS10 is respectively connected to the drain of the ninth PMOS transistor PMOS9, the second end of the latch L1, and the input end of the second inverter Inv2.

[0123] Optionally, continue with reference to Figure 3 The gate of the ninth NMOS transistor NMOS9 is connected to the gate of the tenth NMOS transistor NMOS10, serving as the input of the fifth current mirror 41 and the first input of the output module 4. The gate is connected to the first output of the second noise cancellation module 3 via the D1 node. The source of the ninth NMOS transistor NMOS9 and the source of the tenth NMOS transistor NMOS10 both serve as the reference ground of the fifth current mirror 41 and are connected to the floating ground VS. The drain of the tenth NMOS transistor NMOS10 serves as the second output of the fifth current mirror 41 and is connected to the drain of the ninth PMOS transistor PMOS9. The drain is also connected to the second terminal of the latch L1 and the input of the second inverter Inv2 via the F1 node, thereby charging and discharging the F1 node in differential mode.

[0124] The gate and drain of the tenth PMOS transistor PMOS10 are short-circuited and connected to the gate of the ninth PMOS transistor PMOS9 and the drain of the twelfth NMOS transistor NMOS12. The source of the tenth PMOS transistor PMOS10 and the source of the ninth PMOS transistor PMOS9 are both connected to the floating voltage source.

[0125] Optionally, continue with reference to Figure 3 The gate and drain of the tenth PMOS transistor PMOS10 are short-circuited and connected to the gate of the ninth PMOS transistor PMOS9 and the drain of the twelfth NMOS transistor NMOS12, respectively. The source of the tenth PMOS transistor PMOS10 and the source of the ninth PMOS transistor PMOS9 are both connected to the floating voltage source VB as the power supply terminal of the sixth current mirror 42. The drain of the ninth PMOS transistor PMOS9 serves as the first output terminal of the sixth current mirror 42 and is connected to the drain of the tenth NMOS transistor NMOS10. Furthermore, the drain of the ninth PMOS transistor PMOS9 is connected to the second terminal of the latch L1 and the input terminal of the second inverter Inv2 via the F1 node, thereby charging and discharging the F1 node in differential mode.

[0126] The gate of the twelfth NMOS transistor NMOS12 is connected to the second output terminal of the second noise elimination module 3 and the gate of the eleventh NMOS transistor NMOS11 respectively. The source of the eleventh NMOS transistor NMOS11 and the source of the twelfth NMOS transistor NMOS12 are both connected to the floating ground.

[0127] Optionally, continue with reference to Figure 3 The gate of the twelfth NMOS transistor NMOS12 is connected to the gate of the eleventh NMOS transistor NMOS11, serving as the input of the sixth current mirror 42 and the second input of the output module 4. It is connected to the second output of the second noise cancellation module 3 via the D2 node. The source of the eleventh NMOS transistor NMOS11 and the source of the twelfth NMOS transistor NMOS12 both serve as the reference ground of the sixth current mirror 42 and are connected to the floating ground VS. The drain of the eleventh NMOS transistor NMOS11 serves as the second output of the sixth current mirror 42 and is connected to the drain of the eighth PMOS transistor PMOS8. It is also connected to the first terminal of the latch L1 and the input of the first inverter Inv1 via the F2 node, thereby charging and discharging the F2 node in a differential mode.

[0128] Among them, in the differential mode mode, the two differential mode currents alternately output by the second noise elimination module 3 charge and discharge the D1 node and the D2 node, thereby generating a drain current in the tenth NMOS tube NM10 or the eleventh NMOS tube NM11, so that the nodes F1 and F2 are charged and discharged through the tenth NMOS tube NM10 or the eleventh NMOS tube NM11, thereby triggering the latch L1.

[0129] In this embodiment, in the differential mode, the fifth current mirror composed of the seventh PMOS transistor PMOS7, the eighth PMOS transistor PMOS8, the ninth NMOS transistor NMOS9 and the tenth NMOS transistor NMOS10, and the sixth current mirror composed of the ninth PMOS transistor PMOS9, the tenth PMOS transistor PMOS10, the eleventh NMOS transistor NMOS11 and the twelfth NMOS transistor NMOS12 generate two source currents and charge and discharge the two ends of the latch to trigger the latch, thereby causing the two inverters to alternately turn on and output voltages alternately.

[0130] As an optional implementation, the latch L1 includes: an eleventh PMOS tube PMOS11, a twelfth PMOS tube PMOS12, a thirteenth NMOS tube NMOS13 and a fourteenth NMOS tube NMOS14; the first inverter Inv1 includes: a thirteenth PMOS tube PMOS13 and a fifteenth NMOS tube NMOS15; the second inverter Inv2 includes: a fourteenth PMOS tube PMOS14 and a sixteenth NMOS tube NMOS16.

[0131] Optionally, continue with reference to Figure 3 The latch L1 includes two PMOS transistors and two NMOS transistors, namely the eleventh PMOS transistor PMOS11, the twelfth PMOS transistor PMOS12, the thirteenth NMOS transistor NMOS13, and the fourteenth NMOS transistor NMOS14. The first inverter Inv1 includes one PMOS transistor and one NMOS transistor, namely the thirteenth PMOS transistor PMOS13 and the fifteenth NMOS transistor NMOS15. The second inverter Inv2 includes one PMOS transistor and one NMOS transistor, namely the fourteenth PMOS transistor PMOS14 and the sixteenth NMOS transistor NMOS16.

[0132] The first inverter Inv1 and the second inverter Inv2 are both inverse logic, that is, the logic function of the inverter does not depend on the proportional relationship of the width-to-length ratio of the two MOS tubes. As long as the two MOS tubes can be turned on and off normally, the inverse logic function can be achieved.

[0133] The gate of the eleventh PMOS transistor PMOS11 is respectively connected to the gate of the thirteenth NMOS transistor NMOS13, the drain of the twelfth PMOS transistor PMOS12, the drain of the fourteenth NMOS transistor NMOS14, the second output end of the fifth current mirror 41, the gate of the fourteenth PMOS transistor PMOS14, and the gate of the sixteenth NMOS transistor NMOS16. The drain of the eleventh PMOS transistor PMOS11 is respectively connected to the drain of the thirteenth NMOS transistor NMOS13, the gate of the twelfth PMOS transistor PMOS12, the gate of the fourteenth NMOS transistor NMOS14, the second output end of the sixth current mirror 42, the gate of the thirteenth PMOS transistor MOS13, and the gate of the fifteenth NMOS transistor NMOS15.

[0134] Optionally, continue with reference to Figure 3 The gate of the eleventh PMOS transistor PMOS11 serves as the second terminal of the latch L1 and the input terminal of the second inverter Inv2, and is respectively connected to the gate of the thirteenth NMOS transistor NMOS13, the drain of the twelfth PMOS transistor PMOS12, the drain of the fourteenth NMOS transistor NMOS14, the second output terminal of the fifth current mirror 41, the gate of the fourteenth PMOS transistor PMOS14, and the gate of the sixteenth NMOS transistor NMOS16 through the F1 node. The drain of the eleventh PMOS transistor PMOS11 is respectively connected to the drain of the thirteenth NMOS transistor NMOS13, the gate of the twelfth PMOS transistor PMOS12, the gate of the fourteenth NMOS transistor NMOS14, the second output terminal of the sixth current mirror 42, the gate of the thirteenth PMOS transistor MOS13, and the gate of the fifteenth NMOS transistor NMOS15.

[0135] The source of the eleventh PMOS transistor PMOS11, the source of the twelfth PMOS transistor PMOS12, the source of the thirteenth PMOS transistor PMOS13, and the source of the fourteenth PMOS transistor PMOS14 are all connected to the floating voltage source; the source of the thirteenth NMOS transistor NMOS13, the source of the fourteenth NMOS transistor NMOS14, the source of the fifteenth NMOS transistor NMOS15, and the source of the sixteenth NMOS transistor NMOS16 are all connected to the floating ground.

[0136] Optionally, continue with reference to Figure 3The source of the eleventh PMOS transistor PMOS11 and the source of the twelfth PMOS transistor PMOS12 both serve as the power supply terminal of the latch L1 and are connected to the floating voltage source VB. The source of the thirteenth NMOS transistor NMOS13 and the source of the fourteenth NMOS transistor NMOS14 both serve as the reference ground terminal of the latch L1 and are connected to the floating ground VS. The source of the thirteenth PMOS transistor PMOS13 serves as the power supply terminal of the first inverter Inv1 and is connected to the floating voltage source VB. The source of the fifteenth NMOS transistor NMOS15 serves as the reference ground terminal of the first inverter Inv1 and is connected to the floating ground VS. The source of the fourteenth PMOS transistor PMOS14 serves as the power supply terminal of the second inverter Inv2 and is connected to the floating voltage source VB. The source of the sixteenth NMOS transistor NMOS16 serves as the reference ground terminal of the second inverter Inv2 and is connected to the floating ground VS.

[0137] The drain of the thirteenth PMOS transistor PMOS13 is connected to the drain of the fifteenth NMOS transistor NMOS15 and the first output port respectively. The drain of the fourteenth PMOS transistor PMOS14 is connected to the drain of the sixteenth NMOS transistor NMOS16 and the second output port respectively.

[0138] Optionally, continue with reference to Figure 3 The drain of the thirteenth PMOS transistor PMOS13 is connected to the drain of the fifteenth NMOS transistor NMOS15, and serves as the output terminal of the first inverter Inv1 and the first output terminal of the output module 4, and is connected to the first output port VOUT1. The drain of the fourteenth PMOS transistor PMOS14 is connected to the drain of the sixteenth NMOS transistor NMOS16, and serves as the output terminal of the second inverter Inv2 and the second output terminal of the output module 4, and is connected to the second output port VOUT2.

[0139] In the differential mode, the drain current outputted from the second output terminal of the fifth current mirror 41 charges the F1 node, causing the voltage of the F1 node to exceed the threshold voltage of the latch L1. The feedback effect of the latch L1 accelerates F1 to the floating voltage source VB and accelerates F2 to the floating ground VS, triggering the latch, thereby turning on the second inverter Inv2 and outputting the floating ground VS through the second output port VOUT2, and turning on the first inverter Inv1 and outputting the floating voltage source VB through the first output port VOUT1.

[0140] Alternatively, the drain current output from the second output terminal of the sixth current mirror 42 charges the F2 node, causing the voltage of the F2 node to exceed the threshold voltage of the latch L1. The feedback effect of the latch L1 accelerates F2 to the floating voltage source VB and accelerates F1 to the floating ground VS, triggering the latch, thereby turning on the second inverter Inv2 and outputting the floating voltage source VB through the second output port VOUT2, and turning on the first inverter Inv1 and outputting the floating ground VS through the first output port VOUT1.

[0141] In this embodiment, a latch composed of the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth NMOS transistor, and the fourteenth NMOS transistor performs feedback based on the source current alternately output by the fifth current mirror or the sixth current mirror to control the alternating on-off states of a first inverter composed of the thirteenth PMOS transistor and the fifteenth NMOS transistor and a second inverter composed of the fourteenth PMOS transistor and the sixteenth NMOS transistor, so that the first inverter and the second inverter alternately output a floating voltage source and a floating ground when they are turned on.

[0142] Continue to refer to Figure 3 The level shift circuit further includes: a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first diode D1 and a second diode D2.

[0143] A first end of the first resistor R1, a first end of the second resistor R2, a first end of the first capacitor C1, a first end of the second capacitor C2, an anode of the first diode D1, and an anode of the second diode D2 are all connected to a floating voltage source. The other end of the first resistor R1, the other end of the first capacitor C1, and the cathode of the first diode D1 are all connected to the drain of the first LDMOS transistor LDMOS1, the drain of the first PMOS transistor PMOS1, and the gate of the eighteenth NMOS transistor NM18.

[0144] The other end of the second resistor R2 , the other end of the second capacitor C2 and the cathode of the second diode D2 are connected to the drain of the second LDMOS transistor LDMOS2 , the drain of the second PMOS transistor PMOS2 and the gate of the seventeenth NMOS transistor NM17 .

[0145] Among them, continue to refer to Figure 3The first resistor R1 and the second resistor R2 are used to quickly reset the voltages at nodes A1 and A2 to the floating voltage source VB, allowing the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 to quickly turn on. The first diode D1 and the second diode D2 are both voltage clamping diodes. When the first diode D1 and the second diode D2 turn on, they provide a clamping hysteresis to generate a clamping voltage to prevent breakdown of the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2. The first capacitor C1 provides a discharge path to the floating voltage source VB when the first LDMOS transistor LDMOS1 turns on. The second capacitor C2 provides a discharge path to the floating voltage source VB when the second LDMOS transistor LDMOS2 turns on.

[0146] The above is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the protection scope of the present application.

Claims

1. A level shift circuit, characterized in that: include: A voltage conversion module, a first noise elimination module, a second noise elimination module, and an output module; A first input terminal of the voltage conversion module is connected to a first pulse signal, a second input terminal of the voltage conversion module is connected to a second pulse signal that is in phase with the first pulse signal, a first output terminal of the voltage conversion module is connected to a first input terminal of the first noise elimination module and a first input terminal of the second noise elimination module, and a second output terminal of the voltage conversion module is connected to a second input terminal of the first noise elimination module and a second input terminal of the second noise elimination module; The first output terminal of the first noise cancellation module is connected to the third input terminal of the second noise cancellation module, the second output terminal of the first noise cancellation module is connected to the fourth input terminal of the second noise cancellation module, the third output terminal of the first noise cancellation module is connected to the fifth input terminal of the second noise cancellation module, and the fourth output terminal of the first noise cancellation module is connected to the sixth input terminal of the second noise cancellation module; The first output terminal of the second noise elimination module is connected to the first input terminal of the output module, and the second output terminal of the second noise elimination module is connected to the second input terminal of the output module; the first output terminal and the second output terminal of the output module are used to alternately output a floating voltage source and a floating ground; The first noise elimination module is used to eliminate the common-mode current generated by the voltage conversion module through cross-coupling, and the second noise elimination module is used to suppress the common-mode net current from the first noise elimination module.

2. The level shift circuit according to claim 1, wherein: The first noise elimination module includes: a first current mirror, a second current mirror, a third current mirror and a fourth current mirror; An input end of the first current mirror is connected to a first output end of the voltage conversion module and a first input end of the second noise elimination module, a first output end of the first current mirror is connected to an input end of the third current mirror and a third input end of the second noise elimination module, and a second output end of the first current mirror is connected to an output end of the fourth current mirror and a fifth input end of the second noise elimination module; The input end of the second current mirror is connected to the second output end of the voltage conversion module and the second input end of the second noise elimination module, the first output end of the second current mirror is connected to the first input end of the fourth current mirror and the fourth input end of the second noise elimination module, and the second output end of the second current mirror is connected to the output end of the third current mirror and the sixth input end of the second noise elimination module.

3. The level shift circuit according to claim 1, wherein: The second noise elimination module includes: a first transmission gate and a second transmission gate; The first input terminal of the first transmission gate is connected to the second output terminal of the voltage conversion module and the second input terminal of the first noise elimination module, the second input terminal of the first transmission gate is connected to the first output terminal of the first noise elimination module, the third input terminal of the first transmission gate is connected to the third output terminal of the first noise elimination module, and the output terminal of the first transmission gate is connected to the first input terminal of the output module; A first input terminal of the second transmission gate is connected to the first output terminal of the voltage conversion module and the first input terminal of the first noise elimination module, a second input terminal of the second transmission gate is connected to the second output terminal of the first noise elimination module, a third input terminal of the second transmission gate is connected to the fourth output terminal of the first noise elimination module, and an output terminal of the second transmission gate is connected to the second output terminal of the output module.

4. The level shift circuit according to claim 1, wherein: The output module includes: a fifth current mirror, a sixth current mirror, a latch, a first inverter and a second inverter; an input end of the fifth current mirror connected to the first output end of the second noise elimination module, a first output end of the fifth current mirror connected to the second output end of the sixth current mirror, the first end of the latch, and the input end of the first inverter, and a second output end of the fifth current mirror connected to the first output end of the sixth current mirror, the second end of the latch, and the input end of the second inverter; The input end of the sixth current mirror is connected to the second output end of the second noise elimination module; The output end of the first inverter is connected to the first output port, and the first inverter is used to output the floating voltage source when the second inverter does not output the floating ground. The output end of the second inverter is connected to the second output port, and the second inverter is used to output the floating ground when the first inverter does not output the floating voltage source.

5. The level shift circuit according to claim 1, wherein: The voltage conversion module includes: a first laterally diffused metal oxide semiconductor field effect transistor (LDMOS) tube and a second LDMOS tube; The gate of the first LDMOS transistor is connected to the first pulse signal, the drain of the first LDMOS transistor is connected to the first input terminal of the first noise elimination module and the first input terminal of the second noise elimination module, and the source of the first LDMOS transistor and the source of the second LDMOS transistor are both connected to a common ground; The gate of the second LDMOS transistor is connected to the second pulse signal that is in phase opposite to the first pulse signal, and the drain of the second LDMOS transistor is connected to the second input end of the first noise elimination module and the second input end of the second noise elimination module.

6. The level shift circuit according to claim 2, wherein: The first current mirror includes: a first P-channel metal oxide semiconductor field effect transistor (PMOS), a third PMOS, and a fourth PMOS; the second current mirror includes: a second PMOS, a fifth PMOS, and a sixth PMOS. The gate and drain of the first PMOS transistor are short-circuited and connected to the first output terminal of the voltage conversion module, the first input terminal of the second noise elimination module, the gate of the third PMOS transistor, and the gate of the fourth PMOS transistor. The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the floating voltage source. The gate and drain of the second PMOS transistor are short-circuited and connected to the second output terminal of the voltage conversion module, the second input terminal of the second noise elimination module, the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor; The drain of the third PMOS transistor is connected to the input end of the third current mirror and the third input end of the second noise elimination module, the drain of the fourth PMOS transistor is connected to the output end of the fourth current mirror and the fifth input end of the second noise elimination module, the drain of the sixth PMOS transistor is connected to the first input end of the fourth current mirror and the fourth input end of the second noise elimination module, and the drain of the fifth PMOS transistor is connected to the output end of the third current mirror and the sixth input end of the second noise elimination module; The source of the third PMOS transistor, the source of the fourth PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor are all connected to the floating voltage source.

7. The level shift circuit according to claim 2, wherein: The third current mirror includes: a first N-channel metal oxide semiconductor field effect transistor (NMOS), a second NMOS, a third NMOS, and a fourth NMOS; the fourth current mirror includes: a fifth NMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS. The gate and drain of the first NMOS transistor are short-circuited and connected to the gate of the second NMOS transistor, the first output terminal of the first current mirror, and the third input terminal of the second noise elimination module; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor, and the gate of the fourth NMOS transistor; The drain of the second NMOS transistor is connected to the second output terminal of the second current mirror and the sixth input terminal of the second noise elimination module respectively, the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the third NMOS transistor and the source of the fourth NMOS transistor are both connected to the floating ground; The gate and drain of the sixth NMOS transistor are short-circuited and connected to the gate of the fifth NMOS transistor, the first output terminal of the second current mirror, and the fourth input terminal of the second noise elimination module; the source of the sixth NMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor, and the gate of the seventh NMOS transistor; The drain of the fifth NMOS tube is respectively connected to the second output end of the first current mirror and the fifth input end of the second noise elimination module, the source of the fifth NMOS tube is connected to the drain of the seventh NMOS tube, and the source of the seventh NMOS tube and the source of the eighth NMOS tube are both connected to the floating ground.

8. The level shift circuit according to claim 3, wherein: The first transmission gate includes: a fifteenth PMOS transistor and a seventeenth NMOS transistor; the second transmission gate includes: a sixteenth PMOS transistor and an eighteenth NMOS transistor; The gate of the fifteenth PMOS transistor is connected to the first output terminal of the first noise elimination module, the drain of the fifteenth PMOS transistor is connected to the drain of the seventeenth NMOS transistor and the third output terminal of the first noise elimination module, the source of the fifteenth PMOS transistor and the source of the seventeenth NMOS transistor are both connected to the first input terminal of the output module, and the gate of the seventeenth NMOS transistor is connected to the second output terminal of the voltage conversion module and the second input terminal of the first noise elimination module; The gate of the sixteenth PMOS transistor is connected to the second output terminal of the first noise elimination module, the drain of the sixteenth PMOS transistor is connected to the drain of the eighteenth NMOS transistor and the fourth output terminal of the first noise elimination module, the source of the sixteenth PMOS transistor and the source of the eighteenth NMOS transistor are both connected to the second input terminal of the output module, and the gate of the eighteenth NMOS transistor is connected to the first output terminal of the voltage conversion module and the first input terminal of the first noise elimination module.

9. The level shift circuit according to claim 4, wherein: The fifth current mirror includes: a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; the sixth current mirror includes: a ninth PMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; The gate and drain of the seventh PMOS transistor are short-circuited and connected to the gate of the eighth PMOS transistor and the drain of the ninth NMOS transistor. The source of the seventh PMOS transistor and the source of the eighth PMOS transistor are both connected to the floating voltage source. The drain of the eighth PMOS transistor is respectively connected to the drain of the eleventh NMOS transistor, the first end of the latch, and the input end of the first inverter. The gate of the ninth NMOS transistor is connected to the first output terminal of the second noise elimination module and the gate of the tenth NMOS transistor respectively, the source of the ninth NMOS transistor and the source of the tenth NMOS transistor are both connected to the floating ground, and the drain of the tenth NMOS transistor is connected to the drain of the ninth PMOS transistor, the second terminal of the latch, and the input terminal of the second inverter respectively; The gate and drain of the tenth PMOS transistor are short-circuited and connected to the gate of the ninth PMOS transistor and the drain of the twelfth NMOS transistor. The source of the tenth PMOS transistor and the source of the ninth PMOS transistor are both connected to the floating voltage source. The gate of the twelfth NMOS transistor is connected to the second output end of the second noise elimination module and the gate of the eleventh NMOS transistor respectively, and the source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are both connected to the floating ground.

10. The level shift circuit according to claim 4, wherein: The latch includes: an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor; the first inverter includes: a thirteenth PMOS transistor and a fifteenth NMOS transistor; the second inverter includes: a fourteenth PMOS transistor and a sixteenth NMOS transistor; The gate of the eleventh PMOS transistor is respectively connected to the gate of the thirteenth NMOS transistor, the drain of the twelfth PMOS transistor, the drain of the fourteenth NMOS transistor, the second output terminal of the fifth current mirror, the gate of the fourteenth PMOS transistor, and the gate of the sixteenth NMOS transistor; the drain of the eleventh PMOS transistor is respectively connected to the drain of the thirteenth NMOS transistor, the gate of the twelfth PMOS transistor, the gate of the fourteenth NMOS transistor, the second output terminal of the sixth current mirror, the gate of the thirteenth PMOS transistor, and the gate of the fifteenth NMOS transistor; The source of the eleventh PMOS transistor, the source of the twelfth PMOS transistor, the source of the thirteenth PMOS transistor, and the source of the fourteenth PMOS transistor are all connected to the floating voltage source; the source of the thirteenth NMOS transistor, the source of the fourteenth NMOS transistor, the source of the fifteenth NMOS transistor, and the source of the sixteenth NMOS transistor are all connected to the floating ground; The drain of the thirteenth PMOS tube is connected to the drain of the fifteenth NMOS tube and the first output port respectively, and the drain of the fourteenth PMOS tube is connected to the drain of the sixteenth NMOS tube and the second output port respectively.

Images