Amplifier, ADC and electronic equipment

Abstract

The invention provides an amplifier, an ADC and electronic equipment. The amplifier comprises a first transistor, a second transistor, a third transistor and a feedback circuit, the first transistor and the second transistor form a differential pair transistor, the differential pair transistor is used for receiving and amplifying input voltage, and a source electrode of the first transistor is connected with a source electrode of the second transistor and is connected to a drain electrode of the third transistor; the source electrode of the third transistor is used for receiving power voltage or grounding; the feedback circuit is used for controlling the substrate voltage of the first transistor and the substrate voltage of the second transistor according to the reference voltage and the voltage of the drain electrode of the third transistor. According to the application, the signal output swing of the amplifier can be improved while the feedback coefficient and the gain of the amplifier in closed-loop use are kept basically unchanged.

Description

Technical Field

[0001] The present application relates to the field of analog-to-digital conversion technology, and in particular to an amplifier, an ADC, and an electronic device. Background Art

[0002] Analog-to-digital converters (ADCs) are commonly used in industrial production and everyday life. They convert analog signals such as temperature, pressure, sound, or images into digital signals that are easier to store, process, and transmit. ADCs typically consist of multiple cascaded circuits, each of which includes an analog-to-digital converter, an amplifier, and a digital-to-analog converter.

[0003] Signal output swing is a critical parameter for amplifiers, and therefore every amplifier has specific requirements. Furthermore, ADCs typically employ redundant quantization coding techniques for encoding operations. To ensure that the amplifier's signal output swing meets these requirements, related technologies typically increase redundant bits to reduce the required swing, making it easier for the amplifier to meet these requirements. However, increasing the number of redundant bits reduces the amplifier's feedback coefficient during closed-loop operation and lowers the amplifier's gain. Summary of the Invention

[0004] In order to solve the above technical problems, the present application provides an amplifier, an ADC and an electronic device, which can improve the signal output swing of the amplifier while keeping the feedback coefficient and gain of the amplifier in closed-loop use basically unchanged.

[0005] In a first aspect, the present application provides an amplifier comprising: a first transistor, a second transistor, a third transistor, and a feedback circuit. The first transistor and the second transistor form a differential pair configured to receive and amplify an input voltage. The source of the first transistor is connected to the source of the second transistor and to the drain of the third transistor. The source of the third transistor is configured to receive a power supply voltage or ground. The gate of the first transistor is configured to receive a first input voltage, and the gate of the second transistor is configured to receive a second voltage. In the present application, the gate can be a gate, the source can be a source, and the drain can be a drain. Therefore, the voltage at the drain of the third transistor can be the drain voltage of the third transistor. The feedback circuit is configured to control the substrate voltage of the first transistor and the substrate voltage of the second transistor based on a reference voltage and the voltage of the drain of the third transistor to control the threshold voltage of the first transistor and the threshold voltage of the second transistor, thereby controlling the voltage difference between the gate and source of the first transistor and the voltage difference between the gate and source of the second transistor, thereby clamping the voltage at the drain of the third transistor to a constant value, thereby maximizing the voltage difference between the source and drain of the first transistor and the voltage difference between the source and drain of the second transistor. Because the amplifier's signal output swing is positively correlated with the voltage difference between the source and drain of the first transistor and also with the voltage difference between the source and drain of the second transistor, the amplifier's signal output swing can be increased. Furthermore, because the present application primarily achieves this increase in signal output swing by adding a structural improvement to the first sub-amplifier circuit within the amplifier, without requiring the addition of redundant bits, the amplifier's feedback coefficient and gain during closed-loop operation can be maintained substantially unchanged. In other words, the present application can increase the amplifier's signal output swing while maintaining substantially unchanged the amplifier's feedback coefficient and gain during closed-loop operation.

[0006] Based on this, the drain of the third transistor is connected to the first input of the feedback circuit, the second input of the feedback circuit is used to receive a reference voltage, and the output of the feedback circuit is connected to the substrate of the first transistor and the substrate of the second transistor, respectively. In this way, the feedback circuit can receive the reference voltage and the voltage of the drain of the third transistor, and control the substrate voltage of the first transistor and the substrate voltage of the second transistor based on the reference voltage and the voltage of the drain of the third transistor.

[0007] Furthermore, the feedback circuit includes a first sub-amplifier circuit and a charge pump circuit. The first input terminal of the first sub-amplifier circuit serves as the first input terminal of the feedback circuit and is connected to the drain of the third transistor. The second input terminal of the first sub-amplifier circuit is used to receive a reference voltage. The output terminal of the first sub-amplifier circuit is connected to the input terminal of the charge pump circuit. The output terminal of the charge pump circuit serves as the output terminal of the feedback circuit and is connected to the substrate of the first transistor and the substrate of the second transistor, respectively. The charge pump circuit is used to change the polarity of the voltage output by the first sub-amplifier circuit, increase the voltage output by the first sub-amplifier circuit, or decrease the voltage output by the first sub-amplifier circuit. In this way, the first sub-amplifier circuit can receive the reference voltage and the voltage of the drain of the third transistor, calculate the error between the reference voltage and the drain voltage of the third transistor to obtain a residual, amplify the residual, and transmit the amplified voltage to the charge pump circuit. The charge pump circuit then reverses the polarity, increases the voltage, or decreases the voltage, and transmits the voltage to the substrate of the first transistor and the substrate of the second transistor, thereby controlling the substrate voltage of the first transistor and the substrate voltage of the second transistor.

[0008] Furthermore, the charge pump circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor; the source of the fourth transistor is connected to the source of the fifth transistor and serves as an input end of the charge pump circuit, the drain of the fourth transistor is connected to the drain of the sixth transistor and connected to the second end of the first capacitor, the first end of the first capacitor is used to receive a first clock signal, the gate of the fourth transistor is connected to the gate of the sixth transistor and connected to the drain of the fifth transistor; the gate of the fifth transistor is connected to the gate of the seventh transistor and connected to the drain of the fourth transistor, the drain of the fifth transistor is connected to the drain of the seventh transistor and connected to the first end of the second capacitor, the second end of the second capacitor is used to receive a second clock signal, the drain of the fifth transistor is connected to the drain of the seventh transistor and connected to the first end of the second capacitor, the source of the sixth transistor is connected to the source of the seventh transistor and serves as an output end of the charge pump circuit.

[0009] In some embodiments, the amplifier further includes a voltage supply circuit, wherein an output terminal of the voltage supply circuit is connected to the second input terminal of the feedback circuit, and the voltage supply circuit is configured to transmit a reference signal to the feedback circuit. In this manner, the voltage supply circuit can provide a stable reference voltage to the first sub-amplifier circuit.

[0010] Furthermore, the voltage supply circuit includes: a second sub-amplifier circuit, an eighth transistor, a first resistor, a second resistor, and a third resistor; the first input terminal of the second sub-amplifier circuit serves as the input terminal of the voltage supply circuit and is used to receive an input reference voltage; the output terminal of the second sub-amplifier circuit is connected to the gate of the eighth transistor; the source of the eighth transistor is used to receive a power supply voltage; the drain of the eighth transistor is connected to the first terminal of the first resistor; the second terminal of the first resistor is connected to the first terminal of the second resistor and serves as the output terminal of the voltage supply circuit; the second terminal of the second resistor is connected to the first terminal of the third resistor and is connected to the second input terminal of the second sub-amplifier circuit; and the second terminal of the third resistor is grounded. The second resistor can be a variable resistor, i.e., a resistor with an adjustable resistance value. Thus, the desired reference voltage can be obtained by adjusting the resistance value of the second resistor. For example, the reference voltage output by the voltage supply circuit can be 200 mV, and thus the drain voltage of the third transistor can also be approximately 200 mV. The third transistor can operate in a saturation region, thereby providing more voltage margin for the first and second transistors, thereby increasing the signal output swing. Furthermore, by providing the second sub-amplifier circuit, the reference voltage output by the voltage supply circuit is made more stable.

[0011] Regarding the number of transistor pairs in the amplifier circuit, in one possible embodiment, the amplifier includes a differential pair of transistors. Accordingly, the amplifier circuit also includes a feedback circuit. In another possible embodiment, the amplifier includes at least two differential pairs of transistors, at least two third transistors, and at least two feedback circuits, each differential pair including a first transistor and a second transistor. Exemplarily, the amplifier circuit includes two differential pairs of transistors, two third transistors, and two feedback circuits, wherein the source of one third transistor is configured to receive a power supply voltage, and the source of the other third transistor is configured to be grounded. The drain of the first transistor in one differential pair is connected to the drain of the first transistor in the other differential pair and is configured to output the amplified voltage. The drain of the second transistor in one differential pair is connected to the drain of the second transistor in the other differential pair and is configured to output the amplified voltage. Each feedback circuit is configured to control the substrate voltage of the first transistor and the substrate voltage of the second transistor in each differential pair based on a reference voltage and the drain voltage of each third transistor, thereby clamping the drain voltage of each third transistor to a constant value. The more differential pairs of transistors that can control the substrate voltage, the higher the signal output swing of the amplifier. In other words, this technical solution can further improve the signal output swing of the amplifier.

[0012] In some embodiments, the amplifier further includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a third sub-amplifier circuit, and a fourth sub-amplifier circuit. The source of the ninth transistor is connected to the drain of the first transistor in one of the differential pair transistors and is also connected to the first input terminal of the third sub-amplifier circuit. The drain of the ninth transistor is connected to the drain of the eleventh transistor and serves as one of the output terminals of the amplifier. The source of the eleventh transistor is connected to the drain of the first transistor in another differential pair transistor and is also connected to the first input terminal of the fourth sub-amplifier circuit. The source of the tenth transistor is connected to the drain of the first transistor in one of the differential pair transistors and is also connected to the second input terminal of the third sub-amplifier circuit. The drain of the tenth transistor is connected to the drain of the twelfth transistor and serves as another output terminal of the amplifier. The source of the twelfth transistor is connected to the drain of the first transistor in another differential pair transistor and is also connected to the second input terminal of the fourth sub-amplifier circuit. The first output terminal of the third sub-amplifier circuit is connected to the gate of the ninth transistor, and the second output terminal of the third sub-amplifier circuit is connected to the gate of the tenth transistor. The first output terminal of the fourth sub-amplifier circuit is connected to the gate of the eleventh transistor, and the second output terminal of the fourth sub-amplifier circuit is connected to the gate of the twelfth transistor.

[0013] Based on this, the amplifier further includes a voltage supply circuit, and the second input terminal of each feedback circuit is connected to the output terminal of the voltage supply circuit. In other words, the second input terminal of each feedback circuit is connected to the output terminal of the same voltage supply circuit, thereby enabling each feedback circuit to control the substrate voltage of the first transistor and the second transistor in each differential pair according to the same reference voltage.

[0014] Regarding the number of amplifier stages, in one possible embodiment, the amplifier includes a single-stage amplifier circuit. In another possible embodiment, the amplifier includes at least two cascaded amplifier circuits. Each amplifier stage includes a first transistor, a second transistor, a third transistor, and a feedback circuit. Furthermore, the feedback circuit in each amplifier stage can control the substrate voltages of the first and second transistors. This increases the number of differential pairs with adjustable substrate voltages, further improving the amplifier's signal output swing.

[0015] In a second aspect of the present application, an ADC is provided, comprising an analog-to-digital conversion circuit, a digital-to-analog conversion circuit, and an amplifier according to any of the above embodiments, wherein the output of the analog-to-digital conversion circuit is connected to the first input of the amplifier, the second input of the amplifier is used to receive a reference voltage, and the output of the amplifier is connected to the input of the digital-to-analog conversion circuit. The ADC can achieve all the effects of the amplifier.

[0016] In a third aspect of the present application, an electronic device is provided, comprising a circuit board and the aforementioned ADC, wherein the circuit board is electrically connected to the ADC. The electronic device can achieve all the effects of the ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 Schematic diagram of the circuit structure of the pipeline ADC in the embodiment of the present application;

[0019] Figure 2 for Figure 1 Schematic diagram of the circuit structure of the medium cascade circuit;

[0020] Figure 3 The input-output characteristic curve of the cascade circuit using 2-bit / stage redundancy bits;

[0021] Figure 4 The input-output characteristic curve of the cascade circuit using 2.5 bits / stage redundancy bits;

[0022] Figure 5 This is a structural diagram of an ADC in another embodiment of the present application;

[0023] Figure 6 for Figure 5 Schematic diagram of the structure of the amplifier;

[0024] Figure 7 for Figure 6 A circuit structure diagram of the amplifier shown;

[0025] Figure 8 for Figure 6 Another circuit structure diagram of the amplifier shown;

[0026] Figure 9 for Figure 8 A schematic diagram of a partial circuit structure of a first amplifier circuit in the amplifier shown;

[0027] Figure 10 for Figure 9 A schematic diagram of the circuit structure of the medium voltage supply circuit;

[0028] Figure 11 for Figure 9 Schematic diagram of the circuit structure of the charge pump circuit;

[0029] Figure 12 for Figure 8 A schematic diagram of a partial circuit structure of a second amplifier circuit in the amplifier shown;

[0030] Figure 13 for Figure 6 Another circuit structure diagram of the amplifier shown. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" refers to one or more, and "plurality" refers to two or more. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0033] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0034] "Connected", "connected" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used with respect to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change in the orientation of the components in the drawings.

[0035] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0036] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0037] To facilitate understanding of the ADC provided in this application, the following terms are explained:

[0038] ADC: A device that converts a continuous analog signal into a discrete digital signal.

[0039] Digital to analog converter (DAC): A device that converts discrete digital signals into continuous analog signals.

[0040] Slew rate: The average time rate of change of the output voltage of a closed-loop amplifier when the input is a step signal.

[0041] Signal output swing: The ratio between the maximum amplitude of the output signal and the maximum amplitude of the input signal after the input signal is amplified by the amplifier.

[0042] Voltage margin: It can also be called voltage margin, which indicates the voltage drop consumed internally by the voltage supply.

[0043] Phase margin: Mainly used to measure the stability of the negative feedback system and can be used to predict the overshoot of the closed-loop system step response.

[0044] Voltage clamping: An overvoltage protection measure that requires limiting the voltage at a certain point to a specified voltage.

[0045] Substrate voltage: The voltage difference between the substrate of a transistor and the reference ground.

[0046] ADCs are devices frequently used in industrial production and daily life. They can convert analog signals such as temperature, pressure, sound, or images into digital signals that are easier to store, process, and transmit. Pipeline ADCs are a commonly used type of ADC. Figure 1 The circuit structure of a pipeline ADC is shown, wherein the pipeline ADC includes a sample-and-hold circuit (S / H) 3, a multi-stage cascade circuit 1, a digital error correction logic circuit 2, and a sub-analog-to-digital converter (Sub-ADC) 200. The input terminal of the S / H 3 is used to receive an input voltage V in The output of S / H3 is connected to the first cascade circuit 1, the output of the first cascade circuit 1 is connected to the input of the second cascade circuit 1, the output of the second cascade circuit 1 is connected to the input of the third cascade circuit 1, and so on. The output of the k-1th cascade circuit 1 is connected to the Sub-ADC 200. The output of each cascade circuit 1 is also connected to the input of the digital error correction logic circuit 2 and outputs a digital signal D to the digital error correction logic circuit 2. out1 、D out2 ...D outk-1 The output of Sub-ADC200 is also connected to the input of digital error correction logic circuit 2, and outputs digital signal D to digital error correction logic circuit 2. outk The digital error correction logic circuit 2 calculates each received digital signal to obtain a digital signal D out And output.

[0047] like Figure 2 As shown, each stage of the cascade circuit 1 includes a Sub-ADC 200, a sub-digital-to-analog converter (Sub-DAC) 300, a summing circuit 400, and an amplifier 100. The input terminal of the Sub-ADC 300 is used to connect to the Figure 1 The output signal of the upper stage cascade circuit 1 or the signal output by S / H3 is connected to the output of Sub-ADC200 and the input of Sub-DAC300, and is also connected to Figure 1 The first input terminal of the summing circuit 400 is used to receive the input voltage V inThe second input terminal of the summing circuit 400 is connected to the output terminal of the Sub-DAC 300, and the output terminal of the summing circuit 400 is connected to the first input terminal of the amplifier 100. The second input terminal of the amplifier 100 is used to receive the reference voltage V ref The output terminal of the amplifier 100 is used to output a voltage V to the next cascade circuit 1. res .

[0048] Pipeline ADC usually uses redundant quantization coding technology for encoding operations, so that the conversion accuracy is not limited by the resolution of Sub-ADC200, and can achieve high conversion rate and high conversion accuracy at the same time. Here, the redundant bits are 2 bits / level and 2.5 bits / level as an example. Figure 2 The input and output characteristics of the cascade circuit 1 shown will be described. Figure 3 The figure shows the input-output characteristic curve of the cascade circuit 1 using 2 bits / stage redundant bits. Figure 3 In the figure, the horizontal axis represents the input voltage V of the cascade circuit 1. in , the vertical axis represents the output voltage V of the cascade circuit 1 res The threshold levels of Sub-ADC200 quantization are -0.5V ref , 0 and 0.5V ref , and the feedback level of Sub-DAC is -0.75V ref 、-0.25V ref , 0.25V ref and 0.75V ref If the feedback level is unbiased and the threshold level at 0 is DC offset, as shown by the dotted line in the figure, the offset is V OS In this case, V res Will exceed V ref The range of the next stage Sub-ADC200 will overflow and cause missing code. However, if the next stage can accurately quantize the output margin V res , and finally the correct quantitative results can be obtained.

[0049] Figure 4 Shown is the input-output characteristic curve of the cascade circuit 1 using 2.5 bits / stage redundant bits. Figure 4 In the figure, the horizontal axis represents the input voltage V of the cascade circuit 1. in , the vertical axis represents the output voltage V of the cascade circuit 1 res When the threshold level of Sub-ADC200 changes due to offset, after the 2.5-bit / level redundant digital correction logic shown in Table 1, V res It can still be correctly quantized by the subsequent stage, thus obtaining the correct digital output result. Figure 4 The maximum threshold offset that can be tolerated for Sub-ADC200 is 0.25Vref When the offset voltage is within this range, the final input-output curve of the pipeline ADC still maintains its original linearity.

[0050] Table 1 Redundant digital code correction logic diagram

[0051]

[0052]

[0053] In Table 1, the N-2th bit of the first level, the N-4th bit of the second level, the N-6th bit of the third level, and the 3rd bit of the k-1th level are all redundant bits.

[0054] Figure 2 The amplifier 100 in the embodiment may be an operational amplifier, and the operational amplifier is required to have characteristics such as high gain and large swing. Currently, the signal output swing of the amplifier 100 is difficult to meet the requirements. Therefore, in related art, as shown in Table 2, a method of adding redundant bits, that is, using 2 or more redundant bits, can be adopted to reduce the signal output swing requirement of the amplifier 100, thereby ensuring that the signal output swing of the amplifier 100 meets the requirements.

[0055] Table 2 Redundant digital code correction logic diagram

[0056]

[0057] In Table 2, bits N-2 and N-3 of the first stage, bits N-4 and N-5 of the second stage, bits N-6 and N-5 of the third stage, and bits 3 and 2 of the k-1 stage are all redundant bits. Theoretically, the required signal output swing of amplifier 100 is halved for each additional redundant bit. This reduces the required signal output swing of amplifier 100, allowing amplifier 100 to meet its required signal output swing.

[0058] However, firstly, increasing redundant bits reduces the feedback coefficient of amplifier 100 during closed-loop operation, thereby increasing the requirements for open-loop gain and bandwidth of amplifier 100. Secondly, increasing redundant bits reduces the gain of amplifier 100, worsening the noise contribution of subsequent cascade circuits 1. Thirdly, the DC offset or sampling clock offset of Sub-ADC 200 is the primary factor causing the increased signal output swing of amplifier 100. However, due to limited marginal benefits, these interference factors do not decrease with increasing redundant bits.

[0059] Based on this, the embodiment of the present application provides an amplifier 100, which can be applied to Figure 2 The cascade circuit 1 shown and applied to Figure 1The pipeline ADC shown in the figure can also be applied to Figure 5 In the ADC shown in FIG. 1 , the ADC may be a Pipeline-successive approximation register (SAR) ADC. Figure 5 As shown, the ADC may include: an analog-to-digital conversion circuit 500, an amplifier 100, and a digital-to-analog conversion circuit 600. The analog-to-digital conversion circuit 500 may include a switch control circuit 501a, a switch control circuit 501b, a SAR logic circuit 502, an amplifier EA1, a switch Multiple switches S1, multiple capacitors C1, switches A plurality of switches S2 and a plurality of capacitors C2.

[0060] like Figure 5 As shown, the first terminals of the plurality of capacitors C1 are connected to the first input terminal of the amplifier EA1 and are used to receive the input voltage V cm The second ends of the plurality of capacitors C1 are respectively connected to the fixed ends of the plurality of switches S1, the first switching end of each switch S1 is connected to the switch control circuit 501a, and the second switching end of each switch S1 is used to receive the input voltage V in The output end of the amplifier EA1 is connected to the input end of the SAR logic circuit 502 , and the SAR logic circuit 502 is used to send a signal CK1 to the amplifier EA1 and a clock signal to the switch control circuit 501 a .

[0061] The first ends of the plurality of capacitors C2 are connected, and the second ends of the plurality of capacitors C2 are respectively connected to the fixed ends of the plurality of switches S2. The first switching end of each switch S2 is connected to the switch control circuit 501b, and the second switching end of each switch S2 is used to receive the first input voltage Vin. The SAR logic circuit is also used to send a clock signal to the switch control circuit 501b.

[0062] The first input terminal of the amplifier 100 is connected to the first terminal of each capacitor C2, and the second input terminal of the amplifier 100 is used to connect the input voltage V cm The output of amplifier 100 is connected to the first switching terminals of multiple switches S3, and the second switching terminals of multiple switches S3 are connected to switch control circuit 601. The fixed terminals of multiple switches S3 are respectively connected to the first terminals of multiple capacitors C3, and the second terminals of multiple capacitors C3 are connected to the first input terminal of amplifier EA2. The output of amplifier EA2 is connected to the input terminal of SAR logic circuit 603. SAR logic circuit 603 is used to send signal CK2 to amplifier EA2 and send a clock signal to switch control circuit 501a. Switch control circuit 501b is connected to digital correction logic circuit 602, which is also connected to the SAR logic circuit.

[0063] like Figure 6 As shown, the amplifier 100 may include a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is used to receive a first input voltage V ip The second input terminal is used to receive the second input voltage V in , the first output terminal is used to output the first output voltage V op The second output terminal is used to output the second output voltage V on .

[0064] like Figure 7 As shown, the amplifier 100 can be a two-stage complementary structure sleeve operational amplifier, and the energy efficiency of the amplifier 100 is relatively high. Figure 7 As shown, the amplifier 100 may include: two stages of cascaded amplifier circuits 10 , namely a first amplifier circuit 11 and a second amplifier circuit 12 .

[0065] like Figure 7 As shown, the first amplifier circuit 11 includes a transistor M1 (i.e., a first transistor), a transistor M2 (i.e., a second transistor), a transistor M3 (i.e., an eleventh transistor), a transistor M4 (i.e., a twelfth transistor), a transistor M5 (i.e., a ninth transistor), a transistor M6 (i.e., a tenth transistor), a transistor M7 (i.e., a first transistor), a transistor M8 (i.e., a second transistor), a transistor M9, a transistor M10 (i.e., a third transistor), a transistor M11, a transistor M12, a transistor M13 (i.e., a third transistor), an ammeter A, a sub-amplifier circuit GP (i.e., a third sub-amplifier circuit), and a sub-amplifier circuit GN (i.e., a fourth sub-amplifier circuit). Transistor M7 and transistor M8 can form a differential pair, and both transistors can be P-type metal oxide semiconductor field effect transistors (PMOS). Transistor M1 and transistor M2 can form a differential pair, and both transistors can be NMOS transistors.

[0066] like Figure 7 As shown, a source of the transistor M9 is connected to a source of the transistor M10 and is used to receive a power supply voltage (VDD), and a drain of the transistor M9 is connected to a drain of the transistor M12.

[0067] like Figure 7As shown, the gate of transistor M9 is also connected to the drain of transistor M12, and the gate of transistor M9 is connected to the gate of transistor M10. The drain of transistor M10, the source of transistor M7 and the source of transistor M8 are all connected, the drain of transistor M7 is connected to the first input terminal of sub-amplifier circuit GP, and the drain of transistor M8 is connected to the second input terminal of sub-amplifier circuit GP. The gate of transistor M7 is used to receive the first input voltage V ip The gate of transistor M8 is used to receive the second input voltage V in .

[0068] like Figure 7 As shown, the source of transistor M5 is connected to the drain of transistor M7, and the gate of transistor M5 is connected to the first output terminal of sub-amplifier circuit GP. The source of transistor M6 is connected to the drain of transistor M8, and the gate of transistor M6 is connected to the second output terminal of sub-amplifier circuit GP.

[0069] like Figure 7 As shown, the drain of transistor M3 is connected to the drain of transistor M5 and serves as the first output terminal of the first amplifier circuit 11. The drain of transistor M6 is connected to the drain of transistor M4 and serves as the second output terminal of the first amplifier circuit 11. The gate of transistor M3 is connected to the first output terminal of the sub-amplifier circuit GN, and the gate of transistor M4 is connected to the second output terminal of the sub-amplifier circuit GN. The source of transistor M3 is connected to the drain of transistor M1 and connected to the first input terminal of the sub-amplifier circuit GN. The source of transistor M4 is connected to the drain of transistor M2 and connected to the second input terminal of the sub-amplifier circuit GN. The gate of transistor M1 is used to receive the first input voltage V ip The gate of transistor M2 is used to receive the second input voltage V in The source of transistor M1 is connected to the source of transistor M2 and to the drain of transistor M13, as shown in FIG. Figure 7 As shown, the source of transistor M11, the source of transistor M12, and the source of transistor M13 are all grounded. The gates of transistor M11, transistor M12, and transistor M13 are all connected to the second terminal of ammeter A. The drain of transistor M11 is also connected to the second terminal of ammeter A. The first terminal of ammeter A is used to receive VDD.

[0070] like Figure 7As shown, the second amplifier circuit 12 may include a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22, a capacitor C1, and a capacitor C2. The transistor M16 and the transistor M17 may form a differential pair, and both transistors may be PMOS transistors. The transistor M14 and the transistor M15 may form a differential pair, and both transistors may be NMOS transistors.

[0071] like Figure 7 As shown, the source of transistor M18 is connected to the source of transistor M19 and is used to receive VDD. The drain of transistor M18 is connected to the drain of transistor M21. The gate of transistor M18 is also connected to the drain of transistor M21. The gate of transistor M18 is also connected to the gate of transistor M19. The drain of transistor M19, the source of transistor M16, and the source of transistor M17 are all connected.

[0072] like Figure 7 As shown, the gate of transistor M14 is connected to the gate of transistor M16 and to the drain of transistor M5, that is, connected to the first output terminal of the first amplifier circuit 11. The gate of transistor M17 is connected to the gate of transistor M15 and to the drain of transistor M4, that is, connected to the second output terminal of the first amplifier circuit 11. The drain of transistor M16 is connected to the drain of transistor M14 and serves as the first output terminal of the second amplifier circuit 12, and as the first output terminal of the amplifier 100, for outputting the first output voltage V op The drain of the transistor M117 is connected to the drain of the transistor M15 and serves as the second output terminal of the second amplifier circuit 12 and the second output terminal of the amplifier 100 for outputting the second output voltage V on .

[0073] like Figure 7 As shown, the first end of capacitor C1 is connected to the gate of transistor M16, and the second end of capacitor C1 is connected to the drain of transistor M16. The first end of capacitor C2 is connected to the drain of transistor M17, and the second end of capacitor C2 is connected to the gate of open-hook transistor M17.

[0074] like Figure 7 As shown, the source of transistor M14 is connected to the source of transistor M15 and to the drain of transistor M22. The source of transistor M20, the source of transistor M21, and the source of transistor M22 are all grounded. The gates of transistor M20, transistor M21, and transistor M22 are all connected to the second terminal of ammeter A. The drain of transistor M20 is also connected to the second terminal of ammeter A. The first terminal of ammeter A is used to receive VDD.

[0075] from Figure 7 It can be seen that transistors M10, M13, M22, and M19 provide tail current source bias. Therefore, the first amplifier circuit 11 and the second amplifier circuit 12 both use complementary NMOS and PMOS transistors with constant tail current source bias. The first amplifier circuit 11 consumes current and shares noise, and the first amplifier circuit 11 and the second amplifier circuit 12 both participate in signal amplification. Therefore, under the same current bias, the effective unit gain bandwidth (UGB), gain bandwidth product (GBW), and switching gain are improved. In addition, the complementary NMOS and PMOS transistors of the second amplifier circuit 12 constitute a push-pull output, which can effectively improve the slew rate of large signals. The signal output swing V of the first amplifier circuit 11 is op,n-stg1 The following first expression can be satisfied:

[0076] (V cm-in -V th1,2 +V dsat3,4 )≤V op,n-stg1 ≤(V cm-in +V th7,8 -V dsat5,6 )

[0077] Where V cm-in represents the input common mode voltage of the first amplifier circuit 11, V th1,2 V represents the threshold voltage of transistor M1 or transistor M2, and the threshold voltages of transistor M1 and transistor M2 are usually the same. dsat3,4 Indicates that the drain current of transistor M3 or transistor M4 is no longer affected by V ds The corresponding V ds , V ds is the voltage difference between the source and drain, V th7,8 Represents the threshold voltage of transistor M7 or transistor M8, V dsat5,6 Indicates that the drain current of transistor M5 or transistor M6 is no longer affected by V ds The corresponding V ds .

[0078] The signal output swing V of the second amplifier circuit 12 op,n The following second expression is satisfied:

[0079] (V cm-stg1 -V th14,15 )≤V op,n ≤(V cm-stg1 +V th16,17 )

[0080] Where V cm-stg1represents the input common mode voltage of the second amplifier circuit 12, V th14,15 represents the threshold voltage of transistor M14 or transistor M15, V th16,17 represents the threshold voltage of the transistor M16 or the transistor M17.

[0081] It can be seen from the first and second expressions that the signal output swing V of the first amplifier circuit 11 is op,n-stg1 The signal output swing V of the second amplifier circuit 12 is related to the threshold voltage of the transistor M1 or the transistor M2, the threshold voltage of the transistor M7 or the transistor M8, and the threshold voltage of the transistor M5 or the transistor M6. op,n It is related to the threshold voltage of the transistor M14 or the transistor M15 and the threshold voltage of the transistor M16 or the transistor M17.

[0082] Under process, voltage and temperature (PVT), the threshold voltage V th The change is quite dramatic, and some transistors may not be able to operate in the saturation region. In order to ensure that all transistors operate in the saturation region under any conditions, voltage margin will be wasted on the tail current source bias of transistors M10, transistor M13, transistor M22 and transistor M19.

[0083] Based on this, Figure 8 As shown, in other embodiments of the present application, an amplifier 100 is further provided. Figure 7 The difference between the embodiments shown is that the present embodiment Figure 8 Based on the illustrated embodiment, feedback circuits 110 a , 110 b , 110 c and 110 d are added.

[0084] like Figure 8 As shown, feedback circuit 110a includes sub-amplifier circuit EA1 and charge pump circuit 111a. Feedback circuit 110b includes sub-amplifier circuit EA2 and charge pump circuit 111b. Feedback circuit 110c includes sub-amplifier circuit EA3 and charge pump circuit 111c. Feedback circuit 110d includes sub-amplifier circuit EA4 and charge pump circuit 111d.

[0085] like Figure 9 As shown, the drain of transistor M10 can be connected to the first input terminal A1 of the sub-amplifier circuit EA1. Here, the sub-amplifier circuit EA1 can be an error amplifier circuit. The second input terminal A2 of the sub-amplifier circuit EA1 is used to receive the reference voltage V ref For example, in this embodiment, the amplifier 100 may further include a voltage providing circuit 20, the input end of which is used to receive an input reference voltage Vref-in The output terminal of the voltage providing circuit 20 is connected to the second input terminal A2 of the sub-amplifier circuit EA1. The voltage providing circuit 20 can receive the input reference voltage V ref-in Converted to reference voltage V ref , and output to the sub-amplifier circuit EA1.

[0086] In this embodiment, if Figure 10 As shown, the voltage providing circuit 20 may include a sub-amplifier circuit EA5 (i.e., a second sub-amplifier circuit), a transistor M23 (i.e., an eighth transistor), a resistor R1 (i.e., a first resistor), a resistor R2 (i.e., a second resistor), and a resistor R3 (i.e., a third resistor). The first input terminal A1 of the sub-amplifier circuit EA5 is used to receive an input reference voltage V ref-in The output end of the sub-amplifier circuit EA5 is connected to the gate of the transistor M23, the source of the transistor M23 is used to receive VDD, the drain of the transistor M23 can be connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the first end of the resistor R2 and serves as the output end of the voltage providing circuit 20 to output the reference voltage V ref The second end of the resistor R2 is connected to the first end of the resistor R3 and to the second input end A2 of the sub-amplifier circuit EA5, and the second end of the resistor R3 is grounded.

[0087] Continue to refer to Figure 10 , resistors R1 and R3 can be fixed resistors, i.e., resistors with fixed resistance values. Resistor R2 can be a variable resistor, i.e., a resistor with adjustable resistance value. Thus, the required reference voltage V can be obtained by adjusting the resistance value of resistor R2. ref Moreover, in this embodiment, by setting the sub-amplifier circuit EA5, the reference voltage V output by the voltage supply circuit 20 is ref More stable.

[0088] like Figure 9 As shown, the input terminal A of the charge pump circuit 111 a is connected to the output terminal B of the sub-amplifier circuit EA1 , and the output terminal B of the charge pump circuit 111 a is connected to the substrates of the transistor M7 and the transistor M8 , respectively.

[0089] like Figure 11As shown, the charge pump circuit 111a may include a transistor M24 (i.e., a fourth transistor), a transistor M25 (i.e., a fifth transistor), a transistor M26 (i.e., a sixth transistor), a transistor M27 (i.e., a seventh transistor), a capacitor C3 (i.e., a first capacitor), and a capacitor C4 (i.e., a second capacitor). The source of the transistor M24 is connected to the source of the transistor M25 and serves as the input terminal of the voltage providing circuit 20. The drain of the transistor M24 is connected to the drain of the transistor M26 and to the second end of the capacitor C3. The first end of the capacitor C3 is used to receive the clock signal clk1. The gate of the transistor M24 is connected to the gate of the transistor M26. The drain of the transistor M25 is connected to the drain of the transistor M27 and to the first end of the capacitor C4. The second end of the capacitor C4 is used to receive the clock signal clk2. The source of the transistor M26 is connected to the source of the transistor M27 and serves as the output terminal B of the voltage providing circuit 20. The gate of the transistor M24 is further connected to the drain of the transistor M25 , and the drain of the transistor M24 is further connected to the gate of the transistor M25 .

[0090] The sub-amplifier circuit EA1 can receive the reference voltage V transmitted by the voltage providing circuit 20. ref And the voltage of the drain of transistor M10, the voltage of the drain of transistor M10 is the drain voltage V srcn-stg1 The sub-amplifier circuit EA1 can be used to adjust the reference voltage V ref and V of transistor M10 srcn-stg1 Perform error calculation to obtain the residual and amplify it to obtain the voltage V after error amplification EA1 and the voltage V EA1 is transmitted to the charge pump circuit 111a. The charge pump circuit 111a can realize the voltage V EA1 The polarity of the voltage is reversed and the voltage V is increased. EA1 Or reduce the voltage V EA1 The polarity-inverted, increased, or decreased voltage is transmitted to the substrate of transistor M7 and the substrate of transistor M8, so as to control the substrate voltage of transistor M7 and the substrate voltage of transistor M8 according to the voltage output by charge pump circuit 111a, thereby controlling the threshold voltage of transistor M7 and the threshold voltage of transistor M8.

[0091] Assume that the closed-loop gain of the sub-amplifier circuit EA1 is G EA1 , then the voltage V output by the charge pump circuit 111a bn-stg1 It can be calculated according to the third expression as follows:

[0092] V bn-stg1 =G EA1 ×(V ref -V srcn-stg10 )

[0093] Where G EA1is the closed-loop gain of the sub-amplifier circuit EA1, V ref The reference voltage V is transmitted from the voltage providing circuit 20 to the sub-amplifier circuit EA1. srcn-stg1 is the drain voltage of transistor M10.

[0094] If the drain voltage V srcn-stg10 If the substrate voltage of transistors M7 and M8 is too high, the substrate voltage of transistors M7 and M8 can be increased through the feedback circuit 110a, thereby increasing the threshold voltage of transistors M7 and M8. Figure 8 As shown, the drain voltage V srcn-stg10 is the input voltage V of transistor M7 ip The voltage difference between the gate and source of transistor M7 is the sum of the overdrive saturation voltage and the threshold voltage of transistor M7. Since the threshold voltage of transistor M7 is increased, the drain voltage of transistor M10 will decrease, thereby achieving the drain voltage V srcn-stg1 Therefore, in this embodiment, the drain voltage V srcn-stg10 Maintained at a constant voltage, thereby achieving a voltage difference V between the source and drain of transistor M7 ds and the voltage difference V between the source and drain of transistor M8 ds Because the signal output swing of the amplifier 100 is related to the voltage difference V between the source and drain of the transistor M7, ds is positively correlated with the voltage difference V between the source and drain of transistor M8. ds There is a positive correlation, so the signal output swing can be increased.

[0095] In addition, if Figure 8 As shown, the reference voltage V output by the voltage providing circuit 20 is ref is an adjustable voltage, for example, 200 mV, so the drain voltage V srcn-stg1 It may also be approximately 200 mV, and the transistor M10 may operate in a saturation region, thereby providing more voltage margin for the transistor M7 and the transistor M8, thereby increasing the signal output swing.

[0096] like Figure 9 As shown, the drain of transistor M13 can be connected to the first input terminal A1 of the sub-amplifier circuit EA2. Here, the sub-amplifier circuit EA2 can be an error amplifier circuit. The second input terminal A2 of the sub-amplifier circuit EA2 is used to receive the reference voltage V ref For example, the input terminal of the voltage providing circuit 20 is used to receive the input reference voltage V ref-inThe output terminal of the voltage providing circuit 20 is connected to the second input terminal A2 of the sub-amplifier circuit EA1. The voltage providing circuit 20 can receive the input reference voltage V ref-in Converted to reference voltage V ref , and output to the sub-amplifier circuit EA2.

[0097] like Figure 9 As shown, the input terminal A of the charge pump circuit 111b is connected to the output terminal B of the sub-amplifier circuit EA2, and the output terminal B of the charge pump circuit 111b is connected to the substrates of the transistor M1 and the transistor M2 respectively. The structure of the charge pump circuit 111b can be the same as that of the charge pump circuit 111a. For example, both adopt Figure 11 The circuit structure shown.

[0098] The sub-amplifier circuit EA2 can receive the reference voltage Vref transmitted by the voltage providing circuit 20 and the voltage of the drain of the transistor M13. The voltage of the drain of the transistor M13 is the drain voltage V srcn-stg13 The sub-amplifier circuit EA2 can be used to adjust the reference voltage V ref and the drain voltage V srcn-stg13 Perform error calculation to obtain the residual and amplify it to obtain the voltage V after error amplification EA2 and the voltage V EA2 is transmitted to the charge pump circuit 111b. The charge pump circuit 111b can realize the voltage V EA2 The polarity of the transistor M1 is reversed. The voltage after polarity reversal is transmitted to the substrate of the transistor M1 and the substrate of the transistor M2 to control the substrate voltage of the transistor M1 and the substrate voltage of the transistor M2, thereby controlling the threshold voltage of the transistor M1 and the threshold voltage of the transistor M2, thereby achieving the drain voltage V srcn-stg13 In this way, the drain voltage V srcn-stg13 Maintain a constant and small voltage, thereby achieving a voltage difference V between the source and drain of transistor M1 ds and the voltage difference V between the source and drain of transistor M2 ds Since the signal output swing of the amplifier 100 is related to the voltage difference V between the source and drain of the transistor M1, ds is positively correlated with the voltage difference V between the source and drain of transistor M2. ds There is a positive correlation, so the signal output swing can be increased.

[0099] The signal output swing V of the first amplifier circuit 11 op，n-stg1 The following fourth expression can be satisfied:

[0100] (200mV+V dsat1,2 +V dsat3,4 )≤Vop,n_stg1 ≤(VDD-200mV-V dsat7,8 -V dsat5,6 )

[0101] Where V dsat1,2 Indicates that the drain current of transistor M1 or transistor M2 is no longer affected by V ds The corresponding V ds , V ds is the voltage difference between the source (i.e., source) and drain (i.e., drain), V dsat3,4 Indicates that the drain current of transistor M3 or transistor M4 is no longer affected by V ds The corresponding V ds , V dsat7,8 Indicates that the drain current of transistor M7 or transistor M8 is no longer affected by V ds The corresponding V ds , V dsat5,6 Indicates that the drain current of transistor M5 or transistor M6 is no longer affected by V ds The effect of the change is the corresponding Vds. Figure 12 As shown, the drain of transistor M19 can be connected to the first input terminal A1 of the sub-amplifier circuit EA3. Here, the sub-amplifier circuit EA3 can be an error amplifier circuit. The second input terminal A2 of the sub-amplifier circuit EA3 is used to connect to the output terminal of the voltage providing circuit 20 and can receive the reference voltage V transmitted by the voltage providing circuit 20. ref .

[0102] like Figure 12 As shown, the input terminal A of the charge pump circuit 111c is connected to the output terminal B of the sub-amplifier circuit EA3, and the output terminal B of the charge pump circuit 111c is connected to the substrates of the transistor M16 and the transistor M17 respectively. The structure of the charge pump circuit 111c can be the same as that of the charge pump circuit 111a. For example, both adopt Figure 11 The circuit structure shown.

[0103] The sub-amplifier circuit EA3 can receive the reference voltage V transmitted by the voltage providing circuit 20. ref and the drain voltage V srcn-stg19 The sub-amplifier circuit EA3 can be used to adjust the reference voltage V ref and the drain voltage V srcn-stg19 Perform error calculation to obtain the residual and amplify it to obtain the voltage V after error amplification EA3 and the voltage V EA3 is transmitted to the charge pump circuit 111c. The charge pump circuit 111c can realize the voltage V EA3The polarity of the transistor M16 is reversed. The voltage after polarity reversal is transmitted to the substrate of the transistor M16 and the substrate of the transistor M17 to control the substrate voltage of the transistor M16 and the substrate voltage of the transistor M17, thereby controlling the threshold voltage of the transistor M16 and the threshold voltage of the transistor M17, thereby achieving the drain voltage V srcn-stg19 The voltage of the drain terminal of the transistor M19 can be clamped. srcn-stg19 Maintained at a constant voltage, thereby achieving a voltage difference V between the source and drain of transistor M16 ds and the voltage difference V between the source and drain of transistor M17 ds Because the signal output swing of the amplifier 100 is related to the voltage difference V between the source and drain of the transistor M16, ds is positively correlated with the voltage difference V between the source and drain of transistor M17. ds There is a positive correlation, so the signal output swing can be increased.

[0104] like Figure 12 As shown, the drain of the transistor M22 can be connected to the first input terminal A1 of the sub-amplifier circuit EA4. Here, the sub-amplifier circuit EA4 can be an error amplifier circuit. The second input terminal A2 of the sub-amplifier circuit EA4 is used to connect to the output terminal of the voltage providing circuit 20 and can receive the reference voltage V transmitted by the voltage providing circuit 20. ref .

[0105] like Figure 12 As shown, the input terminal A of the charge pump circuit 111d is connected to the output terminal B of the sub-amplifier circuit EA4, and the output terminal B of the charge pump circuit 111d is connected to the substrates of the transistors M14 and M15 respectively. The structure of the charge pump circuit 111d can be the same as that of the charge pump circuit 111a. For example, both adopt Figure 11 The circuit structure shown.

[0106] The sub-amplifier circuit EA4 can receive the reference voltage V transmitted by the voltage providing circuit 20. ref and the drain voltage V srcn-stg22 The sub-amplifier circuit EA4 can be used to adjust the reference voltage V ref and the drain voltage V srcn-stg22 Perform error calculation to obtain the residual and amplify it to obtain the voltage V after error amplification EA4 and the voltage V EA4 is transmitted to the charge pump circuit 111d. The charge pump circuit 111d can realize the voltage V EA4The polarity of the transistor M22 is reversed. The voltage after polarity reversal is transmitted to the substrate of the transistor M14 and the substrate of the transistor M15 to control the substrate voltage of the transistor M14 and the substrate voltage of the transistor M15, thereby controlling the threshold voltage of the transistor M14 and the threshold voltage of the transistor M15, thereby achieving the drain voltage V srcn-stg22 Therefore, in this embodiment, the drain voltage V srcn-stg22 Maintained at a constant voltage, thereby achieving a voltage difference V between the source and drain of transistor M14 ds and the voltage difference V between the source and drain of transistor M15 ds Because the signal output swing of the amplifier 100 is related to the voltage difference V between the source and drain of the transistor M14, ds is positively correlated with the voltage difference V between the source and drain of transistor M15. ds There is a positive correlation, so the signal output swing can be increased.

[0107] In addition, the signal output swing of the second amplifier circuit 12 is V op,n The following fifth expression can be satisfied:

[0108] (200mV+V dsat14,15 )≤V op,n ≤(VDD-200mV-V dsat16 ,17)

[0109] Where V dsat14,15 This indicates that the drain current of transistors M14 and M15 is no longer affected by V ds The corresponding V ds , V dsat16,14 This means that the drain current of transistors M16 and M17 is no longer affected by V ds The corresponding V ds .

[0110] In addition, in this embodiment, no additional redundant bits need to be added, thereby not reducing the closed-loop feedback coefficient and not deteriorating the noise contribution of the second amplifier circuit 12. Furthermore, the power consumption is low, the noise is low, and the energy efficiency ratio is high.

[0111] It is understood that, in this embodiment, the amplifier 100 includes two cascaded amplifier circuits, namely, a first amplifier circuit 11 and a second amplifier circuit. In other embodiments, the amplifier 100 may include only one amplifier circuit. For example, the amplifier 100 includes the first amplifier circuit 11 but does not include the second amplifier circuit 12. Alternatively, the amplifier 100 includes the second amplifier circuit 12 but does not include the first amplifier circuit 11.

[0112] It is also understood that in this embodiment, the substrate voltages of transistors M7 and M8, transistors M1 and M2, transistors M16 and M17, and transistors M14 and M15 are all controlled. In other embodiments, the substrate voltages of one, two, or three of the four differential pairs may be controlled. Correspondingly, the number of sub-amplifier circuits provided is the same as the number of differential pairs whose substrate voltages need to be controlled. For example, when the substrate voltage of one of the four differential pairs needs to be controlled, only one sub-amplifier circuit is required.

[0113] Moreover, in this embodiment, if Figure 8 As shown, the first amplifier circuit 11 includes two charge pump circuits, namely charge pump circuit 111a and charge pump circuit 111b. In other embodiments, the first amplifier circuit 11 may not include a charge pump circuit, or the first amplifier circuit 11 may include one charge pump circuit. For example, the first amplifier circuit 11 includes charge pump circuit 111a or charge pump circuit 111b. Similarly, the second amplifier circuit 11 may not include a charge pump circuit, or may include charge pump circuit 111c or charge pump circuit 111d.

[0114] In other embodiments of the present application, Figure 13 As shown, amplifier 100 can also be a Class-A telescopic operational amplifier. The telescopic operational amplifier includes transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, transistor M7 (i.e., a first transistor), transistor M8 (i.e., a second transistor), transistor M9 (i.e., a third transistor), transistor M10, transistor M11, transistor M12, transistor M13, transistor M14, a first capacitor C1, a second capacitor C2, a sub-amplifier circuit GP, a sub-amplifier circuit GN, a feedback circuit 110a, and a voltage supply circuit 20. Transistors M7 and M8 can form a differential pair. Feedback circuit 110a includes a sub-amplifier circuit EA1 and a charge pump circuit 111a.

[0115] like Figure 13 As shown, the source of transistor M1 and the source of transistor M2 are both used to receive VDD, the gate of transistor M1 and the gate of transistor M2 are connected, the drain of transistor M1 is connected to the first input terminal of sub-amplifier circuit GP, and the drain of transistor M2 is connected to the second input terminal of sub-amplifier circuit GP.

[0116] like Figure 13As shown, the source of transistor M3 is connected to the drain of transistor M1, and the gate of transistor M3 is connected to the first output terminal of sub-amplifier circuit GP. The source of transistor M4 is connected to the drain of transistor M2, and the gate of transistor M4 is connected to the second output terminal of sub-amplifier circuit GP.

[0117] like Figure 13 As shown, the drain of transistor M5 is connected to the drain of transistor M3, and the gate of transistor M5 is connected to the first output terminal of the sub-amplifier circuit GN. The drain of transistor M6 is connected to the drain of transistor M4, and the gate of transistor M6 is connected to the second output terminal of the sub-amplifier circuit GN. The source of transistor M5 is connected to the drain of transistor M7 and connected to the first input terminal of the sub-amplifier circuit GN. The source of transistor M6 is connected to the drain of transistor M8 and connected to the second input terminal of the sub-amplifier circuit GN. The gate of transistor M7 is used to receive the first input voltage V ip The gate of transistor M8 is used to receive the second input voltage V in The source of the transistor M7 is connected to the source of the transistor M8 and to the drain of the transistor M9. The source of the transistor M9 is grounded. The gate of the transistor M9 is used to receive the third input voltage V b1 .

[0118] like Figure 13 As shown, the source of transistor M11 and the source of transistor M12 are both used to receive VDD, and the gate of transistor M11 is connected to the gate of transistor M12. The drain of transistor M11 is connected to the drain of transistor M13 and to the second end of the first capacitor C1, and serves as the first output terminal of amplifier 100 to output the first output voltage V op The first end of the first capacitor C1 is connected to the drain of the transistor M3 and the gate of the transistor M13. The drain of the transistor M12 is connected to the drain of the transistor M14 and to the first end of the second capacitor C2, and serves as the second output end of the amplifier 100 to output the second output voltage V on The second end of the second capacitor C2 is connected to the drain of the transistor M4 and the gate of the transistor M14. The source of the transistor M13 is connected to the source of the transistor M14 and is also connected to the drain of the transistor M10. The source of the transistor M10 is grounded. The gate of the transistor M10 is used to receive the fourth input voltage V b2 .

[0119] like Figure 13 As shown, the drain of the transistor M9 can be connected to the first input terminal A1 of the sub-amplifier circuit EA1, and the second input terminal A2 of the sub-amplifier circuit EA1 is used to receive the reference voltage V transmitted by the voltage providing circuit 20. refThe input terminal A of the charge pump circuit 111 a is connected to the output terminal B of the sub-amplifier circuit EA1 , and the output terminal B of the charge pump circuit 111 a is connected to the substrates of the transistor M7 and the transistor M8 , respectively.

[0120] In other embodiments of the present application, the amplifier may also be a Class-AB folded cascode amplifier.

[0121] The performance of ADCs with a conversion rate of 125 MS / s and using amplifiers 100 with different structures is calculated and compared. The comparison results are shown in Table 3.

[0122] Table 3 Performance comparison of ADCs using amplifiers 100 with different structures

[0123]

[0124] In Table 3, the comparison Figure 7 The amplifier 100 shown is used in the ADC and Figure 8 The performance of the amplifier 100 shown in FIG. 1 is the same as that of the ADC, and the open-loop gain, phase margin, integrated noise voltage, UGB and power consumption are the same. Figure 8 The signal output swing of the ADC of the amplifier 100 shown is 1.7Vpp. Figure 7 The signal output swing of the ADC of the amplifier 100 is 1.3Vpp, which is obviously different from the Figure 7 The ADC of the amplifier 100 shown uses Figure 8 The signal output swing of the ADC of the amplifier 100 is significantly increased. Figure 8 The amplifier 100 is shown in Figure 7 Based on the amplifier 100 shown, a sub-amplifier circuit, a charge pump circuit, and a voltage supply circuit are added. This shows that this solution can maintain the open-loop gain, phase margin, integrated noise voltage, UGB, and power consumption performance basically unchanged while also improving the signal output swing.

[0125] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. An amplifier, characterized in that: include: a first transistor, a second transistor, a third transistor, and a feedback circuit, wherein the first transistor and the second transistor constitute a differential pair transistor, the differential pair transistor being configured to receive and amplify an input voltage, the source of the first transistor being connected to the source of the second transistor and to the drain of the third transistor, and the source of the third transistor being configured to receive a power supply voltage or be grounded; The feedback circuit is configured to control the substrate voltage of the first transistor and the substrate voltage of the second transistor according to a reference voltage and a voltage of the drain of the third transistor.

2. The amplifier according to claim 1, wherein The drain of the third transistor is connected to the first input terminal of the feedback circuit, the second input terminal of the feedback circuit is used to receive the reference voltage, and the output terminal of the feedback circuit is connected to the substrate of the first transistor and the substrate of the second transistor respectively.

3. The amplifier according to claim 1, wherein The feedback circuit includes a first sub-amplifier circuit and a charge pump circuit. The first input terminal of the first sub-amplifier circuit is connected to the drain of the third transistor as the first input terminal of the feedback circuit. The second input terminal of the first sub-amplifier circuit is used to receive the reference voltage. The output terminal of the first sub-amplifier circuit is connected to the input terminal of the charge pump circuit. The output terminal of the charge pump circuit is connected to the substrate of the first transistor and the substrate of the second transistor respectively as the output terminal of the feedback circuit. The charge pump circuit is used to change the polarity of the voltage output by the first sub-amplifier circuit, increase the voltage output by the first sub-amplifier circuit, or decrease the voltage output by the first sub-amplifier circuit.

4. The amplifier according to claim 3, characterized in that The charge pump circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor; The source of the fourth transistor is connected to the source of the fifth transistor and serves as an input terminal of the charge pump circuit. The drain of the fourth transistor is connected to the drain of the sixth transistor and to the second terminal of the first capacitor. The first terminal of the first capacitor is used to receive a first clock signal. The gate of the fourth transistor is connected to the gate of the sixth transistor and to the drain of the fifth transistor. The gate of the fifth transistor is connected to the gate of the seventh transistor and to the drain of the fourth transistor, the drain of the fifth transistor is connected to the drain of the seventh transistor and to the first end of the second capacitor, the second end of the second capacitor is used to receive a second clock signal, the drain of the fifth transistor is connected to the drain of the seventh transistor and to the first end of the second capacitor, and the source of the sixth transistor is connected to the source of the seventh transistor and serves as the output end of the charge pump circuit.

5. The amplifier according to any one of claims 1 to 4, characterized in that: The amplifier further includes a voltage providing circuit, an output end of the voltage providing circuit is connected to the second input end of the feedback circuit, and the voltage providing circuit is used to transmit the reference signal to the feedback circuit.

6. The amplifier according to claim 5, characterized in that The voltage providing circuit includes: a second sub-amplifier circuit, an eighth transistor, a first resistor, a second resistor and a third resistor; The first input terminal of the second sub-amplifier circuit serves as the input terminal of the voltage providing circuit and is used to receive an input reference voltage. The output terminal of the second sub-amplifier circuit is connected to the gate of the eighth transistor. The source of the eighth transistor is used to receive a power supply voltage. The drain of the eighth transistor is connected to the first end of the first resistor. The second end of the first resistor is connected to the first end of the second resistor and serves as the output terminal of the voltage providing circuit. The second end of the second resistor is connected to the first end of the third resistor and is connected to the second input terminal of the second sub-amplifier circuit. The second end of the third resistor is grounded.

7. The amplifier according to any one of claims 1 to 6, characterized in that: The amplifier includes at least two differential pair transistors, at least two third transistors, and at least two feedback circuits, each of the feedback circuits being configured to control a substrate voltage of the first transistor and a substrate voltage of the second transistor in each differential pair transistor according to the reference voltage and a drain voltage of each third transistor; A source of one of the at least two third transistors is used to receive the power supply voltage, and a source of the other third transistor is used to be grounded; The drain of the first transistor in one of the differential pair tubes is connected to the drain of the first transistor in the other differential pair tube, and is used to output the amplified voltage; the drain of the second transistor in one of the differential pair tubes is connected to the drain of the second transistor in the other differential pair tube, and is used to output the amplified voltage.

8. The amplifier according to claim 7, characterized in that The amplifier further includes a voltage providing circuit, and the second input terminal of each feedback circuit is connected to the output terminal of the voltage providing circuit.

9. The amplifier according to any one of claims 1 to 8, characterized in that: The amplifier includes at least two stages of cascaded amplification circuits, and each stage of the amplification circuit includes the first transistor, the second transistor, the third transistor, and the feedback circuit.

10. An analog-to-digital converter (ADC), characterized in that: It includes an analog-to-digital conversion circuit, a digital-to-analog conversion circuit, and the amplifier according to any one of claims 1 to 8, wherein the output end of the analog-to-digital conversion circuit is connected to the first input end of the amplifier, the second input end of the amplifier is used to receive a reference voltage, and the output end of the amplifier is connected to the input end of the digital-to-analog conversion circuit.

11. An electronic device, characterized in that: The device comprises a circuit board and the ADC according to claim 10, wherein the circuit board is electrically connected to the ADC.

Images