Attenuation compensation method and system for signal transfer function in analog-to-digital converter

Abstract

The present invention discloses a method and system for compensating for the attenuation of a signal transfer function in an analog-to-digital converter (ADC), relating to the field of ADC circuit design and signal processing technology. The method comprises setting an attenuation gain of an integrator, pre-attenuating an analog signal in the analog domain of the integrator; performing analog-to-digital conversion on the pre-attenuated signal through a quantizer to output a digital bit stream; performing gain compensation on the digital bit stream in the digital domain, and constructing a digital domain recovery path corresponding to the analog domain attenuation parameter. The present invention improves system stability by avoiding overload distortion, modulator instability, or modulation loss caused by signal peaks exceeding the dynamic range of the quantizer in the analog front end of the ΣΔ ADC, achieving high-precision ADC conversion of controlled amplitude signals, and setting a corresponding gain compensation factor according to the analog domain attenuation parameter to achieve linear recovery processing of low-amplitude digital signals and compensate for the attenuation introduced in the analog domain.

Description

Technical Field

[0001] The present invention relates to the field of analog-to-digital converter circuit design and signal processing technology, and in particular to an attenuation compensation method and system for a signal transfer function in an analog-to-digital converter. Background Art

[0002] As the requirements for signal accuracy and bandwidth in electronic information systems continue to increase, analog-to-digital converters (ADCs), serving as the interface between analog signals and digital systems, are rapidly evolving toward high resolution, high dynamic range, and low power consumption. Among various ADC architectures, the sigma-delta ADC (ΣΔ ADC) has been widely adopted in audio processing, sensor interfaces, industrial measurement and control, and communications systems due to its high precision, robustness to quantization noise, and ease of digital integration in low- and medium-frequency applications. ΣΔ ADCs typically utilize oversampling and noise shaping techniques to shift quantization noise to higher frequencies, which is then suppressed by digital low-pass filtering, significantly improving the effective signal-to-noise ratio (SNR). The key components of the modulator include an integrator, quantizer, and feedback loop, forming a closed-loop system. Its overall behavior is determined by the signal transfer function (STF) and the noise transfer function (NTF). Typically, in designs, the STF is set to unity gain by default (STF=1) to ensure that the signal is neither compressed nor amplified in the analog front-end, maintaining maximum fidelity. However, as system requirements for dynamic range (DR) continue to increase, the quantizer is prone to overload at full-scale input, leading to distortion, modulation loop instability, and even system crash. To alleviate these issues, some research has attempted to improve them by increasing the number of quantization bits, increasing the dynamic headroom of the feedback path, or employing pre-stage analog gain adjustment. However, these approaches often result in increased circuit complexity, increased power consumption, or parasitic stability issues, making them difficult to implement in applications with stringent requirements for low power consumption and high linearity. Therefore, how to moderately modulate the STF in the signal path to avoid quantizer input overshoot while effectively restoring the signal amplitude in the digital domain, without changing the core modulator structure, has become a key area for improving the stability and performance of ΣΔ ADC systems.

[0003] Existing technologies generally use a fixed STF for unity gain design, ignoring the constraints imposed by the input signal amplitude on the quantizer's linear operation. This can easily lead to nonlinear distortion and abnormal high-order harmonic gain, especially in scenarios with large input signals or wide dynamic ranges. Some solutions incorporate a pre-analog attenuator or automatic gain control (AGC) circuit in the analog front end to dynamically match the quantizer input amplitude. However, these circuits introduce additional noise sources, gain uncertainty, and adjustment hysteresis during implementation, making it difficult to maintain stable overall system linearity. Summary of the Invention

[0004] In view of the above-mentioned problems, the present invention is proposed.

[0005] Therefore, the technical problem solved by the present invention is: the existing ΣΔ analog-to-digital converter has the problems of quantizer input overload and insufficient dynamic range in large signal input scenarios, and how to achieve controlled attenuation of the analog domain signal transfer function and amplitude compensation in the digital domain while maintaining the stability of the modulator structure, thereby enhancing the overload resistance and output signal consistency.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solutions: a method for compensating for attenuation of a signal transfer function in an analog-to-digital converter, comprising setting an attenuation gain of an integrator and pre-attenuating an analog signal in the analog domain of the integrator; performing analog-to-digital conversion on the pre-attenuated signal using a quantizer to output a digital bit stream; performing gain compensation on the digital bit stream in the digital domain and constructing a digital domain recovery path corresponding to the analog domain attenuation parameter; the analog-to-digital conversion comprises: a quantizer pre-stage receiving the attenuated analog signal; periodically initiating a sampling process under the control of an external sampling clock while maintaining signal continuity; comparing the amplitude of the analog signal with a set of reference levels; determining the amplitude range within which the analog signal falls; and generating corresponding digital code values ​​based on the range information, which are output as a continuous digital bit stream; the digital domain recovery path comprises: setting the attenuation parameter in the analog domain, recording the attenuation parameter as a digital domain recovery reference value, and adjusting the amplitude of the digital signal based on the digital domain recovery reference value to obtain an output signal that matches the analog attenuation process.

[0007] As a preferred solution of the attenuation compensation method of the signal transfer function in the analog-to-digital converter described in the present invention, the attenuation gain of the integrator is set, including selecting a first-stage integrator as the attenuation gain position in the analog loop filter of the ΣΔ analog-to-digital converter, setting a feedback network structure in the first-stage integrator, setting the attenuation coefficient by adjusting the parameter ratio between the integral capacitor and the feedback capacitor, and performing amplitude scaling on the analog signal through the first-stage integrator to obtain an analog signal attenuated by the integrator.

[0008] As a preferred solution of the attenuation compensation method of the signal transfer function in the analog-to-digital converter described in the present invention, the feedback network structure includes constructing the integrator as a switched capacitor structure, setting a feedback capacitor in the feedback path, and setting an integrating capacitor in the integrating path, calculating the target integrating capacitor parameters according to a preset attenuation gain coefficient, and setting the capacitance value of the integrating capacitor to a preset multiple of the original design capacitance value.

[0009] As a preferred solution of the attenuation compensation method of the signal transfer function in the analog-to-digital converter described in the present invention, the analog-to-digital conversion of the pre-attenuated signal by the quantizer includes receiving the analog signal attenuated by the integrator at the front stage of the quantizer, and maintaining the input continuity of the analog signal attenuated by the integrator, based on the sampling clock signal control, periodically triggering the quantizer to start a sampling process, in each sampling process, comparing the voltage amplitude of the analog signal attenuated by the integrator with a preset reference level, determining the interval of the analog signal attenuated by the integrator based on the comparison result, obtaining a corresponding digital code value based on the interval of the analog signal attenuated by the integrator, and outputting the digital code value as a digital code stream.

[0010] As a preferred solution of the attenuation compensation method of the signal transfer function in the analog-to-digital converter described in the present invention, the quantizer includes, under the sampling control timing, periodically performing a sampling operation according to a set sampling frequency, determining a corresponding digital code value in each sampling period based on the comparison result of the analog signal attenuated by the integrator and the reference level, and outputting the digital code values ​​obtained in consecutive sampling periods in sequence as a digital code stream.

[0011] As a preferred solution of the attenuation compensation method of the signal transfer function in the analog-to-digital converter described in the present invention, the gain compensation of the digital code stream in the digital domain includes inputting the digital code stream into a digital extraction filter, filtering and data extraction processing the digital code stream to form a low-rate digital signal, providing a digital multiplication unit at the output end of the digital extraction filter, applying a fixed gain factor to the low-rate digital signal, and causing the digital multiplication unit to perform a fixed-value multiplication operation to obtain a digital signal.

[0012] As a preferred solution of the attenuation compensation method of the signal transfer function in the analog-to-digital converter described in the present invention, the digital extraction filter includes receiving a high-sampling-rate digital code stream output by a quantizer as the input of the digital extraction filter, performing integration operations on the input code stream in sequence, accumulating the bit stream generated by the quantizer to form a multi-bit numerical output, constructing an intermediate signal sequence, and based on the integration result, controlling the extraction logic to select an integration output once every fixed sampling period according to a set data extraction ratio to form a low-rate code stream, and performing differential calculations on the extracted code stream.

[0013] As a preferred solution of the attenuation compensation method of the signal transfer function in the analog-to-digital converter described in the present invention, the fixed gain factor includes being pre-set in the gain compensation path in the form of parameters in the digital domain and automatically activated after the extraction filtering is completed.

[0014] As a preferred solution of the attenuation compensation method for the signal transfer function in the analog-to-digital converter described in the present invention, wherein: the construction of a digital domain recovery path corresponding to the analog domain attenuation parameter includes, while setting the analog signal attenuation parameter, recording the attenuation parameter as a digital domain recovery reference value, and adjusting the amplitude of the digital signal based on the digital domain recovery reference value to obtain an output signal that matches the analog attenuation process.

[0015] Another object of the present invention is to provide an attenuation compensation system for the signal transfer function in an analog-to-digital converter, which can introduce a controlled attenuation structure in the analog signal path, construct a gain recovery mechanism in the digital domain, and achieve coordinated regulation of analog domain dynamic range compression and digital domain amplitude restoration, thereby solving the problems in the prior art of easy overload of the quantizer input, uncontrollable signal amplitude, and inconsistent overall system gain.

[0016] As a preferred solution of the attenuation compensation system for the signal transfer function in the analog-to-digital converter described in the present invention, the system comprises an analog signal pre-attenuation module, an analog-to-digital conversion execution module, and a digital domain gain compensation module. The analog signal pre-attenuation module includes an integrator structure configuration submodule and an attenuation gain parameter setting submodule. The integrator structure configuration submodule is used to configure the feedback network structure of the first-stage integrator to achieve the target attenuation of the input signal, and the attenuation gain parameter setting submodule is used to set the gain parameter for controlling the attenuation amplitude, which is used as a reference for digital compensation. The analog-to-digital conversion execution module includes a sampling control submodule and a quantization coding submodule. The sampling control submodule is used to control the working rhythm of the quantizer according to a set sampling frequency. The quantization coding submodule is used to receive the attenuated analog signal, perform amplitude comparison, determine the digital code based on the amplitude comparison result, and output the corresponding digital code stream. The digital domain gain compensation module includes a digital decimation filter submodule and a digital gain compensation submodule. The digital decimation filter submodule is used to filter and decimate the high-sampling-rate digital code stream and output a low-rate digital signal. The digital gain compensation submodule is used to call a fixed gain factor corresponding to the analog attenuation parameter to perform a multiplication operation on the low-rate digital signal to achieve signal amplitude recovery.

[0017] A computer device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of an attenuation compensation method for a signal transfer function in an analog-to-digital converter.

[0018] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of a method for compensating for an attenuation of a signal transfer function in an analog-to-digital converter.

[0019] The beneficial effects of the present invention are as follows: by setting an attenuation gain in the analog front end of the ΣΔ analog-to-digital converter, i.e., the integrator structure, large-amplitude input is limited from the source of the analog signal path, thereby avoiding overload distortion, modulator instability or modulation loss of control caused by the signal peak exceeding the dynamic range of the quantizer, and improving system stability; by setting the quantizer to receive the pre-attenuated analog signal, high-precision analog-to-digital conversion of the controlled amplitude signal is achieved, and a digital code stream matching the amplitude of the attenuated signal is output; by setting a fixed-value multiplication operation unit after the digital extraction filter and setting the corresponding gain compensation factor according to the analog domain attenuation parameter, linear recovery processing of the low-amplitude digital signal is achieved, compensating for the attenuation introduced by the analog domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is an overall flow chart of the attenuation compensation method for the signal transfer function in the analog-to-digital converter provided by the first embodiment of the present invention.

[0022] Figure 2 This is an example diagram of a traditional ΣΔ analog-to-digital converter model for the attenuation compensation method of the signal transfer function in the analog-to-digital converter provided by the second embodiment of the present invention.

[0023] Figure 3 This is an example diagram of a ΣΔ analog-to-digital converter model for the attenuation compensation method of the signal transfer function in the analog-to-digital converter provided by the second embodiment of the present invention.

[0024] Figure 4 This is a performance comparison diagram of conventional ΣΔ analog-to-digital converter model example of the attenuation compensation method for the signal transfer function in the analog-to-digital converter provided by the second embodiment of the present invention, showing the performance comparison between normal amplitude input and full-rail input.

[0025] Figure 5 This is a performance diagram under full-swing input of a ΣΔ analog-to-digital converter model example of the attenuation compensation method for the signal transfer function in the analog-to-digital converter provided by the second embodiment of the present invention.

[0026] Figure 6This is an overall schematic diagram of an attenuation compensation system for a signal transfer function in an analog-to-digital converter provided by a third embodiment of the present invention. DETAILED DESCRIPTION

[0027] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the following detailed description of the specific embodiments of the present invention is given in conjunction with the accompanying drawings. It is obvious that the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in this field without creative work should fall within the scope of protection of the present invention.

[0028] Example 1, reference Figure 1 , as one embodiment of the present invention, provides a method for compensating for attenuation of a signal transfer function in an analog-to-digital converter, comprising:

[0029] S1: Sets the attenuation gain of the integrator and performs pre-attenuation processing on the analog signal in the analog domain of the integrator.

[0030] Furthermore, setting the attenuation gain of the integrator includes selecting a first-stage integrator as the attenuation gain position in the analog loop filter of the ΣΔ analog-to-digital converter, setting a feedback network structure in the first-stage integrator, setting the attenuation coefficient by adjusting the parameter ratio between the integral capacitor and the feedback capacitor, and performing amplitude scaling on the analog signal through the first-stage integrator to obtain an analog signal attenuated by the integrator.

[0031] It should be noted that in the analog loop filter of the ΣΔ analog-to-digital converter, the first-stage integrator is selected as the attenuation gain position, the feedback network structure is set in the first-stage integrator, the attenuation coefficient is set by adjusting the parameter ratio between the integral capacitor and the feedback capacitor, and the analog signal is amplitude-scaled by the first-stage integrator to obtain an analog signal attenuated by the integrator.

[0032] The integrator can be a switched capacitor structure, with a feedback capacitor set in the integrator feedback network and an integrating capacitor set in the integrating path. By setting the integrating capacitor value to a preset multiple of the original design value, the required attenuation factor can be achieved. By fine-tuning the first-stage integrator parameters, the input signal amplitude can be constrained without changing the overall loop structure of the ΣΔ modulator, so that it falls into the linear input range of the quantizer, thereby improving the stability of the system under high-amplitude input conditions. The amplitude compression of the analog signal not only prevents the quantizer from being overloaded and distorted, but also establishes a parameter mapping relationship with the subsequent digital domain amplitude compensation path, which serves as a reference basis for subsequent gain restoration, effectively supports the multiplication gain scheduling logic in the digital recovery path, and ensures the gain closed-loop consistency of the overall signal chain.

[0033] Furthermore, the feedback network structure includes constructing the integrator as a switched capacitor structure, setting a feedback capacitor in the feedback path, and setting an integral capacitor in the integral path, calculating the target integral capacitor parameters based on a preset attenuation gain coefficient, and setting the capacitance value of the integral capacitor to a preset multiple of the original design capacitance value.

[0034] Furthermore, the integrator is constructed as a switched capacitor structure to achieve high-precision analog signal integration operations under low power consumption and high linearity conditions. A feedback capacitor is set in the feedback path of the integrator, and an integrating capacitor is set in the integration path. The feedback capacitor and the integrating capacitor jointly determine the gain characteristics of the integrator. The feedback capacitor is responsible for establishing a reverse coupling channel between the output and the input, while the integrating capacitor determines the integral amplitude response that can be generated by the unit input signal. To achieve the preset attenuation effect of the signal transfer function, the theoretical numerical parameters of the target integrating capacitor are calculated based on the set attenuation gain coefficient and the proportional relationship of the capacitor network. Then, the actual capacitor device is selected to adapt. Under the premise of keeping the feedback capacitor unchanged, the capacitance of the integrating capacitor is set to a preset multiple of the original design capacitance, thereby achieving proportional attenuation of the integrator gain. The switched capacitor structure not only realizes controlled scaling of the signal amplitude, but also matches the input dynamic range of the subsequent quantizer input through the ratio design of the feedback capacitor and the integrating capacitor, providing a hardware foundation for improving the overall dynamic range of the system and suppressing distortion.

[0035] S2: Perform analog-to-digital conversion on the pre-attenuated signal through a quantizer and output a digital bit stream.

[0036] Furthermore, performing analog-to-digital conversion on the pre-attenuated signal through a quantizer includes receiving the analog signal attenuated by an integrator at the front stage of the quantizer, and maintaining the input continuity of the analog signal attenuated by the integrator, and periodically triggering the quantizer to start a sampling process based on the sampling clock signal control. In each sampling process, the voltage amplitude of the analog signal attenuated by the integrator is compared with a preset reference level, and the interval in which the analog signal attenuated by the integrator is located is determined according to the comparison result. According to the interval in which the analog signal attenuated by the integrator is located, a corresponding digital code value is obtained, and the digital code value is output as a digital code stream.

[0037] It should be noted that the quantizer receives the analog signal after attenuation by the integrator and maintains the continuity of its input voltage to avoid quantization errors caused by input interruptions or sudden sampling changes. Regarding sampling control, the system is controlled by a set sampling clock signal. The sampling control circuit periodically triggers the quantizer to initiate a sampling process. During each sampling process, the quantizer compares the voltage amplitude of the current analog signal input with a set of preset reference levels. The reference levels are distributed in a step-like pattern, covering the effective input range of the quantizer. This level comparison determines the voltage interval within which the analog signal falls and generates a corresponding digital code value based on the interval position. The digital code value can be represented using a multi-bit parallel structure to improve quantization accuracy and adapt to the requirements of subsequent digital filtering. This process is repeated over multiple consecutive sampling cycles to form a structured and stable digital output sequence, thereby converting the analog input signal with controlled amplitude into the corresponding discrete digital bit stream. The digital bit stream serves as the input to the subsequent digital domain compensation and filtering modules, ensuring consistency in the time and amplitude domains of the entire signal chain. The digital code value output by the quantizer constitutes the basic digital code stream of the system, providing key input for the restoration and processing of the system's overall signal amplitude.

[0038] Furthermore, the quantizer includes, under the sampling control timing, periodically performing sampling operations according to the set sampling frequency, determining the corresponding digital code value according to the comparison result of the analog signal attenuated by the integrator and the reference level in each sampling period, and outputting the digital code values ​​obtained in consecutive sampling periods in sequence as a digital code stream.

[0039] It should be noted that the quantizer operates under sampling control timing, performing sampling and encoding operations once per sampling cycle according to the set sampling frequency and period. Specifically, the sampling control timing is provided by the system clock module, which provides a periodic trigger signal, allowing the quantizer to sample the input analog signal at a stable frequency, ensuring temporal continuity and amplitude response consistency during the signal sampling process.

[0040] During each sampling cycle, the quantizer receives the analog signal input from the integrator output and compares it with a set of preset multi-level reference levels. By determining the amplitude range of the analog signal between the reference levels, it determines the digital code value corresponding to the input signal. The reference levels are typically evenly distributed or unevenly spaced according to the design objectives, used to improve resolution and coding efficiency within the target signal range. The resulting digital code values ​​are output one by one according to the sampling order, forming a continuous digital bit stream that serves as the input to the subsequent digital filter and gain compensation module. This quantization mechanism not only ensures the accuracy of the analog-to-digital conversion but also seamlessly integrates with the signal pre-attenuation operation of the analog front-end, ensuring that the quantizer always operates within its linear operating region, avoiding overload or code saturation, thereby improving the dynamic stability and signal-to-noise ratio performance of the entire ΣΔ analog-to-digital conversion system.

[0041] S3: Perform gain compensation on the digital bit stream in the digital domain and construct a digital domain recovery path corresponding to the analog domain attenuation parameter.

[0042] Furthermore, gain compensation is performed on the digital code stream in the digital domain, including inputting the digital code stream into a digital extraction filter, filtering and data extraction processing the digital code stream to form a low-rate digital signal, setting a digital multiplication unit at the output end of the digital extraction filter, applying a fixed gain factor to the low-rate digital signal, and causing the digital multiplication unit to perform a fixed-value multiplication operation to obtain a digital signal.

[0043] It should be noted that the high-rate digital bitstream output by the quantizer is input into a digital decimation filter, which performs digital filtering and data extraction, converting the high-sampled-rate original bitstream into a low-rate, low-bandwidth target bitstream. This not only achieves anti-aliasing but also reduces the complexity of subsequent computations. The digital decimation filter can utilize a cascaded integrator-comb filter (CIC filter) or other multi-stage structure. It performs integration, differentiation, and decimation, depending on design requirements, to generate a time-domain continuous, amplitude-accurate low-rate digital signal. A digital multiplication unit is provided at the output of the digital decimation filter to apply a fixed gain compensation factor to the decimated low-rate digital signal. This fixed factor corresponds one-to-one to the attenuation gain parameter set in the analog domain and is pre-stored in a register or lookup table for direct recall during system initialization or during the operating cycle. After receiving the extracted signal, the digital multiplication unit performs a fixed-value multiplication operation according to the set factor, and restores the original signal amplitude proportionally. Through the gain compensation operation, the gain closed loop between the analog domain signal pre-attenuation and the digital domain signal amplitude recovery is completed, so that the entire analog-to-digital conversion path maintains the consistency and linearity of the transfer function at the system level. The output digital signal amplitude is proportionally matched to the original input analog signal, ensuring the complete transmission of the signal amplitude and improving the system accuracy and overload resistance.

[0044] Furthermore, the digital extraction filter includes receiving a high sampling rate digital code stream output by a quantizer as an input of the digital extraction filter, performing integration operations on the input code stream in sequence, accumulating the bit stream generated by the quantizer to form a multi-bit numerical output, constructing an intermediate signal sequence, and based on the integration result, according to the set data extraction ratio, controlling the extraction logic to select the integration output once every fixed sampling period to form a low-rate code stream, and performing differential calculations on the extracted code stream.

[0045] It should be noted that the high-sampling-rate digital bit stream output by the quantizer is received as input, and integration and decimation are sequentially performed on the input bit stream to generate a low-rate digital signal for use in subsequent operations. The digital decimation filter can adopt a cascaded integrator-comb (CIC) structure, performing multi-stage integration operations on the input bit stream in the integration stage. Each bit output of the quantizer serves as an incremental input to the input accumulator. In each integration stage, the accumulated result of the previous cycle is updated to form an intermediate value sequence, which is used to enhance the signal amplitude and stability of the decimated signal. After the integration stage, the decimation logic module in the decimation stage selects the integration result as output every fixed sampling period according to the set data decimation ratio, thereby reducing the data rate. The decimation ratio is designed based on the system oversampling ratio (OSR) and can be flexibly set to integer multiples of 2, 4, or 8 to match the bandwidth requirements of the subsequent signal. After data decimation, the digital decimation process not only ensures the preservation of characteristics within the effective bandwidth of the signal, but also provides a stable input bit stream for subsequent amplitude recovery and digital processing.

[0046] Furthermore, the fixed gain factor includes being preset in the gain compensation path in the form of parameters in the digital domain and automatically activated after the decimation filtering is completed.

[0047] It should be noted that in the digital domain, the fixed gain factor is preset in the gain compensation path in the form of parameters as a static multiplication factor for signal amplitude recovery, which is used to compensate for the amplitude scaling caused by the integrator attenuation operation set in the analog domain. The fixed gain factor is automatically activated after the extraction and filtering operation is completed. The system looks up the matching recovery factor in the gain path according to the attenuation parameter set in the previous integrator, and inputs the factor into the digital multiplication unit to perform amplitude restoration operation on the low-rate digital signal.

[0048] The one-to-one correspondence between the gain factor and the analog attenuation parameter forms a linear mapping relationship between the forward and backward paths. This mechanism not only ensures the accuracy of signal recovery but also facilitates the unified management and dynamic analysis of signal amplitudes by subsequent modules, improving the linearity, consistency, and calibration traceability of the entire analog-to-digital conversion system.

[0049] Furthermore, constructing a digital domain recovery path corresponding to the analog domain attenuation parameter includes, while setting the analog signal attenuation parameter, recording the attenuation parameter as a digital domain recovery reference value, and adjusting the amplitude of the digital signal based on the digital domain recovery reference value to obtain an output signal that matches the analog attenuation process.

[0050] It should be noted that when setting the analog signal attenuation parameters, the attenuation parameters are also recorded as a reference for subsequent digital signal amplitude recovery. In the digital domain recovery path, the recorded reference value is used as a fixed gain factor and applied to the low-rate digital signal after the digital decimation filter to perform amplitude amplification. The amplification operation is performed by the multiplication unit. The multiplication coefficient is the inverse of the analog attenuation factor or its function mapping value, ensuring that the amplitude of the compensated output signal remains consistent with the original input signal.

[0051] By establishing a parameter correspondence between the analog and digital domains, a complete attenuation-recording-compensation recovery link is formed. Even if the signal intensity is compressed at the analog front end, the original amplitude can still be accurately restored at the digital back end, realizing linear closed-loop control of the gain of each link in the signal transmission chain, and effectively ensuring the amplitude accuracy of the analog-to-digital conversion system output and the consistency of the system response.

[0052] Example 2, reference Figure 2-Figure 5 , which is an embodiment of the present invention, provides an attenuation compensation method for the signal transfer function in an analog-to-digital converter. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation and simulation experiments.

[0053] Taking the analog domain second-order four-bit ΣΔ modulator and the digital domain third-order decimation filter as typical examples, the traditional modulator STF gain has no attenuation, such as Figure 2 , Figure 2 The STF gain is 1, there is no attenuation structure, the analog signal directly enters the modulator core path without amplitude adjustment, the analog signal is processed by a two-stage integrator (i.e., a second-order ΣΔ structure), and the output of each stage is superimposed with the input signal through the feedback path. The quantizer has a 4-bit accuracy and no overload protection mechanism. Figure 2 The structure in the embodiment has good performance under low amplitude input, but when the input is close to full amplitude, it will cause the quantizer to overload, resulting in distortion and a significant decrease in SNR. The STF gain attenuation and post-stage digital compensation structure designed by the present invention are as follows: Figure 3 As shown, Figure 3The middle structure adds a 13 / 16 times pre-attenuation module at the input end, which is used to pre-attenuate the analog signal so that its amplitude is controlled before entering the quantizer. The feedforward path coefficient is set to 3 / 4, which together with the attenuation path constitutes a feedforward plus feedback structure to improve the modulation accuracy of the modulator to the input. A multiplication compensation unit is added after the digital filter to restore the amplitude after the front-end 13 / 16 attenuation to ensure consistent output amplitude. The modulator architecture of the present invention example adopts a second-order four-bit ΣΔ modulator with a cascade integrator structure with input feedforward. After being processed by the feedforward path and the cascade integrator, the input signal enters the four-bit quantizer. The cascade integrator consists of two integrators connected in series, and the output signal of each integrator is combined with the input signal through a feedback path. The attenuation gain factor is set by adjusting the feedback coefficient of the first-stage integrator , set the signal scaling factor of the feedforward path to , the overall signal transfer function of the modulator is expressed as:

[0054] ;

[0055] in, Represents the signal transfer function, which is used to describe the transfer characteristics of the input analog signal after being modulated in the ΣΔ modulator and reaching the output end. is the attenuation gain factor, which represents the proportional factor of amplitude compression applied to the input analog signal. Its value is less than 1 (e.g. ), the purpose is to compress the signal amplitude at the front end of the modulator to avoid quantizer overload, is the signal scale factor of the feedforward path, which represents the feedforward weight of the modulator structure directly applied by the input signal without being processed by the integrator. is a Z-domain complex frequency variable, a complex transform variable in discrete-time signal processing, and is used to describe the frequency response characteristics of the ΣΔ modulator system in the Z-domain.

[0056] by , For example, the transfer function is:

[0057] ;

[0058] in, ,in, represents the normalized angular frequency, ,in, Represents the analog signal frequency, Indicates the oversampling rate of the modulator. Since the oversampling rate of the modulator is high, Approaching 0.

[0059] The attenuation gain factor within the bandwidth is ,Right now Figure 2The attenuation gain factor from point X to point Y is: The digital filter behind the modulator takes a third-order cascaded integrator-comb filter (CIC filter) as an example. At the output of the CIC filter, a multiplier is set, and its gain coefficient is , the input signal is the digital signal output by the CIC filter, and the output signal is the digital signal after gain compensation.

[0060] The performance of the traditional ΣΔ analog-to-digital converter model is verified. The input signals Vin=-1dBFs and Vin=0dBFs are used. The output results are processed by FFT. The results are as follows: Figure 4 As shown, when the input amplitude is slightly lower than the full amplitude, the system performance is good, the signal-to-noise ratio (SNR) reaches 102dB, the noise floor in the spectrum is low, and the spectrum line is smooth, indicating that the quantizer operates in the linear region. When the input amplitude reaches the full amplitude, the SNR drops sharply to 74dB, and a large amount of spurious noise appears in the spectrum. This is because part of the input of the quantizer exceeds the quantization level, resulting in performance degradation. The performance of the ΣΔ analog-to-digital converter model shown in the present invention is also verified. When the input signal Vin=0dBF, that is, the full amplitude input, the output result is processed by FFT, and the result is shown as follows Figure 5 As shown in the figure, when the input signal is close to the full swing, the SNR still remains at the 100dB level, the spectrum curve is smooth, there are no obvious harmonics and noise peaks, and the noise floor is low, indicating that the quantizer is not overloaded and operates stably.

[0061] Example 3, reference Figure 6 , which is an embodiment of the present invention, provides an attenuation compensation system for a signal transfer function in an analog-to-digital converter, including an analog signal pre-attenuation module 100, an analog-to-digital conversion execution module 200, and a digital domain gain compensation module 300.

[0062] Among them, S4: the analog signal pre-attenuation module 100 includes an integrator structure configuration submodule 101 and an attenuation gain parameter setting submodule 102. The integrator structure configuration submodule 101 is used to configure the feedback network structure of the first-stage integrator to achieve the target attenuation of the input signal. The attenuation gain parameter setting submodule 102 is used to set the gain parameter for controlling the attenuation amplitude, which is used as a digital compensation reference.

[0063] It should also be noted that the integrator structure configuration submodule 101 receives an external analog signal and outputs it to the attenuation gain parameter setting submodule 102 .

[0064] S5: The analog-to-digital conversion execution module 200 includes a sampling control submodule 201 and a quantization coding submodule 202. The sampling control submodule 201 is used to control the working rhythm of the quantizer according to the set sampling frequency. The quantization coding submodule 202 is used to receive the attenuated analog signal, perform amplitude comparison, determine the digital code according to the amplitude comparison result, and output the corresponding digital code stream.

[0065] It should also be noted that the sampling control submodule 201 outputs the timing control signal to the quantization coding submodule 202. The quantization coding submodule 202 receives the analog signal output from the pre-attenuation module 100 and the sampling timing signal from the sampling control submodule 201, and outputs the corresponding digital code stream.

[0066] S6: The digital domain gain compensation module 300 includes a digital extraction filter submodule 301 and a digital gain compensation submodule 302. The digital extraction filter submodule 301 is used to filter and extract the high sampling rate digital code stream and output a low-rate digital signal. The digital gain compensation submodule 302 is used to call the fixed gain factor corresponding to the analog attenuation parameter, perform multiplication operation on the low-rate digital signal, and realize signal amplitude recovery.

[0067] It should also be noted that the digital extraction and filtering submodule 301 receives the high sampling rate digital code stream output by the quantization and coding submodule 202, and outputs a low-rate digital signal to the digital gain compensation submodule 302. The digital gain compensation submodule 302 receives the low-rate digital signal from the digital extraction and filtering submodule 301, and combines it with the previously recorded attenuation parameters to output the final digital signal after amplitude restoration.

Claims

1. A method for compensating for attenuation of a signal transfer function in an analog-to-digital converter, characterized in that: include: Set the attenuation gain of the integrator to pre-attenuate the analog signal in the analog domain of the integrator; Perform analog-to-digital conversion on the pre-attenuated signal through a quantizer and output a digital code stream; Perform gain compensation on the digital bit stream in the digital domain and construct a digital domain recovery path corresponding to the analog domain attenuation parameter; The analog-to-digital conversion includes a quantizer pre-stage receiving an attenuated analog signal, periodically starting a sampling process under the control of an external sampling clock while maintaining signal continuity, comparing the amplitude of the analog signal with a set of reference levels, determining the amplitude range within which the analog signal falls, and generating a corresponding digital code value based on the range information, outputting the result as a continuous digital code stream; The digital domain recovery path includes setting the attenuation parameter in the analog domain, recording the attenuation parameter as a digital domain recovery reference value, and adjusting the amplitude of the digital signal according to the digital domain recovery reference value to obtain an output signal that matches the analog attenuation process; Setting the attenuation gain of the integrator includes selecting a first-stage integrator as an attenuation gain position in an analog loop filter of the ΣΔ analog-to-digital converter, setting a feedback network structure in the first-stage integrator, setting an attenuation coefficient by adjusting a parameter ratio between an integrating capacitor and a feedback capacitor, and performing amplitude scaling on an analog signal through the first-stage integrator to obtain an analog signal attenuated by the integrator; The analog-to-digital conversion of the pre-attenuated signal by the quantizer includes receiving the analog signal attenuated by the integrator at a front stage of the quantizer, maintaining the input continuity of the analog signal attenuated by the integrator, periodically triggering the quantizer to start a sampling process based on the sampling clock signal control, comparing the voltage amplitude of the analog signal attenuated by the integrator with a preset reference level during each sampling process, determining the interval in which the analog signal attenuated by the integrator is located based on the comparison result, obtaining a corresponding digital code value based on the interval in which the analog signal attenuated by the integrator is located, and outputting the digital code value as a digital code stream; The gain compensation of the digital code stream in the digital domain includes inputting the digital code stream into a digital extraction filter, filtering and data extraction processing the digital code stream to form a low-rate digital signal, providing a digital multiplication unit at the output end of the digital extraction filter, applying a fixed gain factor to the low-rate digital signal, and causing the digital multiplication unit to perform a fixed-value multiplication operation to obtain a digital signal.

2. The method for compensating for attenuation of a signal transfer function in an analog-to-digital converter according to claim 1, wherein: The feedback network structure includes constructing the integrator as a switched capacitor structure, setting a feedback capacitor in the feedback path, and setting an integrating capacitor in the integrating path. According to a preset attenuation gain coefficient, a target integrating capacitor parameter is calculated, and the capacitance value of the integrating capacitor is set to a preset multiple of the original design capacitance value.

3. The method for compensating for attenuation of a signal transfer function in an analog-to-digital converter according to claim 2, wherein: The quantizer includes, under the sampling control timing, periodically performing sampling operations according to the set sampling frequency, determining the corresponding digital code value in each sampling period based on the comparison result of the analog signal attenuated by the integrator and the reference level, and outputting the digital code values ​​obtained in consecutive sampling periods in sequence as a digital code stream.

4. The method for compensating for attenuation of a signal transfer function in an analog-to-digital converter according to claim 3, wherein: The digital decimation filter includes receiving a high-sampling-rate digital code stream output by a quantizer as a digital decimation filter input, sequentially performing integration operations on the input code stream, accumulating the bit stream generated by the quantizer to form a multi-bit numerical output, constructing an intermediate signal sequence, and based on the integration result, controlling the decimation logic to select the integration output once every fixed sampling period according to a set data decimation ratio to form a low-rate code stream, and performing differential calculations on the decimated code stream.

5. The method for compensating for attenuation of a signal transfer function in an analog-to-digital converter according to claim 4, wherein: The fixed gain factor is preset in the gain compensation path in the form of a parameter in the digital domain and is automatically activated after the decimation filtering is completed.

6. The method for compensating for attenuation of a signal transfer function in an analog-to-digital converter according to claim 5, wherein: The construction of a digital domain recovery path corresponding to the analog domain attenuation parameter includes, while setting the analog signal attenuation parameter, recording the attenuation parameter as a digital domain recovery reference value, and adjusting the amplitude of the digital signal based on the digital domain recovery reference value to obtain an output signal that matches the analog attenuation process.

7. A system using the attenuation compensation method for a signal transfer function in an analog-to-digital converter according to any one of claims 1 to 6, characterized in that: It includes an analog signal pre-attenuation module (100), an analog-to-digital conversion execution module (200), and a digital domain gain compensation module (300); The analog signal pre-attenuation module (100) comprises an integrator structure configuration submodule (101) and an attenuation gain parameter setting submodule (102), wherein the integrator structure configuration submodule (101) is used to configure the feedback network structure of the first-stage integrator to achieve the target attenuation of the input signal, and the attenuation gain parameter setting submodule (102) is used to set the gain parameter for controlling the attenuation amplitude, which is used as a digital compensation reference; The analog-to-digital conversion execution module (200) includes a sampling control submodule (201) and a quantization coding submodule (202). The sampling control submodule (201) is used to control the working rhythm of the quantizer according to the set sampling frequency. The quantization coding submodule (202) is used to receive the attenuated analog signal, perform amplitude comparison, determine the digital code according to the amplitude comparison result, and output the corresponding digital code stream. The digital domain gain compensation module (300) comprises a digital decimation filter submodule (301) and a digital gain compensation submodule (302). The digital decimation filter submodule (301) is used to filter and extract a high-sampling-rate digital code stream and output a low-rate digital signal. The digital gain compensation submodule (302) is used to call a fixed gain factor corresponding to an analog attenuation parameter and perform a multiplication operation on the low-rate digital signal to achieve signal amplitude recovery.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the processor implements the steps of the attenuation compensation method for a signal transfer function in an analog-to-digital converter according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for compensating for the attenuation of a signal transfer function in an analog-to-digital converter according to any one of claims 1 to 6 are implemented.

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