Circuit board and manufacturing method thereof

Abstract

A circuit board comprises an insulating metal substrate, a first electrode sintering layer, a lower sintering layer, a metal column, a chip and an upper sintering layer. The insulating metal substrate is provided with a first surface, a second surface, a first metal layer and a second metal layer. The first electrode sintering layer and the lower sintering layer are located on the first surface and electrically connected with the first metal layer. The metal columns are located on the lower sintering layer and electrically connected with the lower sintering layer. The chip is located on the first electrode sintering layer and comprises a body and a first electrode. The body has an upper surface and a lower surface. The first electrode is located on the lower surface and electrically connected with the first electrode sintering layer. The upper sintering layer is located on the metal columns and electrically connected with the metal columns. According to the circuit board, the reliability and the product yield can be improved, and the manufacturing cost can be reduced.

Description

Technical Field

[0001] The present invention relates to a circuit board and a manufacturing method thereof, and in particular to a circuit board including a chip and a manufacturing method thereof. Background Art

[0002] Currently, power chips are often packaged in power modules using wire bonding. However, power modules or power circuit boards may need to be used in high-frequency switching products, but wire bonding packaging is prone to parasitic inductance and cannot meet high-frequency switching requirements. Furthermore, the ceramic substrates used for insulation and thermal conductivity in typical power module packaging are expensive, further increasing manufacturing costs. Summary of the Invention

[0003] The object of the present invention is to provide a circuit board including a chip, which can avoid parasitic inductance, reduce electrical resistance and thermal resistance, improve reliability and product yield, and reduce manufacturing costs.

[0004] Another object of the present invention is to provide a method for manufacturing the above-mentioned circuit board to help improve the reliability and product yield of the above-mentioned circuit board and reduce manufacturing costs.

[0005] At least one embodiment of the present invention provides a circuit board comprising an insulated metal substrate, a first electrode sintered layer, a lower sintered layer, a metal pillar, a chip, and an upper sintered layer. The insulated metal substrate has a first surface and a second surface opposite the first surface, and comprises a first metal layer and a second metal layer, wherein the first metal layer has a first surface and the second metal layer has a second surface. The first electrode sintered layer is disposed on the first surface and electrically connected to the first metal layer. The lower sintered layer is disposed on the first surface and electrically connected to the first metal layer. The metal pillar is disposed on the lower sintered layer and electrically connected to the lower sintered layer. The chip is disposed on the first electrode sintered layer and comprises a body and a first electrode. The body has an upper surface and a lower surface opposite the upper surface. The first electrode is disposed on the lower surface and electrically connected to the first electrode sintered layer, and is electrically connected to the metal pillar through the first metal layer. The upper sintered layer is disposed on the metal pillar and electrically connected to the metal pillar.

[0006] In at least one embodiment of the present invention, the chip further includes a second electrode and a third electrode arranged on the upper surface, and the circuit board further includes a second electrode sintered layer and a third electrode sintered layer, the second electrode sintered layer is arranged on the second electrode and electrically connected to the second electrode, and the third electrode sintered layer is arranged on the third electrode and electrically connected to the third electrode.

[0007] In at least one embodiment of the present invention, the thickness of each of the first electrode, the second electrode, and the third electrode is not less than 100 μm.

[0008] In at least one embodiment of the present invention, the circuit board further includes a first electrode pad, a second electrode pad, and a third electrode pad. The first electrode pad is disposed on the upper sintered layer and electrically connected to the upper sintered layer. The second electrode pad is disposed on the second electrode sintered layer and electrically connected to the second electrode sintered layer. The third electrode pad is disposed on the third electrode sintered layer and electrically connected to the third electrode sintered layer.

[0009] In at least one embodiment of the present invention, the circuit board further includes an adhesive layer disposed between the first metal layer and the first electrode pad, the second electrode pad, and the third electrode pad.

[0010] In at least one embodiment of the present invention, the XY-axis thermal expansion coefficient of the adhesive layer is between 9 ppm / °C and 10 ppm / °C.

[0011] In at least one embodiment of the present invention, the thickness of the first metal layer is smaller than the thickness of the second metal layer.

[0012] In at least one embodiment of the present invention, the thickness of the first metal layer is between 35 μm and 210 μm.

[0013] In at least one embodiment of the present invention, the thickness of the second metal layer is between 500 μm and 2000 μm.

[0014] At least one embodiment of the present invention provides a method for manufacturing a circuit board, comprising providing an insulated metal substrate having a first surface and a second surface opposite the first surface, and comprising a first metal layer and a second metal layer, the first metal layer having a first surface and the second metal layer having a second surface. A first electrode sintered layer is formed on the first surface and electrically connected to the first metal layer. A lower sintered layer is formed on the first surface and electrically connected to the first metal layer. A metal post is fixedly disposed on the lower sintered layer and electrically connected to the lower sintered layer. A chip is provided, comprising a body, a first electrode, a second electrode, and a third electrode. The body has an upper surface and a lower surface opposite the upper surface, the first electrode is disposed on the lower surface, the second electrode is disposed on the upper surface, and the third electrode is disposed on the upper surface. The first electrode of the chip is fixedly disposed on the first electrode sintered layer and electrically connected to the first electrode sintered layer. A first sub-glue layer is provided, the first sub-glue layer having a plurality of first grooves corresponding to the metal post and the chip, respectively. After the metal post is fixed to the lower sintered layer and the first electrode of the chip is fixed to the first electrode sintered layer, the first sub-glue layer is pressed onto the first surface. After the first sub-glue layer is laminated onto the first surface, a portion of the first sub-glue layer is removed to expose the metal pillar, the second electrode, and the third electrode. A second electrode sintered layer is formed on the second electrode and electrically connected to the second electrode. A third electrode sintered layer is formed on the third electrode and electrically connected to the third electrode. An upper sintered layer is formed on the metal pillar and electrically connected to the metal pillar. A second sub-glue layer is provided, the second sub-glue layer having a plurality of second grooves corresponding to the second electrode sintered layer, the third electrode sintered layer, and the upper sintered layer, respectively. A core board is provided, the core board comprising a third sub-glue layer and an electrode layer formed on and passing through the third sub-glue layer. After the second electrode sintered layer, the third electrode sintered layer, and the upper sintered layer are formed, the core board, the second sub-glue layer, and the first sub-glue layer are laminated, and the third sub-glue layer, the second sub-glue layer, and the first sub-glue layer form a glue layer. The electrode layer is patterned to form a first electrode pad, a second electrode pad, and a third electrode pad, which are electrically connected to the upper sintered layer, the second electrode sintered layer, and the third electrode sintered layer, respectively.

[0015] In at least one embodiment of the present invention, the chip manufacturing method includes fixing a wafer on a first carrier. Forming a first conductive layer on the wafer. After forming the first conductive layer on the wafer, removing the first carrier and cutting the wafer to form a plurality of dies, each of which includes an initial second electrode and an initial third electrode formed by the first conductive layer. Providing a second carrier, and forming a plurality of conductive pillars on the second carrier. Fixing a plurality of dies on the second carrier, the plurality of dies and the plurality of conductive pillars are staggered. Forming a second conductive layer on the plurality of dies and the plurality of conductive pillars, each of which includes a second electrode formed by the initial second electrode and the second conductive layer, an initial third electrode, and a third electrode formed by the conductive pillars and the second conductive layer. Removing the second carrier. Forming a third conductive layer on the surface of each dies exposed after removing the second carrier, each of which includes a first electrode formed by the third conductive layer. Separating the plurality of dies to form a plurality of chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 4 is a partial cross-sectional schematic diagram of a circuit board according to at least one embodiment of the present invention.

[0017] Figures 2A to 2G 1 is a partial cross-sectional view of a circuit board at different process stages according to at least one embodiment of the present invention.

[0018] Figures 3A to 3O 1 is a partial cross-sectional view of a chip at different process stages according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0019] In the following text, in order to clearly present the technical features of the present invention, the dimensions (such as length, width, thickness and depth) of the elements (such as layers, films, substrates and regions, etc.) in the drawings will be enlarged in a non-proportional manner, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes and deviations thereof caused by actual processes and / or tolerances. For example, the flat surfaces shown in the drawings may have rough and / or nonlinear features, while the sharp angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of the rights of the present invention.

[0020] Secondly, the terms "approximately," "approximately," or "substantially" used in this disclosure encompass not only the explicitly stated values and ranges of values, but also the permissible deviations understood by those skilled in the art. This deviation may be determined by measurement errors, such as those arising from limitations of the measurement system or process conditions. For example, when two objects (e.g., planes or traces on a substrate) are "substantially parallel" or "substantially perpendicular," "substantially parallel" and "substantially perpendicular," respectively, mean that the parallelism and perpendicularity between the two objects may include non-parallelism and non-perpendicularity resulting from the permissible deviations.

[0021] Spatially relative terms used in this disclosure, such as "below," "under," "above," and "on," are intended to facilitate description of the relative relationship between one element or feature and another, as depicted in the figures. The true meaning of these spatially relative terms encompasses other orientations. For example, when a figure is flipped 180 degrees, the relationship between one element and another may change from "below" or "under" to "above" or "on." Furthermore, spatially relative descriptions used in this disclosure should be interpreted similarly.

[0022] It should be understood that although the present invention may use terms such as "first," "second," and "third" to describe various elements or features, these elements or features should not be limited by these terms. These terms are primarily used to distinguish one element from another, or one feature from another. In addition, the term "or" used in the present invention may include any one or more combinations of the associated listed items, depending on the actual situation.

[0023] Although a series of operations or steps are used to illustrate the manufacturing method in the present invention, the order in which these operations or steps are shown should not be construed as limiting the present invention. For example, certain operations or steps may be performed in different orders and / or simultaneously with other steps. In addition, each operation or step described herein may include several sub-steps or actions.

[0024] In addition, the present invention may be implemented or applied through other different specific embodiments, and the details of the present invention may also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.

[0025] Figure 1 FIG is a partial cross-sectional view of a circuit board according to at least one embodiment of the present invention. Figure 1The circuit board 1 includes an insulated metal substrate 10, a first electrode sintered layer 11, a lower sintered layer 12, a metal pillar 13, a chip 14, and an upper sintered layer 17. The insulated metal substrate 10 has a first surface S1 and a second surface S2 opposite to the first surface S1, and includes a first metal layer 101 and a second metal layer 102. The first metal layer 101 has a first surface S1, and the second metal layer 102 has a second surface S2. The first electrode sintered layer 11 is disposed on the first surface S1 and electrically connected to the first metal layer 101. The lower sintered layer 12 is disposed on the first surface S1 and electrically connected to the first metal layer 101. The metal pillar 13 is disposed on the lower sintered layer 12 and electrically connected to the lower sintered layer 12.

[0026] Chip 14 is disposed on first electrode sintered layer 11 and includes a body 141 and a first electrode 142. Body 141 has an upper surface US and a lower surface LS opposite upper surface US. First electrode 142 is disposed on lower surface LS and electrically connected to first electrode sintered layer 11. It is also electrically connected to metal pillar 13 via first metal layer 101. Upper sintered layer 17 is disposed on metal pillar 13 and electrically connected to metal pillar 13.

[0027] The first electrode 142 of the chip 14 is electrically connected to the first metal layer 101 of the insulated metal substrate 10 via the first electrode sintered layer 11, which helps dissipate heat. The first electrode 142 on the lower surface LS is then transferred to the upper side via the lower sintered layer 12, metal pillars 13, and upper sintered layer 17, all electrically connected to the first metal layer 101. The use of sintered layers instead of wire bonds or through-hole vias avoids parasitic inductance and reduces electrical and thermal resistance, thereby improving reliability and product yield. Furthermore, the use of an insulated metal substrate instead of a ceramic substrate reduces manufacturing costs.

[0028] like Figure 1 As shown, the chip 14 further includes a second electrode 143 and a third electrode 144. The second electrode 143 is disposed on the upper surface US. The third electrode 144 is disposed on the upper surface US. The circuit board 1 further includes a second electrode sintered layer 15 and a third electrode sintered layer 16. The second electrode sintered layer 15 is disposed on the second electrode 143 and electrically connected to the second electrode 143. The third electrode sintered layer 16 is disposed on the third electrode 144 and electrically connected to the third electrode 144.

[0029] The circuit board 1 further includes a first electrode pad 18, a second electrode pad 19, and a third electrode pad 20. The first electrode pad 18 is disposed on and electrically connected to the upper sintered layer 17. The second electrode pad 19 is disposed on and electrically connected to the second electrode sintered layer 15. The third electrode pad 20 is disposed on and electrically connected to the third electrode sintered layer 16. Furthermore, the circuit board 1 further includes an adhesive layer 21 disposed between the first metal layer 101 and the first electrode pad 18, the second electrode pad 19, and the third electrode pad 20.

[0030] In some embodiments, the thermal conductivity of the insulated metal substrate 10 is 15.5 W / mK. In some embodiments, the thickness of the first metal layer 101 is less than the thickness of the second metal layer 102. For example, the thickness of the first metal layer 101 is between 35 μm and 210 μm (inclusive), and the thickness of the second metal layer 102 is between 500 μm and 2000 μm (inclusive). In some embodiments, the XY-axis thermal expansion coefficient of the adhesive layer 21 is between 9 ppm / °C and 10 ppm / °C (inclusive). In addition, the insulated metal substrate 10 further includes a substrate 103, the first metal layer 101 and the second metal layer 102 are respectively formed on two opposite surfaces of the substrate 103, and the thickness of the substrate 103 is between 100 μm and 175 μm (inclusive).

[0031] The physical properties of the insulating metal substrate 10 and the adhesive layer 21, as well as the thickness design of each layer of the insulating metal substrate 10, can help dissipate heat and prevent deformation under high temperature conditions when forming a sintering layer, thereby improving reliability and product yield.

[0032] Please continue reading Figure 1 The first metal layer 101 has a through-hole O, in which a filler material F is disposed. Through the aforementioned structural design, a portion of the first metal layer 101 can serve as an electrical connection layer between the first electrode sintered layer 11 and the lower sintered layer 12, while another portion of the first metal layer 101, separated by the through-hole O, can be used for other circuits, such as a power supply circuit. Furthermore, disposing the filler material F in the through-hole O to fill it provides a smooth surface for improved adhesion when the adhesive layer 21 is subsequently applied, thereby improving product yield.

[0033] In some embodiments, the first electrode sintering layer 11 and the lower sintering layer 12 are disposed on the first surface S1 and directly contact the first metal layer 101. The first electrode 142 of the chip 14 is disposed on the first electrode sintering layer 11 and directly contact the first electrode sintering layer 11. The metal pillar 13 is disposed on the lower sintering layer 12 and directly contact the lower sintering layer 12. The upper sintering layer 17 is disposed on the metal pillar 13 and directly contact the metal pillar 13. The first electrode pad 18 is disposed on the upper sintering layer 17 and directly contact the upper sintering layer 17. Therefore, the first electrode 142 of the chip 14 receives an external signal through the first electrode sintering layer 11, the first metal layer 101, the lower sintering layer 12, the metal pillar 13, the upper sintering layer 17, and the first electrode pad 18.

[0034] Furthermore, the second electrode sintering layer 15 and the third electrode sintering layer 16 are disposed on the second electrode 143 and the third electrode 144, respectively, and directly contact the second electrode 143 and the third electrode 144, respectively. The second electrode pad 19 and the third electrode pad 20 are disposed on the second electrode sintering layer 15 and the third electrode sintering layer 16, respectively, and directly contact the second electrode sintering layer 15 and the third electrode sintering layer 16, respectively. Therefore, the second electrode 143 and the third electrode 144 of the chip 14 receive external signals through the second electrode sintering layer 15 and the third electrode sintering layer 16, and the second electrode pad 19 and the third electrode pad 20, respectively.

[0035] In some embodiments, the chip 14 may be a power chip, such as a power semiconductor device. For example, the chip 14 may be a silicon carbide power device, and the first electrode 142 , the second electrode 143 , and the third electrode 144 may be the drain, source, and gate of the chip 14 , respectively.

[0036] Figures 2A to 2G is a partial cross-sectional view of a circuit board in different process stages according to at least one embodiment of the present invention. Figures 2A to 2C , providing an insulating metal substrate 10, the insulating metal substrate 10 has a first surface S1 and a second surface S2 opposite to the first surface S1, and includes a first metal layer 101 and a second metal layer 102, the first metal layer 101 has a first surface S1, and the second metal layer 102 has a second surface S2.

[0037] In detail, first, Figure 2A As shown, an initial substrate 10' is provided, and the initial substrate 10' comprises a substrate 103 and an initial first metal layer 101' and a second metal layer 102 respectively disposed on two opposite surfaces of the substrate 103. Figure 2B As shown, the initial first metal layer 101' is patterned to form a first metal layer 101 having a through hole O. Figure 2C As shown, a filling material F is formed in the through-hole O to form the insulated metal substrate 10 .

[0038] In some embodiments, the material of substrate 103 may include a resin, such as prepreg. The materials of initial first metal layer 101' and second metal layer 102 may include copper. The material of filler material F may include ink. Furthermore, first metal layer 101 having through-holes O may be formed by patterning initial first metal layer 101' via an etching process, while filler material F may be formed via a printing and baking process.

[0039] See also Figure 2D First, a first electrode sintered layer 11 is formed on the first surface S1 and electrically connected to the first metal layer 101. A lower sintered layer 12 is formed on the first surface S1 and electrically connected to the first metal layer 101. Next, a metal pillar 13 is fixed on the lower sintered layer 12 and electrically connected to the lower sintered layer 12. A chip 14 is provided. The chip 14 includes a body 141, a first electrode 142, a second electrode 143, and a third electrode 144. The body 141 has an upper surface US and a lower surface LS opposite to the upper surface US. The first electrode 142 is disposed on the lower surface LS, the second electrode 143 is disposed on the upper surface US, and the third electrode 144 is disposed on the upper surface US. The first electrode 142 of the chip 14 is fixed on the first electrode sintered layer 11 and electrically connected to the first electrode sintered layer 11. In some embodiments, the material of the metal pillar 13 may include copper.

[0040] See also Figure 2E A first sub-glue layer 211 is provided. The first sub-glue layer 211 has a plurality of first grooves G1 corresponding to the metal pillars 13 and the chip 14, respectively. After the metal pillars 13 are fixed to the lower sintering layer 12 and the first electrodes 142 of the chip 14 are fixed to the first electrode sintering layer 11, the first sub-glue layer 211 is pressed onto the first surface S1. A portion of the first sub-glue layer 211 is removed to expose the metal pillars 13, the second electrodes 143, and the third electrodes 144.

[0041] In detail, Figure 2E As shown, the metal pillars 13 and the chip 14 are respectively located within the multiple orthographic projection areas of the multiple first grooves G1 of the first sub-glue layer 211 on the insulated metal substrate 10. In other words, the multiple orthographic projection areas of the multiple first grooves G1 of the first sub-glue layer 211 on the insulated metal substrate 10 overlap with the metal pillars 13 and the chip 14, respectively. In some embodiments, the diameter of the first groove G1 corresponding to the chip 14 is larger than the diameter of the chip 14, and the difference between the two is not less than 0.3 mm. In addition, in some embodiments, a portion of the first sub-glue layer 211 can be removed by a grinding process to expose the metal pillars 13, the second electrode 143, and the third electrode 144.

[0042] See also Figure 2FA second electrode sintered layer 15 is formed on the second electrode 143 and electrically connected to the second electrode 143. A third electrode sintered layer 16 is formed on the third electrode 144 and electrically connected to the third electrode 144. An upper sintered layer 17 is formed on the metal pillar 13 and electrically connected to the metal pillar 13.

[0043] like Figure 2F As shown, a second sub-glue layer 212 is provided, and the second sub-glue layer 212 has a plurality of second grooves G2 corresponding to the second electrode sintered layer 15, the third electrode sintered layer 16, and the upper sintered layer 17. A core board B is provided, and the core board B includes a third sub-glue layer 213 and an electrode layer M formed on and passing through the third sub-glue layer 213.

[0044] Specifically, the second electrode sintering layer 15, the third electrode sintering layer 16, and the upper sintering layer 17 are respectively located within the orthographic projection areas of the plurality of second grooves G2 of the second sub-glue layer 212 on the insulated metal substrate 10. In other words, the orthographic projection areas of the plurality of second grooves G2 of the second sub-glue layer 212 on the insulated metal substrate 10 overlap with the second electrode sintering layer 15, the third electrode sintering layer 16, and the upper sintering layer 17. In some embodiments, the diameters of the plurality of second grooves G2 corresponding to the second electrode sintering layer 15, the third electrode sintering layer 16, and the upper sintering layer 17 are respectively larger than the diameters of the second electrode sintering layer 15, the third electrode sintering layer 16, and the upper sintering layer 17, and the difference between the two diameters is not less than 0.2 mm.

[0045] See also Figure 2G After forming the second electrode sintering layer 15 , the third electrode sintering layer 16 and the upper sintering layer 17 , the core board B, the second sub-glue layer 212 and the first sub-glue layer 211 , the third sub-glue layer 213 , the second sub-glue layer 212 and the first sub-glue layer 211 are pressed together to form the glue layer 21 .

[0046] like Figure 1 As shown, the electrode layer M is patterned to form a first electrode pad 18 , a second electrode pad 19 and a third electrode pad 20 , which are electrically connected to the upper sintering layer 17 , the second electrode sintering layer 15 and the third electrode sintering layer 16 , respectively.

[0047] In some embodiments, the material of the first electrode sintering layer 11, the lower sintering layer 12, the second electrode sintering layer 15, the third electrode sintering layer 16, and the upper sintering layer 17 may include silver paste or copper paste, and its thermal conductivity may be, for example, 150 W / mK. The first electrode sintering layer 11, the lower sintering layer 12, the second electrode sintering layer 15, the third electrode sintering layer 16, and the upper sintering layer 17 may be formed by a printing process, a baking process, and a lamination process.

[0048] For example, the first electrode sintered layer 11 and the lower sintered layer 12 can be pressed at a temperature of 250°C and a pressure of 10 MPa. The thicknesses of the first electrode sintered layer 11 and the lower sintered layer 12 before the pressing process can each be 100 μm, and after the pressing process, the thicknesses can each be 30 μm to 40 μm (inclusive). The second electrode sintered layer 15, the third electrode sintered layer 16, and the upper sintered layer 17 can be pressed at a temperature of 220°C and a pressure of 4 MPa. The thicknesses of the second electrode sintered layer 15, the third electrode sintered layer 16, and the upper sintered layer 17 before the pressing process can each be 125 μm, and after the pressing process, the thicknesses can each be 100 μm.

[0049] Therefore, the pressing temperature and pressure for the second electrode sintering layer 15, the third electrode sintering layer 16, and the upper sintering layer 17 are lower than the pressing temperature and pressure for the first electrode sintering layer 11 and the lower sintering layer 12. Through the aforementioned process design, the first electrode sintering layer 11 and the lower sintering layer 12 can be made thinner and have a smoother surface to facilitate the mounting of the chip 14 and the metal pillars 13. After the chip 14 is mounted, the second electrode sintering layer 15, the third electrode sintering layer 16, and the upper sintering layer 17 are formed using a pressing process with lower pressing temperature and pressure, which prevents damage to the chip 14 and thereby improves product yield.

[0050] In some embodiments, the material of the first sub-glue layer 211, the second sub-glue layer 212, and the third sub-glue layer 213 may include a resin, such as a film. The material of the electrode layer M may include a metal, such as copper. Furthermore, the electrode layer M may be formed by an electroplating process, while the first electrode pad 18, the second electrode pad 19, and the third electrode pad 20 may be formed by patterning the electrode layer M by an etching process.

[0051] Figures 3A to 3O is a partial cross-sectional view of a chip at different process stages according to at least one embodiment of the present invention. Figure 3A , the wafer W is fixed on the first carrier C1. Specifically, the wafer W is fixed on the first carrier C1 by the first adhesive layer A1. Figure 3B , forming a first conductive layer M1 on the wafer W. Figure 3C and Figure 3D After forming the first conductive layer M1 on the wafer W, the first carrier C1 is removed and the wafer W is cut to form a plurality of dies C. Each die C includes an initial second electrode 143 ′ and an initial third electrode 144 ′ formed of the first conductive layer M1 .

[0052] In detail, Figure 3C As shown, a first adhesive material F1 is formed on the first conductive layer M1, and the first adhesive material F1 covers the first conductive layer M1 and the wafer W. Figure 3DAs shown, after removing the first carrier C1 and the first adhesive layer A1, the wafer W is cut into a plurality of dies C. The dies C include initial second electrodes 143' and initial third electrodes 144' formed from the first conductive layer M1. In some embodiments, the thickness of the initial second electrodes 143' and the initial third electrodes 144' are each approximately 30 μm.

[0053] See also Figure 3E , providing a second carrier C2, and forming a plurality of conductive pillars P on the second carrier C2. Figure 3F , multiple dies C are fixed on a second carrier C2, with the dies C and the conductive pillars P interlaced. Specifically, the dies C are fixed to the second carrier C2 via a second adhesive layer A2, with the dies C and the conductive pillars P interlaced in a direction perpendicular to the normal of the second carrier C2. In some embodiments, the conductive pillars P have a height of approximately 150 μm.

[0054] See also Figure 3G to Figure 3I , forming a second conductive layer M2 on multiple grains C and multiple conductive pillars P, each grain C includes a second electrode 143 and an initial third electrode 144' formed by the initial second electrode 143' and the second conductive layer M2, and a third electrode 144 formed by each conductive pillar P and the second conductive layer M2.

[0055] In detail, first, Figure 3G As shown, the second adhesive material F2 is formed on the plurality of crystal grains C and the plurality of conductive pillars P, and the second adhesive material F2 covers the plurality of crystal grains C and the plurality of conductive pillars P. Figure 3H As shown, a portion of the first adhesive F1 and a portion of the second adhesive F2 are removed to expose the conductive pillars P, the initial second electrodes 143 ′, and the initial third electrodes 144 ′.

[0056] Then, if Figure 3I As shown, a second conductive layer M2 is formed on the die C and the conductive pillar P. The die C includes a second electrode 143 and a third electrode 144' formed by an initial second electrode 143' and the second conductive layer M2, and a third electrode 144 formed by the conductive pillar P and the second conductive layer M2. In some embodiments, the thickness of the second conductive layer M2 is about 100 μm.

[0057] However, it is worth noting that in order to make the expression of the drawings more concise, Figures 3I to 3N Only one die C and one conductive pillar P are shown. It is understandable that other die C and conductive pillars P may be included in areas not shown in the drawings.

[0058] See also Figures 3J to 3L , remove the second carrier C2. Specifically, first, as Figure 3JAs shown, a third adhesive material F3 is formed on the second conductive layer M2, and the third adhesive material F3 covers the second conductive layer M2. Figure 3K As shown, a portion of the third adhesive F3 is removed to expose the second conductive layer M2. Figure 3L As shown, the second carrier C2 and the second adhesive layer A2 are removed to expose the surface ES of each die C.

[0059] See also Figure 3M A third conductive layer M3 is formed on the surface ES of each die C exposed after the second carrier C2 is removed. Each die C includes a first electrode 142 formed by the third conductive layer M3. In some embodiments, the thickness of the third conductive layer M3 is about 100 μm.

[0060] See also Figure 3N and Figure 3O , separate the plurality of crystal grains C to form a plurality of chips 14. Specifically, first, as Figure 3N As shown, a fourth adhesive material F4 is formed on the third conductive layer M3, and the fourth adhesive material F4 covers the third conductive layer M3. Figure 3O As shown, a portion of the fourth adhesive F4 is removed to expose the third conductive layer M3 , and then the plurality of die C are separated to form a plurality of chips 14 .

[0061] In some embodiments, the material of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the conductive pillars P may include a metal, such as copper. The first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the conductive pillars P may be formed by an electroplating process. The material of the first adhesive F1, the second adhesive F2, the third adhesive F3, and the fourth adhesive F4 may include a resin, such as a film. Furthermore, a grinding process may be used to remove portions of the first adhesive F1, the second adhesive F2, the third adhesive F3, and the fourth adhesive F4.

[0062] Through the above Figures 3A to 3O In the manufacturing method of the chip 14, the first electrode 142, the second electrode 143 and the third electrode 144 are formed by a redistribution process. In detail, the thickness of the first electrode 142, the second electrode 143 and the third electrode 144 can be increased by forming the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3. For example, the thickness of the first electrode 142, the second electrode 143 and the third electrode 144 can be increased to not less than 100μm. In addition, the area of the third electrode 144 can be increased by forming the conductive pillar P and the second conductive layer M2. For example, the area of the third electrode 144 can be increased by 2 times to 5 times (including the end value). Therefore, it can help dissipate heat and reduce the risk of alignment deviation, thereby improving reliability and product yield.

[0063] In summary, in at least one embodiment of the present invention, the circuit board and its manufacturing method utilize a sintered layer instead of wire bonding or through-hole vias, thereby avoiding parasitic inductance and reducing electrical and thermal resistance, thereby improving reliability and product yield. Furthermore, the use of an insulated metal substrate instead of a ceramic substrate reduces manufacturing costs. Furthermore, the use of a redistribution process to form the chip's electrodes facilitates heat dissipation and reduces the risk of misalignment, thereby improving reliability and product yield.

[0064] Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Those skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended claims.

[0065]

Explanation of symbols

[0066] 1: Circuit board

[0067] 10: Insulated metal substrate

[0068] 10': Initial substrate

[0069] 101: First metal layer

[0070] 101': Initial first metal layer

[0071] 102: Second metal layer

[0072] 103: Base material

[0073] 11: First electrode sintering layer

[0074] 12: Lower sintering layer

[0075] 13:Metal column

[0076] 14: Chip

[0077] 141:Ontology

[0078] 142: first electrode

[0079] 143: Second electrode

[0080] 143': Initial second electrode

[0081] 144: Third electrode

[0082] 144': Initial third electrode

[0083] 15: Second electrode sintering layer

[0084] 16: Third electrode sintering layer

[0085] 17: Upper sintering layer

[0086] 18: First electrode pad

[0087] 19: Second electrode pad

[0088] 20: Third electrode pad

[0089] 21: Adhesive layer

[0090] 211: first sub-layer

[0091] 212: Second sub-layer

[0092] 213: The third sub-layer

[0093] A1: First adhesive layer

[0094] A2: Second adhesive layer

[0095] B: Core board

[0096] C: Grain

[0097] C1: First carrier board

[0098] C2: Second carrier board

[0099] ES: Surface

[0100] F: Filling material

[0101] F1: First rubber material

[0102] F2: Second adhesive

[0103] F3: The third adhesive

[0104] F4: The fourth adhesive

[0105] G1: First slot

[0106] G2: Second slot

[0107] LS: Lower surface

[0108] M: electrode layer

[0109] M1: first conductive layer

[0110] M2: second conductive layer

[0111] M3: The third conductive layer

[0112] O: Perforation

[0113] P: Conductive column

[0114] S1: First surface

[0115] S2: Second surface

[0116] US: Upper surface

[0117] W: Wafer.

Claims

1. A circuit board, characterized in that: include: an insulated metal substrate having a first surface and a second surface opposite to the first surface, and comprising a first metal layer and a second metal layer, wherein the first metal layer has the first surface, and the second metal layer has the second surface; a first electrode sintered layer, disposed on the first surface and electrically connected to the first metal layer; a lower sintered layer, disposed on the first surface and electrically connected to the first metal layer; a metal column, disposed on the lower sintered layer and electrically connected to the lower sintered layer; A chip is disposed on the first electrode sintered layer and includes: a body having an upper surface and a lower surface opposite to the upper surface; and a first electrode disposed on the lower surface and electrically connected to the first electrode sintered layer, and electrically connected to the metal pillar through the first metal layer; and The upper sintering layer is disposed on the metal pillar and electrically connected to the metal pillar.

2. The circuit board according to claim 1, wherein: The chip also includes a second electrode and a third electrode arranged on the upper surface, and the circuit board also includes a second electrode sintered layer and a third electrode sintered layer, wherein the second electrode sintered layer is arranged on the second electrode and electrically connected to the second electrode, and the third electrode sintered layer is arranged on the third electrode and electrically connected to the third electrode.

3. The circuit board according to claim 2, wherein: The thickness of each of the first electrode, the second electrode, and the third electrode is not less than 100 μm.

4. The circuit board according to claim 2, wherein: Also includes: a first electrode pad, disposed on the upper sintered layer and electrically connected to the upper sintered layer; a second electrode pad, disposed on the second electrode sintered layer and electrically connected to the second electrode sintered layer; as well as The third electrode pad is disposed on the third electrode sintered layer and electrically connected to the third electrode sintered layer.

5. The circuit board according to claim 4, characterized in that It also includes an adhesive layer disposed between the first metal layer and the first electrode pad, the second electrode pad, and the third electrode pad.

6. The circuit board according to claim 5, characterized in that The XY-axis thermal expansion coefficient of the adhesive layer is between 9 ppm / °C and 10 ppm / °C.

7. The circuit board according to claim 1, wherein: The thickness of the first metal layer is smaller than that of the second metal layer.

8. The circuit board according to claim 7, wherein: The thickness of the first metal layer is between 35 μm and 210 μm.

9. The circuit board according to claim 7, wherein: The thickness of the second metal layer is between 500 μm and 2000 μm.

10. A method for manufacturing a circuit board, characterized in that: include: Providing an insulated metal substrate, wherein the insulated metal substrate has a first surface and a second surface opposite to the first surface, and includes a first metal layer and a second metal layer, the first metal layer has the first surface, and the second metal layer has the second surface; forming a first electrode sintered layer on the first surface and electrically connected to the first metal layer; forming a lower sintered layer on the first surface and electrically connected to the first metal layer; Fixing a metal column on the lower sintered layer and electrically connecting the metal column to the lower sintered layer; A chip is provided, wherein the chip comprises: a body having an upper surface and a lower surface opposite to the upper surface; a first electrode disposed on the lower surface; a second electrode disposed on the upper surface; and a third electrode disposed on the upper surface; Fixing the first electrode of the chip on the first electrode sintered layer and electrically connecting the first electrode sintered layer; Providing a first sub-glue layer, wherein the first sub-glue layer has a plurality of first grooves corresponding to the metal pillars and the chip respectively; After the metal pillar is fixed on the lower sintered layer and the first electrode of the chip is fixed on the first electrode sintered layer, pressing the first sub-glue layer onto the first surface; After the first sub-glue layer is laminated on the first surface, a portion of the first sub-glue layer is removed to expose the metal pillar, the second electrode, and the third electrode; forming a second electrode sintered layer on the second electrode and electrically connecting the second electrode; forming a third electrode sintered layer on the third electrode and electrically connecting the third electrode; forming an upper sintering layer on the metal pillar and electrically connecting the metal pillar; Providing a second sub-glue layer, wherein the second sub-glue layer has a plurality of second grooves corresponding to the second electrode sintering layer, the third electrode sintering layer and the upper sintering layer respectively; Providing a core board, the core board including a third sub-glue layer and an electrode layer formed on and passing through the third sub-glue layer; After forming the second electrode sintering layer, the third electrode sintering layer and the upper sintering layer, pressing the core board, the second sub-glue layer and the first sub-glue layer, wherein the third sub-glue layer, the second sub-glue layer and the first sub-glue layer form a glue layer; and The electrode layer is patterned to form a first electrode pad, a second electrode pad, and a third electrode pad, which are electrically connected to the upper sintering layer, the second electrode sintering layer, and the third electrode sintering layer respectively.

11. The method for manufacturing a circuit board according to claim 10, wherein: The chip manufacturing method includes: Fixing the wafer on the first carrier; forming a first conductive layer on the wafer; After forming the first conductive layer on the wafer, removing the first carrier and dicing the wafer to form a plurality of dies, wherein each of the dies includes an initial second electrode and an initial third electrode formed by the first conductive layer; Providing a second carrier, and forming a plurality of conductive pillars on the second carrier; Fixing the plurality of dies on the second carrier, wherein the plurality of dies and the plurality of conductive pillars are arranged alternately; forming a second conductive layer on the plurality of crystal grains and the plurality of conductive pillars, wherein each crystal grain includes a second electrode formed by the initial second electrode and the second conductive layer, and a third electrode formed by the initial third electrode, the conductive pillar, and the second conductive layer; removing the second carrier board; forming a third conductive layer on a surface of each die exposed after the second carrier is removed, wherein each die includes a first electrode formed by the third conductive layer; and The plurality of dies are separated to form a plurality of chips.

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