Three-dimensional memory device with contact plug and method of manufacturing same

Abstract

The invention relates to a three-dimensional memory device with contact plugs and a method of manufacturing the same. A semiconductor device includes: a laminate including a plurality of electrode layers and a plurality of interlayer insulating layers alternately laminated on a substrate; a contact plug including a pad portion disposed in the same layer as one of the plurality of electrode layers and a pillar portion extending to the pad portion by penetrating through the laminate; a spacer surrounding a side surface of the pillar portion; and a hard mask pattern disposed between the electrode layers around the spacer.

Description

Technical Field

[0001] Various embodiments of the disclosed technology relate generally to semiconductor technology, and more particularly, to a three-dimensional memory device with contact plugs and a method of manufacturing the same. Background Art

[0002] Compared to conventional devices, three-dimensional memory devices have the advantage of achieving greater capacity within the same area by increasing the number of stacks and vertically stacking memory cells, thereby providing high performance and excellent power efficiency.

[0003] In three-dimensional memory devices, electrode layers connected to memory cells are arranged at different heights. To independently apply electrical signals to the electrode layers at different heights, contact plugs are connected to the corresponding electrode layers. To this end, methods have been studied to form contact plugs that extend to the electrode layers by penetrating the stack. Summary of the Invention

[0004] In an embodiment, a three-dimensional memory device may include: a stack including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked on a substrate; a contact plug including a pad portion disposed in the same layer as one of the plurality of electrode layers and a pillar portion penetrating the stack and extending to the pad portion; a spacer surrounding a side surface of the pillar portion; and a hard mask pattern disposed between the electrode layers and surrounding an outer surface of the spacer.

[0005] In an embodiment, a method for manufacturing a three-dimensional memory device may include the following steps: forming a pre-stack by alternately stacking multiple sacrificial layers and multiple interlayer insulating layers on a substrate; forming a vertical hole penetrating the pre-stack and extending to one of the multiple sacrificial layers; forming a first horizontal trench connected to a side surface of the vertical hole and a second horizontal trench connected to a lower end of the vertical hole by removing the sacrificial layer around the vertical hole; forming a first hard mask pattern in the first horizontal trench and forming a second hard mask pattern in a second horizontal trench shared with the interlayer insulating layer; forming a spacer on the side surface of the vertical hole; removing the second hard mask pattern in the interlayer insulating layer; forming a contact plug including a pad portion replacing the second hard mask pattern removed from the interlayer insulating layer and a pillar portion filling the vertical hole; and replacing the multiple sacrificial layers with multiple electrode layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional view of a three-dimensional memory device according to an embodiment of the present disclosure.

[0007] Figure 2 It shows Figure 1 A plan view of the connection area.

[0008] Figure 3 yes Figure 1 An enlarged view of part A of FIG.

[0009] Figure 4 is a flowchart illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure.

[0010] Figures 5 to 13 is a cross-sectional view illustrating a method of manufacturing a three-dimensional memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, although they may be shown in different drawings, the same elements will be referred to by the same reference numerals. In addition, in the following description of the present disclosure, when it is possible to make the subject matter of the present disclosure unclear, the detailed description of the known functions and configurations contained herein will be omitted. It will be understood that, unless otherwise specifically stated, the terms "comprise", "have", "include" etc. used in the specification and claims should not be interpreted as being limited to the means listed thereafter. When an indefinite article or a definite article (e.g., "a", "a kind of" and "the") is used when referring to a singular noun, the singular noun may include the plural number of the noun unless otherwise specifically stated.

[0012] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are only used to distinguish one component from another, and do not limit the substance, order, sequence, or quantity of the components.

[0013] In the description of the positional relationship of components, when it is described that at least two components are “connected,” “coupled,” or “linked,” it will be understood that the at least two components may be directly “connected,” “coupled,” or “linked,” but the components may also be indirectly “connected,” “coupled,” or “linked” when another component is interposed between the two components. Here, the other component may be included in at least one of the at least two components that are “connected,” “coupled,” or “linked” to each other.

[0014] In the description of the relationship between components, operating methods, or manufacturing methods in terms of the time flow, for example, the terms "after," "subsequently," "next," or "before" are used to describe the "before" and "after" relationship in terms of time or the "before" and "after" relationship in terms of process. Unless "immediately" or "directly" is used, non-sequential situations can be included.

[0015] In the case of using numerical values of components or their corresponding information, even without separate explicit description, the numerical values or their corresponding information can be construed as including error ranges related to various factors (e.g., process variables, internal or external impacts, noise, etc.).

[0016] Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0017] Various embodiments of the disclosed technology relate to a three-dimensional memory device having a contact plug penetrating a layer stack to extend to an electrode layer.

[0018] According to an embodiment of the disclosed technology, a three-dimensional memory device can be provided having a contact plug that penetrates a stack and extends to an electrode layer by penetrating the stack.

[0019] Figure 1 is a cross-sectional view of a three-dimensional memory device according to an embodiment of the present disclosure, Figure 2 It shows Figure 1 A plan view of the connection area.

[0020] Reference Figure 1 , the stack ST may be provided in the connection region CNR and the cell array region CAR of the substrate 10 .

[0021] The stack ST may include a plurality of electrode layers 20 and a plurality of interlayer insulating layers 30 alternately stacked. The electrode layers 20 may include a conductive material. For example, the electrode layers 20 may include at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). The interlayer insulating layers 30 may include an oxide, such as silicon oxide.

[0022] The electrode layers 20 can be configured as row lines. Row lines can include at least one source select line, at least one drain select line, and multiple word lines. Among the electrode layers 20, at least one electrode layer 20 starting from the bottom electrode layer 20 can be configured as a source select line, and at least one electrode layer 20 starting from the top electrode layer 20 can be configured as a drain select line. The electrode layers 20 between the source select lines and the drain select lines can be configured as word lines.

[0023] The contact plugs 40 may vertically penetrate the stack ST in the connection region CNR. Each contact plug 40 may extend to one of the plurality of electrode layers 20 by vertically penetrating the stack ST from an upper surface thereof and may be electrically connected to the one electrode layer 20.

[0024] Each contact plug 40 may include a pad portion 41 and a pillar portion 42. The pad portion 41 may be provided in the same layer as one of the plurality of electrode layers 20 and may be electrically connected to the one electrode layer 20. A side surface of the pad portion 41 may contact a side surface of the one electrode layer 20.

[0025] The pillar portion 42 may extend to the pad portion 41 by vertically penetrating the stack ST to the pad portion 41. The pad portion 41 and the pillar portion 42 may be formed simultaneously. The pad portion 41 and the pillar portion 42 may be provided as an integrated element or structure.

[0026] To simplify the illustration, Figure 1 Only two contact plugs 40 connected to the two electrode layers 20 are shown. However, a plurality of contact plugs 40 may be provided corresponding to the plurality of electrode layers 20 , respectively, and each contact plug 40 may be electrically connected to the corresponding electrode layer 20 .

[0027] The spacer 50 may be provided on the side surface of the pillar portion 42. Figure 2 As shown, the spacer 50 may surround the side surface of the column portion 42. For example, the column portion 42 may have a column shape, and the spacer 50 may have a cylindrical or tubular structure surrounding the outer surface of the column portion 42. The inner surface of the spacer 50 may contact the outer surface of the column portion 42.

[0028] The spacer 50 may include an oxide, such as silicon oxide.

[0029] The first hard mask patterns 61 may be disposed between the spacers 50 and the electrode layers 20 around the spacers 50. The first hard mask patterns 61 may be disposed at the same layer as the corresponding electrode layers 20, respectively.

[0030] like Figure 2 As shown, each first hard mask pattern 61 may be disposed to surround the outer surface of the spacer 50. For example, the spacer 50 may have a cylindrical or tubular structure, and the first hard mask pattern 61 may have a cylindrical or tubular structure surrounding the outer surface of the spacer 50. The inner surface of the first hard mask pattern 61 may contact the outer surface of the spacer 50.

[0031] The first hard mask pattern 61 may have an etch selectivity different from that of the spacer 50 and the interlayer insulating layer 30. For example, the spacer 50 and the interlayer insulating layer 30 may include an oxide such as silicon oxide, and the first hard mask pattern 61 may include a material having an etch selectivity different from that of the oxide. For example, the first hard mask pattern 61 may include silicon oxynitride (SiON), which is thermally stable and thus can withstand high temperatures without being damaged.

[0032] A plurality of cell plugs 70 may vertically penetrate the stack ST in the cell array region CAR and extend into the substrate 10. Each cell plug 70 may include a memory pattern 71 and a channel structure 72.

[0033] Although not shown, the memory pattern 71 may include a tunnel insulating layer, a data storage layer, and a first blocking insulating layer. The tunnel insulating layer may extend along the surface of the channel structure 72 and may include an insulating material capable of charge tunneling. The data storage layer may extend along the surface of the channel structure 72, with the tunnel insulating layer interposed therebetween. The data storage layer may include a material layer capable of storing data that can be changed using Fowler-Nordheim tunneling. For example, the data storage layer may include a nitride layer capable of charge capture, but the example is not limited thereto. The data storage layer may include a phase change material, nanodots, etc. The first blocking insulating layer may extend along the surface of the channel structure 72, with the tunnel insulating layer and the data storage layer interposed therebetween. The first blocking insulating layer may include an insulating material capable of blocking the movement of charges.

[0034] The channel structure 72 may include a cell channel layer 72A, a capping pattern 72B, and a core insulating pattern 72C. The cell channel layer 72A serves as a channel for the memory cell string. The cell channel layer 72A is disposed on the memory pattern 71 and may be formed of a semiconductor material. For example, the cell channel layer 72A may include silicon. The capping pattern 72B and the core insulating pattern 72C may fill the central region of the channel structure 72. The core insulating pattern 72C may include an oxide. The capping pattern 72B may be disposed on the core insulating pattern 72C and may include a sidewall surrounded by the upper end portion of the cell channel layer 72A. The capping pattern 72B may include a doped semiconductor layer including at least one of n-type impurities and p-type impurities.

[0035] Figure 3 yes Figure 1 An enlarged view of part A of FIG.

[0036] Reference Figure 3 , the horizontal size of the pad portion 41 of the contact plug 40 may be different from the horizontal size of the first hard mask pattern 61. Figure 3 As shown, the horizontal dimension of the pad portion 41 is D1 and the horizontal dimension of the first hard mask pattern 61 is D2, and D1 may be smaller than D2. The horizontal dimension of the pad portion 41 may be smaller than the horizontal dimension of the first hard mask pattern 61.

[0037] The horizontal size of the pad portion 41 of the contact plug 40 may be different from the horizontal size of the pillar portion 42 of the contact plug 40. Figure 3 As shown, the horizontal dimension of the pad portion 41 is D1 and the horizontal dimension of the pillar portion 42 is D3, and D1 may be larger than D3. The horizontal dimension of the pad portion 41 may be larger than the horizontal dimension of the pillar portion 42.

[0038] The pad portion 41 may include a recess R on its upper surface. The recess R may penetrate the upper surface of the pad portion 41. The spacer 50 may be provided on the side surface of the recess R, and the column portion 42 may be provided in the central area of the recess R. Within the recess R, the column portion 42 may be surrounded by the spacer 50. Although Figure 3 The pad portion 41 is shown to be provided with a recess R on the upper surface, but the disclosed technology is not limited thereto, and in other embodiments, the recess R may be omitted.

[0039] Figure 4 is a flowchart illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure, Figures 5 to 13 is a cross-sectional view illustrating a method of manufacturing a three-dimensional memory device according to an embodiment of the present disclosure.

[0040] Reference Figure 4 and Figure 5 , the step of forming a pre-stack PST (S401) may be performed. Figures 5 to 13 It is shown that the pre-laminate PST is formed only in the connection region CNR. Although not shown, the pre-laminate PST is formed in the cell region as well as the connection region CNR.

[0041] The pre-stack PST may be formed by alternately stacking a plurality of sacrificial layers 22 and a plurality of interlayer insulating layers 30 on a substrate 10. The sacrificial layers 22 and the interlayer insulating layers 30 may have different etching selectivities. The interlayer insulating layers 30 may include oxide (e.g., silicon oxide), and the sacrificial layers 22 may include a material having an etching selectivity different from that of the oxide (e.g., nitride in silicon nitride).

[0042] Reference Figure 4 and Figure 6 , a step of forming a vertical hole VH ( S402 ) may be performed.

[0043] Each vertical hole VH may extend into one of the plurality of sacrificial layers 22 by penetrating the pre-stack PST from the upper surface of the pre-stack PST. Figure 6 Only two vertical holes VH are shown in FIG. 2 , but a plurality of vertical holes VH may be formed corresponding to some of the plurality of sacrificial layers 22 , respectively.

[0044] Reference Figure 4 and Figure 7 , a step ( S403 ) of forming the first horizontal trench HH1 and the second horizontal trench HH2 may be performed.

[0045] The first and second horizontal trenches HH1 and HH2 may be formed by selectively removing portions of the sacrificial layer 22 exposed by the vertical hole VH. The first horizontal trench HH1 may be connected to a side surface of the vertical hole VH. The second horizontal trench HH2 may be connected to a lower end of the vertical hole VH.

[0046] The first and second horizontal trenches HH1 and HH2 may be formed using an isotropic etching process using an etchant capable of selectively removing the sacrificial layer 22 .

[0047] The first horizontal trench HH1 may extend horizontally from the side surface of the vertical hole VH. The second horizontal trench HH2 may extend horizontally from the center portion of the lowermost sacrificial layer 22 shared with the vertical hole VH. Therefore, the first horizontal trench HH1 and the second horizontal trench HH2 may have different sizes. The cross-sectional dimension of the second horizontal trench HH2 may be smaller than the cross-sectional dimension of the first horizontal trench HH1.

[0048] Reference Figure 4 and Figure 8 , a step of forming a first hard mask pattern 61 and a second hard mask pattern 62 may be performed ( S404 ).

[0049] A hard mask layer may be formed to fill the first horizontal trench HH1 and the second horizontal trench HH2. The hard mask layer may have an etch selectivity different from that of the sacrificial layer 22 and the interlayer insulating layer 30. For example, the interlayer insulating layer 30 may include an oxide (e.g., silicon oxide), the sacrificial layer 22 may include a nitride (e.g., silicon nitride), and the hard mask layer may include a material having an etch selectivity different from that of the oxide and the nitride. For example, the hard mask layer may include silicon oxynitride (SiON).

[0050] By removing the hard mask layer formed outside the first horizontal trench HH1 and the second horizontal trench HH2, the Figure 6 When the vertical hole VH is formed, a first hard mask pattern 61 may be formed in the first horizontal trench HH1, and a second hard mask pattern 62 may be formed in the second horizontal trench HH2.

[0051] When the first horizontal trench HH1 is completely filled with the hard mask layer, the central region of the second horizontal trench HH2 may be partially unfilled so that a recess R may be formed on the upper surface of the second hard mask pattern 62. Figure 8 The recess R formed on the upper surface of the second hard mask pattern 62 is shown, but the disclosed technology is not limited thereto, and in other embodiments, the recess R may not be formed.

[0052] Reference Figure 4 、 Figure 9 and Figure 10 , a step of forming the spacer 50 ( S405 ) may be performed.

[0053] An insulating layer 50A may be formed in the vertical hole VH. Figure 9As shown, the insulating layer 50A may be formed to completely fill the vertical hole VH. However, in other embodiments, the insulating layer 50A may be formed to cover the side surfaces of the vertical hole VH and only partially fill the central region of the vertical hole VH.

[0054] The insulating layer 50A may have an etch selectivity different from that of the sacrificial layer 22 and the second hard mask pattern 62. For example, the sacrificial layer 22 may include a nitride (e.g., silicon nitride), the second hard mask pattern 62 may include silicon oxynitride (SiON), and the insulating layer 50A may include an insulating material having an etch selectivity different from that of the nitride and silicon oxynitride (SiON). For example, the insulating layer 50A may include an oxide (e.g., silicon oxide).

[0055] like Figure 10 As shown, the insulating layer 50A in the central region of the vertical hole VH can be removed by an etching process using the second hard mask pattern 62 as an etch stopper, leaving the insulating layer 50A on the side surfaces of the vertical hole VH. In this way, a cylindrical or tubular spacer 50 extending into the second hard mask pattern 62 can be formed.

[0056] Due to the difference in etching selectivity between the insulating layer 50A and the second hard mask pattern 62, etching during the etching process for removing the insulating layer 50A in the central region of the vertical hole VH can stop at the second hard mask pattern 62, thereby preventing the sacrificial layer 22 and the interlayer insulating layer 30 below the second hard mask pattern 62 from being etched. In other words, over-etching can be prevented.

[0057] Reference Figure 4 and Figure 11 , a step of removing the second hard mask pattern 62 may be performed ( S406 ).

[0058] The second hard mask pattern 62 may be removed using an etchant capable of selectively removing the second hard mask pattern 62 .

[0059] Reference Figure 4 and Figure 12 , a step of forming the contact plug 40 ( S407 ) may be performed.

[0060] The contact plug 40 may be formed of a conductive material filling the second horizontal trench HH2 and the central area of the vertical hole VH exposed by the removal of the second hard mask pattern 62. The contact plug 40 may include a pad portion 41 filling the second horizontal trench HH2 and a pillar portion 42 filling the central area of the vertical hole VH.

[0061] The pad portion 41 and the pillar portion 42 may be formed by simultaneously or substantially simultaneously growing or depositing a conductive material in the central region of the vertical hole VH and the second horizontal trench HH2. Therefore, the pad portion 41 and the pillar portion 42 may be integrally formed.

[0062] Reference Figure 4 and Figure 13 , performing a step of replacing the sacrificial layer 22 with the electrode layer 20 ( S408 ).

[0063] The electrode layer 20 is formed by selectively removing the sacrificial layer 22 and filling the empty areas created by the removal of the sacrificial layer 22 with an electrode material.

[0064] Although exemplary embodiments of the present disclosure have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered in an illustrative sense only and not for limiting the scope of the technology. The scope of the technology of the present disclosure is not limited by these embodiments and drawings.

[0065] CROSS-REFERENCE TO RELATED APPLICATIONS

[0066] This application claims the benefit of Korean Patent Application No. 10-2024-0017268, filed on February 5, 2024, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional memory device, comprising: a laminate comprising a plurality of electrode layers and a plurality of interlayer insulating layers alternately laminated on a substrate; a contact plug including a pad portion and a pillar portion, the pad portion being provided in the same layer as one of the plurality of electrode layers, the pillar portion penetrating the stack and extending to the pad portion; a spacer surrounding a side surface of the pillar portion; as well as A hard mask pattern is disposed between the electrode layer and the spacer.

2. The three-dimensional memory device according to claim 1, wherein: The etch selectivity of the hard mask pattern is different from the etch selectivity of the spacer.

3. The three-dimensional memory device according to claim 1, wherein: The spacer includes oxide, and the hard mask pattern includes silicon oxynitride.

4. The three-dimensional memory device according to claim 1, wherein: The hard mask pattern has an etch selectivity different from an etch selectivity of the plurality of interlayer insulating layers.

5. The three-dimensional memory device according to claim 1, wherein The plurality of interlayer insulating layers include oxide, and the hard mask pattern includes silicon oxynitride.

6. The three-dimensional memory device according to claim 1, wherein: In cross-section, a horizontal dimension of the pad portion is greater than a horizontal dimension of the pillar portion.

7. The three-dimensional memory device according to claim 1, wherein: In a cross-section, a horizontal dimension of the pad portion is smaller than a horizontal dimension of the hard mask pattern.

8. The three-dimensional memory device according to claim 1, wherein: The pad portion and the pillar portion are integrated.

9. The three-dimensional memory device according to claim 1, wherein: The spacer surrounds the outer surface of the column portion, The hard mask pattern surrounds a portion of an outer surface of the spacer, and The hard mask pattern is disposed at the same layer as the corresponding electrode layer.

10. The three-dimensional memory device according to claim 1, wherein: The pad portion includes a recess on an upper surface thereof, The spacer is provided on the side surface of the recess, and The pillar portion is disposed in a central region of the recess surrounded by the spacer.

11. A method for manufacturing a three-dimensional memory device, the method comprising the steps of: forming a pre-stack by alternately stacking a plurality of sacrificial layers and a plurality of interlayer insulating layers on a substrate; forming a vertical hole penetrating the pre-stack and extending to one of the plurality of sacrificial layers; forming a first horizontal trench connected to a side surface of the vertical hole and a second horizontal trench connected to a lower end portion of the vertical hole by removing a sacrificial layer around the vertical hole; forming a first hard mask pattern in the first horizontal trench and forming a second hard mask pattern in the second horizontal trench shared with the interlayer insulating layer; forming spacers on side surfaces of the vertical hole; removing the second hard mask pattern in the interlayer insulating layer; forming a contact plug including a pad portion replacing the second hard mask pattern removed from the interlayer insulating layer and a pillar portion filling the vertical hole; as well as The plurality of sacrificial layers are replaced with a plurality of electrode layers.

12. The method according to claim 11, wherein The step of forming the spacer comprises the following steps: forming an insulating layer in the vertical hole; and The insulating layer in a central region of the vertical hole is etched using the second hard mask pattern as an etch stopper.

13. The method according to claim 11, wherein An etch selectivity of the second hard mask pattern is different from an etch selectivity of the spacer.

14. The method according to claim 11, wherein The spacer includes oxide, and the second hard mask pattern includes silicon oxynitride.

15. The method according to claim 11, wherein The first and second hard mask patterns have etch selectivities different from etch selectivities of the plurality of interlayer insulating layers and the plurality of sacrificial layers.

16. The method according to claim 11, wherein The plurality of interlayer insulating layers include oxide, the plurality of sacrificial layers include nitride, and the hard mask pattern includes silicon oxynitride.

17. The method according to claim 11, wherein The first and second horizontal trenches are formed by isotropically etching the sacrificial layer exposed through the vertical hole.

18. The method according to claim 11, wherein In a cross section, a size of the second horizontal groove is smaller than a size of the first horizontal groove.

19. The method according to claim 11, wherein In a cross section, a size of the second horizontal groove is larger than a size of the vertical hole.

20. The method according to claim 11, wherein The step of forming the first hard mask pattern and the second hard mask pattern includes the following steps: forming a hard mask material to fill the first horizontal trench and the second horizontal trench; and The hard mask material formed outside the first horizontal trench and the second horizontal trench is removed.

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