Radio frequency switch and reconfigurable surface

Abstract

The invention relates to a radio frequency switch (100) for a reconfigurable surface (200). The radio frequency switch (100) comprises a first storage latch (110) for receiving data bits and outputting the data bits to a gate (136) of an FET (130), the FET (130) comprising: a drain (132) for connecting to a first connection point (212) of an antenna unit cell (210) of the reconfigurable surface (200); and a source (134) for connecting to a second connection point (214) of the antenna unit cell (210). Thus, the FET (130) is configured to be in a closed state when the data bit has a first value, and in an open state when the data bit has a second value different from the first value, thereby acting as a switch. In addition, the embodiment of the invention also relates to a reconfigurable surface comprising the radio frequency switch.

Description

Technical Field

[0001] Embodiments of the present invention relate to a radio frequency switch for a reconfigurable surface. In addition, embodiments of the present invention also relate to a reconfigurable surface comprising such a radio frequency switch. Background Art

[0002] To meet the demand for higher data rates in communication systems, operators must expand mobile data networks to millimeter wave bands, which offer greater bandwidth compared to saturated lower frequency bands. To overcome the shadowing limitations typically associated with these high frequencies, operators have three main options for increasing coverage: densifying macrocells, deploying ultra-dense millimeter wave networks, and using passive or active repeater technologies.

[0003] A reconfigurable intelligent surface (RIS) is a passive repeater technology that combines wave-reflecting panels with beamforming arrays. It shapes electromagnetic (EM) wave reflections into open paths from base stations (BSs) to user equipment (UEs), which would otherwise be in shadowed locations. Adding RIS devices to communications networks is a promising approach to improving coverage while maintaining low power consumption. RIS is an environmentally friendly technology that allows operators to remain at the site of existing BS installations. Summary of the Invention

[0004] An object of the embodiments of the present invention is to provide a solution to reduce or solve the disadvantages and problems of conventional solutions.

[0005] Another object of an embodiment of the present invention is to provide an RF switch solution with lower power consumption compared to conventional solutions.

[0006] The above and other objects are achieved by the subject-matter of the independent claims. Further embodiments of the invention are provided in the dependent claims.

[0007] According to a first aspect of the present invention, the above and other objects are achieved by a radio frequency switch for a reconfigurable surface, the radio frequency switch comprising:

[0008] a first storage latch, the first storage latch comprising: a clock input terminal for receiving a clock signal, a data input terminal for receiving a data bit, and a data output terminal for outputting the data bit;

[0009] a first field effect transistor (FET), the first FET comprising: a drain for connecting to a first connection point of an antenna unit cell of the reconfigurable surface; a source for connecting to a second connection point of the antenna unit cell; and a gate connected to the data output of the first storage latch, wherein the first FET is configured to be in a closed state when the data bit has a first value and to be in an open state when the data bit has a second value different from the first value, thereby acting as a switch.

[0010] The RF switch according to the first aspect has the advantage of lower steady-state power consumption compared to diode-based RF switches, making it suitable, for example, for reconfigurable surface applications with stringent power requirements. Other advantages of adding a storage latch include simplified control of the reconfigurable surface, fewer output driver circuits for the control device, and reduced wiring complexity on the reconfigurable surface printed circuit board (PCB).

[0011] In an implementation of the radio frequency switch according to the first aspect, the first storage latch and the first FET are arranged on a common single chip.

[0012] The advantage of this implementation is that integrating one or more FETs and one or more storage latches onto the same chip supports high-volume manufacturing of chip devices at low cost. In addition, this common chip has built-in resistance to temperature changes through logic level threshold design. In addition, when the storage latch is located at the antenna unit cell together with the FET switch, row / column addressing can be achieved, thereby simplifying the control circuit and reducing the complexity of the PCB. In addition, locating the FET and storage latch together on the same chip makes the component size of the required function as small as possible. For antenna performance (such as minimizing reflection loss and maximizing bandwidth), it is very important that any component assembled into the antenna unit cell is physically small compared to the size of the antenna element. Therefore, the advantage of integrating RF switches is that the performance of the reconfigurable surface is better than that of dividing the functions into several separate chips.

[0013] In an implementation of the radio frequency switch according to the first aspect, the first FET is an N-channel FET.

[0014] The advantage of this implementation is that N-channel FETs have higher electron mobility than P-channel FETs. Therefore, when using N-channel FETs, the switch can be implemented with lower RF signal on-resistance. This will reduce reflection losses in the reconfigurable metasurface.

[0015] In an implementation of the radio frequency switch according to the first aspect, the source of the first FET is connected to a common reference ground through a first resistor.

[0016] The advantage of this implementation is that, since the resistor establishes a potential close to zero for the source terminal of the first FET, control of the FET from the logic output of the storage latch becomes reliable. Due to the high gate input resistance, the value of the resistor can be set high enough so that it is barely visible to the RF circuit being switched.

[0017] In an implementation of the radio frequency switch according to the first aspect, the clock input terminal of the first storage latch is used to connect to the column line of the reconfigurable surface, and the data input terminal of the first storage latch is used to connect to the row line of the reconfigurable surface, or vice versa.

[0018] The advantage of this implementation is that it enables row / column addressing of RF switches. A specific switch on the array can be assigned a pair of coordinates corresponding to a row and column number. This significantly reduces the number of electrical control line outputs required for the control device of the reconfigurable surface. The clock input of the memory latch is used to transmit the data bit presented on the row line to the memory latch. When no other columns on the array receive a clock signal, the RF switches on that row in other columns do not respond to the presented data bit.

[0019] In an implementation of the radio frequency switch according to the first aspect, the radio frequency switch further includes:

[0020] A second storage latch, the second storage latch comprising: a clock input terminal for receiving a common control signal for the antenna unit cell of the reconfigurable surface; a data input terminal connected to the data output terminal of the first storage latch; and a data output terminal connected to the gate of the first FET, wherein the second storage latch is used to transfer a data bit from the data input terminal to the data output terminal when receiving the common control signal.

[0021] The advantage of this implementation is that the data bits representing the new beamforming settings (i.e., the new codeword) can be uploaded to the antenna array before the moment the beamforming is changed. That is, the transition time for changing the beamforming settings from one setting to another, as experienced by the radio signal to be reflected, can be significantly reduced. The transition time represents ambiguous and undefined beamforming and is therefore equivalent to a communication interruption. It is desirable to minimize such interruptions. With the addition of the second storage latch, the new codeword is first uploaded to the first storage latch while the current codeword is held by the second storage latch. Once all the first storage latches have received their new code data bits, the change from the current array beamforming setting to the new setting is achieved by switching the common control signal for one cycle. Instead of the array receiving an interruption period equal to the number of clock cycles of its columns, the interruption is now reduced to less than one clock cycle.

[0022] In an implementation of the radio frequency switch according to the first aspect, the radio frequency switch further includes:

[0023] a third storage latch, the third storage latch comprising: a clock input terminal for receiving the clock signal, a data input terminal connected to the data output terminal of the first storage latch, and a data output terminal;

[0024] a fourth storage latch, the fourth storage latch comprising: a clock input terminal for receiving a common control signal for the antenna unit cell of the reconfigurable surface; a data input terminal connected to the data output terminal of the third storage latch; and a data output terminal, wherein the fourth storage latch is configured to transfer a data bit from the data input terminal to the data output terminal when receiving the common control signal;

[0025] A second FET includes: a drain for connecting to the third connection point of the antenna unit cell; a source for connecting to the fourth connection point of the antenna unit cell; and a gate connected to the data output end of the fourth storage latch.

[0026] An advantage of this implementation is that if more than one RF switch is provided, the reconfigurability of the antenna element can be further optimized. By connecting two storage switches to different parts of the antenna layout pattern, control over the RF current pattern, which is the basis of the antenna's radiation characteristics and performance, can be enhanced. This implementation allows the RF switches to be controlled by independent data bits, resulting in the RF switches being set to closed or open independently of each other. An example of utilizing this advantage is to separately control two different orthogonal polarizations of the incident RF wave so that their reflections in different directions form a beam. In addition, in this implementation, the second and fourth storage latches have the advantage that the new codeword can be uploaded to the array before the beamforming setting is changed. This reduces the change time for changing the beamforming setting from one setting to another and minimizes interruption of the wireless signal.

[0027] In an implementation of the radio frequency switch according to the first aspect, the radio frequency switch further includes:

[0028] a third storage latch, the third storage latch comprising: a clock input terminal for receiving the clock signal, a data input terminal connected to the data output terminal of the first storage latch, and a data output terminal;

[0029] a fourth storage latch, the fourth storage latch comprising: a clock input terminal for receiving a common control signal for the antenna unit cell of the reconfigurable surface; a data input terminal connected to the data output terminal of the third storage latch; and a data output terminal, wherein the fourth storage latch is configured to transfer a data bit from the data input terminal to the data output terminal when receiving the common control signal;

[0030] a second FET, the second FET comprising: a drain connected to the source of the first FET; a source connected to the second connection point of the antenna unit cell; and a gate connected to the data output terminal of the second storage latch;

[0031] The first FET has a first gate width, and the second FET has a second gate width different from the first gate width.

[0032] The advantage of this implementation is that it utilizes independent control of two internal series-connected switches to present not only two states, closed and open, but also intermediate impedance states between two external connection terminals. These intermediate states manifest as different capacitances, effectively resulting in a step capacitor with low resistance as the end state. Through appropriate RF design methods, this step capacitance can be used to create a greater number of quantized phase states for the antenna unit cell reflection coefficient, rather than just two. Multiple phase states with finer resolution unit cells are beneficial for improving the radiation pattern shape of the reconfigurable surface and increasing sidelobe suppression. The capacitance of the intermediate states is controlled by selecting the FET device size (i.e., gate width). In addition, in this implementation, the second and fourth storage latches have the advantage that the new beamforming settings can be uploaded to the array before the moment the beamforming settings are changed. This reduces the change time of changing the beamforming settings from one setting to another and minimizes interruption of the wireless signal.

[0033] In an implementation of the radio frequency switch according to the first aspect, the radio frequency switch further includes:

[0034] a second storage latch, the second storage latch comprising: a clock input terminal for receiving the clock signal, a data input terminal connected to the data output terminal of the first storage latch, and a data output terminal;

[0035] A second FET includes: a drain for connecting to the third connection point of the antenna unit cell; a source for connecting to the fourth connection point of the antenna unit cell; and a gate connected to the data output end of the second storage latch.

[0036] This is a simpler implementation that achieves the advantages described above for having two independent, individually controlled switches. This implementation is suitable when the speed of operation of the reconfigurable surface is not a priority, but when low power consumption is. Another advantage is that the RF switch requires one less connection terminal, which helps minimize size, cost, and PCB routing.

[0037] In an implementation of the radio frequency switch according to the first aspect, the radio frequency switch further includes:

[0038] a second storage latch, the second storage latch comprising: a clock input terminal for receiving the clock signal, a data input terminal connected to the data output terminal of the first storage latch, and a data output terminal;

[0039] a second FET, the second FET comprising: a drain connected to the source of the first FET; a source connected to the second connection point of the antenna unit cell; and a gate connected to the data output terminal of the second storage latch;

[0040] The first FET has a first gate width, and the second FET has a second gate width different from the first gate width.

[0041] This is a simpler implementation that achieves the advantages described previously for having two independently controlled, internally series-connected switches. It also offers the same advantages associated with a greater number of phase states for the antenna, resulting from the multiple impedance states of the series FET pair. This implementation is advantageous when low power consumption is a priority. Another advantage is that the RF switch assembly requires one fewer connection terminal, which helps minimize size, cost, and PCB routing.

[0042] In an implementation of the radio frequency switch according to the first aspect, the source of the second FET is connected to a common reference ground through a second resistor.

[0043] The advantage of this implementation is that, because the resistor establishes a near-zero potential for the source terminal of the second FET, the logic output of the storage latch, which controls the second FET switch, has a reliable logic input transition level. The resistor also ensures this when the first FET is in the off state. Due to the high gate input resistance, the resistor value can be set very high so that it is almost invisible to the RF circuit being switched.

[0044] In an implementation of the radio frequency switch according to the first aspect, the radio frequency is in the centimeter or millimeter wave range.

[0045] According to a second aspect of the present invention, the above and other objects are achieved by a reconfigurable surface, the reconfigurable surface comprising:

[0046] A plurality of antenna unit cells, wherein each antenna unit cell comprises a radio frequency switch according to any one of the preceding claims, the radio frequency switch being connected between connection points of the antenna unit cells;

[0047] A control device is connected to the plurality of antenna unit cells through a plurality of column lines and a plurality of row lines, and is used to control the radio frequency switches of the plurality of antenna unit cells by providing a clock signal on the row lines and a plurality of data bits on the column lines, or vice versa.

[0048] The reconfigurable surface according to the second aspect has the advantage that the RF switch according to the first aspect is suitable for reconfigurable surface applications with strict power requirements. Other advantages brought about by the addition of a storage latch are simplified control of the reconfigurable surface, fewer output drive circuits for the control device, and reduced wiring complexity of the reconfigurable surface PCB.

[0049] In one implementation of the reconfigurable surface according to the second aspect, the control device is also connected to the multiple antenna unit units through a common control line, and is used to transfer the data bits at the data input end of the storage latch to the output end of the storage latch by providing a common control signal.

[0050] The advantage of this implementation is that, as the control device clocks the storage latches in all the RF switches connected to it on the array using a common control line, the data bits representing the new beamforming setting (i.e., codeword) can be uploaded to the array before the moment the beamforming setting changes. This significantly reduces the transition time, as experienced by radio signals, required to change the beamforming setting from one setting to another. As previously mentioned, transition time represents ambiguous and undefined beamforming and is therefore equivalent to a communication interruption. It is desirable to minimize this interruption. Once all first latches have received their new code data bits, the change from the current array beamforming setting to the new setting is achieved by toggling the common control signal for one cycle. Instead of the array experiencing an interruption period equal to the number of clock cycles in its columns, the interruption is now reduced to less than one clock cycle.

[0051] In an implementation manner of the reconfigurable surface according to the second aspect, the plurality of data bits represent codewords of a beamforming scheme.

[0052] Other applications and advantages of embodiments of the present invention will be apparent from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings are intended to illustrate and explain different embodiments of the present invention, in which:

[0054] Figure 1 An RF switch including a storage latch and a FET provided by an embodiment of the present invention is shown;

[0055] Figure 2 Shown include Figure 1 The physical layout of the chip device of the RF switch shown;

[0056] Figure 3 Shown include Figure 1 The reconfigurable surface of the RF switch shown;

[0057] Figure 4 shows a change in phase of an exemplary unit cell of a reconfigurable surface;

[0058] Figure 5 shows a unit cell connected to a reconfigurable surface multilayer PCB;

[0059] Figure 6 An implementation example of a device including a reconfigurable surface is shown;

[0060] Figure 7 The reflective and transmissive properties of the reconfigurable surface provided by an embodiment of the present invention are shown;

[0061] Figure 8 An RF switch including two storage latches provided by an embodiment of the present invention is shown;

[0062] Figure 9 Shown include Figure 8 The reconfigurable surface of the RF switch shown;

[0063] Figure 10 An RF switch including two storage latches and two FETs is shown;

[0064] Figure 11 Shown include Figure 8 The physical layout of the chip device of the RF switch shown;

[0065] Figure 12 An RF switch including four storage latches and two FETs provided by an embodiment of the present invention is shown;

[0066] Figure 13 An RF switch including two storage latches and two FETs provided by an embodiment of the present invention is shown;

[0067] Figure 14 An equivalent model of a single FET used as a switch is shown;

[0068] Figure 15 A schematic diagram showing possible device selection and equivalent model for a series FET pair as a combined switch and step varactor diode is shown;

[0069] Figure 16 An RF switch including four storage latches and two FETs provided by an embodiment of the present invention is shown;

[0070] Figure 17 shows the physical layout of the chip device provided by the embodiment of the present invention;

[0071] Figure 18a and Figure 18b The use of a reconfigurable surface in an exemplary communication scenario is shown. DETAILED DESCRIPTION

[0072] As mentioned above, RIS uses passive radio frequency (RF) technology and operates without signal amplification. Compared to active repeaters, RIS offers the advantage of being able to operate without an external connection to the power grid, but can be powered by batteries and / or solar panels. However, to achieve this, both the RIS control system and the electronics used to reconfigure the RIS must be designed to minimize power consumption. Therefore, this article discloses an RF switch that meets stringent power requirements.

[0073] Figure 1 1 shows an RF switch 100 including a storage latch and one or more FETs in a first embodiment of the present invention, and Figure 2 Shown include Figure 1 An example of the physical layout of a chip of an RF switch is shown. In a first embodiment, the RF switch 100 includes a first storage latch 110, which further includes: a clock input 112 for receiving a clock signal (CLK in the figure); a data input 114 for receiving a data bit (DATA in the figure); and a data output 116 for outputting the data bit. The RF switch 100 also includes a first FET 130, which includes: a drain 132 for connecting to a first connection point 212 (also denoted as a switch drain, SWD) of an antenna unit cell 210 of the reconfigurable surface 200; a source 134 for connecting to a second connection point 214 (also denoted as a switch source, SWS) of the antenna unit cell 210; and a gate 136 connected to the data output 116 of the first storage latch 110. The first FET 130 is configured to be in a closed state when the data bit has a first value and in an open state when the data bit has a second value different from the first value, thereby acting as a switch.

[0074] In a non-limiting example, the first storage latch 110 can be a D-type flip-flop. Its purpose is to receive a data bit that controls the state of the FET switch and store that data bit in memory. There is no need to read the memory state via access lines 232 and 234. Additionally, a VDD connection can be present to provide a DC supply voltage to the storage latch 110 from a common PCB power plane whose voltage is adapted to the selected semiconductor process.

[0075] In order for the logic circuit of the storage latch 110 to operate, it needs to be connected to the supply voltage VDD and the common reference ground 204, which are shared with the control system 230. The drain and source terminals 212, 214 (216, 218) of the FET switch can be considered to have a floating potential relative to the RF circuit of the antenna unit cell 210. This is because the antenna pattern can have the design freedom to float or be tied to the RF ground plane. It is important that a well-defined logic level is reliably established at the gate 136 of the first FET 130 in order to correctly turn the FET channel on or off. To this end, the source 134 of the first FET 130 can be connected to the common reference ground 204 via a first resistor 140, which establishes a defined gate-source voltage for operating the first FET 130 as a switch. The first resistor 140 can be a high value resistor. Therefore, as Figure 1 As disclosed in , the source 134 of the first FET 130 is connected to the common reference ground 204 through the first resistor 140. From an RF perspective, this connection is not visible, and the terminals 212, 214 of the first FET 130 can be considered floating. However, the terminals 212 and 214 should not be connected to a surface with a direct current (DC) potential that is not equal to zero (≠0V), as this will disrupt the switching control of the first FET 130.

[0076] The RF switch 100 may further include an electrostatic sensitive device (ESD) protection circuit, which is not shown in the drawings. However, it should be noted that it is best not to place the ESD protection circuit on the first connection point 212 and the second connection point 214 terminals because the parasitic capacitance of any protection diode to ground will degrade the performance of the RF switch through capacitive loading.

[0077] In an embodiment of the present invention, the first FET 130 is an N-channel FET (NFET) because electrons are the primary charge carriers in NFETs and have a higher mobility than holes in PFETs. This results in NFETs having lower on-resistance and, therefore, higher RF performance. A CMOS process is also preferred because digital complementary logic can be easily added to the same chip as the switch FET 130. This is not the case with GaAs-based semiconductor processes. GaAs metal-semiconductor field effect transistors (MESFETs) or pseudomorphic high electron mobility transistors (pHEMTs) can be made into excellent RF switches, but cannot implement complementary logic and, therefore, cannot be integrated on a single chip. The drain and source of the first FET 130 become the switch RF terminals and are therefore connected to the external circuit via connection points, while the gate of the first FET 130 is used to control the switching function of the first FET 130. NFET device designs for this process can be optimized for good performance as RF switches, including features such as triple-well device isolation and meandering gate designs.

[0078] In an embodiment, the first FET 130 and the first storage latch 110 may be integrated into the same semiconductor wafer, such as Figure 2 As shown. Thus, the first storage latch 110 and the first FET 130 can be arranged on a common single chip 202. The first FET 130 can be designed to achieve optimal RF switching performance in the frequency range of interest and arranged on the chip with the shortest possible path from its drain and source terminals to the first connection point 212 and the second connection point 214. The first connection point 212 and the second connection point 214 are connected to the antenna unit cell between the points where switching action is required.

[0079] Integrating one or more FETs and one or more storage latches on the same chip can be achieved, for example, using a suitable CMOS process ("RFCMOS") with optimized characteristics for high-frequency design. The small scale of integration and the small number of components eliminate the need to use the most advanced nanometer-scale process nodes. The physical design of the chip device of the first embodiment can be shaped into small-sized components with a symmetrical layout. Figure 2 In the present invention, a first embodiment is shown as a flip chip ball grid array (BGA) device with controlled folded chip connection (C4) bumps, the purpose of which is to minimize the parasitic series inductance from the connection in order to optimize the RF performance at high frequencies. Figure 2The pinout shown is just one example; other variations are possible. Adaptation and co-design with the antenna element of the antenna unit cell 210 are crucial for functionality. The key point here is the ability to co-locate the storage latches along with the FETs on a small chip that can be assembled into each antenna unit cell 210 of the configurable surface 200. This co-location of functionality enables simple row / column addressing to set the beamforming code on the reconfigurable surface 200 using a switch chip. The chip 202 should be small enough relative to the operating wavelength to present very low reactive parasitic elements to the RF switch connections and can be assembled directly onto the antenna surface in each antenna unit cell 210 without significantly covering the antenna element. The total number of connections to the chip should be kept low to enable layout integration without compromising RF performance. Therefore, a package-free flip-chip design with small bumps and low connection pitch may be the best choice. If the RF switch 100 is intended for use in the low GHz frequency range, where the negative impact of reactive parasitic elements is low, the size and packaging design can be larger.

[0080] From the perspective of the RF design of antenna unit cell 210, first FET 130 with connections 212, 214 can be considered a discrete high-frequency semiconductor component similar to a conventional discrete transistor or diode, rather than part of an integrated circuit. Functionality associated with switch control, such as storage latch 110, control lines 232, 234, supply voltage VDD, and control system 230, is effectively invisible to the RF functionality of configurable surface 200 and should not affect reflected electromagnetic waves.

[0081] Integrating multiple FET switches into a single chip, combined with unbiased switching channels, also solves the problem of implementing an antenna unit cell 210 capable of handling both polarizations. For a single chip to suffice, it needs to be positioned in the center of the antenna unit cell layout, and the antenna unit cell 210 and switch configuration needs to have 4x symmetry. This is possible in this solution, while still benefiting from a simplified addressing network and the freedom to design RF patterns without worrying about DC voltage conflicts.

[0082] A general requirement for any component that should act as a lumped element in an RF circuit is that it should be small compared to the RF signal wavelength λ, i.e., less than λ / 10. The antenna unit cell 210 in the reflecting surface 200 is typically around half a wavelength (λ / 2), and for example, if the operating frequency is 30 GHz, this corresponds to 5 mm. Therefore, in order not to interfere with antenna operation, the length of the assembled chip can be about 0.5 mm. In addition, reactive parasitic elements in the package with internal lead frame and chip connections in series or parallel with the switching elements tend to degrade phase shift performance and reduce the operating bandwidth. This small design minimizes reactive parasitic elements and allows operation at high frequencies (FR2 defined by 3GPP). For use and operation at low frequencies (FR1 defined by 3GPP), the size of the chip 202 is not expected to change much, but the size of the antenna unit cell 210 will increase depending on the wavelength used. At 3 GHz, the chip size is only about λ / 100, and it is possible to use chips housed in small packages such as a 10-pin lead frame chip scale package (LFCSP) or wafer-level chip scale package (WLCSP), land grid array (LGA), or similar types of packages.

[0083] Figure 3 It also shows that Figure 1 A reconfigurable surface 200 including multiple RF switches is shown. The reconfigurable surface 200 disclosed herein includes multiple antenna unit cells 210, each of which includes the RF switch 100 provided in the first embodiment. The RF switch 100 is connected between connection points of the antenna unit cells 210. The reconfigurable surface 200 also includes a control device 230 connected to the multiple antenna unit cells 210 via multiple column lines 234 and multiple row lines 232. The control device 230 is configured to control the RF switches 100 of the multiple antenna unit cells 210 by providing a clock signal on the row lines 232 and multiple data bits on the column lines 234, or vice versa. Therefore, the clock input 112 of the first storage latch 110 is configured to be connected to the column lines 234 of the reconfigurable surface 200, and the data input 114 of the first storage latch 110 is configured to be connected to the row lines 232 of the reconfigurable surface 200, or vice versa.

[0084] Typically, the storage latches of the RF switch circuitry maintain the state of the RF switches and support row / column addressing of unit cells across the array of the configurable surface 200, similar to the functionality of static random-access memory (SRAM) memory. On a reconfigurable surface 200 with an array of M×M antenna unit cells 210, this eliminates the need for separate address lines for all M2 RF switches in conventional schemes, requiring only 2M address lines. Setting a new codeword across the array can be done column-by-column or row-by-row, depending on the application. One such die is used for each antenna unit cell 210 to populate the array. These components enable configuration of the phase response of the reflective surface 200. With this arrangement, new array code patterns can be implemented row-by-row in a sequential scan. Thus, multiple data bits can represent codewords for beamforming schemes, such as those used in 3GPP New Radio (NR) communication systems. At the edges of the array, row and column lines can be accessed and connected to the control circuitry of the control device 230. This is equivalent to memory cell access in SRAM memory. The programmed state of the RF switch (i.e., ON or OFF state) is retained by the storage latch as long as the supply voltage is present. The static power consumption in the retention state depends on the leakage current of the complementary metal-oxide-semiconductor (CMOS) process used, but can be assumed to be close to zero.

[0085] Figure 4 An exemplary antenna unit cell 210 of a reconfigurable surface 200 is shown. Reconfigurability can be achieved at the antenna unit cell level by adding the ability for the antenna unit cell to have at least two different equidistant phase shifts in its reflection or transmission coefficient. A 1-bit antenna unit cell has a reflection phase difference of 360° / 2 = 180° between its two programmable states, the "0" state and the "1" state. Correspondingly, a 2-bit antenna unit cell will exhibit a quantization of 360° / 22 = 90° of phase states, so 90° between the 00 and 01 states, 180° between the 00 and 10 states, and 270° between the 00 and 11 states.

[0086] To achieve reconfigurability, the RF switch 100 is used to change the impedance in the antenna unit cell 210 to change between different surface current modes by using an RF switch. According to general circuit theory, it is known that the reflection phase shift of an open circuit is 0°, while the reflection phase shift of a short circuit is 180°. A skilled designer can transfer this property to the response of the antenna element. Intuitively, it can be understood that the very large impedance shift from open circuit to short circuit shows that the present RF switch is a very effective means of adding phase reconfigurability. For the antenna unit cell, the resulting reflection phase can show a specific characteristic curve that varies according to frequency, and the switch is in one of its states. When the switch is switched to its other state, the reflection phase characteristic curve changes, and the difference between the two curves can be optimized by design to be as close to 180° as possible within the operating bandwidth. Figure 4 Four non-limiting examples (a) to (c) of antenna unit cells are shown, in which RF switches are incorporated to change the reflection response of the reconfigurable surface 200. However, reconfigurability can also be achieved, for example, by switching the reactance coupled to the antenna.

[0087] Figure 4 Figure a shows a single patch antenna whose reflected phase can be changed by shorting a point on one side to RF ground. This has been previously demonstrated with conventional switches implemented using PIN diodes, which require a DC bias control current to be applied to the antenna patch via a biasing device (not shown). Adding a second PIN diode to this unit cell type does not enable independent control of both polarizations, as only a single bias potential can be applied to the antenna patch. The switching action for this unit cell type is well suited to achieving single polarization using embodiments of the present invention. Figure 4 b shows another type of single-polarization antenna unit cell, in which the reflection phase is reconstructed by opening and closing the switch between the two sub-patches. This switching action can also be implemented by the RF switch provided by the embodiment of the present invention. Figure 4 c shows an exemplary type of antenna unit cell designed for controlling two polarizations, in which the RF switch for phase reconstruction has been positioned near the center point of the unit cell. The motivation is that if the connection points of the RF switches can be reasonably close, they can be spanned by the size of a single chip, which can contain multiple switches. This becomes particularly suitable for switch chips provided by embodiments of the present invention, wherein the embodiment contains multiple independently controlled RF switches. Of course, several variations of the design and switch connection pattern are also possible.

[0088] Figure 5 a to 5d can be considered as Figure 4 d, and further illustrates an antenna unit cell 210 connected to a reconfigurable surface multilayer PCB. Figure 5a shows the size and shape of the chip in a flip-chip version with C4 solder bumps. Figure 5 b shows a type of antenna unit cell 210 with 90° rotational symmetry relative to the orthogonal horizontal and vertical polarization planes. A single-chip solution is possible by designing the switching function to be located in the center of the antenna unit cell 210. In 5c, a magnification of the central area of the antenna unit cell 210 is shown. Control and bias for the chip are routed through vias from the lower printed circuit board (PCB) layer (i.e., the AA cut plane). The top layer is the antenna pattern and the RF switch terminals of the chip connected to this pattern, i.e., the BB cut plane. Figure 5 Figure d shows a cross section along the AA and BB planes, including the chip and multilayer antenna PCB with configurable surface 200. The control signals, introduced from the backside layer of the PCB via microvias, can be seen connecting to the chip. The RF switch 100 connections operate directly between points 212+214 and 216+218 on the top layer, thus opening and closing the cross-connections between diagonal pairs of sub-patches. The center bump is the common ground reference for the chip, but there is no RF ground between the chip connections because the RF switch 100 is a floating device in terms of potential.

[0089] Figure 6 An example implementation of a communication device 300 including a reconfigurable surface 200, shown in a partially exploded view, is shown. The purpose of the communication device 300 may be, but is not limited to, enhancing coverage in a cellular infrastructure. The reconfigurable surface 200 may be provided in different sizes as required for a particular installation location. The exemplary communication device 300 includes a metal backplane cover 242 that may accommodate a battery compartment 244 on its upper side. A radome front cover 246 is aligned with the metal backplane cover 242 and acts as radio-transparent weather protection for the entire reconfigurable surface 200. The substrate of the reconfigurable surface 200 is arranged between the metal backplane cover 242 and the protective radome front cover 246. The antenna of the reconfigurable surface 200 is formed by rows and columns of antenna unit cells 210 arranged in an array of rows and columns. A semiconductor chip 202 containing an RF switch 100 is assembled on each unit cell 210. Furthermore, a control device 230 including control circuitry may also be located on the reconfigurable surface 200 and connected to the RF switch 100 , wherein control lines run on the multi-layer substrate of the reconfigurable surface 200 .

[0090] Figure 7 The reflective and transmissive properties of the reconfigurable surface 200 are shown, which means that the present solution can also be designed to be a transmissive reconfigurable surface (ie, Figure 7 b), and is designed not only to reflect reconfigurable surfaces (i.e. Figure 7 a) In this case, there will be no Figure 6The metal backplane cover 242 is shown to make the reconfigurable surface 200 open to EM waves in two normal directions (front and back) of the reconfigurable surface 200. This approach can also be used in other types of EM surfaces not intended for communication, such as EM shielding or filtering. These aspects are discussed in more detail in the last section of this disclosure.

[0091] Figure 8 The RF switch 100 further illustrates a second embodiment of the present invention including two memory latches. The RF switch 100 further includes a second memory latch 110', which includes a clock input 112' for receiving a common control signal (CCS) for the antenna unit cell 210 of the reconfigurable surface 200; a data input 114' connected to the data output 116 of the first memory latch 110; and a data output 116' connected to the gate 136 of the first FET 130. The second memory latch 110' is configured to transfer a data bit from the data input 114' to the data output 116' upon receiving the common control signal (CCS).

[0092] Therefore, in the second embodiment, an additional second storage latch 110' is connected to the output of the first storage latch 110. The clock input of the second storage latch 110' is connected to a common control signal (CCS), which can be represented as a LOAD signal. The gate of the first FET 130 is connected to the output of the second storage latch 110'. The first storage latch 110 is used to receive and hold the upcoming next information bit to set the first FET 130, while the second storage latch 110' holds the current information bit and directly drives the first FET 130. Thus, the first storage latch 110 becomes a "shadow register" for the next beam code bit. Cycling the common control signal through one clock cycle transfers the "next" bit from the first storage latch 110 to become the "current" bit in the second storage latch 110'.

[0093] Figure 9 Shown include Figure 8The reconfigurable surface 200 of the RF switch 100 is shown, with each RF switch having two storage latches. In this configuration, the control device 230 of the reconfigurable surface 200 is also connected to the plurality of antenna unit cells 210 via a common control line 226 and is used to transfer the data bits at the data input terminals 114', 124' of the storage latches 110', 120' to the output terminals 116', 126' of the storage latches 110', 120' by providing a common control signal (CCS).

[0094] Compared to the reconfigurable surface 200 including the RF switch provided in the first embodiment, the reconfigurable surface 200 supports the array to change its codeword pattern to a new codeword pattern immediately, rather than through sequential scanning. This requires that the common control signals (CCS) of all chips on the array are connected together and driven by a control signal from the control device 230. Therefore, for a RIS array with a size of M×M unit cells, 2M+1 outputs from the control device 230 are necessary. Depending on the driving capability of the control device 230, it may be necessary to provide a buffer level for the common control signal, for example, one buffer per column. Uploading the codeword to the array is still performed in a sequential scanning manner, and the time taken is the same as Figure 3 The previous embodiment shown is the same, but the change from one array codeword to a new codeword can now only be performed within a single clock cycle. This reduces the time that the radio waves experience undefined beamforming, during which time there is a functional interruption in the reconfigurable surface 200. Minimizing this interruption is often an important aspect of wireless network systems.

[0095] Figure 10 Also shown is an RF switch 100 including two storage latches and two FETs in a third embodiment of the present invention. In the third embodiment, the RF switch 100 further includes a second storage latch 110' and a second FET 130'. The second storage latch 110' includes a clock input 112' for receiving a clock signal (CLK), a data input 114' connected to the data output 116 of the first storage latch 110, and a data output 116'; while the second FET 130' includes a drain 132' for connecting to a third connection point 216 of the antenna unit cell 210; a source 134' for connecting to a fourth connection point 218 of the antenna unit cell 210; and a gate 136' connected to the data output 116' of the second storage latch 110'.

[0096] In the third embodiment, a second storage latch 110' and a second FET 130' are added to the RF switch circuit 100 of the first embodiment. The gate 136 of the first FET 130 is connected to the output 116 of the first storage latch 110, and the gate 136' of the second FET 130' is connected to the output 116' of the second storage latch 110'. A general extension of the third embodiment is to use two or more FET switch / latch pairs added in parallel to form a multi-bit switch chip. The multi-bit switch chip is suitable for creating multiple phase states for the antenna unit cell 210 by controlling multiple surface current paths in different patterns between multiple connection points on the reconfigurable surface 200, and can be regarded as replicating the RF switch circuit 100 of the first embodiment. Figure 10 The two storage latches in the array are connected as a shift register. Thus, bits are written to the chip as a sequence on DATA while clocking CLK for the required period. Each data output of the storage latch drives the gate of a FET switch. As with the first embodiment of the RF switch, codeword programming on the array can be accomplished by sequentially scanning column by column.

[0097] Figure 11 An example of the physical layout of the chip device 202 as viewed from the bottom side is shown, including the external connections to the solder bumps. Figure 8 The RF switch 100 is shown. In this example, two RF switches are arranged crosswise so that they are suitable for reconstructing the reflection phase for two orthogonal polarizations. The antenna layout requires that the four switch connection points are very close to each other so that the chip can span them. Figure 11 As can be seen in Figure 2, the chip size is largely determined by the number, size, and spacing of the connection bumps. In comparison, the chip area required to layout one or more storage latches and one or more RF switch FETs is smaller and fits within the space between the interconnects.

[0098] Figure 12FIG. 4 illustrates an RF switch 100 including four storage latches and two FETs, provided by a fourth embodiment of the present invention. In this embodiment, the RF switch 100 includes a third storage latch 120, which includes a clock input 122 for receiving a clock signal; a data input 124 connected to the data output 116 of the first storage latch 110; and a data output 126. The RF switch 100 also includes a fourth storage latch 120', which includes a clock input 122' for receiving a common control signal for the antenna unit cells 210 of the reconfigurable surface 200; a data input 124' connected to the data output 126 of the third storage latch 120; and a data output 126'. The fourth storage latch 120' is configured to transmit a data bit from the data input 124' to the data output 126' upon receiving the common control signal. The RF switch 100 further includes a second FET 130', which includes a drain 132' for connecting to the third connection point 216 of the antenna unit cell 210; a source 134' for connecting to the fourth connection point 218 of the antenna unit cell 210; and a gate 136' connected to the data output terminal 126' of the fourth storage latch 120'.

[0099] The fourth embodiment relates to the third embodiment in the same way as the second embodiment relates to the first embodiment. First and second storage latches 110, 110' are connected as a shift register, which is loaded by sequentially presenting two data bits on DATA while cycling CLK twice. Third and fourth storage latches 120, 120' are connected to the outputs of first and second storage latches 110, 110', respectively. The output of second storage latch 110' drives first FET 130, and the output of fourth storage latch 120' drives second FET 130'. A common control signal is added and connected to the clock inputs of second and fourth storage latches 110', 120'. The codeword is uploaded to the shadow registers of first and third storage latches 110, 120, while the current codeword remains stable in the array. Like the second embodiment, the additional storage latches, ie, the second storage latch 110 ′ and the fourth storage latch 120 ′, can instantly change the switch state when the common control signal is switched for one cycle.

[0100] A general extension of the fourth embodiment is to use more than two RF switches, in which case the number of storage latches will increase accordingly. This forms a multi-bit switch chip that is suitable for creating phase states for the antenna unit cell 210 by controlling multiple surface current paths in different modes between multiple connection points on the reconfigurable surface 200. In embodiments where the RF switch 100 includes two or more FETs, each FET can be connected to a common reference ground 204. Therefore, in Figure 12 In the embodiment, the source 134 ′ of the second FET 130 ′ is connected to the common reference ground 204 through the second resistor 140 ′.

[0101] Figure 13 The fifth embodiment of the present invention is shown as an RF switch 100 including two storage latches and two FETs. In this embodiment, the two FETs are connected in series between a first connection point 212 and a second connection point 214. Therefore, the RF switch 100 includes a second storage latch 110', which includes: a clock input terminal 112' for receiving a clock signal; a data input terminal 114' connected to the data output terminal 116 of the first storage latch 110; and a data output terminal 116'. The RF switch 100 also includes a second FET 130', which includes: a drain 132' for connecting to the source 134 of the first FET 130; a source 134' for connecting to the second connection point 214 of the antenna unit cell 210; and a gate 136' connected to the data output terminal 116' of the second storage latch 110'. In this embodiment, the first FET 130 has a first gate width, and the second FET 130 ′ has a second gate width different from the first gate width, which will be further explained below.

[0102] Thus, in the fifth embodiment, two or more storage latches are integrated with two FETs connected in series to form a multi-bit switch chip suitable for creating multiple phase states for antenna unit cell 210 by varying the capacitance between two connection points on reconfigurable surface 200, ultimately creating a short circuit or low resistance between the two connection points. The fifth embodiment is based on the same principles as the third embodiment, but the first FET 110 and the second FET 110' are internally connected in series and connected to two connection points 212 and 214. The distinguishing feature of this configuration is that, due to the difference in gate width, the "off capacitance" and "on resistance" of the first FET 110 and the second FET 110' are combined to create a step-variable impedance, which can be used to create phase change steps with increased resolution on antenna unit cell 210. In this sense, the first FET 110 and the second FET 110' operate as a combined switch and a step-variable capacitance diode, the operation of which is described below. Figure 14 Figure 1 shows an equivalent model of a single FET operating in switch mode. When in the off state, the switch exhibits a leakage capacitance determined by the size and geometry of the transistor, primarily its gate width for a given process. To maximize the switch's isolation of RF signals, this capacitance needs to be kept as small as possible and its reactance as large as possible. However, it is never possible to achieve zero capacitance, so there will always be a residual "off capacitance," denoted as C. off When in the closed state, the FET channel enters conduction, C off Effectively represented as R on The "closing resistor" should be much smaller than C for effective switching operation. off The reactance generated.

[0103] When designing a high-frequency antenna unit cell for the reconfigurable surface 200, it was found that the switch C off The magnitude of C affects the reflection phase. This is natural because the capacitor has a 90° phase shift between current and voltage. If the switch is designed so that C off can be changed, this can be turned into an advantage for the reconfigurable surface 200. By increasing the quantization of the phase reconstruction of the antenna unit cells 210, the beamforming radiation pattern can be improved in terms of better reflection gain, lower sidelobe level and wider steering angle.

[0104] By connecting two switching FETs in series and utilizing the formula for series capacitors, a step impedance device can be realized with three capacitance values followed by a fourth resistance value. Figure 15 Explained in Figure 15 Possible options and equivalent model schematics are shown, which present the situation when the upper FET, the lower FET, or the upper FET and the lower FET are closed and open. Due to the different sizes of the first FET 130 and the second FET 130', the capacitance step size can be customized. Figure 15 In the example shown in FIG1 , the gate width of the first FET 130 is twice that of the second FET 130′. This will make the C off The value is approximately the C of the second FET 130' off twice the value, and R on The value is approximately the R on half of its value. From the connection points 212 and 214, it will appear as a single component that can take on different impedance values. By jointly designing the antenna unit cell and the FET switch in series, the reflection phase can be designed to obtain more quantization levels. Compared to a single FET switch, the fifth embodiment increases R on, thus slightly sacrificing the reflection loss of the reconfigurable surface. More than two FETs can be used and the switch control can be expanded accordingly, at the expense of further increasing the series resistance R on .

[0105] Figure 16 The sixth embodiment of the present invention shows an RF switch 100 including four storage latches and two FETs. The two FETs are connected in series between a first connection point 212 and a second connection point 214. Therefore, the RF switch 100 includes a third storage latch 120, which includes a clock input 122 for receiving a clock signal (CLK); a data input 124 connected to the data output 116 of the first storage latch 110; and a data output 126. The RF switch 100 includes a fourth storage latch 120', the fourth storage latch 120' including: a clock input 122' for receiving a common control signal for the antenna unit cell 210 of the reconfigurable surface 200; a data input 124' connected to the data output 126 of the third storage latch 120; and a data output 126', wherein the fourth storage latch 120' is used to transfer a data bit from the data input 124' to the data output 126' when the common control signal is received. The RF switch 100 includes a second FET 130', the second FET 130' including: a drain 132' for connecting to the source 134 of the first FET 130; a source 134' for connecting to the second connection point 214 of the antenna unit cell 210; and a gate 136' connected to the data output 116' of the second storage latch 110'. Figure 13 As shown, the first FET 130 has a first gate width, and the second FET 130' has a second gate width different from the first gate width.

[0106] The sixth embodiment is an extension of the fifth embodiment and follows the same principle as the fourth embodiment. Figure 16 Compared to the fourth embodiment, the first FET 130 and the second FET 130' are internally connected in series and connected to two connection points 212 and 214. Therefore, the switching function is equivalent to the fifth embodiment, while the programming and codeword switching functions are equivalent to the fourth embodiment. This forms a multi-bit RF switch that is suitable for creating multiple phase states for the antenna unit cell 210 by creating a step-variable impedance between the two connection points 212 and 214 on the reconfigurable surface. The addition of the third storage latch 120 and the fourth storage latch 120' supports preloading the next bit pattern into the shadow register composed of the first storage latch 110 and the third storage latch 120, and then changing to the new switch setting by cycling the common control signal instead of scanning row by row in one instance.

[0107] Figure 17 The physical layout of the chip device is shown, in which the design concepts from the disclosed embodiments can be combined to achieve various goals of RF switch paths with higher complexity. 17a shows such a combination provided by the fourth embodiment with two independent switch paths, each switch path including the 2-bit RF switch provided by the sixth embodiment. Independently setting up the two 2-bit switch paths requires uploading 4 bits, so the shift register needs to have 4 storage latches to form a shadow register. The outputs of the 4 storage latches drive 4 other storage latches that form a current register, and the output of the current register drives the gate of the FET. In contrast, if complementary switch path operation is required, the number of storage latches can be reduced to 4, and the complementary outputs Q and Q from the third storage latch 120 and the fourth storage latch 120' are connected to the gate of the FET. It can be used to drive four switches of two 2-bit switch paths. The chip pinout is Figure 17 The top of a is shown, the equivalent circuit diagram is Figure 17 17b shows another example of increased complexity, where two switching sections are grouped according to the second embodiment, each holding a 2-bit RF switch, using two series-connected FETs to create the step-variable impedance provided by the sixth embodiment. The total number of bits required to set the switching conditions is 4, so in this case a shadow register with four storage latches is required. The current register also requires four storage latches, but because the opposite sections are grouped, the output of each storage latch is shared between the first FET 130 and the second FET 130′ in the two paths, respectively.

[0108] Figure 18a and Figure 18b Together, the reconfigurable surface 200 is shown as being used in a communication scenario. For example, the communication system may be 3GPP NR using a high frequency band for high bit rates. Therefore, the radio frequency used for the RF switch 100 and the reconfigurable surface 200 may be in the centimeter or millimeter wavelength range. Figure 18a A street scene is shown with one BS on top of a building B1, and five users UE1 to UE5. The BS can connect to users UE1 to UE3 via direct beamforming, but users UE4 and UE5 are blocked by building B2 and cannot be connected via the BS beam in the line of sight (LOS) path. There are also no reflections different from other buildings, and users UE4 and UE5 can be connected to via a non-line of sight (NLOS) path. By arranging the configurable surface 200 provided by an embodiment of the present invention on the wall of building B3 on an open line-of-sight path starting from the BS, a new controllable NLOS path can be created from the BS to the shadow area behind building B2, as shown in FIG. Figure 18b As shown. Users UE4 and UE5 can thus also be connected to the BS, increasing its coverage area. The BS directs the beam toward the configurable surface 200, which in turn redirects the reflected beam over a wide range of angles to locate the user. The controlled beamforming performed by the configurable surface 200 is reciprocal and effective for both downlink and uplink communications. The configurable surface 200 can be controlled by the BS via a separate control link. To achieve low deployment cost, low visual impact, and non-intrusiveness, the configurable surface 200 can be installed on the building without a wired connection to the power or data network. The average power consumption of the configurable surface 200 is low, typically less than 0.5W, so it is sufficient to be powered by a small solar panel with a rechargeable battery backup. To achieve this low power consumption, it is necessary to use a beam steering technique on the antenna array that has near-zero static power consumption and very low power consumption when actively switching the beam.

[0109] In addition to applications of the configurable surface 200, such as RIS as a coverage enhancer in cellular networks, embodiments of the present invention can also be used for the reconfigurability of frequency selective surfaces (FSS) and radar-hiding surfaces. One aspect here is the need for reconfigurable properties, for example, the FSS can be provided with a band-stop filtering function that can be turned on or off or moved in frequency, such as a 1-bit filter surface that can be changed between two frequency responses. An example could be a radome designed to block strong interference sources from a communication link. The radome would be assisted by an observation receiver that determines the frequency of the interference source and adjusts the stopband frequency of the reconfigurable radome to a range that covers the interference source. The radome can be designed to be a conformal shape or a planar surface. Extending this concept to a larger scale, another application is that compartments or entire rooms can be sealed or opened to communicate with radio waves in a specific frequency range, such as blocking Bluetooth or cellular communications in certain situations.

[0110] Finally, it should be understood that the present invention is not limited to the embodiments described above, but also relates to and incorporates all embodiments within the scope of the appended independent claims.

Claims

1. A radio frequency switch (100) for a reconfigurable surface (200), characterized in that: The radio frequency switch (100) comprises: A first storage latch (110), comprising: a clock input terminal (112) for receiving a clock signal (CLK), a data input terminal (114) for receiving a data bit, and a data output terminal (116) for outputting the data bit; A first field effect transistor (FET) (130) includes a drain (132) for connecting to a first connection point (212) of an antenna unit cell (210) of the reconfigurable surface (200); a source (134) for connecting to a second connection point (214) of the antenna unit cell (210); and a gate (136) connected to the data output terminal (116) of the first storage latch (110), wherein the first FET (130) is configured to be in a closed state when the data bit has a first value and in an open state when the data bit has a second value different from the first value, thereby acting as a switch.

2. The radio frequency switch (100) according to claim 1, characterized in that The first storage latch (110) and the first FET (130) are arranged on a common single chip (202).

3. The radio frequency switch (100) according to claim 1 or 2, characterized in that: The first FET (130) is an N-channel FET.

4. The radio frequency switch (100) according to any one of the preceding claims, characterized in that: The source (134) of the first FET (130) is connected to a common reference ground (204) via a first resistor (140).

5. The radio frequency switch (100) according to any one of the preceding claims, characterized in that: The clock input terminal (112) of the first storage latch (110) is used to connect to the column line (234) of the reconfigurable surface (200), and the data input terminal (114) of the first storage latch (110) is used to connect to the row line (232) of the reconfigurable surface (200), or vice versa.

6. The radio frequency switch (100) according to any one of claims 1 to 5, characterized in that: Also includes: A second storage latch (110'), the second storage latch (110') comprising: a clock input terminal (112') for receiving a common control signal (CCS) for the antenna unit cell (210) of the reconfigurable surface (200); a data input terminal (114') connected to the data output terminal (116) of the first storage latch (110); and a data output terminal (116') connected to the gate (136) of the first FET (130), wherein the second storage latch (110') is configured to transfer a data bit from the data input terminal (114') to the data output terminal (116') when receiving the common control signal (CCS).

7. The radio frequency switch (100) according to claim 6, characterized in that: Also includes: a third storage latch (120), the third storage latch (120) comprising: a clock input terminal (122) for receiving the clock signal (CLK), a data input terminal (124) connected to the data output terminal (116) of the first storage latch (110), and a data output terminal (126); a fourth storage latch (120'), the fourth storage latch (120') comprising: a clock input terminal (122') for receiving a common control signal (CCS) for the antenna unit cell (210) of the reconfigurable surface (200); a data input terminal (124') connected to the data output terminal (126) of the third storage latch (120); and a data output terminal (126'), wherein the fourth storage latch (120') is configured to transmit a data bit from the data input terminal (124') to the data output terminal (126') when receiving the common control signal (CCS); A second FET (130'), the second FET (130') comprising: a drain (132') for connecting to a third connection point (216) of the antenna unit cell (210); a source (134') for connecting to a fourth connection point (218) of the antenna unit cell (210); and a gate (136') connected to the data output terminal (126') of the fourth storage latch (120').

8. The radio frequency switch (100) according to claim 6, characterized in that: Also includes: a third storage latch (120), the third storage latch (120) comprising: a clock input terminal (122) for receiving the clock signal (CLK), a data input terminal (124) connected to the data output terminal (116) of the first storage latch (110), and a data output terminal (126); a fourth storage latch (120'), the fourth storage latch (120') comprising: a clock input terminal (122') for receiving a common control signal (CCS) for the antenna unit cell (210) of the reconfigurable surface (200); a data input terminal (124') connected to the data output terminal (126) of the third storage latch (120); and a data output terminal (126'), wherein the fourth storage latch (120') is configured to transmit a data bit from the data input terminal (124') to the data output terminal (126') when receiving the common control signal (CCS); a second FET (130'), the second FET (130') comprising: a drain (132') for connecting to the source (134) of the first FET (130); a source (134') for connecting to the second connection point (214) of the antenna unit cell (210); and a gate (136') connected to the data output terminal (116') of the second storage latch (110'); wherein The first FET (130) has a first gate width, and the second FET (130') has a second gate width different from the first gate width.

9. The radio frequency switch (100) according to any one of claims 1 to 5, characterized in that: Also includes: a second storage latch (110'), the second storage latch (110') comprising: a clock input terminal (112') for receiving the clock signal (CLK), a data input terminal (114') connected to the data output terminal (116) of the first storage latch (110), and a data output terminal (116'); A second FET (130'), the second FET (130') comprising: a drain (132') for connecting to a third connection point (216) of the antenna unit cell (210); a source (134') for connecting to a fourth connection point (218) of the antenna unit cell (210); and a gate (136') connected to the data output terminal (116') of the second storage latch (110').

10. The radio frequency switch (100) according to any one of claims 1 to 5, characterized in that: Also includes: a second storage latch (110'), the second storage latch (110') comprising: a clock input terminal (112') for receiving the clock signal (CLK), a data input terminal (114') connected to the data output terminal (116) of the first storage latch (110), and a data output terminal (116'); a second FET (130'), the second FET (130') comprising: a drain (132') for connecting to the source (134) of the first FET (130); a source (134') for connecting to the second connection point (214) of the antenna unit cell (210); and a gate (136') connected to the data output terminal (116') of the second storage latch (110'); wherein The first FET (130) has a first gate width, and the second FET (130') has a second gate width different from the first gate width.

11. The radio frequency switch (100) according to any one of claims 7 to 10, characterized in that: The source (134') of the second FET (130') is connected to a common reference ground (204) via a second resistor (140').

12. The radio frequency switch (100) according to any one of the preceding claims, characterized in that: The radio frequency is in the centimeter or millimeter wavelength range.

13. A reconfigurable surface (200), characterized in that include: A plurality of antenna unit cells (210), wherein each antenna unit cell (210) comprises a radio frequency switch (100) according to any one of the preceding claims, the radio frequency switch (100) being connected between connection points (212, 214, 216, 218) of the antenna unit cell (210); A control device (230) is connected to the plurality of antenna unit cells (210) via a plurality of column lines (234) and a plurality of row lines (232), and is used to control the radio frequency switches (100) of the plurality of antenna unit cells (210) by providing a clock signal (CLK) on the row lines (222) and a plurality of data bits on the column lines (224), or vice versa.

14. The reconfigurable surface (200) according to claim 13, characterized in that The control device (230) is also connected to the plurality of antenna unit cells (210) via a common control line (226) and is used to transmit the data bits at the data input terminals (114', 124') of the storage latches (110', 120') to the output terminals (116', 126') of the storage latches (110', 120') by providing a common control signal (CCS).

15. The reconfigurable surface (200) according to claim 13 or 14, characterized in that The plurality of data bits represent a codeword of a beamforming scheme.

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