Sensing and computing integrated method based on composite dielectric gate dual transistor photodetector

Abstract

The present invention discloses a sensing and computing integrated method based on a composite dielectric gate dual-transistor photodetector, which belongs to the intersection of optoelectronic devices and analog computing. By using the change in the threshold voltage generated by the composite dielectric gate dual-transistor photodetector after photoelectric conversion as a signal to characterize the excitation, and a period of driving voltage timing applied to its gate end as a signal to characterize the positive and negative weights; the multiplication calculation of the optical excitation signal and the weight signal of the composite dielectric gate dual-transistor photodetector is realized according to the threshold voltage and the driving voltage; this method provides an efficient and low-power solution for the application requirements of the fusion of composite dielectric gate dual-transistor photodetector and analog multiplication calculation, while breaking through the limitation that traditional optoelectronic devices can only process non-negative signals, realizing the coordinated symbolic operation of the analog domain and the digital domain, and providing an innovative way of device-level multiplication operation for edge visual sensing and real-time neural network calculation.

Description

Technical Field

[0001] The present invention belongs to the intersection of optoelectronic devices and analog computing, and specifically relates to a sensing and computing integrated method based on a composite dielectric gate dual-transistor photosensitive detector. Background Art

[0002] With the rapid development of artificial intelligence, the Internet of Things, and edge computing, traditional visual information processing systems based on the von Neumann architecture face challenges such as data handling bottlenecks, high power consumption, and latency. Especially in the optical signal processing scenario, existing technologies usually require the analog signals collected by the optical sensor to be converted into digital form before being transmitted to the processor for calculation. In addition to the conversion time of the analog-to-digital converter itself, the process of transmitting data to the processor will increase the system latency; and these transmitted data may include non-critical data or data that is not required for subsequent processing, resulting in redundant data migration, increasing the burden of data transmission, and thus affecting the operating efficiency of the entire system; in addition, this physically separated sensing and computing mode cannot achieve efficient and coordinated energy consumption control, resulting in increased energy consumption of the system; seriously restricting the energy efficiency and real-time performance of the system.

[0003] Although traditional photodetectors can convert light intensity to current, the subsequent weighted multiplication and addition operations still rely on digital processors, resulting in a large amount of redundant data migration and energy consumption. In recent years, the rise of near-sensing computing and in-memory computing technologies has provided new solutions to this problem. Near-sensing computing connects sensors with front-end data processing, migrating some computing tasks from traditional processors to locations close to the sensors. In-memory computing is a computing model that embeds computing tasks directly into data storage for processing. The rise of these two technologies has provided new solutions to this problem, but existing solutions based on these two technologies mostly implement analog computing at the circuit level. During the calculation process, the analog signal is disturbed, resulting in reduced accuracy and affecting the final calculation results. In addition, a certain bias current is required to ensure the processing of the analog signal, and additional linear components are needed to maintain the stability of the analog calculation, which leads to limited energy efficiency. In addition, analog computing circuits have high manufacturing process requirements and poor scalability, making it difficult to achieve a deep integration of the intrinsic characteristics of optoelectronic devices and computing functions.

[0004] Although some sensing and computing devices made of new materials can solve the above-mentioned problems, such as photoelectric memristors, spintronic devices, and two-dimensional material devices, the preparation process of these devices is difficult and their stability is relatively poor.

[0005] In this context, there is an urgent need to develop a device architecture that is compatible with standard semiconductor processes and has the dual functions of photoelectric sensing and analog computing. Through the coordinated optimization of photoelectric physical effects and transistor control mechanisms, parallel multiplication operations of optical signals and electrical signals can be realized directly at the device level, thereby breaking through the energy efficiency bottleneck of traditional systems and providing a hardware foundation for intelligent visual perception and optical computing acceleration. Summary of the Invention

[0006] The purpose of the present invention is to provide a multiplication calculation method based on a composite dielectric gate dual-transistor photosensitive detector. The method uses the change in threshold voltage generated after photoelectric conversion of the composite dielectric gate dual-transistor photosensitive detector as a signal representing light excitation, and uses a section of driving voltage applied to its gate end as a signal representing positive and negative weights; and realizes the multiplication calculation of the light excitation signal and the weight signal of the composite dielectric gate dual-transistor photosensitive detector according to the threshold voltage and the driving voltage.

[0007] The source terminal of the composite dielectric gate dual-transistor photodetector is grounded, the gate terminal is connected to a driving voltage, and the drain terminal is connected to an analog-to-digital converter.

[0008] The driving voltage applied to the gate terminal is a constant voltage, and the corresponding weight is W. The timing is divided into two equal-length stages A and B. The weights corresponding to stages A and B are W_1 and W_2, respectively. The relationship between the driving voltage weight W and the corresponding weights of stages A and B is:

[0009] W = W_1–W_2;

[0010] When the weight W_1 corresponding to stage A is greater than the weight W_2 corresponding to stage B, the weight W of the driving voltage is positive; when the weight W_1 corresponding to stage A is less than the weight W_2 corresponding to stage B, the weight W of the driving voltage is negative.

[0011] The drain terminal is connected to an N-bit analog-to-digital converter, which converts the results generated by phases A and B from the analog domain to the digital domain;

[0012] Under the action of the gate driving voltage in phase A and phase B and the N-bit analog-to-digital converter connected to the drain, the composite dielectric gate dual-transistor photodetector generates two N-bit binary data, Result_A and Result_B, respectively. The two are subjected to a signed subtraction operation in the digital domain, and finally the multiplication calculation result Result of the excitation signal generated by the composite dielectric gate dual-transistor photodetector and the weight signal is obtained. The result is also an N-bit signed number.

[0013] Furthermore, the driving voltage at the gate end of the composite dielectric gate dual-transistor photosensitive detector is a positive high voltage VP, and the driving timing is composed of alternating high and low levels. When the driving timing is a high level, the voltage applied to the gate end of the composite dielectric gate dual-transistor photosensitive detector is VP; when the driving timing is a low level, the voltage applied to the gate end of the composite dielectric gate dual-transistor photosensitive detector is 0.

[0014] Furthermore, the timing of the driving voltage includes two forms:

[0015] Form 1: Pulse width modulation operation is performed on n-bit binary weights, assuming that the n-bit binary number is M, that is, , then in a single phase A or phase B, it contains M consecutive high levels, A continuous low level;

[0016] Form 2: Based on the number of bits n of the binary weight, a single phase A or phase B contains n intervals. The duration of each interval is configurable, and the drive voltage is high or low within each interval depending on whether the n-bit binary data corresponding to the interval is 1 or 0. In a single phase A or phase B, the drive voltage is low except for the aforementioned n intervals.

[0017] Furthermore, corresponding to different forms of driving voltage timing, the calculation results are:

[0018] Result 1: After passing through the N-bit analog-to-digital converter, phases A and B will generate two N-bit binary data, Result_A and Result_B. Result_A and Result_B are directly subtracted in the digital domain to obtain the final multiplication result.

[0019] Result 2: Taking stage A as an example, in stage A, each of the n intervals produces an ADC result. That is, after the ADC passes through n intervals, it produces Result_A_tmp_1, Result_A_tmp_2, Result_A_tmp_3, …, Result_A_tmp_n-1, Result_A_tmp_n, for a total of n ADC results. Result_A_tmp_n, generated by the nth interval (the interval corresponding to the most significant bit) corresponding to the n-bit binary weight, is shifted left one bit and then added to Result_A_tmp_n-1, generated by the n-1th interval (the interval corresponding to the next most significant bit) corresponding to the n-bit binary weight. The accumulated result is then shifted left one bit again, and this process is repeated until Result_A_tmp_1, generated by the first interval (the interval corresponding to the least significant bit) corresponding to the n-bit binary weight, is added. This result is then passed through an N-bit analog-to-digital converter to obtain the final Result_A for stage A. The same process applies to stage B. Result_A and Result_B are then subtracted in the digital domain to obtain the final multiplication result, Result.

[0020] The beneficial effects of the present invention are:

[0021] The present invention provides a sensing-computing integrated method based on a composite dielectric gate dual-transistor photodetector. By converting the light excitation signal into a change in the device's threshold voltage and using the gate drive voltage modulated in stages as programmable positive and negative weight signals, combined with a digital domain differential computing mechanism, this method solves the problems of low energy efficiency and high latency caused by the separation of photoelectric sensing and computing units in traditional light detection systems, as well as the difficulty of existing sensing-computing integrated solutions in directly supporting positive and negative weight operations. This method achieves efficient multiplication of light signals and weights in situ at the sensor end, significantly reducing data movement energy consumption and system latency. Furthermore, this method utilizes flexible configuration of the drive voltage timing (pulse width modulation or binary bit mapping) to achieve weight precision expansion, and naturally compatibility with positive and negative weight operations through two-stage differential output, significantly improving the energy efficiency and flexibility of the optical computing system. This provides an innovative approach to device-level multiplication operations for edge visual sensing and real-time neural network computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1This is a hardware structure and principle diagram of a sensing and computing method based on a composite dielectric gate dual-transistor photodetector provided by the present invention, in which the driving voltage is a pulse width modulated driving waveform to achieve a multiplication calculation of 4-bit weight × 4-bit excitation;

[0024] Figure 2 This is a hardware structure and principle diagram of a sensing and computing method based on a composite dielectric gate dual-transistor photodetector provided by the present invention, which realizes the multiplication calculation of 4-bit weight × 4-bit excitation in a binary representation form of the driving voltage. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0026] Example 1

[0027] This embodiment provides a sensing and computing method based on a composite dielectric gate dual-transistor photosensitive detector. This method uses the change in threshold voltage generated after photoelectric conversion of the composite dielectric gate dual-transistor photosensitive detector as a signal representing light excitation, and uses a driving voltage applied to its gate end as a signal representing positive and negative weights; the multiplication calculation of the light excitation signal and the weight signal of the composite dielectric gate dual-transistor photosensitive detector is realized according to the threshold voltage and the driving voltage.

[0028] The source terminal of the composite dielectric gate dual-transistor photodetector is grounded, the gate terminal is connected to a driving voltage, and the drain terminal is connected to an analog-to-digital converter.

[0029] The driving voltage applied to the gate terminal is a constant voltage, and the corresponding weight is W. The timing is divided into two equal-length stages A and B. The weights corresponding to stages A and B are W_1 and W_2, respectively. The relationship between the driving voltage weight W and the corresponding weights of stages A and B is:

[0030] W = W_1–W_2;

[0031] When the weight W_1 corresponding to stage A is greater than the weight W_2 corresponding to stage B, the weight W of the driving voltage is positive; when the weight W_1 corresponding to stage A is less than the weight W_2 corresponding to stage B, the weight W of the driving voltage is negative.

[0032] The drain terminal is connected to an N-bit analog-to-digital converter, which converts the results generated by phases A and B from the analog domain to the digital domain;

[0033] Under the action of the gate driving voltage in phase A and phase B and the N-bit analog-to-digital converter connected to the drain, the composite dielectric gate dual-transistor photodetector generates two N-bit binary data, Result_A and Result_B, respectively. The two are subjected to a signed subtraction operation in the digital domain, and finally the multiplication calculation result Result of the excitation signal generated by the composite dielectric gate dual-transistor photodetector and the weight signal is obtained. The result is also an N-bit signed number.

[0034] The driving voltage at the gate end of the composite dielectric gate dual-transistor photosensitive detector is a positive high voltage VP, and the driving timing is composed of alternating high and low levels. When the driving timing is a high level, the voltage applied to the gate end of the composite dielectric gate dual-transistor photosensitive detector is VP; when the driving timing is a low level, the voltage applied to the gate end of the composite dielectric gate dual-transistor photosensitive detector is 0.

[0035] The timing of the driving voltage includes: using pulse width modulation operation on n-bit binary weight, that is, assuming that the n-bit binary number is M, that is , then in a single phase A or phase B, it contains M consecutive high levels, A continuous low level;

[0036] Phase A and phase B will generate two N-bit binary data Result_A and Result_B respectively. The obtained Result_A and Result_B are directly subtracted in the digital domain with a sign to obtain the final multiplication result Result.

[0037] Example 2

[0038] This embodiment provides a sensing and computing integrated method based on a composite dielectric gate dual transistor photodetector, which is introduced by taking the implementation of 4-bit weight × 4-bit excitation as an example. Figure 1 As shown, a driving voltage sequence representing positive and negative weights is applied to the gate of a composite dielectric gate dual-transistor photodetector. The weight is a 4-bit signed number + 10, represented by a pulse-width modulation waveform. Phases A and B both maintain a 32 (2 to the fifth power) clock cycle. If the high level in phase A lasts for 18 clock cycles, then the high level in phase B lasts for 8 clock cycles. The source is grounded, and the drain is connected to a 9-bit analog-to-digital converter (ADC).

[0039] Since the photodetector generates photogenerated electrons when it senses light, it changes the threshold voltage of the detector. This change is considered as an excitation signal. Therefore, the excitation signal is an analog quantity, which is set to 4 bits + 12 in this embodiment. In principle, the greater the light intensity, the greater the threshold of the composite dielectric gate dual transistor photodetector, which can be regarded as a larger 4-bit excitation signal. For the same gate drive voltage timing, the larger the 4-bit excitation signal, the larger the ADC value; the smaller the excitation signal, the smaller the ADC value. In addition, for the same 4-bit excitation signal, the greater the weight represented by stage A or stage B, the longer the corresponding drive time, which means that the drain current integration time is longer, the integration capacitor voltage is higher, and the ADC value is larger; conversely, the smaller the drive time corresponding to the weight value, the smaller the ADC value.

[0040] Phase A maintains a total of 32 clks, with 18 consecutive high levels. The ADC result obtained after phase A is 9-bit Result_A, which is 9'b011011000. Phase B maintains a total of 32 clks, with 8 consecutive high levels. The ADC result obtained after phase A is 9-bit Result_B, which is 9'b001100000. Signed subtraction of Result_A and Result_B in the digital domain produces a signed 8-bit multiplication result, Result, which is 8'b01111000.

[0041] Example 3

[0042] This embodiment provides another implementation method of the sensing-calculation integrated method based on a composite dielectric gate dual-transistor photosensitive detector. This method uses the change in the threshold voltage generated after the photoelectric conversion of the composite dielectric gate dual-transistor photosensitive detector as a signal representing light excitation, and uses a section of driving voltage applied at its gate end as a signal representing positive and negative weights; and implements the multiplication calculation of the light excitation signal and the weight signal of the composite dielectric gate dual-transistor photosensitive detector based on the threshold voltage and the driving voltage.

[0043] The source terminal of the composite dielectric gate dual-transistor photodetector is grounded, the gate terminal is connected to a driving voltage, and the drain terminal is connected to an analog-to-digital converter.

[0044] The driving voltage applied to the gate terminal is a constant voltage, and the corresponding weight is W. The timing is divided into two equal-length stages A and B. The weights corresponding to stages A and B are W_1 and W_2, respectively. The relationship between the driving voltage weight W and the corresponding weights of stages A and B is:

[0045] W = W_1–W_2;

[0046] When the weight W_1 corresponding to stage A is greater than the weight W_2 corresponding to stage B, the weight W of the driving voltage is positive; when the weight W_1 corresponding to stage A is less than the weight W_2 corresponding to stage B, the weight W of the driving voltage is negative.

[0047] The drain terminal is connected to an N-bit analog-to-digital converter, which converts the results generated by phases A and B from the analog domain to the digital domain;

[0048] Under the action of the gate driving voltage in phase A and phase B and the N-bit analog-to-digital converter connected to the drain, the composite dielectric gate dual-transistor photodetector generates two N-bit binary data, Result_A and Result_B, respectively. The two are subjected to a signed subtraction operation in the digital domain, and finally the multiplication calculation result Result of the excitation signal generated by the composite dielectric gate dual-transistor photodetector and the weight signal is obtained. The result is also an N-bit signed number.

[0049] The driving voltage at the gate end of the composite dielectric gate dual-transistor photosensitive detector is a positive high voltage VP, and the driving timing is composed of alternating high and low levels. When the driving timing is a high level, the voltage applied to the gate end of the composite dielectric gate dual-transistor photosensitive detector is VP; when the driving timing is a low level, the voltage applied to the gate end of the composite dielectric gate dual-transistor photosensitive detector is 0.

[0050] The timing of the drive voltage is determined by the number of bits, n, of binary weights, with each phase A or B containing n intervals. The duration of each interval is configurable, and whether the drive voltage is high or low within each interval depends on whether the n-bit binary data corresponding to the interval is 1 or 0. In a single phase A or B, the drive voltage is low except for the aforementioned n intervals.

[0051] Taking stage A as an example, in stage A, each of the n intervals produces an ADC result. That is, after the ADC passes through n intervals, it produces Result_A_tmp_1, Result_A_tmp_2, Result_A_tmp_3, …, Result_A_tmp_n-1, Result_A_tmp_n, for a total of n ADC results. Result_A_tmp_n, generated by the nth interval (the interval corresponding to the most significant bit) corresponding to the n-bit binary weight, is shifted left one bit and then added to Result_A_tmp_n-1, generated by the n-1th interval (the interval corresponding to the next most significant bit) corresponding to the n-bit binary weight. The accumulated result is then shifted left one bit again, and this process is repeated until Result_A_tmp_1, generated by the first interval (the interval corresponding to the least significant bit) corresponding to the n-bit binary weight, is added to obtain the final Result_A for stage A. The same process applies to stage B. Result_A and Result_B are then subtracted in the digital domain using signed subtraction to obtain the final multiplication result.

[0052] Example 4

[0053] This embodiment provides a sensing and computing integrated method based on a composite dielectric gate dual transistor photodetector. Based on the implementation method introduced in the third embodiment, the method is introduced by taking the implementation of 4-bit weight × 4-bit excitation as an example. Figure 2 As shown, a driving timing waveform representing a 4-bit negative weight of -6 is passed through the gate end of the composite dielectric gate dual-transistor photodetector. The driving timing waveform is also divided into stage A and stage B. The weight represented by stage A is set to be the 4-bit signed number 1001, that is, +9; the weight represented by stage B is set to be the 4-bit signed number 1111, that is, +15; its source end is grounded, and the drain end is connected to a 9-bit analog-to-digital converter (i.e., ADC); the excitation signal from the composite dielectric gate dual-transistor photodetector is an analog quantity, set to 8-bit +9.

[0054] Both phase A and phase B contain 4 intervals, and the driving voltage in each interval is high or low depending on the value of the bit corresponding to the 4-bit weight value. Taking stage A as an example, when the driving voltage corresponding to the highest bit interval of stage A is applied to the gate terminal, a 9-bit ADC result Result_A_tmp1 is obtained, which is 9'b000001001. Then, the result obtained by entering the second highest bit is Result_A_tmp2, which is 9'b000000000. This is repeated to obtain Result_A_tmp3 (9'b000000000) and Result_A_tmp4 (9'b000001001). Then, the 13-bit full-precision unsigned accumulation result Result_A corresponding to stage A is obtained by 2^3*Result_A_tmp1+2^2*Result_A_tmp2+2^1*Result_A_tmp3+2^0*Result_A_tmp4, which is 13'b0000001010001.

[0055] Similarly, after going through four intervals in stage B, the corresponding 13-bit full-precision unsigned accumulation result Result_B is obtained, which is 13'b0000010000111. Then, by performing a signed subtraction between Result_A and Result_B in the digital domain, a signed 12-bit multiplication result Result is obtained, which is 12'b111111001010, or -54 in decimal.

[0056] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A sensing and computing method based on a composite dielectric gate dual transistor photodetector, characterized in that: The sensing and computing integrated method uses the change in threshold voltage generated by photoelectric conversion of the composite dielectric gate dual-transistor photosensitive detector as a signal representing light excitation, and the driving voltage applied to its gate end as a signal representing positive and negative weights; and implements multiplication calculation of the light excitation signal of the composite dielectric gate dual-transistor photosensitive detector and the weight signal based on the change in threshold voltage and the driving voltage; The source terminal of the composite dielectric gate dual transistor photosensitive detector is grounded, the gate terminal is connected to a driving voltage, and the drain terminal is connected to an analog-to-digital converter; The driving voltage is a constant voltage, and the corresponding weight is W. The timing is divided into two equal-length stages A and B. The weights corresponding to stages A and B are W_1 and W_2, respectively. The relationship between the driving voltage weight W and the corresponding weights of stages A and B is: W=W_1–W_2 When the weight W_1 corresponding to stage A is greater than the weight W_2 corresponding to stage B, the weight W of the driving voltage is positive; when the weight W_1 corresponding to stage A is less than the weight W_2 corresponding to stage B, the weight W of the driving voltage is negative. The driving voltage of the gate end of the composite dielectric gate dual transistor photosensitive detector is a positive high voltage VP, and the driving timing is composed of alternating high and low levels; When the driving timing is high, the voltage applied to the gate terminal of the composite dielectric gate dual transistor photodetector is VP; when the driving timing is low, the voltage applied to the gate terminal of the composite dielectric gate dual transistor photodetector is 0. When the driving voltage is in pulse form, the n-bit binary number is M, that is, , then in a single phase A or phase B, it contains M consecutive high levels, A continuous low level; The phases A and B will generate two N-bit binary data Result_A and Result_B respectively, and the obtained Result_A and Result_B are directly subtracted in digital domain to obtain the final multiplication result Result.

2. The sensing-computing integrated method according to claim 1, characterized in that: When the driving voltage is in the form of binary data, the number of n intervals included in a single stage A or stage B is determined based on the number of bits n of the binary weight, and whether the driving voltage in each interval is a high level or a low level depends on whether the bit of the n-bit binary data corresponding to the interval is 1 or 0; in a single stage A or stage B, except for the n intervals, the driving voltage is at a low level.

3. The sensing-computing integrated method according to claim 2, characterized in that: In the stage A, each of the n intervals will generate an ADC result. That is, after the ADC goes through n intervals, it will generate Result_A_tmp_1, Result_A_tmp_2, Result_A_tmp_3...Result_A_tmp_n-1, Result_A_tmp_n, for a total of n ADC results. The Result_A_tmp_n generated by the n-th interval corresponding to the n-bit binary weight needs to be shifted left by one bit, and then added to the Result_A_tmp_n-1 generated by the n-1-th interval corresponding to the n-bit binary weight. Then, the accumulated result is shifted left by one bit again, and this process is repeated until the Result_A_tmp_1 generated by the first interval corresponding to the n-bit binary weight is added, thereby obtaining the final Result_A corresponding to stage A. In the stage B, each of the n intervals will generate an ADC result. That is, after the ADC goes through n intervals, it will generate Result_B_tmp_1, Result_B_tmp_2, Result_B_tmp_3...Result_B_tmp_n-1, Result_B_tmp_n, a total of n ADC results; Result_B_tmp_n generated by the n-th interval corresponding to the n-bit binary weight needs to be shifted left by one bit, and then added to Result_B_tmp_n-1 generated by the n-1-th interval corresponding to the n-bit binary weight. Then, the accumulated result is shifted left by one bit again, and this process is repeated until Result_B_tmp_1 generated by the first interval corresponding to the n-bit binary weight is added, thereby obtaining the final Result_B corresponding to stage B. Perform signed subtraction of Result_A and Result_B in the digital domain to obtain the final multiplication result Result.

4. The sensing-computing integrated method according to claim 3, characterized in that: The drain end of the composite dielectric gate dual transistor photodetector is connected to an N-bit analog-to-digital converter, which converts the results generated in phases A and B from the analog domain to the digital domain.

5. A sensing and computing system based on a composite dielectric gate dual transistor photodetector, characterized in that: The integrated sensing and computing system is implemented based on the integrated sensing and computing method described in any one of claims 1 to 4 above.

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