Direct access type Hall current transmitter

Abstract

The invention discloses a direct access type Hall current transmitter which isolates the interference of a power supply on sampling input and signal output and can ensure the measurement accuracy of large current and small current. The direct access type Hall current transmitter comprises a shell and a circuit board, the circuit board is arranged in the shell, and a power input terminal, a power circuit, a power isolation circuit, a current signal input terminal, a current sampling circuit, a signal conditioning circuit and an analog signal output terminal are arranged on the circuit board; the power supply input terminal is electrically connected with the input end of the power supply circuit, the output end of the power supply circuit provides a power supply required by components on the circuit board, and the power supply isolation circuit is used for isolating interference of the power supply circuit on the current sampling circuit and the signal conditioning circuit; the current signal input terminal is electrically connected with the input end of the current sampling circuit, the output end of the current sampling circuit is electrically connected with the input end of the signal conditioning circuit, and the output end of the signal conditioning circuit is electrically connected with the analog signal output terminal.

Description

Technical Field

[0001] The present invention relates to the technical field of electric energy measurement, and in particular to a direct-access Hall current transmitter. Background Art

[0002] Currently, most Hall-effect current transmitters have the following drawbacks: 1. Most Hall-effect current transmitters use a through-hole connection, which means they can only measure high currents and cannot guarantee the accuracy of low current measurements. 2. Most through-hole Hall-effect current transmitters are three-wire transmitters, and the auxiliary power supply is not isolated from the signal output. A failure of the auxiliary power supply may damage the ports of downstream receiving devices. 3. Most Hall-effect current transmitters have an internal magnetic core, which can produce residual magnetism after being subjected to high current shocks, resulting in signal output when there is no current. Summary of the Invention

[0003] The purpose of the present invention is to overcome the defects in the prior art and provide a direct-access Hall current transmitter that isolates the interference of power supply on sampling input and signal output and can ensure the measurement accuracy of large current and small current.

[0004] To achieve the above-mentioned purpose, the technical solution of the present invention is to design a direct-access Hall current transmitter, comprising: a housing and a circuit board; The circuit board is arranged in the housing, and is provided with a power input terminal, a power circuit, a power isolation circuit, a current signal input terminal, a current sampling circuit, a signal conditioning circuit, and an analog signal output terminal; The power input terminal is electrically connected to the input end of the power circuit, the output end of the power circuit provides the power required by the components on the circuit board, and the power isolation circuit is used to isolate the interference of the power circuit on the current sampling circuit and the signal conditioning circuit; The current signal input terminal is electrically connected to the input end of the current sampling circuit, the output end of the current sampling circuit is electrically connected to the input end of the signal conditioning circuit, and the output end of the signal conditioning circuit is electrically connected to the analog signal output terminal; The current signal input terminal is used to connect to a circuit that requires current sampling. The current sampling circuit includes a Hall current chip. The Hall current chip is used to isolate and sample the input current of the current signal input terminal and output an analog signal whose waveform corresponds to the waveform of the input current. The signal conditioning circuit is used to zero and full adjust the output of the analog signal. The analog signal output terminal is used to transmit the analog signal to the outside.

[0005] Furthermore, the power supply circuit includes a connector J4, a varistor RV1, a first inductor L2, a second inductor L4, a first TVS tube D13, a fuse resistor F1, a first diode D9, a first electrolytic capacitor C20, a first capacitor C19, a second capacitor C21, a power chip IC1, a third inductor L3, a third capacitor C16, a fourth capacitor C10, and a fifth capacitor C22; The varistor RV1 is connected in parallel between the positive and negative pins of the connector J4. The first inductor L2 is connected to the positive pin of the connector J4. The anode of the first diode D9 is connected to the first inductor L2. The cathode of the first diode D9 is connected to the fuse resistor F1. The fuse resistor F1 is connected to the input pin of the power chip IC1. The switch pin of the power chip IC1 is connected to the first end of the third inductor L3. The switch pin of the power chip IC1 outputs a first +5V power supply. The negative electrode pin of the connector J4 is connected to the second inductor L4, which is grounded. The positive electrode of the first electrolytic capacitor C20 is connected in parallel between the path of the fuse resistor F1 and the input pin of the power chip IC1, and the negative electrode of the first electrolytic capacitor C20 is grounded. The first ends of the first capacitor C19 and the second capacitor C21 are connected in parallel between the path of the fuse resistor F1 and the input pin of the power chip IC1, and the second ends of the first capacitor C19 and the second capacitor C21 are grounded. The third capacitor C16, the fourth capacitor C10 and the fifth capacitor C22 are connected in parallel to the second end of the third inductor L3, and the second ends of the third capacitor C16, the fourth capacitor C10 and the fifth capacitor C22 are grounded.

[0006] Furthermore, the power isolation circuit includes an inverter chip IC2, a transformer T3, a second diode D10, a third diode D17, a fourth diode D18, a fifth diode D19, a second TVS tube D4, a third TVS tube D14, a sixth capacitor C15, a seventh capacitor C26, a first load resistor R15, and a second load resistor R20; The input pin of the inverter chip IC2 is connected to the output end of the power supply circuit, the first end of the first primary winding of the transformer T3 is connected to the first power supply pin of the inverter chip IC2, the second end of the first primary winding is connected to the input pin of the inverter chip IC2, the first end of the second primary winding of the transformer T3 is connected to the input pin of the inverter chip IC2, the second end of the second primary winding is connected to the second power supply pin of the inverter chip IC2, the first end of the first secondary winding of the transformer T3 is connected to the anode of the second diode D10, the second end of the first secondary winding is grounded, the first end of the second secondary winding of the transformer T3 is grounded, the second end of the second secondary winding is connected to the cathode of the fifth diode D19, the cathode of the second diode D10 is connected to the first end of the second TVS tube D4, the second end of the second TVS tube D4 is connected to the anode of the second diode D10, the second end of the first secondary winding is grounded, the first end of the second secondary winding of the transformer T3 is grounded, the second end of the second secondary winding is connected to the cathode of the fifth diode D19, the cathode of the second diode D10 is connected to the first end of the second TVS tube D4 Two terminals are grounded, the anode of the fifth diode D19 is connected to the first terminal of the third TVS tube D14, the second terminal of the third TVS tube D14 is grounded, the anode of the third diode D17 is connected in parallel between the path between the second terminal of the second secondary winding and the cathode of the fifth diode D19, the cathode of the third diode D17 is connected in parallel to the cathode of the second diode D10, the cathode of the fourth diode D18 is connected in parallel between the path between the first terminal of the first secondary winding and the anode of the second diode D10, the anode of the fourth diode D18 is connected in parallel to the anode of the fifth diode D19, a positive power supply voltage VCC is output between the cathode of the second diode D10 and the path between the first terminal of the second TVS tube D4, and a negative power supply voltage VEE is output between the anode of the fifth diode D19 and the path between the first terminal of the third TVS tube D14; A first end of the sixth capacitor C15 is connected in parallel between the cathode of the second diode D10 and the path of the first end of the second TVS transistor D4, and a second end of the sixth capacitor C15 is grounded. A first end of the seventh capacitor C26 is connected in parallel between the anode of the fifth diode D19 and the path of the first end of the third TVS transistor D14, and a second end of the seventh capacitor C26 is grounded. A first end of the first load resistor R15 is connected in parallel between the cathode of the second diode D10 and the path of the first end of the second TVS transistor D4, and a second end of the first load resistor R15 is grounded. A first end of the second load resistor R20 is connected in parallel between the anode of the fifth diode D19 and the path of the first end of the third TVS transistor D14, and a second end of the second load resistor R20 is grounded.

[0007] Furthermore, the current signal input terminal includes a first current signal input terminal and a second current signal input terminal, and the current sampling circuit also includes a voltage stabilizing chip U3, an eighth capacitor C27, a ninth capacitor C23, a tenth capacitor C24, an eleventh capacitor C25, a fourth TVS tube D1, a twelfth capacitor C17, and a thirteenth capacitor C1; The input pin of the voltage regulator chip U3 is connected to the positive power supply voltage VCC, the output pin of the voltage regulator chip U3 outputs the second +5V power supply, the eighth capacitor C27 and the ninth capacitor C23 are connected in parallel between the input pin of the voltage regulator chip U3 and the ground line, the fourth TVS diode D1, the tenth capacitor C24 and the eleventh capacitor C25 are connected in parallel between the output pin of the voltage regulator chip U3 and the ground line, and the twelfth capacitor C17 and the thirteenth capacitor C1 are connected in parallel between the second +5V power supply and the ground line; The positive input pin of the Hall current chip is connected to the first current signal input terminal, the negative input pin is connected to the second current signal input terminal, the power pin is connected to the second +5V power supply, and the output pin is connected to the input end of the signal conditioning circuit.

[0008] Furthermore, the Hall current chip is a Hall current chip without a magnetic core.

[0009] Furthermore, the signal conditioning circuit includes an output signal zeroing circuit and an analog signal output circuit, wherein the output signal zeroing circuit is used to zero-adjust the output of the analog signal, and the analog signal output circuit is used to output the analog signal and fully adjust the output of the analog signal; The output signal zeroing circuit includes a first potentiometer RP1, a first operational amplifier U1B, a fourteenth capacitor C3, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; The first end of the first resistor R1 is connected to the second +5V power supply, the first end of the first potentiometer RP1 is connected to the second end of the first resistor R1, the second end of the first potentiometer RP1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is grounded, the control end of the first potentiometer RP1 is connected to the first end of the third resistor R3, the fourteenth capacitor C3 is connected in parallel between the second end of the third resistor R3 and the second end of the second resistor R2, the second end of the third resistor R3 is connected to the positive input end of the first operational amplifier U1B, the output end of the first operational amplifier U1B is connected to the first end of the fourth resistor R4, the negative input end of the first operational amplifier U1B is connected in parallel to the second end of the fourth resistor R4, and the output end of the first operational amplifier U1B outputs the reference level VREF.

[0010] Furthermore, the analog signal output circuit includes a second potentiometer RP2, a second operational amplifier U1A, a fifth resistor R11, a sixth resistor R10, a seventh resistor R7, an eighth resistor R13, a ninth resistor R9, a fifteenth capacitor C4, a sixteenth capacitor C6, a seventeenth capacitor C11, an eighteenth capacitor C8, a nineteenth capacitor C1, a common-mode inductor T1, a fifth TVS diode D7, and a sixth TVS diode D6; The first end of the fifth resistor R11 is connected to the output pin of the Hall current chip, the second end of the fifth resistor R11 is connected to the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the first end of the second potentiometer RP2, and the control end of the second potentiometer RP2 is connected to the second end of the second potentiometer. The fifteenth capacitor C4 is connected between the first end of the seventh resistor R7 and the second end of the second potentiometer. The negative input end of the second operational amplifier U1A is connected between the path between the fifth resistor R11 and the seventh resistor R7. The positive input end of the second operational amplifier U1A is connected to the first end of the sixth resistor R10. The second end of the sixth resistor R10 is connected to the reference level VREF. The sixteenth capacitor C6 is connected between the negative input end and the positive input end of the second operational amplifier U1A. The first end of the eighth resistor R13 is connected between the path between the sixth resistor R10 and the positive input end of the second operational amplifier U1A. The second end of the eighth resistor R13 is grounded. The seventeenth capacitor C11 is connected in parallel across the eighth resistor R13. The output end of the second operational amplifier U1A is connected to the first end of the ninth resistor R9. The second end of the second potentiometer is connected in parallel to the second end of the ninth resistor R9. The second end of the ninth resistor R9 is connected to the first electrode of the first end of the common-mode inductor T1, and the second electrode of the first end of the common-mode inductor T1 is grounded. The eighteenth capacitor C8 is connected in parallel between the first and second electrodes of the first end of the common-mode inductor T1. The first and second electrodes of the second end of the common-mode inductor T1 are respectively connected to the positive and negative electrodes of the analog signal output terminal. The nineteenth capacitor C1 is connected in parallel between the first and second electrodes of the second end of the common-mode inductor T1. The signal pin of the fifth TVS diode D7 is connected in parallel to the first electrode of the second end of the common-mode inductor T1. The positive power supply pin of the fifth TVS diode D7 is connected to the positive power supply voltage VCC, and the negative power supply pin of the fifth TVS diode D7 is connected to the negative power supply voltage VEE. The sixth TVS diode D6 is connected in parallel between the first and second electrodes of the second end of the common-mode inductor T1.

[0011] Furthermore, the circuit board is also provided with a power indicator light circuit, which includes a tenth resistor R12 and an indicator light D8. The first end of the tenth resistor R12 is connected to the positive power supply voltage VCC, the second end of the tenth resistor R12 is connected to the positive pole of the indicator light D8, and the negative pole of the indicator light D8 is grounded. The indicator light D8 is used to indicate the status when the power supply is working normally.

[0012] Furthermore, the housing includes an upper housing and a lower housing, the upper housing and the lower housing are connected by a snap fastener, a sliding cover is provided on the upper housing, and when the sliding cover is opened, the first potentiometer RP1 and the second potentiometer RP2 on the circuit board are exposed.

[0013] Furthermore, the housing further includes a locking member, which is used to be installed into the bottom of the lower housing for fixed installation.

[0014] The advantages and beneficial effects of the present invention are: the circuit to be measured is connected to the Hall current chip through the current signal input terminal, so that direct access to the circuit to be measured is achieved, and the measurement accuracy of large current and small current can be guaranteed at the same time; the interference of the power supply circuit to the current sampling circuit and the signal conditioning circuit is isolated by the power isolation circuit, and the interference between the input signal and the output signal is isolated by the Hall current chip, so that the auxiliary power supply, input signal, and output signal are isolated from each other, which can improve the measurement accuracy and avoid damage to the port of the subsequent receiving device due to failure of the auxiliary power supply. A Hall current chip without a magnetic core is used, which has no residual magnetism after being impacted by a large current, and ensures that there is no signal output when there is no current. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the exploded structure of the direct-access Hall current transmitter of the present invention; Figure 2 This is a schematic diagram of the overall structure of the direct-access Hall current transmitter of the present invention; Figure 3 This is a schematic diagram of the working process of the direct-access Hall current transmitter of the present invention; Figure 4 It is a power supply circuit diagram of the present invention; Figure 5 It is a power isolation circuit diagram of the present invention; Figure 6 This is a current sampling circuit diagram of the present invention; Figure 7 This is the output signal zeroing circuit diagram of the present invention; Figure 8 This is the analog signal output circuit diagram of the present invention; Figure 9 It is a circuit diagram of a power indicator light of the present invention.

[0016] In the figure: 1. Upper housing; 2. Indicator light; 3. First potentiometer; 4. Analog signal output terminal; 5. Power input terminal; 6. Circuit board; 7. Lower housing; 8. Locking piece; 9. Hall current chip; 10. First current signal input terminal; 11. Second current signal input terminal; 12. Second potentiometer; 13. Sliding cover. DETAILED DESCRIPTION

[0017] The following embodiments are further described in conjunction with the accompanying drawings and examples. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0018] according to Figures 1 to 9 As shown, the present invention is a direct-access Hall current transmitter, comprising: a housing and a circuit board; the circuit board is arranged in the housing, and is provided with a power input terminal, a power circuit, a power isolation circuit, a current signal input terminal, a current sampling circuit, a signal conditioning circuit, and an analog signal output terminal on the circuit board; the power input terminal is electrically connected to the input end of the power circuit, and the output end of the power circuit provides the power required by the components on the circuit board, and the power isolation circuit is used to isolate the interference of the power circuit on the current sampling circuit and the signal conditioning circuit; the current signal input terminal is electrically connected to the input end of the current sampling circuit, the output end of the current sampling circuit is electrically connected to the input end of the signal conditioning circuit, and the output end of the signal conditioning circuit is electrically connected to the analog signal output terminal; the current signal input terminal is used to access a circuit that requires current sampling, the current sampling circuit includes a Hall current chip, the Hall current chip is used to isolate and sample the input current of the current signal input terminal, and output an analog signal whose waveform corresponds to the waveform of the input current, the signal conditioning circuit is used to zero and full adjust the output of the analog signal, and the analog signal output terminal is used to transmit the analog signal to the outside.

[0019] The power input terminal 5 is connected to an external power supply, and the power supply circuit on the circuit board 6 steps down the input of the external power supply and isolates and stabilizes it into the voltage required by the Hall current transmitter through the power isolation circuit. The first current signal input terminal 10 and the second current signal input terminal 11 can be directly connected to the circuit that needs to sample the current. The sampled current signal is isolated and converted into an analog voltage signal by the Hall current chip and transmitted to the signal conditioning circuit. The output signal is zeroed by the first potentiometer 3 in the signal conditioning circuit on the circuit board 6, and the output signal is fully adjusted by the second potentiometer 12. The analog output circuit in the signal conditioning circuit can convert the current signal sampled by the Hall current chip into a corresponding analog output signal, and finally transmit it to the outside through the analog signal output terminal 4.

[0020] The present invention connects the circuit to be measured to the Hall current chip through the current signal input terminal, realizes direct access to the circuit to be measured, and can simultaneously ensure the measurement accuracy of large current and small current; isolates the interference of the power supply circuit to the current sampling circuit and the signal conditioning circuit through the power isolation circuit, isolates the interference between the input signal and the output signal through the Hall current chip, realizes the mutual isolation between the auxiliary power supply, the input signal, and the output signal, can improve the measurement accuracy, avoids the damage of the port of the subsequent receiving device caused by the failure of the auxiliary power supply, adopts a Hall current chip without a magnetic core, has no residual magnetism after being impacted by a large current, and ensures that there is no signal output when there is no current.

[0021] In order to achieve a stable +5V power output, a preferred embodiment of the present invention is that the power supply circuit includes a connector J4, a varistor RV1, a first inductor L2, a second inductor L4, a first TVS tube D13, a fuse resistor F1, a first diode D9, a first electrolytic capacitor C20, a first capacitor C19, a second capacitor C21, a power chip IC1, a third inductor L3, a third capacitor C16, a fourth capacitor C10, and a fifth capacitor C22.

[0022] The varistor RV1 is connected in parallel between the positive pin and the negative pin of the connector J4, the first inductor L2 is connected to the positive pin of the connector J4, the anode of the first diode D9 is connected to the first inductor L2, the cathode of the first diode D9 is connected to the fuse resistor F1, the fuse resistor F1 is connected to the input pin (VIN) of the power chip IC1, the switch pin (SW) of the power chip IC1 is connected to the first end of the third inductor L3, and the switch pin of the power chip IC1 outputs the first +5V power supply +5V1; the negative pin of the connector J4 is connected to the second inductor L4, the second inductor L4 is grounded, and the third The positive electrode of an electrolytic capacitor C20 is connected in parallel between the path of the fuse resistor F1 and the input pin (VIN) of the power chip IC1, the negative electrode of the first electrolytic capacitor C20 is grounded, the first ends of the first capacitor C19 and the second capacitor C21 are connected in parallel between the path of the fuse resistor F1 and the input pin of the power chip IC1, the second ends of the first capacitor C19 and the second capacitor C21 are grounded, the third capacitor C16, the fourth capacitor C10 and the fifth capacitor C22 are connected in parallel to the second end of the third inductor L3, and the second ends of the third capacitor C16, the fourth capacitor C10 and the fifth capacitor C22 are grounded.

[0023] The ground pin (GND) of the power chip IC1 is grounded, the enable pin (EN) is connected in parallel between the input pin (VIN) and the path of the fuse resistor F1, the bootstrap pin (BST) is connected in parallel between the switch pin (SW) and the path of the third inductor L3, and the feedback pin (FB) is connected in parallel to the second end of the third inductor L3.

[0024] Inductors L2 and L4 are power inductors, capable of withstanding high currents to protect the entire circuit. They also suppress common-mode and differential-mode interference, increasing power supply stability. Fuse F1, varistor RV1, and TVS diode D13 provide EMC protection for the power input. Diode D9 provides reverse polarity protection. Capacitors C19, C20, and C21 filter the power circuit input. Inductor L3 and capacitors C19, C20, and C21 filter the power circuit output. Power chip IC1 provides DC5V output conversion.

[0025] In order to isolate interference from the power supply circuit and provide the VCC power required by some components in the circuit board, a preferred embodiment of the present invention is that the power isolation circuit includes an inverter chip IC2, a transformer T3, a second diode D10, a third diode D17, a fourth diode D18, a fifth diode D19, a second TVS diode D4, a third TVS diode D14, a sixth capacitor C15, a seventh capacitor C26, a first load resistor R15, and a second load resistor R20.

[0026] The input pin of the inverter chip IC2 is connected to the output end of the power supply circuit, the first end of the first primary winding of the transformer T3 is connected to the first power supply pin of the inverter chip IC2, the second end of the first primary winding is connected to the input pin of the inverter chip IC2, the first end of the second primary winding of the transformer T3 is connected to the input pin of the inverter chip IC2, the second end of the second primary winding is connected to the second power supply pin of the inverter chip IC2, the first end of the first secondary winding of the transformer T3 is connected to the anode of the second diode D10, the second end of the first secondary winding is grounded, the first end of the second secondary winding of the transformer T3 is grounded, the second end of the second secondary winding is connected to the cathode of the fifth diode D19, the cathode of the second diode D10 is connected to the first end of the second TVS tube D4, and the second end of the second TVS tube D4 is connected to the cathode of the fifth diode D19. The anode of the fifth diode D19 is connected to the first end of the third TVS tube D14, the second end of the third TVS tube D14 is grounded, the anode of the third diode D17 is connected in parallel between the second end of the second secondary winding and the cathode of the fifth diode D19, the cathode of the third diode D17 is connected in parallel to the cathode of the second diode D10, the cathode of the fourth diode D18 is connected in parallel between the first end of the first secondary winding and the anode of the second diode D10, the anode of the fourth diode D18 is connected in parallel to the anode of the fifth diode D19, a positive power supply voltage VCC is output between the cathode of the second diode D10 and the first end of the second TVS tube D4, and a negative power supply voltage VEE is output between the anode of the fifth diode D19 and the first end of the third TVS tube D14.

[0027] A first end of the sixth capacitor C15 is connected in parallel between the cathode of the second diode D10 and the path of the first end of the second TVS transistor D4. A second end of the sixth capacitor C15 is grounded. A first end of the seventh capacitor C26 is connected in parallel between the anode of the fifth diode D19 and the path of the first end of the third TVS transistor D14. A second end of the seventh capacitor C26 is grounded. A first end of the first load resistor R15 is connected in parallel between the cathode of the second diode D10 and the path of the first end of the second TVS transistor D4. A second end of the first load resistor R15 is grounded. A first end of the second load resistor R20 is connected in parallel between the anode of the fifth diode D19 and the path of the first end of the third TVS transistor D14. A second end of the second load resistor R20 is grounded.

[0028] Inverter chip IC2 converts 5V power into AC power, which is isolated and converted by transformer T3. Diodes D10, D17, D18, and D19 form a full-wave rectifier circuit to rectify the output of transformer T3. TVS diodes D4 and D14 act as clamps, capacitors C15 and C26 filter the output, and resistors R15 and R20 act as dummy loads.

[0029] In order to provide a more stable +5V power supply to the Hall current chip, improve measurement accuracy, and reduce interference from the +5V power supply, a preferred embodiment of the present invention is that the current signal input terminal includes a first current signal input terminal and a second current signal input terminal, and the current sampling circuit also includes a voltage stabilizing chip U3, an eighth capacitor C27, a ninth capacitor C23, a tenth capacitor C24, an eleventh capacitor C25, a fourth TVS tube D1, a twelfth capacitor C17, and a thirteenth capacitor C1.

[0030] The input pin of the voltage regulator chip U3 is connected to the positive power supply voltage VCC, the output pin of the voltage regulator chip U3 outputs the second +5V power supply +5V, the eighth capacitor C27 and the ninth capacitor C23 are connected in parallel between the input pin of the voltage regulator chip U3 and the ground, the fourth TVS tube D1, the tenth capacitor C24 and the eleventh capacitor C25 are connected in parallel between the output pin of the voltage regulator chip U3 and the ground, and the twelfth capacitor C17 and the thirteenth capacitor C1 are connected in parallel between the second +5V power supply +5V and the ground.

[0031] The positive input pin (IP+) of the Hall current chip U2 is connected to the first current signal input terminal, the negative input pin (IP-) is connected to the second current signal input terminal, the power pin (VCC) is connected to the second +5V power supply +5V, and the output pin (VOUT) is connected to the input end of the signal conditioning circuit.

[0032] Voltage regulator chip U3 outputs a regulated DC5V voltage to power Hall effect chip U2. Capacitors C1, C17, C23, C27, C24, and C25 serve as filter capacitors. Hall effect chip U2 isolates and samples the input current, outputting an analog voltage signal with a waveform corresponding to the current waveform.

[0033] In order to prevent the Hall current chip from having residual magnetism after being impacted by a large current and to ensure that there is no signal output when there is no current, a preferred embodiment of the present invention is that the Hall current chip U2 is a Hall current chip without a magnetic core.

[0034] In order to achieve zeroing of the analog signal output and improve measurement accuracy, a preferred embodiment of the present invention is that the signal conditioning circuit includes an output signal zeroing circuit and an analog signal output circuit, the output signal zeroing circuit is used to zero the output of the analog signal, and the analog signal output circuit is used to output the analog signal and fully adjust the output of the analog signal.

[0035] The output signal zeroing circuit includes a first potentiometer RP1, a first operational amplifier U1B, a fourteenth capacitor C3, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4.

[0036] The first end of the first resistor R1 is connected to the second +5V power supply +5V, the first end of the first potentiometer RP1 is connected to the second end of the first resistor R1, the second end of the first potentiometer RP1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is grounded, the control end of the first potentiometer RP1 is connected to the first end of the third resistor R3, the fourteenth capacitor C3 is connected in parallel between the second end of the third resistor R3 and the second end of the second resistor R2, the second end of the third resistor R3 is connected to the positive input end of the first operational amplifier U1B, the output end of the first operational amplifier U1B is connected to the first end of the fourth resistor R4, the negative input end of the first operational amplifier U1B is connected in parallel to the second end of the fourth resistor R4, and the output end of the first operational amplifier U1B outputs the reference level VREF.

[0037] The circuit consisting of operational amplifier chip U1B, resistors R1 and R2, and potentiometer RP1 outputs the reference level of the sampled signal. Capacitor C3 provides filtering, while resistor R4 limits the current of chip U1B. Potentiometer RP1 adjusts the reference level of the output sampled signal, thereby achieving zero adjustment of the analog signal output.

[0038] In order to achieve full adjustment of the analog signal output, filter out noise interference, and improve measurement accuracy, a preferred embodiment of the present invention is that the analog signal output circuit includes a second potentiometer RP2, a second operational amplifier U1A, a fifth resistor R11, a sixth resistor R10, a seventh resistor R7, an eighth resistor R13, a ninth resistor R9, a fifteenth capacitor C4, a sixteenth capacitor C6, a seventeenth capacitor C11, an eighteenth capacitor C8, a nineteenth capacitor C1, a common-mode inductor T1, a fifth TVS diode D7, and a sixth TVS diode D6.

[0039] A first end of the fifth resistor R11 is connected to the output pin of the Hall current chip, a second end of the fifth resistor R11 is connected to the first end of the seventh resistor R7, a second end of the seventh resistor R7 is connected to the first end of the second potentiometer RP2, a control end of the second potentiometer RP2 is connected in parallel to the second end of the second potentiometer, a fifteenth capacitor C4 is connected in parallel between the first end of the seventh resistor R7 and the second end of the second potentiometer, a negative input end of the second operational amplifier U1A is connected in parallel between the path between the fifth resistor R11 and the seventh resistor R7, a positive input end of the second operational amplifier U1A is connected to the first end of the sixth resistor R10, a second end of the sixth resistor R10 is connected to the reference level VREF, a sixteenth capacitor C6 is connected in parallel between the negative input end and the positive input end of the second operational amplifier U1A, a first end of the eighth resistor R13 is connected in parallel between the path between the sixth resistor R10 and the positive input end of the second operational amplifier U1A, a second end of the eighth resistor R13 is grounded, and a seventeenth capacitor C6 is connected in parallel between the negative input end and the positive input end of the second operational amplifier U1A. Capacitor C11 is connected in parallel across the eighth resistor R13. The output end of the second operational amplifier U1A is connected to the first end of the ninth resistor R9. The second end of the second potentiometer is connected in parallel to the second end of the ninth resistor R9. The second end of the ninth resistor R9 is connected to the first terminal of the first end of the common-mode inductor T1, and the second terminal of the first end of the common-mode inductor T1 is grounded. An eighteenth capacitor C8 is connected in parallel between the first and second terminals of the first end of the common-mode inductor T1. The first and second terminals of the second end of the common-mode inductor T1 are connected to the positive and negative terminals of the analog signal output terminal, respectively. A nineteenth capacitor C1 is connected in parallel between the first and second terminals of the second end of the common-mode inductor T1. The signal pin of the fifth TVS diode D7 is connected in parallel to the first terminal of the second end of the common-mode inductor T1. The positive power supply pin of the fifth TVS diode D7 is connected to the positive power supply voltage VCC, and the negative power supply pin of the fifth TVS diode D7 is connected to the negative power supply voltage VEE. The sixth TVS diode D6 is connected in parallel between the first and second terminals of the second end of the common-mode inductor T1.

[0040] Resistors R28 and R31 and capacitors C2, C5, C7, and C29 filter the sampled signal. Resistors R7, R10, R11, and R13, potentiometer RP2, and operational amplifier chip U1A form a differential amplifier circuit. Adjusting potentiometer RP2 allows full adjustment of the output signal. Capacitors C4, C6, and C11 filter high-frequency noise from the input of operational amplifier chip U1A. Capacitors C12 and C13 serve as power supply filter capacitors for operational amplifier chip U1A, and resistor R9 serves as the output current-limiting resistor for chip U1A. Common-mode inductor T1 and capacitors C8 and C1 form a π-type filter circuit, which filters high-frequency noise from the output signal while retaining the effective low-frequency signal. TVS diode D6 and diode D7 clamp the output signal.

[0041] In order to indicate the status of the power supply when it is working normally, a preferred embodiment of the present invention is that a power indicator light circuit is also provided on the circuit board, and the power indicator light circuit includes a tenth resistor R12 and an indicator light D8. The first end of the tenth resistor R12 is connected to the positive power supply voltage VCC, the second end of the tenth resistor R12 is connected to the positive electrode of the indicator light D8, and the negative electrode of the indicator light D8 is grounded. The indicator light D8 is used to indicate the status of the power supply when it is working normally.

[0042] To facilitate assembly and operation of the Hall effect current transmitter, a preferred embodiment of the present invention comprises an upper housing 1 and a lower housing 7, connected by a snap fastener. A sliding cover 13 is provided on the upper housing 1. When the sliding cover 13 is opened, the first and second potentiometers 3 and 12 on the circuit board are exposed. The housing also includes a locking member 8, which is inserted into the bottom of the lower housing 7 for secure installation.

[0043] During device assembly, the circuit board 6 is installed in the lower housing 7. The upper housing 1 and lower housing 7 are then connected via snaps, securing the circuit board 6 within the upper and lower housings 1 and 7. Finally, the locking member 8 is inserted into the bottom of the lower housing 7 to secure the Hall effect current transmitter. Opening the sliding cover 13 on the upper housing 1 exposes the first potentiometer 3 and second potentiometer 12 on the circuit board 6. The output signal is zeroed using the first potentiometer 3, while the output signal is fully adjusted using the second potentiometer 12.

[0044] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A direct-access Hall current transmitter, characterized in that: include: Housing and circuit board; The circuit board is arranged in the housing, and is provided with a power input terminal, a power circuit, a power isolation circuit, a current signal input terminal, a current sampling circuit, a signal conditioning circuit, and an analog signal output terminal; The power input terminal is electrically connected to the input end of the power circuit, the output end of the power circuit provides the power required by the components on the circuit board, and the power isolation circuit is used to isolate the interference of the power circuit on the current sampling circuit and the signal conditioning circuit; The current signal input terminal is electrically connected to the input end of the current sampling circuit, the output end of the current sampling circuit is electrically connected to the input end of the signal conditioning circuit, and the output end of the signal conditioning circuit is electrically connected to the analog signal output terminal; The current signal input terminal is used to connect to a circuit that requires current sampling. The current sampling circuit includes a Hall current chip. The Hall current chip is used to isolate and sample the input current of the current signal input terminal and output an analog signal whose waveform corresponds to the waveform of the input current. The signal conditioning circuit is used to zero and full adjust the output of the analog signal. The analog signal output terminal is used to transmit the analog signal to the outside.

2. The direct-access Hall current transmitter according to claim 1, characterized in that: The power supply circuit includes a connector J4, a varistor RV1, a first inductor L2, a second inductor L4, a first TVS tube D13, a fuse resistor F1, a first diode D9, a first electrolytic capacitor C20, a first capacitor C19, a second capacitor C21, a power chip IC1, a third inductor L3, a third capacitor C16, a fourth capacitor C10, and a fifth capacitor C22; The varistor RV1 is connected in parallel between the positive and negative pins of the connector J4. The first inductor L2 is connected to the positive pin of the connector J4. The anode of the first diode D9 is connected to the first inductor L2. The cathode of the first diode D9 is connected to the fuse resistor F1. The fuse resistor F1 is connected to the input pin of the power chip IC1. The switch pin of the power chip IC1 is connected to the first end of the third inductor L3. The switch pin of the power chip IC1 outputs a first +5V power supply. The negative electrode pin of the connector J4 is connected to the second inductor L4, which is grounded. The positive electrode of the first electrolytic capacitor C20 is connected in parallel between the path of the fuse resistor F1 and the input pin of the power chip IC1, and the negative electrode of the first electrolytic capacitor C20 is grounded. The first ends of the first capacitor C19 and the second capacitor C21 are connected in parallel between the path of the fuse resistor F1 and the input pin of the power chip IC1, and the second ends of the first capacitor C19 and the second capacitor C21 are grounded. The third capacitor C16, the fourth capacitor C10 and the fifth capacitor C22 are connected in parallel to the second end of the third inductor L3, and the second ends of the third capacitor C16, the fourth capacitor C10 and the fifth capacitor C22 are grounded.

3. The direct-access Hall current transmitter according to claim 1, characterized in that: The power isolation circuit includes an inverter chip IC2, a transformer T3, a second diode D10, a third diode D17, a fourth diode D18, a fifth diode D19, a second TVS tube D4, a third TVS tube D14, a sixth capacitor C15, a seventh capacitor C26, a first load resistor R15, and a second load resistor R20; The input pin of the inverter chip IC2 is connected to the output end of the power supply circuit, the first end of the first primary winding of the transformer T3 is connected to the first power supply pin of the inverter chip IC2, the second end of the first primary winding is connected to the input pin of the inverter chip IC2, the first end of the second primary winding of the transformer T3 is connected to the input pin of the inverter chip IC2, the second end of the second primary winding is connected to the second power supply pin of the inverter chip IC2, the first end of the first secondary winding of the transformer T3 is connected to the anode of the second diode D10, the second end of the first secondary winding is grounded, the first end of the second secondary winding of the transformer T3 is grounded, the second end of the second secondary winding is connected to the cathode of the fifth diode D19, the cathode of the second diode D10 is connected to the first end of the second TVS tube D4, the second end of the second TVS tube D4 is connected to the anode of the second diode D10, the second end of the first secondary winding is grounded, the first end of the second secondary winding of the transformer T3 is grounded, the second end of the second secondary winding is connected to the cathode of the fifth diode D19, the cathode of the second diode D10 is connected to the first end of the second TVS tube D4 Two terminals are grounded, the anode of the fifth diode D19 is connected to the first terminal of the third TVS tube D14, the second terminal of the third TVS tube D14 is grounded, the anode of the third diode D17 is connected in parallel between the path between the second terminal of the second secondary winding and the cathode of the fifth diode D19, the cathode of the third diode D17 is connected in parallel to the cathode of the second diode D10, the cathode of the fourth diode D18 is connected in parallel between the path between the first terminal of the first secondary winding and the anode of the second diode D10, the anode of the fourth diode D18 is connected in parallel to the anode of the fifth diode D19, a positive power supply voltage VCC is output between the cathode of the second diode D10 and the path between the first terminal of the second TVS tube D4, and a negative power supply voltage VEE is output between the anode of the fifth diode D19 and the path between the first terminal of the third TVS tube D14; A first end of the sixth capacitor C15 is connected in parallel between the cathode of the second diode D10 and the path of the first end of the second TVS transistor D4, and a second end of the sixth capacitor C15 is grounded. A first end of the seventh capacitor C26 is connected in parallel between the anode of the fifth diode D19 and the path of the first end of the third TVS transistor D14, and a second end of the seventh capacitor C26 is grounded. A first end of the first load resistor R15 is connected in parallel between the cathode of the second diode D10 and the path of the first end of the second TVS transistor D4, and a second end of the first load resistor R15 is grounded. A first end of the second load resistor R20 is connected in parallel between the anode of the fifth diode D19 and the path of the first end of the third TVS transistor D14, and a second end of the second load resistor R20 is grounded.

4. The direct-access Hall current transmitter according to claim 3, characterized in that: The current signal input terminal includes a first current signal input terminal and a second current signal input terminal, and the current sampling circuit further includes a voltage stabilizing chip U3, an eighth capacitor C27, a ninth capacitor C23, a tenth capacitor C24, an eleventh capacitor C25, a fourth TVS tube D1, a twelfth capacitor C17, and a thirteenth capacitor C1; The input pin of the voltage regulator chip U3 is connected to the positive power supply voltage VCC, the output pin of the voltage regulator chip U3 outputs the second +5V power supply, the eighth capacitor C27 and the ninth capacitor C23 are connected in parallel between the input pin of the voltage regulator chip U3 and the ground line, the fourth TVS diode D1, the tenth capacitor C24 and the eleventh capacitor C25 are connected in parallel between the output pin of the voltage regulator chip U3 and the ground line, and the twelfth capacitor C17 and the thirteenth capacitor C1 are connected in parallel between the second +5V power supply and the ground line; The positive input pin of the Hall current chip is connected to the first current signal input terminal, the negative input pin is connected to the second current signal input terminal, the power pin is connected to the second +5V power supply, and the output pin is connected to the input end of the signal conditioning circuit.

5. The direct-access Hall current transmitter according to claim 1, characterized in that: The Hall current chip is a Hall current chip without a magnetic core.

6. The direct-access Hall current transmitter according to claim 4, characterized in that: The signal conditioning circuit includes an output signal zeroing circuit and an analog signal output circuit, wherein the output signal zeroing circuit is used to zero-adjust the output of the analog signal, and the analog signal output circuit is used to output the analog signal and to fully adjust the output of the analog signal; The output signal zeroing circuit includes a first potentiometer RP1, a first operational amplifier U1B, a fourteenth capacitor C3, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; The first end of the first resistor R1 is connected to the second +5V power supply, the first end of the first potentiometer RP1 is connected to the second end of the first resistor R1, the second end of the first potentiometer RP1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is grounded, the control end of the first potentiometer RP1 is connected to the first end of the third resistor R3, the fourteenth capacitor C3 is connected in parallel between the second end of the third resistor R3 and the second end of the second resistor R2, the second end of the third resistor R3 is connected to the positive input end of the first operational amplifier U1B, the output end of the first operational amplifier U1B is connected to the first end of the fourth resistor R4, the negative input end of the first operational amplifier U1B is connected in parallel to the second end of the fourth resistor R4, and the output end of the first operational amplifier U1B outputs the reference level VREF.

7. The direct-access Hall current transmitter according to claim 6, characterized in that: The analog signal output circuit includes a second potentiometer RP2, a second operational amplifier U1A, a fifth resistor R11, a sixth resistor R10, a seventh resistor R7, an eighth resistor R13, a ninth resistor R9, a fifteenth capacitor C4, a sixteenth capacitor C6, a seventeenth capacitor C11, an eighteenth capacitor C8, a nineteenth capacitor C1, a common-mode inductor T1, a fifth TVS diode D7, and a sixth TVS diode D6; The first end of the fifth resistor R11 is connected to the output pin of the Hall current chip, the second end of the fifth resistor R11 is connected to the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the first end of the second potentiometer RP2, and the control end of the second potentiometer RP2 is connected to the second end of the second potentiometer. The fifteenth capacitor C4 is connected between the first end of the seventh resistor R7 and the second end of the second potentiometer. The negative input end of the second operational amplifier U1A is connected between the path between the fifth resistor R11 and the seventh resistor R7. The positive input end of the second operational amplifier U1A is connected to the first end of the sixth resistor R10. The second end of the sixth resistor R10 is connected to the reference level VREF. The sixteenth capacitor C6 is connected between the negative input end and the positive input end of the second operational amplifier U1A. The first end of the eighth resistor R13 is connected between the path between the sixth resistor R10 and the positive input end of the second operational amplifier U1A. The second end of the eighth resistor R13 is grounded. The seventeenth capacitor C11 is connected in parallel across the eighth resistor R13. The output end of the second operational amplifier U1A is connected to the first end of the ninth resistor R9. The second end of the second potentiometer is connected in parallel to the second end of the ninth resistor R9. The second end of the ninth resistor R9 is connected to the first electrode of the first end of the common-mode inductor T1, and the second electrode of the first end of the common-mode inductor T1 is grounded. The eighteenth capacitor C8 is connected in parallel between the first and second electrodes of the first end of the common-mode inductor T1. The first and second electrodes of the second end of the common-mode inductor T1 are respectively connected to the positive and negative electrodes of the analog signal output terminal. The nineteenth capacitor C1 is connected in parallel between the first and second electrodes of the second end of the common-mode inductor T1. The signal pin of the fifth TVS diode D7 is connected in parallel to the first electrode of the second end of the common-mode inductor T1. The positive power supply pin of the fifth TVS diode D7 is connected to the positive power supply voltage VCC, and the negative power supply pin of the fifth TVS diode D7 is connected to the negative power supply voltage VEE. The sixth TVS diode D6 is connected in parallel between the first and second electrodes of the second end of the common-mode inductor T1.

8. The direct-access Hall current transmitter according to claim 3, characterized in that: The circuit board is also provided with a power indicator light circuit, which includes a tenth resistor R12 and an indicator light D8. The first end of the tenth resistor R12 is connected to the positive power supply voltage VCC, the second end of the tenth resistor R12 is connected to the positive electrode of the indicator light D8, and the negative electrode of the indicator light D8 is grounded. The indicator light D8 is used to indicate the status of the power supply when it is working normally.

9. The direct-access Hall current transmitter according to claim 7, characterized in that: The housing includes an upper housing and a lower housing, and the upper housing and the lower housing are connected by a snap. A sliding cover is provided on the upper housing, and when the sliding cover is opened, the first potentiometer RP1 and the second potentiometer RP2 on the circuit board are exposed.

10. The direct-access Hall current transmitter according to claim 9, characterized in that: The housing further comprises a locking member, which is used to be installed into the bottom of the lower housing for fixed installation.

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