SiC MOSFET degradation test circuit and method based on repeated inductive switch stress
By designing a SiC MOSFET degradation test circuit based on repeated inductive switching stress, the working state of the device in an inductive load converter environment is simulated, and the problem of ignoring load current and bus voltage in traditional testing methods is solved, and the precise evaluation of the SiC MOSFET degradation level is achieved.
Patent Information
- Application Number
- CN202510610098.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-08-08
AI Technical Summary
The degradation testing methods of existing SiC MOSFETs ignore the blocking voltage and load current of the device in the actual converter, resulting in overestimation or underestimation of the degradation level, affecting its highly reliable application.
A SiC MOSFET degradation test circuit based on repeated inductive switching stress is designed, including a two-level gate driving circuit, a freewheeling diode, a linear constant current source and a DC bus capacitor. The degree of degradation is evaluated by simulating the operating state of the device in an inductive load converter environment and measuring the threshold voltage variation.
The degradation trend and level of SiC MOSFET in the actual converter was accurately evaluated, which improved the accuracy and reliability of the test, and further matched the degradation behavior of the device under actual operating conditions.
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Figure CN120446705A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor device testing, and relates to a SiC MOSFET degradation testing circuit and method based on repeated inductive switching stress. Background Art
[0002] Third-generation semiconductor materials, represented by SiC, offer advantages such as a wide bandgap, high breakdown voltage, high thermal conductivity, and high electron saturation velocity, making them widely used in the fabrication of power semiconductor devices. Compared to traditional Si IGBTs, SiC MOSFETs offer faster switching speeds and a higher upper switching frequency limit, helping power electronic converters achieve higher power density and operating efficiency. Currently, SiC MOSFETs are widely used in renewable energy generation, electric vehicles, and industrial automation.
[0003] However, due to limitations in the fabrication process, trap defects exist at the interface between SiC and SiO2 in the SiC MOSFET structure. These traps can capture holes / electrons during the device's switching state, destroying the insulating integrity of the gate oxide layer and causing degradation of the device's conductivity. To carefully assess the reliability of the device's gate oxide, SiC MOSFETs must be subjected to repeated switching stress degradation testing. Traditional testing methods short-circuit the drain and source of the SiC MOSFET, apply an AC drive voltage across the device's gate and source, and determine the device's degradation level by monitoring the extent of the threshold voltage shift after degradation. Although this method is relatively simple, it ignores the device's blocking voltage and load current in actual converters, resulting in overestimation or underestimation of the degradation level, which significantly restricts the high-reliability application of SiC MOSFETs. Summary of the Invention
[0004] The purpose of the present invention is to provide a SiC MOSFET degradation test circuit and method based on repeated inductive switching stress, which is used to test the degradation behavior of SiC MOSFET in an inductive load converter environment.
[0005] In order to achieve the above object, the solution of the present invention is:
[0006] A SiC MOSFET degradation test circuit based on repetitive inductive switching stress includes a two-level gate drive circuit, a freewheeling diode, a linear constant current source, and a DC bus capacitor. The gate of the SiC MOSFET under test is connected to the output end of the two-level gate drive circuit; the drain of the SiC MOSFET under test is connected to the anode of the freewheeling diode, the cathode of the freewheeling diode is connected to one end of the DC bus capacitor, and both are externally connected to a DC bus voltage, and the other end of the DC bus capacitor is connected to the negative electrode of the DC bus; the positive electrode of the linear constant current source is connected to the DC bus voltage, and the negative electrode of the linear constant current source is connected to the anode of the freewheeling diode; and the source of the SiC MOSFET under test is connected to the negative electrode of the DC bus.
[0007] The above-mentioned two-level gate drive circuit includes a first drive transistor, a second drive transistor and a drive resistor, wherein the first drive transistor and the second drive transistor are connected in sequence, and the connection point between the two is also connected to one end of the drive resistor, and the other end of the drive resistor serves as the output end of the two-level gate drive circuit and is connected to the gate of the SiC MOSFET under test; the other end of the first drive transistor is connected to a positive drive voltage, and the other end of the second drive transistor is connected to a negative drive voltage.
[0008] The linear constant current source comprises a linear voltage stabilizing source, a DC electronic load operating in a constant current mode, and an air-core inductor which are sequentially connected from the positive electrode to the negative electrode.
[0009] A SiC MOSFET degradation testing method based on repeated inductive switching stress comprises the following steps:
[0010] Step 1: Connect the gate of the SiC MOSFET under test to a degradation test circuit and apply a drive signal to the SiC MOSFET under test. At this time, the SiC MOSFET under test operates in a degradation cycle.
[0011] Step 2: After the degradation is completed, the SiC MOSFET under test is disconnected from the degradation test circuit, a DC excitation is applied, and the threshold voltage is obtained;
[0012] Step 3: Adjust the switching frequency and duty cycle of the driving signal, and / or adjust the parameters of the degradation test circuit, and repeat steps 1-2 to obtain several threshold voltages;
[0013] Step 4: Obtain a degradation test result based on the obtained change in threshold voltage.
[0014] In step 2 above, after the SiC MOSFET under test is disconnected from the degradation test circuit, the gate, drain, and source of the SiC MOSFET under test are short-circuited and left to stand for a period of time, and then a DC excitation is applied.
[0015] In step 2 above, the method for applying DC excitation is to short-circuit the drain and gate of the SiC MOSFET under test, apply DC excitation between the drain and source, and obtain the threshold voltage when the drain current reaches a set threshold.
[0016] The beneficial effects of the present invention are demonstrated by the above scheme: Conventional SiC MOSFET switch stress degradation testing methods require shorting the drain and source of the device under test and continuously applying a gate drive voltage, which differs significantly from actual converter operating conditions. The proposed testing method overcomes the shortcomings of conventional switch degradation testing, which ignores load current and bus voltage. It is simple, easy to implement, scientifically sound, and can accurately extract the degradation trends and levels of SiC MOSFETs in actual converters. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a connection diagram of the test circuit of the present invention;
[0018] Figure 2 It is the switching trace waveform of the device under test;
[0019] Among them, (a) represents the switching trajectory waveform under working condition 1, and (b) represents the switching trajectory waveform under working condition 2;
[0020] Figure 3 This is a schematic diagram of the threshold voltage test process of the device under test;
[0021] (a) is a schematic diagram of the connection of the device under test when it is at rest, and (b) is a schematic diagram of the connection of the device under test when measuring the threshold voltage;
[0022] Figure 4 It is the degradation curve of the device under test under different test parameter conditions;
[0023] Where, (a) is the different load current I L The curve graph below, (b) is different duty cycle D s The curve graph below, (c) is different switching frequencies f s The curve graph below, (d) is different shell temperatures T c The following curve graph. DETAILED DESCRIPTION
[0024] The technical solutions and beneficial effects of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0025] like Figure 1 As shown, the present invention provides a SiC MOSFET degradation test circuit based on repeated inductive switching stress, which is used to test the device under test SiC MOSFET (DUT), including a driving transistor Q H , Q L, driving resistor R g , freewheeling diode D f , linear constant current source I L , DC bus capacitor C dc , the external power supply includes the DC bus voltage V dc , drive positive pressure V GG , driving negative pressure V EE , V GG and V EE Externally adjustable, the package case temperature T c It is also regulated by an external heater; the drain of the device under test is connected to the D f Connect to the positive pole of DC bus, the source and the negative pole of bus are directly connected, I L and D f The topology is in anti-parallel connection form, V GG , Q H 、V EE , Q L 、R g Constitutes a typical two-level gate drive circuit; linear constant current source I L The positive electrode is connected to the positive electrode of the DC bus, the negative electrode is connected to the DUT drain, and the linear voltage regulator V s , DC electronic load R working in constant current mode cc 、Air-core inductor L s Series structure, L s There is an absorption resistor R in parallel at both ends s , L s To ensure the transient stability of the load current, R s It is used to damp the high frequency oscillation formed by transient switching to ensure that the linear constant current source is f Reliable switching between the DUT and the
[0026] The present invention also provides a SiC MOSFET degradation test method based on repeated inductive switching stress. After building the test circuit and setting the working bias, a drive signal is applied to the DUT to make it work under a degradation cycle of cyclic blocking voltage and on-current. After a certain degradation time, the DUT is removed and its threshold voltage V is measured. th , observe V th The drift trend and level can be used to judge the degradation trend and degree of DUT.
[0027] Among them, the switching frequency of the driving signal f s , duty cycle D s and action time t s Freely adjustable according to the converter modulation strategy, which determines the number and duration of the cyclic stress that the tested SiC MOSFET withstands; the working bias includes the bus voltage V dc , load current IL , driving voltage V GG and V EE , shell temperature T c It is freely adjustable according to the operating conditions of the converter, which determines the energy level of the device's single switching stress.
[0028] In this embodiment, the air-core inductor L s To ensure the transient stability of the load current, set it to a typical value of 1mH to reduce I L Ripple; absorption resistor R s The high-frequency oscillation formed by transient switching can be damped and set to a typical value of 1kΩ to absorb loop parasitic oscillation.
[0029] Adjust the switching frequency f s , duty cycle D s , degradation time t s , bus voltage V dc , load current I L , driving voltage V GG and V EE , shell temperature T c By repeating the degradation and measurement steps, the modulation strategy and operating conditions of the actual converter can be simulated to observe the degradation trend and level of the inductive switch stress.
[0030] like Figure 2 As shown, the test method includes applying a frequency f to the driving circuit s , duration t s , duty cycle D s When the device under test is turned off, its drain-source blocks the DC bus voltage V dc , constant current source I L Via D f Free flow, when the device under test is turned on, the constant current source will be from D f The current is commutated to the device under test, and finally the drain of the device under test conducts the load current I L , which applies repeated inductive switching stress to the SiC MOSFET, where the positive driving voltage V GG , driving negative pressure V EE , driving resistance R g , switching frequency f s , duty cycle D s , degradation time t s , bus voltage V dc , load current I L 、Device case temperature T c All can be freely adjusted according to the needs to restore the operating conditions of the device in the actual converter to the greatest extent. Figure 2 (a) shows V GG =20V, V EE=-10V, R g =10Ω, V dc =400V, I L =4A, T c =25℃, f s =100kHz, D s =10% device v gs 、i d 、v ds Waveform, recorded as the switching trajectory waveform under working condition 1; Figure 2 (b) shows V GG =15V, V EE =-4V, R g =20Ω, V dc =200V, I L =10A, T c =75℃, f s =100kHz, D s =50% device v gs 、i d 、v ds The waveform is recorded as the switching trajectory waveform under working condition 2.
[0031] like Figure 3 As shown in Figure 2, after the repeated inductive switching overstress applied to the SiC MOSFET under test is completed, the gate, drain, and source of the device under test are short-circuited and left to stand for 1 hour as shown in (a) to avoid measurement errors caused by the threshold voltage hysteresis effect. Subsequently, the drain and gate are short-circuited, and a DC excitation is applied between the drain and source. The connection is shown in Figure (b), and the threshold voltage V is obtained when the drain current is 1mA. th , according to V under different stress levels th The degradation trend and level of the device can be judged based on the changes in the device's performance. A high-precision voltmeter is connected in parallel with a precision DC power supply to achieve accurate adjustment of the DC excitation, and a high-precision current source is connected in series with the device drain to achieve accurate measurement of the drain current.
[0032] like Figure 4 As shown, the actual converter design and operating conditions can be adjusted, for example, I L 、D s 、f s 、T c Parameters such as , observe the offset level of the device threshold voltage. In this embodiment, it is found that the degradation of the device under different load currents, switching frequencies, and duty cycles shows a non-monotonic trend, which can be referred to (a)-(c) respectively. As the case temperature T c The increase, with Figure 4 (d) The degradation degree of the device decreases monotonically, that is, high temperature is beneficial to slowing down the repeated switching stress degradation of the device.
[0033] In summary, the present invention connects a linear voltage regulator, a DC constant current electronic load, and an air-core inductor in series, and connects an absorption resistor in parallel at both ends of the air-core inductor to construct a low-ripple, high-stability linear constant current source. The drain of the SiC MOSFET under test is connected to the positive pole of the DC bus through a freewheeling diode, and the source is connected to the negative pole of the DC bus. A linear constant current source is connected in anti-parallel at both ends of the freewheeling diode, and an excitation voltage is applied to the gate of the device. This allows the SiC MOSFET under test to operate in a repeated inductive switching state to cyclically conduct the load current and block the bus voltage. The amplitude, frequency, and duty cycle of its stress can be freely adjusted on the drive side. By measuring the threshold voltage of the device after the overstress cycle test, the degradation trend and level of the device under test can be obtained. The present invention makes up for the deficiency of ignoring the drain blocking voltage and load current in the traditional gate switch stress degradation test, is more consistent with the working state of the device in the actual converter, and greatly improves the accuracy of the SiC MOSFET switch stress degradation assessment.
[0034] It will be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention may be implemented in various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.
[0035] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0036] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0037] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0038] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.
[0039] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.
Claims
1. A SiC MOSFET degradation test circuit based on repetitive inductive switching stress, characterized by: The device comprises a two-level gate drive circuit, a freewheeling diode, a linear constant current source and a DC bus capacitor, wherein the gate of the SiC MOSFET under test is connected to the output end of the two-level gate drive circuit; the drain of the SiC MOSFET under test is connected to the anode of the freewheeling diode, the cathode of the freewheeling diode is connected to one end of the DC bus capacitor, and they are both externally connected to the DC bus voltage, and the other end of the DC bus capacitor is connected to the negative electrode of the DC bus; the positive electrode of the linear constant current source is connected to the DC bus voltage, and the negative electrode of the linear constant current source is connected to the anode of the freewheeling diode; and the source of the SiC MOSFET under test is connected to the negative electrode of the DC bus.
2. The degradation test circuit according to claim 1, wherein: The two-level gate drive circuit includes a first drive transistor, a second drive transistor and a drive resistor, wherein the first drive transistor and the second drive transistor are connected in sequence, and the connection point between the two is also connected to one end of the drive resistor, and the other end of the drive resistor serves as the output end of the two-level gate drive circuit and is connected to the gate of the SiC MOSFET under test; the other end of the first drive transistor is connected to a positive drive voltage, and the other end of the second drive transistor is connected to a negative drive voltage.
3. The degradation test circuit according to claim 1, wherein: The linear constant current source comprises a linear voltage stabilizing source, a DC electronic load operating in a constant current mode, and an air-core inductor, which are sequentially connected from a positive electrode to a negative electrode.
4. A SiC MOSFET degradation test method based on repeated inductive switching stress, characterized in that The steps include: Step 1: Connect the gate of the SiC MOSFET under test to a degradation test circuit and apply a drive signal to the SiC MOSFET under test. At this time, the SiC MOSFET under test operates in a degradation cycle. Step 2: After the degradation is completed, the SiC MOSFET under test is disconnected from the degradation test circuit, a DC excitation is applied, and the threshold voltage is obtained; Step 3: Adjust the switching frequency and duty cycle of the driving signal, and / or adjust the parameters of the degradation test circuit, and repeat steps 1-2 to obtain several threshold voltages; Step 4: Obtain a degradation test result based on the obtained change in threshold voltage.
5. The degradation testing method according to claim 4, wherein: In step 2, after the SiC MOSFET under test is disconnected from the degradation test circuit, the gate, drain, and source of the SiC MOSFET under test are short-circuited and left to stand for a period of time, and then a DC excitation is applied.
6. The degradation testing method according to claim 4, wherein: In step 2, the method of applying DC excitation is to short-circuit the drain and gate of the SiC MOSFET under test, apply DC excitation between the drain and source, and obtain the threshold voltage when the drain current reaches a set threshold.