Matrix caching method, device and equipment and computer readable storage medium
By generating blocked random matrices in the cache and reducing dimensionality, the problem of low matrix cache efficiency is solved, and more efficient matrix processing is achieved.
Patent Information
- Application Number
- CN202510589299.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-08
- Publication Date
- 2025-08-08
AI Technical Summary
In the prior art, matrix cache efficiency is low, and the access stock from main storage to cache is too high, which affects data processing efficiency.
Generate a blocked random matrix in the cache, and reduce the dimensionality reduction matrix through the blocked random matrix until the matrix blocking is completed, and perform dimensionality reduction operations directly in the cache to avoid calling the blocked random matrix from the main memory.
Improve the efficiency of matrix cache, reduce the amount of access from main memory to cache, and optimize the memory access time.
Smart Images
Figure CN120448293A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to a matrix caching method, apparatus, device, and computer-readable storage medium. Background Art
[0002] To maximize the peak performance of randomized matrix-matrix multiplication, data movement must be minimized. This applies to the two operators in randomized linear algebra, Generate Dense Sketch (randomized dense matrix) and Sketch-matrix multiplication. Currently, when performing matrix multiplication, data must first be stored in main memory. When the operation is subsequently called, the data must be transferred to the cache. This results in excessive main memory to cache accesses, affecting data processing efficiency.
[0003] Therefore, how to improve the efficiency of matrix cache and reduce the amount of memory access from main memory to cache is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention
[0004] In view of this, an object of the present invention is to provide a matrix caching method, apparatus, device and computer-readable storage medium, which solve the technical problem of low matrix caching efficiency in the prior art.
[0005] To solve the above technical problems, the present invention provides a matrix caching method, comprising:
[0006] Generating a first block random matrix in a cache based on first block parameters; wherein the first block parameters include parameters related to generating the block random matrix;
[0007] Calling the first block random matrix from the cache to perform dimensionality reduction on the matrix to be reduced, to obtain a first reduced dimensionality matrix;
[0008] generating a second block random matrix in the cache based on a second block parameter; wherein the first block random matrix and the second block random matrix are different;
[0009] The second block random matrix is called from the cache to reduce the dimension of the first dimensionality reduction matrix to obtain a second dimensionality reduction matrix, and block random matrices are continuously generated to reduce the dimension of the last dimensionality reduction matrix until the random matrix is completely blocked to obtain a target dimensionality reduction matrix.
[0010] Optionally, generating a first block random matrix in a cache based on the first block parameter includes:
[0011] Get all performance data of the current system;
[0012] Analyze all the performance data to obtain performance parameters;
[0013] When the performance parameter is greater than a minimum performance parameter threshold, a step of generating a first block random matrix in a cache based on the first block parameter is performed.
[0014] Optionally, the matrix to be reduced in dimensionality is a dense matrix; the dense matrix is a matrix in which the number of non-zero values is greater than a set minimum threshold.
[0015] Optionally, generating a first block random matrix in a cache based on the first block parameter includes:
[0016] Determine a target block loop framework based on a time parameter corresponding to the current system; wherein the time parameter is a parameter related to the time cost of matrix block; and the target block loop framework is a block loop framework corresponding to the lowest access memory;
[0017] A first block random matrix is generated in a buffer based on the target block loop framework and based on the first block parameters.
[0018] Optionally, the process of determining the time parameters includes:
[0019] Obtain the first time cost of generating a random number and the second time cost of moving a random number;
[0020] A division operation is performed based on the first time cost and the second time cost to obtain the time parameter.
[0021] Optionally, a target block loop framework is determined based on time parameters corresponding to the current system, including:
[0022] When the time parameter is less than 1, the target block loop framework is determined to be an mnk loop framework or an mkn loop framework; the mnk loop framework first traverses the rows of the matrix to be reduced in dimension, then traverses the columns of the block random matrix, and finally traverses the columns of the result matrix; the mkn loop framework first traverses the columns of the block random matrix, then traverses the columns of the result matrix, and finally traverses the rows of the matrix to be reduced in dimension;
[0023] When the time parameter is not less than 1, the target block loop framework is determined to be an nkm loop framework; wherein the nkm loop framework first traverses the columns of the block random matrix, then traverses the columns of the result matrix, and finally traverses the rows of the matrix to be reduced.
[0024] The present invention also provides a matrix cache device, comprising:
[0025] A first block random matrix generation module, configured to generate a first block random matrix in a cache based on first block parameters; wherein the first block parameters include parameters related to generating the block random matrix;
[0026] A dimensionality reduction module, configured to call the first block random matrix from the cache to perform dimensionality reduction on the matrix to be reduced, to obtain a first reduced dimensionality matrix;
[0027] A second block random matrix generation module, configured to generate a second block random matrix in the cache based on a second block parameter; wherein the first block random matrix and the second block random matrix are different;
[0028] The target dimensionality reduction matrix determination module is used to call the second block random matrix from the cache to reduce the dimensionality of the first dimensionality reduction matrix to obtain a second dimensionality reduction matrix, and continuously generate block random matrices to reduce the dimensionality of the last dimensionality reduction matrix until the random matrix is blocked and the target dimensionality reduction matrix is obtained.
[0029] Optionally, the first block random matrix generation module may include:
[0030] Performance data acquisition unit, used to obtain all performance data of the current system;
[0031] a performance parameter determination unit, configured to analyze all the performance data to obtain performance parameters;
[0032] The first block random matrix generating unit is configured to, when the performance parameter is greater than a minimum performance parameter threshold, execute the step of generating a first block random matrix in a cache based on the first block parameter.
[0033] The present invention also provides a matrix cache device, comprising:
[0034] Memory for storing computer programs;
[0035] A processor is configured to execute the computer program to implement the steps of the above matrix caching method.
[0036] The present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the matrix caching method described above are implemented.
[0037] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the above matrix caching method when executed by a processor.
[0038] It can be seen that the present invention generates a first block random matrix in a cache based on a first block parameter; wherein the first block parameter includes parameters related to the generation of the block random matrix; the first block random matrix is called from the cache to reduce the dimension of the matrix to be reduced, and a first reduced dimension matrix is obtained; based on the second block parameter, a second block random matrix is generated in the cache; wherein the first block random matrix and the second block random matrix are different; the second block random matrix is called from the cache to reduce the dimension of the first reduced dimension matrix, and a second reduced dimension matrix is obtained, and block random matrices are continuously generated to reduce the dimension of the reduced dimension matrix obtained last time until the random matrix is blocked and the target reduced dimension matrix is obtained.
[0039] The beneficial effect of the present invention is that, compared with the current method of storing all generated block matrices in the main memory and then calling the block matrices from the main memory to the cache for dimensionality reduction when needed, the present invention directly generates a block random matrix in the cache, thereby directly obtaining the block random matrix from the cache for dimensionality reduction, realizing dimensionality reduction while generating the block random matrix, thereby eliminating the need to call the block random matrix from the main memory, thereby improving the efficiency of the matrix cache.
[0040] In addition, the present invention also provides a matrix cache device, equipment and computer-readable storage medium, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0042] Figure 1 A flowchart of a matrix caching method provided by an embodiment of the present invention;
[0043] Figure 2 An example flowchart of a matrix caching method provided by an embodiment of the present invention;
[0044] Figure 3 A schematic diagram of generating a block random matrix according to an embodiment of the present invention is provided;
[0045] Figure 4 A schematic structural diagram of a matrix cache device provided by an embodiment of the present invention;
[0046] Figure 5 A schematic structural diagram of a matrix cache device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.
[0048] Please refer to Figure 1 , Figure 1 A flowchart of a matrix caching method provided by an embodiment of the present invention. The method may include:
[0049] S101 : Generate a first block random matrix in a cache based on first block parameters; wherein the first block parameters include parameters related to generating the block random matrix.
[0050] The executor of this embodiment is an electronic device. This embodiment does not limit the specific electronic device. For example, the electronic device in this embodiment can be a computer, a mobile phone, etc. This embodiment does not limit the specific first block parameter, as long as block partitioning can be performed based on the block parameter. For example, A is a random matrix, B is the matrix to be reduced, and C is the target matrix for dimension reduction. A is an mXk matrix; B is kXn, and C is mXn. The block parameters can include nb (the block size of the random matrix column), kb (the size of the random matrix row dimension), mb (the block size of the matrix to be reduced in the row dimension), nr (nb is a small block), and mr (mb is a small block). nb represents the block size of the random matrix in the column direction. Application scenario: In block matrix operations, the matrix is divided into multiple sub-blocks, and the number of columns in each sub-block is nb. Example: If the matrix has 12 columns and nb = 3, the matrix will be divided into 4 sub-blocks in the column direction, each sub-block has 3 columns. kb represents the block size of the matrix in the row direction. Application scenario: Used to determine the number of rows in the matrix block in the row direction. Example: If the matrix has 10 rows and kb=2, the matrix will be divided into 5 sub-blocks in the row direction, and each sub-block has 2 rows. mb usually represents the size of the blocks of matrix A in the row direction. Application scenario: In matrix multiplication, the row block size of matrix A affects the efficiency of calculation and memory access pattern. Example: If matrix A is an 8-row matrix and mb=4, matrix A will be divided into 2 sub-blocks in the row direction, and each sub-block has 4 rows. nr represents a finer-grained block size, for further division of columns. Example: If nb=4 and nr=2, each block of size 4 will be further divided into two small blocks of size 2. mr represents a further subdivision of mb, indicating a finer-grained division of blocks in the row direction. Example: If mb=4 and mr=2, each row block of size 4 will be further divided into two small blocks of size 2. In this embodiment, the first block random matrix refers to the first block of the matrix generated based on the above block parameters.
[0051] It should be further explained that, based on any of the above embodiments, the above-mentioned generation of the first block random matrix in the cache based on the first block parameter may include: obtaining all performance data of the current system; analyzing based on all performance data to obtain performance parameters; when the performance parameters are greater than the minimum performance parameter threshold, executing the step of generating the first block random matrix in the cache based on the first block parameter. This embodiment does not limit the specific performance parameters. For example, it can be CPU usage, total memory and usage, total disk and usage, and the number of bytes sent and received by the network. This embodiment does not limit the specific performance parameters. After obtaining the system performance data, the data can be analyzed to obtain a comprehensive performance parameter. This embodiment compares the obtained performance parameter with a preset minimum performance parameter threshold. If the performance parameter is greater than the threshold, the subsequent operation is executed; otherwise, it is not executed. This embodiment will only be executed if the performance meets the requirements, ensuring that the dimensionality reduction process can be carried out on the matrix to be reduced, and preventing the performance from being insufficient for dimensionality reduction, thereby requiring re-dimensionality reduction processing.
[0052] S102: Call a first block random matrix from the cache to perform dimensionality reduction on the matrix to be reduced, to obtain a first reduced dimensionality matrix.
[0053] This embodiment does not limit the specific matrix to be reduced. For example, the matrix to be reduced in this embodiment may be a dense matrix, where the number of non-zero values in a dense matrix is greater than a set minimum threshold. This embodiment does not limit the specific minimum threshold; for example, the minimum threshold in this embodiment may be 50, 60, etc. Alternatively, the matrix to be reduced in this embodiment may be a high-dimensional matrix. This embodiment does not limit the specific method for performing dimensionality reduction. For example, this embodiment may use an mnk loop framework, an mkn loop framework, etc.
[0054] It should be further explained that, based on any of the above embodiments, in order to improve the performance of the dimensionality reduction algorithm, generating the first block random matrix in the cache based on the first block parameter may include:
[0055] S1021, determining a target block loop framework based on a time parameter corresponding to the current system; wherein the time parameter is a parameter related to the time cost of matrix block; and the target block loop framework is a block loop framework corresponding to the lowest access memory;
[0056] S1022 : Generate a first block random matrix in a cache based on the target block loop framework and the first block parameters.
[0057] This embodiment does not specify a time parameter. For example, the time parameter in this embodiment can be the time cost of generating a random number; or the time parameter in this embodiment can be the time cost of moving a random number. This embodiment does not limit the specific target block loop framework, as long as the access volume is minimized when performing dimensionality reduction based on the target block loop framework.
[0058] It should be further explained that, based on the above embodiment, the method for determining the time parameter may include: obtaining a first time cost for generating a random number and a second time cost for moving a random number; performing a division operation based on the first time cost and the second time cost to obtain the time parameter. The time parameter in this embodiment is a, and the other , b represents the time cost of generating a double (double-precision floating-point) random number, and c is the time cost of transporting a double number.
[0059] It should be further explained that, based on any of the above embodiments, the above determination of the target block loop framework based on the time parameter a corresponding to the current system may include: when the time parameter a is less than 1, determining that the target block loop framework is an mnk loop framework or an mkn loop framework; the mnk loop framework first traverses the rows of the matrix to be reduced in dimension, then traverses the columns of the block random matrix, and finally traverses the columns of the result matrix; the mkn loop framework first traverses the columns of the block random matrix, then traverses the columns of the result matrix, and finally traverses the rows of the matrix to be reduced in dimension; when the time parameter a is not less than 1, determining that the target block loop framework is an nkm loop framework; wherein, the nkm loop framework first traverses the columns of the block random matrix, then traverses the columns of the result matrix, and finally traverses the rows of the matrix to be reduced in dimension. In this embodiment, when the time parameter a<1, the use of the mnk and mkn loop frameworks can reduce memory access, and the maximum amount of memory access saved is: . When the time parameter a time parameter>=1, the use of the nkm loop framework can reduce memory access, and the maximum memory access saved is 2nk. It is understandable that the theoretical computer community uses the concept of I / O complexity to define the memory access of the algorithm. Suppose in a processor with only two layers of memory, one layer is a fast cache cache of size S, and the other layer is an infinitely large slow storage DISK. To enter the CPU for calculation, data needs to be loaded from the DISK to the cache. Under the ideal cache model, the minimum amount of data movement is defined as the I / O complexity of the algorithm. (Mainly considering the amount of data movement from the DISK to the cache), first generate a sketch (random matrix), and then perform matrix multiplication: the I / O complexity of the random matrix-matrix layer algorithm, , when 2mnk is much larger than 2S+2nk, the I / O complexity C of the matrix multiplication algorithm is , calculate the memory access ratio , the current algorithm's computational memory access ratio is much smaller than and Therefore, the memory access can be reduced, and the maximum memory access saved is 2nk. The I / O complexity of the random matrix-matrix multiplication algorithm , when 2mnk is much larger than 2S, C is , calculate the memory access ratio , the access amount of the non-integrated version is , the access volume of the fusion version is , which reduces the memory access by 2nk. When the time parameter a<1, using the mnk and mkn loop framework can reduce the memory access. The maximum amount of memory access saved is: The cost of accessing memory and generating random matrices for the unfused version is The cost of accessing memory and generating random matrices for the fused version (using the optimal mkn or mnk loop framework) is In this embodiment, the fused version generates random matrices in blocks in the cache, and then multiplies them with the corresponding parts of the matrix to be reduced to reduce the dimension. The unfused version refers to the original one, which generates a complete random matrix stored in the main memory and then transfers it to the cache in blocks for calculation.
[0060] For ease of understanding, the embodiment of the present invention provides a loop framework of nkm, which uses nkm to scan from 0-n and from n to k dimensions to obtain a block random matrix.
[0061] / / Loop 1: Traverse column blocks
[0062] for jc=0 to n-1 step nc{
[0063] / / Loop 2: Traverse the block
[0064] for pc=0 to k-1 step kc{
[0065] / / Generate random matrix B matrix blocks and save them directly in packB format (packed format)
[0066] S(pc:pc+kc-1,jc:jc+nc-1)->Bc
[0067] / / Loop 3: Traverse the row block
[0068] for ic=0 to m-1 step mc{
[0069] / / Pack the A matrix block into Ac
[0070] A(ic:ic+mc-1,pc:pc+kc-1)->Ac
[0071] / / Loop 4: Traverse the column blocks of the result matrix
[0072] for jr=0 to nc-1 step nr{
[0073] / / Loop 5: Traverse the row blocks of the result matrix
[0074] for ir=0 to mc-1 step mr{
[0075] / / Loop 6: Micro-kernel, traverse the elements of the block
[0076] for pr=0 to kc-1 step 1{
[0077] / / Perform matrix multiplication and accumulate the result into Cc
[0078] Cc(ir:ir+mr-1,jr:jr+nr-1)+=
[0079] Ac(ir:ir+mr-1,pr)*
[0080] Bc(pr, r:jr+nr-1)
[0081] }
[0082] }
[0083] }
[0084] }
[0085] }
[0086] }
[0087] S103: Generate a second block random matrix in the cache based on the second block parameter; wherein the first block random matrix and the second block random matrix are different.
[0088] This embodiment does not limit the specific second block parameters. The second block parameters and the first block parameters in this embodiment may be different or the same, as long as the first block random matrix and the second block random matrix are different.
[0089] S104, calling the second block random matrix from the cache to reduce the dimension of the first dimensionality reduction matrix to obtain a second dimensionality reduction matrix, and continuously generating block random matrices to reduce the dimension of the previously obtained dimensionality reduction matrix until the random matrix is completely blocked to obtain a target dimensionality reduction matrix.
[0090] This embodiment generates a block random matrix while performing dimensionality reduction. Specifically, each time a block random matrix is generated in the cache, dimensionality reduction is immediately performed on the matrix to be reduced. The cache in this embodiment is a small-capacity, high-speed memory located between the CPU (central processing unit) and main memory, also known as a cache memory. It can be understood that by integrating the matrix multiplication operator with the sampling dimensionality reduction operator, the present invention reduces redundant memory accesses and optimizes memory access time, thereby achieving an acceleration effect.
[0091] The matrix caching method provided by an embodiment of the present invention may include: S101, generating a first block random matrix in a cache based on a first block parameter; wherein the first block parameter includes parameters related to generating the block random matrix; S102, calling the first block random matrix from the cache to reduce the dimension of the matrix to be reduced, thereby obtaining a first reduced dimension matrix; S103, generating a second block random matrix in the cache based on a second block parameter; wherein the first block random matrix and the second block random matrix are different; S104, calling the second block random matrix from the cache to reduce the dimension of the first reduced dimension matrix, thereby obtaining a second reduced dimension matrix, and continuously generating block random matrices to reduce the dimension of the reduced dimension matrix obtained last time, until the random matrix is completely blocked, thereby obtaining a target reduced dimension matrix. Compared with the current method of storing all generated block matrices in the main memory and then calling them from the main memory to the cache for dimensionality reduction when needed, the present invention directly generates a block random matrix in the cache, and then directly obtains the block random matrix from the cache for dimensionality reduction, realizing dimensionality reduction while generating the block random matrix, thereby eliminating the need to call the block random matrix from the main memory, thereby improving the efficiency of the matrix cache.
[0092] In order to make the present invention easier to understand, please refer to Figure 2 , Figure 2 An example flow chart of a matrix caching method provided in an embodiment of the present invention may specifically include:
[0093] S201, obtaining a first time cost of generating a random number and a second time cost of moving a random number.
[0094] The goal of this invention is to implement a random matrix-matrix multiplication operation with optimal memory usage on a multi-core CPU (central processing unit) processor, minimizing the amount of memory access from main memory (typically the primary storage device in a computer system, often referred to as RAM or random access memory) to cache. It is understood that to maximize the peak performance of random matrix-matrix multiplication, data handling must be minimized. This patent proposes a fusion algorithm for randomized dense matrix-matrix multiplication, focusing on the two operators in randomized linear algebra: generating dense sketches (randomized dense matrices) and sketch-matrix multiplication. This algorithm minimizes the memory usage of this core component of randomized linear algebra. This patent addresses the shortcomings of randomized matrix-matrix multiplication in existing literature: it generates B (a random matrix) and reads it only once, while A and C are read repeatedly. This improvement is addressed by designing B to be generated directly in cache, while A and C are shared across multiple cores. This reduces memory usage and provides a method for calculating the block parameters to ensure minimal memory usage. A is the matrix to be reduced, C is the target matrix, and B is the random matrix. For easier understanding, please refer to Figure 3 , Figure 3 A schematic diagram of a block random matrix generated by the present invention is provided in an embodiment of the present invention, from Figure 3 As can be seen in the figure, the present invention generates random matrices in blocks directly in the cache. The green line represents matrix C, the red line represents matrix B generated randomly by the first operator, and the blue line represents matrix A, the original matrix of the matrix multiplication.
[0095] S202: Determine a time parameter based on the first time cost and the second time cost.
[0096] S203: When the time parameter is less than 1, the target block cycle frames are determined to be mnk and mkn.
[0097] S204: When the time parameter is greater than 1, determine the target block loop frame as nkm.
[0098] S205 , generating block random parameters in the cache, and reducing the dimension of the current matrix to be reduced by using the current block random parameters based on the target block loop framework.
[0099] S206 , continuously generating block random parameters in the cache, and reducing the dimension of the matrix to be reduced based on the block random parameters until the block random parameters are completely generated, thereby obtaining a target reduced dimension matrix.
[0100] The embodiment of the present invention generates a block random matrix while reducing the dimension, and adopts a target block loop framework method to reduce the memory access amount of random dense matrix-matrix multiplication to the minimum.
[0101] The matrix caching device provided by an embodiment of the present invention is introduced below. The matrix caching device described below and the matrix caching method described above can be referred to in correspondence with each other.
[0102] Please refer to Figure 4 , Figure 4 A schematic structural diagram of a matrix cache device provided in an embodiment of the present invention may include:
[0103] A first block random matrix generation module 100 is configured to generate a first block random matrix in a cache based on first block parameters; wherein the first block parameters include parameters related to generating the block random matrix;
[0104] A dimensionality reduction module 200 is configured to call the first block random matrix from the cache to perform dimensionality reduction on the matrix to be reduced, thereby obtaining a first reduced dimensionality matrix;
[0105] A second block random matrix generating module 300 is configured to generate a second block random matrix in the cache based on a second block parameter; wherein the first block random matrix and the second block random matrix are different;
[0106] The target dimensionality reduction matrix determination module 400 is used to call the second block random matrix from the cache to reduce the dimensionality of the first dimensionality reduction matrix to obtain a second dimensionality reduction matrix, and continuously generate block random matrices to reduce the dimensionality of the dimensionality reduction matrix obtained last time until the random matrix is blocked and the target dimensionality reduction matrix is obtained.
[0107] Furthermore, based on any of the above embodiments, the first block random matrix generation module may include:
[0108] Performance data acquisition unit, used to obtain all performance data of the current system;
[0109] a performance parameter determination unit, configured to analyze all the performance data to obtain performance parameters;
[0110] The first block random matrix generating unit is configured to, when the performance parameter is greater than a minimum performance parameter threshold, execute the step of generating a first block random matrix in a cache based on the first block parameter.
[0111] Furthermore, based on any of the above embodiments, the matrix to be reduced in dimensionality is a dense matrix; the dense matrix is a matrix in which the number of non-zero values is greater than a set minimum threshold.
[0112] Further, based on any of the above embodiments, the first block random matrix generation module 100 may include:
[0113] a target block loop frame determining unit, configured to determine a target block loop frame based on a time parameter corresponding to a current system; wherein the time parameter is a parameter related to a time cost of matrix block; and the target block loop frame is a block loop frame corresponding to a minimum access memory;
[0114] The first block random matrix generating unit is configured to generate a first block random matrix in a cache based on the target block loop framework and the first block parameters.
[0115] Further, with respect to any of the above embodiments, the matrix cache device may further include:
[0116] A time cost acquisition module, used to acquire a first time cost of generating a random number and a second time cost of moving a random number;
[0117] A time parameter determination module is configured to perform a division operation based on the first time cost and the second time cost to obtain the time parameter.
[0118] Further, based on any of the above embodiments, the target block cycle framework determination unit may include:
[0119] A first target block loop framework determination unit is configured to determine, when the time parameter is less than 1, that the target block loop framework is an mnk loop framework or an mkn loop framework; the mnk loop framework first traverses the rows of the matrix to be reduced in dimension, then traverses the columns of the block random matrix, and finally traverses the columns of the result matrix; the mkn loop framework first traverses the columns of the block random matrix, then traverses the columns of the result matrix, and finally traverses the rows of the matrix to be reduced in dimension;
[0120] The second target block loop frame determination unit is used to determine that the target block loop frame is an nkm loop frame when the time parameter is not less than 1; wherein, the nkm loop frame first traverses the columns of the block random matrix, then traverses the columns of the result matrix, and finally traverses the rows of the matrix to be reduced.
[0121] It should be noted that the order of the modules and units in the above matrix cache device can be changed without affecting the logic.
[0122] A matrix cache device provided by an embodiment of the present invention may include: a first block random matrix generation module 100, used to generate a first block random matrix in a cache based on a first block parameter; wherein the first block parameter includes parameters related to the generation of a block random matrix; a dimensionality reduction module 200, used to call the first block random matrix from the cache to reduce the dimension of the matrix to be reduced, to obtain a first reduced dimension matrix; a second block random matrix generation module 300, used to generate a second block random matrix in the cache based on a second block parameter; wherein the first block random matrix and the second block random matrix are different; a target reduced dimension matrix determination module 400, used to call the second block random matrix from the cache to reduce the dimension of the first reduced dimension matrix, to obtain a second reduced dimension matrix, and continuously generate block random matrices to reduce the dimension of the reduced dimension matrix obtained last time until the random matrix is completely blocked, and a target reduced dimension matrix is obtained. Compared with the current method of storing all generated block matrices in the main memory and then calling them from the main memory to the cache for dimensionality reduction when needed, the present invention directly generates a block random matrix in the cache, and then directly obtains the block random matrix from the cache for dimensionality reduction, realizing dimensionality reduction while generating the block random matrix, thereby eliminating the need to call the block random matrix from the main memory, thereby improving the efficiency of the matrix cache.
[0123] A matrix caching device provided by an embodiment of the present invention is introduced below. The matrix caching device described below and the matrix caching method described above can be referred to in correspondence with each other.
[0124] Please refer to Figure 5 , Figure 5 A schematic structural diagram of a matrix cache device provided in an embodiment of the present invention may include:
[0125] Memory 10, for storing computer programs;
[0126] The processor 20 is configured to execute a computer program to implement the above matrix caching method.
[0127] The memory 10 , the processor 20 , and the communication interface 30 all communicate with each other via a communication bus 40 .
[0128] In the embodiment of the present invention, the memory 10 is used to store one or more programs. The program may include program code, and the program code includes computer operation instructions. In the embodiment of the present invention, the memory 10 may store programs for implementing the following functions:
[0129] Generate a first block random matrix in the cache based on the first block parameters; wherein the first block parameters include parameters related to generating the block random matrix;
[0130] Call the first block random matrix from the cache to reduce the dimension of the matrix to be reduced, and obtain a first reduced dimension matrix;
[0131] generating a second block random matrix in the cache based on the second block parameter; wherein the first block random matrix and the second block random matrix are different;
[0132] The second block random matrix is called from the cache to reduce the dimension of the first dimensionality reduction matrix to obtain the second dimensionality reduction matrix. The block random matrix is continuously generated to reduce the dimension of the last dimensionality reduction matrix until the random matrix is blocked and the target dimensionality reduction matrix is obtained.
[0133] In one possible implementation, the memory 10 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and applications required for at least one function, etc.; the data storage area may store data created during use.
[0134] In addition, the memory 10 may include a read-only memory and a random access memory, and provides instructions and data to the processor. A portion of the memory may also include NVRAM. The memory stores an operating system and operating instructions, executable modules or data structures, or a subset or an extended set thereof. The operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic tasks and processing hardware-based tasks.
[0135] The processor 20 may be a central processing unit (CPU), an application-specific integrated circuit, a digital signal processor, a field programmable gate array, or other programmable logic device. The processor 20 may be a microprocessor or any conventional processor. The processor 20 may call a program stored in the memory 10 .
[0136] The communication interface 30 may be an interface of a communication module, and is used to connect to other devices or systems.
[0137] Of course, it needs to be explained that Figure 5 The structure shown does not constitute a limitation on the matrix buffer device in the embodiment of the present invention. In actual applications, the matrix buffer device may include Figure 5 More or fewer components than shown, or combinations of certain components.
[0138] The following describes a computer-readable storage medium provided by an embodiment of the present invention. The computer-readable storage medium described below and the matrix caching method described above may refer to each other.
[0139] The present invention also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the above-mentioned matrix caching method are implemented.
[0140] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., which can store program codes.
[0141] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.
[0142] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.
[0143] Finally, it should be noted that, in this document, relationships such as first and second, etc., are used solely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0144] The matrix caching method, apparatus, device, and computer-readable storage medium provided by the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concept of the present invention. Furthermore, those skilled in the art will appreciate that variations in the specific implementation methods and scope of application may occur based on the concepts of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.
Claims
1. A matrix caching method, characterized in that: include: Generating a first block random matrix in a cache based on first block parameters; wherein the first block parameters include parameters related to generating the block random matrix; Calling the first block random matrix from the cache to perform dimensionality reduction on the matrix to be reduced, to obtain a first reduced dimensionality matrix; generating a second block random matrix in the cache based on a second block parameter; wherein the first block random matrix and the second block random matrix are different; The second block random matrix is called from the cache to reduce the dimension of the first dimensionality reduction matrix to obtain a second dimensionality reduction matrix, and block random matrices are continuously generated to reduce the dimension of the last dimensionality reduction matrix until the random matrix is completely blocked to obtain a target dimensionality reduction matrix.
2. The matrix caching method according to claim 1, wherein: Generating a first block random matrix in a buffer based on the first block parameters includes: Get all performance data of the current system; Analyze all the performance data to obtain performance parameters; When the performance parameter is greater than a minimum performance parameter threshold, a step of generating a first block random matrix in a cache based on the first block parameter is performed.
3. The matrix caching method according to claim 1, wherein: The matrix to be reduced in dimension is a dense matrix; the dense matrix is a matrix in which the number of non-zero values is greater than a set minimum threshold.
4. The matrix caching method according to any one of claims 1 to 3, characterized in that: Generating a first block random matrix in a buffer based on the first block parameters includes: Determine a target block loop framework based on a time parameter corresponding to the current system; wherein the time parameter is a parameter related to the time cost of matrix block; and the target block loop framework is a block loop framework corresponding to the lowest access memory; A first block random matrix is generated in a buffer based on the target block loop framework and based on the first block parameters.
5. The matrix caching method according to claim 4, characterized in that: The process of determining time parameters includes: Obtain the first time cost of generating a random number and the second time cost of moving a random number; A division operation is performed based on the first time cost and the second time cost to obtain the time parameter.
6. The matrix caching method according to claim 4, wherein: Determine the target block loop framework based on the time parameters corresponding to the current system, including: When the time parameter is less than 1, the target block loop framework is determined to be an mnk loop framework or an mkn loop framework; the mnk loop framework first traverses the rows of the matrix to be reduced in dimension, then traverses the columns of the block random matrix, and finally traverses the columns of the result matrix; the mkn loop framework first traverses the columns of the block random matrix, then traverses the columns of the result matrix, and finally traverses the rows of the matrix to be reduced in dimension; When the time parameter is not less than 1, the target block loop framework is determined to be an nkm loop framework; wherein the nkm loop framework first traverses the columns of the block random matrix, then traverses the columns of the result matrix, and finally traverses the rows of the matrix to be reduced.
7. A matrix cache device, characterized in that: include: A first block random matrix generation module, configured to generate a first block random matrix in a cache based on first block parameters; wherein the first block parameters include parameters related to generating the block random matrix; A dimensionality reduction module, configured to call the first block random matrix from the cache to perform dimensionality reduction on the matrix to be reduced, to obtain a first reduced dimensionality matrix; A second block random matrix generation module, configured to generate a second block random matrix in the cache based on a second block parameter; wherein the first block random matrix and the second block random matrix are different; The target dimensionality reduction matrix determination module is used to call the second block random matrix from the cache to reduce the dimensionality of the first dimensionality reduction matrix to obtain a second dimensionality reduction matrix, and continuously generate block random matrices to reduce the dimensionality of the last dimensionality reduction matrix until the random matrix is blocked and the target dimensionality reduction matrix is obtained.
8. The matrix cache device according to claim 7, characterized in that: The first block random matrix generation module may include: Performance data acquisition unit, used to obtain all performance data of the current system; a performance parameter determination unit, configured to analyze all the performance data to obtain performance parameters; The first block random matrix generating unit is configured to, when the performance parameter is greater than a minimum performance parameter threshold, execute the step of generating a first block random matrix in a cache based on the first block parameter.
9. A matrix cache device, characterized in that: include: memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the matrix caching method according to any one of claims 1 to 6.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the matrix caching method according to any one of claims 1 to 6.