MMU acceleration method and device and SoC chip

Abstract

The invention relates to the technical field of chips, and provides an MMU acceleration method and device and an SoC chip. The method comprises the following steps: presetting a cache, determining the number of residual addresses in a current virtual page according to complete address information of a task and current address information of a current task sub-operation, and judging whether the task has a required next virtual page or not; wherein the current virtual page is a virtual page required by a current task sub-operation; and if it is determined that the number of the remaining addresses in the current virtual page is smaller than a first preset number and the task has a required next virtual page, loading the next virtual page into a cache from a memory so as to load the next virtual page in the cache into an address mapping table of the MMU for use when the address mapping table of the MMU loses a target. The whole execution time of the task can be shortened.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an MMU acceleration method, device and SoC chip. Background Art

[0002] The Memory Management Unit (MMU) is primarily responsible for translating virtual addresses into physical addresses. MMUs are commonly found in various System-on-Chip (SoC) chips. For ease of use, software often uses virtual addresses to manage memory, but hardware requires physical addresses to access the correct location. Therefore, virtual addresses must be translated into physical addresses whenever memory is accessed.

[0003] Both physical and virtual addresses are managed using paging. Physical addresses typically occupy 4KB per page, while virtual addresses are more flexible, typically with page sizes of 4KB, 16KB, 128KB, and so on. The offset address within a 4KB page is the same for both physical and virtual addresses. Therefore, address translation only requires translating addresses above 4KB.

[0004] The mapping between each virtual address and physical address is typically stored in Double Data Rate SDRAM (DDR). However, accessing DDR has a relatively long latency, typically hundreds of cycles. To reduce this latency, a Translation Lookaside Buffer (TLB) is typically built into the MMU to cache previously used mappings. If the virtual address mapping can be found in the TLB, then there's no need to access the DDR again. The MMU latency is reduced to just a dozen cycles, or even one or two, allowing for rapid address translation. However, due to the limited space of the MMU, it is difficult to store all mapping relationships in the TLB. Therefore, usually after the MMU misses, the corresponding virtual page is searched from the memory and loaded into the MMU. In the process of searching for the virtual page, the task that needs to use the corresponding virtual address is stalled and cannot continue to execute until the virtual page found is loaded into the MMU. The task can then be continued. However, since a large number of virtual pages are stored in the memory, searching for the virtual page takes a lot of time, which increases the execution time of the task.

[0005] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in this technical field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method, device and SoC chip for MMU acceleration to shorten the overall execution time of a task.

[0007] The present invention adopts the following technical solutions:

[0008] In a first aspect, the present invention provides a method for MMU acceleration, presetting a cache, the method comprising:

[0009] Determining the number of remaining addresses in the current virtual page based on the complete address information of the task and the current address information of the current task sub-operation, and judging whether the task has a next virtual page required; wherein the current virtual page is the virtual page required by the current task sub-operation;

[0010] If it is determined that the number of remaining addresses in the current virtual page is less than a first preset number, and the task has the required next virtual page, the next virtual page is loaded from the memory into the cache, so that when the address mapping table of the MMU misses the target, the next virtual page in the cache is loaded into the address mapping table of the MMU for use.

[0011] Preferably, the step of loading the next virtual page from the memory into the cache is performed by loading the base address of the next virtual page and the base address of the corresponding physical page into the cache, which specifically includes:

[0012] Calculating a base address of a next virtual page according to the current address information and the complete address information;

[0013] According to the base address of the next virtual page, searching the memory for the base address of the corresponding physical page;

[0014] The base address of the next virtual page and the base address of the corresponding physical page are stored in the cache.

[0015] Preferably, searching the memory for the base address of the corresponding physical page according to the base address of the next virtual page specifically includes:

[0016] Determining offsets at various levels according to the base address of the next virtual page;

[0017] According to the base address and n-level offset of the n-level page table in the memory, the corresponding n-level storage position is determined, and the base address of the n-1-level page table is read from the n-level storage position until the base of the 1-level page table is read, and then the base address of the physical page corresponding to the next virtual page is read from the 1-level storage position in the 1-level page table.

[0018] Preferably, before loading the next virtual page from the memory into the cache, the method further comprises:

[0019] The MMU is searched for the existence of the next virtual page. If the MMU finds that the next virtual page exists, the next virtual page is not loaded from the memory into the cache.

[0020] Preferably, when the address mapping table of the MMU misses the target, loading the next virtual page in the cache into the address mapping table of the MMU for use specifically includes:

[0021] Intercepting a page table query instruction from the MMU and searching the cache for the next virtual page;

[0022] If the next virtual page is found, the next virtual page is returned to the MMU so that the MMU loads the next virtual page into the address mapping table of the MMU for use.

[0023] Preferably, the method further comprises:

[0024] Determining the number of remaining addresses required for the task based on the complete address information and the current address information;

[0025] If the number of remaining addresses required for the task is less than a second preset number, sending a pre-read command to the instruction execution unit, so that the instruction execution unit issues task pre-read information according to the pre-read command;

[0026] receiving task pre-read information from the instruction execution unit, reading complete address information of a next task from the task pre-read information, and determining a virtual page required by the next task according to the complete address information of the next task;

[0027] The virtual pages required for the next task are loaded from the memory into the cache, so that when the next task is executed, the virtual pages required for the next task in the cache are loaded into the address mapping table of the MMU for use.

[0028] Preferably, the complete address information of the task is issued by the instruction execution unit when starting to execute the task, and the current address information is issued by the instruction execution unit when executing the current task sub-operation.

[0029] In a second aspect, the present invention further provides an MMU acceleration device for implementing the MU acceleration method described in the first aspect, the device comprising:

[0030] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor to perform the MU acceleration method described in the first aspect.

[0031] In a third aspect, the present invention provides an MMU acceleration device, comprising an instruction execution unit, an acceleration unit, an MMU, and a memory; the acceleration unit is the MMU acceleration device described in the second aspect;

[0032] The memory is used to store each virtual page;

[0033] The instruction execution unit is used to send the complete address information required for the task to the acceleration unit when the task starts to be executed, and send the current address information of the current task sub-operation to the acceleration unit when executing the current task sub-operation;

[0034] The acceleration unit is used to determine the number of remaining addresses in the current virtual page based on the complete address information of the task and the current address information of the current task sub-operation, and to determine whether the task has a next virtual page required; wherein the current virtual page is the virtual page required by the current task sub-operation;

[0035] If it is determined that the number of remaining addresses in the current virtual page is less than a first preset number, and the task has the required next virtual page, the next virtual page is loaded from the memory into the cache, so that when the address mapping table of the MMU misses the target, the next virtual page in the cache is loaded into the address mapping table of the MMU for use.

[0036] In a fourth aspect, the present invention further provides a non-volatile computer storage medium, wherein the computer storage medium stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors to complete the method described in the first aspect.

[0037] In a fifth aspect, a chip is provided, comprising: a processor and an interface, for calling and running a computer program stored in the memory from a memory, and executing the method of the first aspect.

[0038] In a sixth aspect, a computer program product comprising instructions is provided, which, when executed on a computer or a processor, causes the computer or the processor to execute the method of the first aspect.

[0039] In a seventh aspect, a SoC chip is provided, comprising the MMU acceleration device described in the third aspect.

[0040] The present invention uses complete address information and current address information to calculate the number of remaining addresses of the current virtual page, thereby determining the time required for the task to execute to the next virtual page. Therefore, before the task is about to execute to the next virtual page, the virtual page is searched and loaded, so that when the task execution reaches the next virtual page, the next virtual page can be quickly called, thereby shortening the time the task is stagnant after the MMU misses the target, and ultimately reducing the overall execution time of the task. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0042] Figure 1 This is a flowchart of a first MMU acceleration method provided by an embodiment of the present invention;

[0043] Figure 2 Schematic diagram of a first MMU acceleration method provided by an embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of the architecture of an MMU acceleration device in the prior art;

[0045] Figure 4 1 is a schematic diagram of the architecture of an MMU acceleration device provided by an embodiment of the present invention;

[0046] Figure 5 1 is a flow chart of a second MMU acceleration method provided by an embodiment of the present invention;

[0047] Figure 6 1 is a flow chart of a third MMU acceleration method provided by an embodiment of the present invention;

[0048] Figure 7 2 is a schematic diagram of a second MMU acceleration method provided by an embodiment of the present invention;

[0049] Figure 8 4 is a flowchart of a fourth MMU acceleration method provided by an embodiment of the present invention;

[0050] Figure 9 4 is a flowchart of a fifth MMU acceleration method provided by an embodiment of the present invention;

[0051] Figure 10 2 is a schematic diagram of a third MMU acceleration method provided by an embodiment of the present invention;

[0052] Figure 11 This is another schematic diagram of the architecture of an MMU acceleration device in the prior art;

[0053] Figure 12 1 is a schematic diagram of the architecture of another MMU acceleration device provided by an embodiment of the present invention;

[0054] Figure 13 This is a schematic diagram of the architecture of another MMU acceleration device provided by an embodiment of the present invention;

[0055] Figure 14 is a schematic diagram of a fourth MMU acceleration method provided by an embodiment of the present invention;

[0056] Figure 15 2 is a schematic diagram of a fifth MMU acceleration method provided by an embodiment of the present invention;

[0057] Figure 16 1 is a schematic diagram of a sixth MMU acceleration method provided by an embodiment of the present invention;

[0058] Figure 17 This is a schematic diagram of the architecture of another MMU acceleration device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0060] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as meaning open inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that the specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner, that is, although they may be carried in the embodiments or examples of the above terms due to reasons such as the order and position of appearance, it is not limited to that they can be carried in combination by one embodiment or example.

[0061] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. In addition, for example, the description may also use the method of adding "A" and "B" at the end to describe the same type of nouns as two independent individuals. In this case, the corresponding features defined as "A" and "B" are only used to distinguish the description purposes of the same type of individuals, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0062] In the description of the present invention, the expression "A and / or B" (where A and B are used to formally represent specific characteristic contents) will be involved, and the corresponding expressions include the following three combinations: only A, only B, and a combination of A and B.

[0063] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0064] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0065] In the prior art, when the MMU's address mapping table misses the target, the virtual page is searched from the memory. During the search for the virtual page, the task that needs to use the corresponding virtual address is stalled and cannot continue to execute until the virtual page found is loaded into the MMU. However, since a large number of virtual pages are stored in the memory, it takes a lot of time to search for the virtual page, which results in a longer execution time of the task. To solve this problem, an embodiment of the present invention provides a method for accelerating the MMU, which pre-sets a cache, such as Figure 1 As shown, the method includes:

[0066] In step 201, the number of remaining addresses in the current virtual page is determined based on the complete address information of the task and the current address information of the current task sub-operation, and it is determined whether the task has the next virtual page required; wherein, the current virtual page is the virtual page required for the current task sub-operation; the complete address information of the task can be understood as information that can obtain all addresses required for the operation of the task. If a task needs to operate 4 consecutive addresses, namely address 1, address 2, address 3 and address 4, then the complete address information of the task may include a starting address and an address size, wherein the starting address is address 1, the address size is 4×size, and size is the size of the position of a single address, so that each address required for the operation of the task can be obtained through the starting address and the address size.

[0067] The current address information can be understood as the address required for the current task sub-operation, also called the current address.

[0068] A task can be understood as having multiple task sub-operations, and the current task sub-operation is the currently executed task sub-operation. A virtual page can be understood as a continuous virtual storage space. A virtual page corresponds to a continuous physical storage space. This physical storage space is also called a physical page, that is, a virtual page corresponds to a physical page; wherein, each virtual page has the same size, and each virtual page is continuous with each other. For example, a virtual storage space corresponding to 300 virtual addresses can be divided into 3 virtual pages, namely the first virtual page, the second virtual page and the third virtual page. The first virtual page corresponds to the 1st to 100th virtual addresses, the second virtual page corresponds to the 101st to 200th virtual addresses, and the third virtual page corresponds to the 201st to 300th virtual addresses. Since the first virtual The base address of the page (that is, the starting address of the first virtual page) is known, so the virtual page in which the current address exists can be determined based on the current address, that is, the value obtained by subtracting the starting address of the first virtual page from the current address is divided by the size of the virtual page to obtain the virtual page where the current address is located (that is, the current virtual page). Similarly, the value obtained by subtracting the starting address of the first virtual page from the current address is modulo the size of the virtual page to obtain the position of the current address in the current virtual page. According to the position of the current address in the current virtual page, the number of remaining addresses in the current virtual page (that is, the number of addresses from the current address to the end of the current virtual page) can be calculated.

[0069] The virtual page required for the task to be operated can also be determined based on the complete address information, and then combined with the current virtual page, the next virtual page can be determined. For example, if the task needs to operate the 1st to 4th virtual pages and the current virtual page is the 2nd virtual page, the next virtual page is the 3rd virtual page.

[0070] It should be noted that this embodiment is applicable to tasks that operate continuous virtual addresses, such as DMA instruction tasks or image area rendering tasks, and the remaining addresses in the current virtual page can be understood as the addresses that need to be operated before the task reaches the next virtual page.

[0071] In step 202, if it is determined that the number of remaining addresses in the current virtual page is less than a first preset number, and the task has a required next virtual page, the next virtual page is loaded from the memory into the cache, so that when the address mapping table of the MMU misses the target, the next virtual page in the cache is loaded into the address mapping table of the MMU for use.

[0072] The first preset number is obtained by those skilled in the art based on empirical analysis. In actual use, the first preset number needs to be analyzed in combination with the time required to execute the task sub-operation and the time required to load the virtual page from the memory, so that when the task execution ends at the current virtual page and the next virtual page needs to be operated, the next virtual page has been successfully loaded into the cache. The number of remaining addresses in the current virtual page is used to represent the time it takes for the task execution to reach the next virtual page, that is, the more remaining addresses in the current virtual page, the longer it takes to execute to reach the next virtual page, and conversely, the fewer remaining addresses in the current virtual page, the shorter it takes to execute to reach the next virtual page.

[0073] In some embodiments, the address mapping table is a TLB. Since multiple physical pages are not necessarily continuous, for example, the physical page corresponding to the first virtual page (i.e., the first physical page) can correspond to physical addresses 101 to 200, the physical page corresponding to the second virtual page (i.e., the second physical page) can correspond to physical addresses 241 to 340, and the physical page corresponding to the third virtual page (i.e., the third physical page) can correspond to physical addresses 341 to 440, that is, the first physical page and the second physical page are discontinuous, while the second physical page and the third physical page are continuous. In actual use, the task passes the virtual address, and the address actually operated is the physical address in the physical storage space. Therefore, it is necessary to implement the conversion from virtual address to physical address during operation. Therefore, it is necessary to load the virtual page first (i.e., load the mapping relationship between the virtual page and the physical page). The address mapping table is a table used to store the mapping relationship between the virtual page and the physical page.

[0074] The MMU address mapping table miss is also called an MMU miss, that is, the mapping relationship of the required virtual address is not found from the MMU TLB. The memory uses a page table to manage the mapping relationship between virtual pages and physical pages.

[0075] It should be noted here that the above steps 201 to 202 describe the process of executing a task to a certain virtual page (i.e., the current virtual page), that is, in actual use, when the current virtual page remains unchanged, step 201 is only executed before it is determined that the number of remaining addresses in the current virtual page is less than the first preset number. After it is determined that the number of remaining addresses in the current virtual page is less than the first preset number, step 201 is no longer executed until the current virtual page changes (i.e., after the task is executed to the next virtual page), and then step 201 is executed again; similarly, when the current virtual page remains unchanged, step 203 is only executed once when it is first determined that the number of remaining addresses in the current virtual page is less than the first preset number, and is no longer executed subsequently until the current virtual page changes and it is first determined that the number of remaining addresses in the current virtual page is less than the first preset number.

[0076] For example, if a task task1 needs to operate three virtual pages (task1.Ppage0, task1.Ppage1 and task1.Ppage2), then Figure 2 As shown, Figure 2 (a) is the prior art, which can be understood as searching and loading the virtual page after missing the target. Figure 2 As shown in (b), the virtual page is searched and loaded in advance when the next virtual page is about to be executed, which can greatly reduce the overall execution time of the task. Figure 2 In the example, num is the number of addresses from the next virtual page when the task operates to the corresponding virtual page position (i.e., the number of remaining addresses in the current virtual page), and M can be understood as the first preset number. Since the process of searching and loading virtual pages is mainly to search for virtual pages from the memory, which is relatively time-consuming, and the process of loading virtual pages into the MMU is relatively short, Figure 2 This is presented in a way that the time it takes to load the virtual page into the MMU is negligible.

[0077] This embodiment uses the complete address information and the current address information to calculate the number of remaining addresses of the current virtual page, thereby determining the time required for the task to execute to the next virtual page. Therefore, before the task is about to execute to the next virtual page, the virtual page is searched and loaded. When the task execution reaches the next virtual page, the next virtual page can be quickly called, thereby shortening the duration of the task stagnation after the MMU misses the target, and ultimately reducing the overall task execution time.

[0078] This embodiment chooses to load the next virtual page into the cache first, and then load the next virtual page into the MMU's address mapping table when the MMU's address mapping table misses, rather than directly loading it into the MMU. This implementation has a deeper level of consideration, namely, since the MMU space is limited, if the next virtual page is directly loaded into the MMU, it may occupy the space of the existing mapping relationship in the MMU, causing the existing mapping relationship to be discarded. However, the existing mapping relationship is very likely to be still needed by the task, thereby further causing the MMU to miss. Therefore, this embodiment first loads the next virtual page into the cache. At this time, the existing mapping relationship in the MMU can still be used normally. When the MMU misses, it can be considered that the MMU urgently needs to use the mapping relationship in the next virtual page (that is, the highest priority). At this time, the next virtual page is loaded into the MMU, thereby ensuring the normal and orderly progress of the task to the greatest extent possible.

[0079] In actual use, this embodiment can be implemented by the instruction execution unit itself, or an independent acceleration unit can be added, such as Figure 3 The figure shows the prior art architecture, wherein the instruction execution unit is connected to the MMU, and the MMU is connected to the memory. Figure 3 Based on the architecture of the prior art shown in FIG, an acceleration unit is added to obtain the following Figure 4 In the architecture shown, an acceleration unit is provided between the MMU and the memory (the MMU is connected to the acceleration unit, which is in turn connected to the memory, so that the MMU's page table query instructions must be passed to the memory via the acceleration unit), and an instruction execution unit is connected to the acceleration unit. In this architecture, the complete address information of a task is issued by the instruction execution unit at the beginning of task execution, and the current address information is issued by the instruction execution unit when executing the current task sub-operation.

[0080] It can be understood as follows: the instruction execution unit sends the complete address information of the task to the acceleration unit when starting to execute the task, and sends the address information of the task sub-operation to the acceleration unit when executing the task sub-operation, so that the acceleration unit executes the above steps 201 to 202 based on the complete address information and the current address information.

[0081] In a specific application scenario, the loading of the next virtual page from the memory into the cache is performed by loading the base address of the next virtual page and the base address of the corresponding physical page into the cache, such as Figure 5 As shown, specifically including:

[0082] In step 301, the base address of the next virtual page is calculated based on the current address information and the complete address information. That is, the base address of the current virtual page is first calculated, and then the base address of the next virtual page is calculated by adding the base address of the current virtual page to the size of the virtual page. It should be noted that the base address of the virtual page can be understood as the first virtual address in the virtual page, that is, the starting address of the virtual page.

[0083] In step 302, the base address of the corresponding physical page is searched from the memory according to the base address of the next virtual page.

[0084] In step 303, the base address of the next virtual page and the base address of the corresponding physical page are stored in the cache.

[0085] In an optional embodiment, the memory uses a multi-level page table to manage virtual pages, and according to the base address of the next virtual page, the base address of the corresponding physical page is searched from the memory, such as Figure 6 As shown, specifically including:

[0086] In step 401, offsets at various levels are determined based on the base address of the next virtual page. These offsets include the Nth level offset, the N-1th level offset, and so on, to the 1st level offset, where N is the total number of levels in the page table. The base address of each virtual page is derived from the corresponding offsets at various levels. Therefore, by decomposing the base address of the virtual address, the offsets at various levels can be obtained.

[0087] In step 402, the corresponding n-level storage location is determined based on the base address of the n-level page table in the memory and the n-level offset. The base address of the n-1-level page table is read from the n-level storage location until the base of the first-level page table is read. Then, the base address of the physical page corresponding to the next virtual page is read from the first-level storage location in the first-level page table. The n-level storage location is the location in the n-level page table where the base address of the n-1-level page table that ultimately leads to the corresponding physical page base address is stored. In actual use, the n-level storage location is the base address of the n-1-level page table obtained by the search plus the n-level offset.

[0088] The memory uses a multi-level page table to manage the mapping relationship between virtual pages and physical pages, wherein the mapping relationship is mainly manifested as a corresponding relationship between the base address of the virtual page and the base address of the physical page.

[0089] During the first search, the base address of the N-1th level page table is read from the Nth level page table. The memory has only one Nth level page table, and the base address of the Nth level page table is known.

[0090] The physical address of each virtual page is stored in the first-level page table, and the base address of the corresponding next-level page table is stored in the second to N-level page tables, that is, the base address of the n-1-level page table is stored in the n-level page table (n is an integer, n is greater than 1 and n is less than or equal to N). Steps 401 to 402 can be understood as a process of retrieving the physical address of the physical page corresponding to the virtual page using the base address of the virtual page as an index. The physical address of the virtual page can be understood as the base address of the physical page corresponding to the starting address of the virtual page. Since the virtual page and the physical page are both a continuous storage space, it is only necessary to know the base address of the physical page corresponding to the starting address of the virtual page, and then the base address of the physical page corresponding to each virtual address in the virtual page can be obtained by the offset of the address.

[0091] by Figure 7 For example, the 4-level page table shown in FIG. 4 , where N=4, Figure 7 Taking the example of two base addresses in each page table, the first 4-level page table includes two base addresses, which lead to the first 3-level page table and the second 3-level page table respectively (that is, the two base addresses are the base address of the first 3-level page table and the base address of the second 3-level page table respectively). Similarly, the first 3-level page table includes two base addresses, which lead to the first 2-level page table and the second 2-level page table respectively. The second 3-level page table includes two base addresses, which lead to the third 2-level page table and the fourth 2-level page table respectively. And so on. There are 8 1-level page tables, and these 8 1-level page tables are directed by the base addresses in the 4 2-level page tables respectively.

[0092] In addition, the base address of each virtual page is stored in the 8 level 1 page tables to calculate the base address of the next virtual page as 0x12345678000. For example, assuming that the size of a physical page is 4096, the virtual address is first split into 5 parts: 0x12, 0x34, 0x56, 0x78 and 0x000, where the first 4 parts are the offsets at each level, and 0x000 is the offset of the base address within the virtual page. Since the base address of the virtual page is the starting address of the virtual page, the offset within the virtual page is 0.

[0093] 0x12, 0x34, 0x56, and 0x78 are the offsets at each level, that is, the indexes in each level of page table used to retrieve the next level of page table. First, look up the 4th-level page table. The base address of the 4th-level page table is known. Assuming that the base address of the 4th-level page table is 0x10000 and the 4th-level offset is 0x12, the calculated 4th-level storage location is 0x10012, and the data at address 0x10012 is read; the address 0x10012 stores the base address of the required 3rd-level page table, and so on. Assuming its value is 0x20000, then read the address 0x20034; this address stores the base address of the 2nd-level page table. Assuming its value is 0x30000, then read the address 0x30056; this address stores the base address of the 1st-level page table, and its value is 0x40000, and then read the address 0x40078. The value stored in this address is the base address of the physical page corresponding to the next virtual page, assuming its value is 0x50000.

[0094] Thus, the base address 0x12345678000 of the next virtual page and the base address 0x50000 of its corresponding physical page are loaded into the cache, and when a miss occurs in the MMU, they are loaded from the cache into the MMU.

[0095] After loading into the MMU, assuming that a virtual address passed by the task is 0x12345678990, it can be calculated that the virtual address is located in the virtual page with a base address of 0x12345678000, and the offset relative to the base address 0x12345678000 is 0x990. Since the physical address corresponding to the base address 0x12345678000 is 0x50000, the physical address corresponding to the virtual address 0x12345678990 is 0x50990.

[0096] In actual use, before loading the next virtual page from the memory into the cache, the method also includes: searching the MMU for the next virtual page; if the next virtual page is found in the MMU, the next virtual page is not loaded from the memory into the cache; if the next virtual page cannot be found in the MMU, the next virtual page is loaded from the memory into the cache.

[0097] When the acceleration unit is used to execute the method of this embodiment, when the address mapping table of the MMU misses, the next virtual page in the cache is loaded into the address mapping table of the MMU for use, such as Figure 8 As shown, specifically including:

[0098] In step 501, a page table query instruction from the MMU is intercepted to check whether the next virtual page exists in the cache; the page table query instruction is issued by the MMU when the MMU's address mapping table misses the target.

[0099] In step 502, if the next virtual page is found, the next virtual page is returned to the MMU so that the MMU loads the next virtual page into the address mapping table of the MMU for use.

[0100] In step 503, if the next virtual page cannot be found in the cache, the page table query instruction is passed to the memory to find the next virtual page from the memory.

[0101] In actual application scenarios, the page table query instruction carries the virtual address to be queried, and the corresponding virtual page is determined based on the virtual address. If the virtual page exists in the cache, the virtual page is directly loaded from the cache into the MMU, otherwise, the virtual page is searched from the memory.

[0102] In actual use, it is not only during the execution of a single task that the MMU may miss the target and cause the task to stall. In addition, between tasks, that is, when the previous task is finished and the next task is about to start, the task may also stall. In order to solve this problem, this embodiment also provides a preferred implementation method, such as Figure 9 As shown, the method further includes:

[0103] In step 601, the number of remaining addresses required for the task is determined based on the complete address information and the current address information; wherein, the number of remaining virtual pages in the current virtual page is the number of addresses required for the task to operate to reach the next virtual page, and the number of remaining addresses required for the task is the number of addresses required for the task to operate to complete execution.

[0104] In step 602, if the number of remaining addresses required for the task is less than a second preset number, a pre-read command is sent to the instruction execution unit so that the instruction execution unit can issue task pre-read information according to the pre-read command; the second preset number is obtained by technical personnel in this field based on empirical analysis.

[0105] In step 603, task pre-read information is received from the instruction execution unit, the complete address information of the next task is read from the task pre-read information, and the virtual page required for the next task is determined based on the complete address information of the next task; the task pre-read information may include the complete address information of the next task and a task pre-read identifier, so that the acceleration unit can recognize that the complete address information belongs to the next task.

[0106] In step 604, the virtual page required for the next task is loaded from the memory into the cache, so that when the next task is executed, the virtual page required for the next task in the cache is loaded into the address mapping table of the MMU for use. It can be understood as: before the next task starts to execute, the address of the operation required for the next task is obtained in advance, and the virtual page where the address is located is pre-loaded. Among them, the first virtual page required for the next task can be loaded, and multiple virtual pages required can also be loaded. Figure 10 As shown, Figure 10 Take the execution of task1 and task2 as an example. Figure 10 (a) is the time required to perform these two tasks in the prior art, Figure 10 (b) is the time required to execute the two tasks in this embodiment, where K is the second preset number.

[0107] Among them, the execution of the next task can also be when the address mapping table of the MMU misses the target, which can be understood as: the page table query instruction issued when the MMU misses the target carries the virtual address to be queried, and the corresponding virtual page is determined according to the virtual address. If the virtual page exists in the cache, it is directly loaded from the cache to the MMU, otherwise, the virtual page is searched from the memory.

[0108] Among them, when the corresponding virtual page is loaded into the MMU, the virtual page in the cache is discarded to provide reserved space for the subsequent loading of other virtual pages. In actual use, a usage flag can be set for each virtual page. When the virtual page is loaded from the memory into the cache, the value of the usage flag is unused. When the virtual page is loaded from the cache into the MMU, the value of the usage flag is used. When a new virtual page is subsequently loaded from the memory into the cache, if the value of the usage flag of an existing virtual page in the cache is used, the new virtual page can be stored in the position of the existing virtual page to replace the existing virtual page, and the value of the usage flag of the new virtual page is updated to unused.

[0109] It should be noted that, in this embodiment, loading a virtual page and searching for a virtual page both refer to loading or searching for a mapping relationship between a virtual page and a physical page, so that a physical storage address corresponding to a virtual address can be obtained through the mapping relationship.

[0110] The present invention is based on the above-mentioned method, combined with specific application scenarios, and uses technical descriptions in related scenarios to illustrate the implementation process of the present invention in the characteristic scenarios.

[0111] This embodiment takes the execution of DMA instruction tasks as an example. The architecture related to task execution in the SoC chip in the prior art is as follows: Figure 11As shown in the figure, during the DMA transfer process, the address received by the DMA is a virtual address, which must be converted to a physical address to enable data access and transfer. If an MMU miss occurs during the address translation process, the DMA transfer process will stall. After an MMU miss, a page table lookup (also called a page table walk) is performed, which involves issuing a page table lookup instruction. This requires multiple DDR accesses. For example, if the DDR latency is 200 cycles for a four-level page table, four DDR accesses are required, totaling 800 cycles. This waste is enormous.

[0112] This embodiment adds an acceleration unit (also called MMU accelerator) to the SoC chip to form Figure 12 The architecture shown, such as Figure 13 As shown, the MMU accelerator includes an address distance calculation unit, a cache and a mapping relationship acquisition unit.

[0113] The address distance calculation unit is used to calculate how long the current page (i.e., the current virtual page) will be used up. Then, based on the configured threshold value (i.e., the first preset number), the address mapping relationship acquisition of the next virtual page (i.e., the next virtual page) is started. If the current entire DMA has reached the last virtual page, the virtual address of the next page is obtained from the DMA command FIFO (i.e., the complete address information of the next task is obtained). Otherwise, the address of the virtual page is directly set to the current virtual address plus the size of the virtual page.

[0114] When the address distance calculation unit detects that the current virtual page is almost used up, it sends a request to the mapping acquisition unit and provides the address of the next virtual page to be processed. The mapping acquisition unit first searches the MMU for the virtual page. If the page is found in the MMU, the mapping acquisition unit completes its operation. If not, it accesses the DDR to obtain the address mapping for the virtual page and stores it in the cache.

[0115] When an MMU miss occurs, a page table walk is performed, requiring access to the DDR. This access is intercepted by the MMU accelerator, which first searches the cache. If the virtual page that the MMU missed is found in the cache, the mapping entry (i.e., the address mapping) is directly returned to the MMU. The data related to this virtual page in the cache is simultaneously deleted to make room for subsequent requests.

[0116] The core of this embodiment is to detect in advance whether the required PPage (i.e. virtual page) can be found in the MMU. If not, it is retrieved from the DDR in advance. In this way, the delay of getting the PPage can be hidden in the delay of DMA accessing the DDR. Figure 14 As shown, Figure 14 The upper part shows the time occupied without MMU acceleration. Figure 14 The lower part shows the time occupied by the MMU accelerator.

[0117] As can be seen in the figure above, due to the lack of an MMU accelerator, an MMU miss occurs when switching Ppages within a task and switching tasks. At this time, it is necessary to wait until the MMU obtains the Ppage before continuing to run subsequent DMA instruction tasks.

[0118] With an MMU accelerator, the MMU's Ppage is pre-fetched. Even if an MMU miss occurs when switching Ppages within a task or between tasks, the missed Ppage is in the internal cache, so it only takes one or two cycles to find the Ppage. This allows DMA execution with an MMU accelerator to be much faster than with an accelerator without an MMU.

[0119] The cache here can be a cache built with registers. If the cache size is relatively large, then Static Random-Access Memory (SRAM) can be used to build it. However, no matter which method is used to build the cache, its latency can be reduced to a few cycles. The logical structure of the virtual page stored in the cache can be as follows: Figure 15 As shown, a total of 8 mapping relationships between the base address of the virtual page and the entry of the virtual page (that is, the base address of the physical page corresponding to the virtual page) can be stored, where: Figure 15 The valid flag in is the usage flag mentioned above. When its value is 1, it means it is not used. When its value is 0, it means it is used. The MMU read address is the base address of the virtual page, and the MMU Entry is the base address of the corresponding physical page.

[0120] When searching for a Miss in a certain level of MMU page table, continue searching the previous level page table until the last level page table is found. When the page table of the highest level Miss is found, the MMU accelerator will fetch the corresponding MMU Entry from the DDR according to the virtual address division of the MMU. When the MMU Entry is returned to the cache, the corresponding read address and Entry will be cached in the following places: Figure 15The DDR read address is then combined with the returned MMU entry and the virtual address of the next-level page table to form a new DDR read address, which is used to obtain the entry for the next-level page table. This process continues until the MMU entry for the last-level page table is returned.

[0121] When DMA actually needs to access the MMU, after an MMU Miss, it will access the DDR again using the same method as before, but these accesses will be intercepted by the MMU accelerator, which will then quickly find the required data in the cache. In this way, an MMU Miss can be completed in a few cycles.

[0122] Whenever a group of registers is read by the MMU, its valid flag will be rewritten to 0, indicating that this group of registers is free and can be used again.

[0123] The base address of a virtual page is composed of Figure 16 As shown in the figure, the 12th bit represents the offset within a 4KB Ppage. This offset is the same for both Ppages and Vpages and does not require conversion. The high-order bits are divided into four parts, each representing an offset within its corresponding page table.

[0124] If page table 2 misses, the page table in DDR is stored in page table 3. Page table 3 must first retrieve the address of page table 2 before the required content can be obtained. Page table 4 is the highest level page table, and its location in DDR is typically specified by a register. Therefore, the address the MMU reads from DDR consists of the entry in the previous level page table plus the bits corresponding to the virtual address. These addresses and the returned entry are stored in the MMU accelerator.

[0125] This embodiment uses a method of predicting the next DMA virtual address to read the mapping relationship from the DDR in advance and store it in an internal cache during the previous DMA data transfer process. In this way, when the next DMA starts, if an MMU miss occurs, the mapping relationship can be directly found in the cache. This can effectively hide the latency of the page table walk and greatly reduce the time required for task execution.

[0126] like Figure 17 FIG. 1 is a schematic diagram of the architecture of an MMU accelerated device according to an embodiment of the present invention. The MMU accelerated device according to this embodiment includes one or more processors 21 and a memory 22. Figure 17 A processor 21 is taken as an example.

[0127] The processor 21 and the memory 22 may be connected via a bus or other means. Figure 17 The bus connection is taken as an example.

[0128] Memory 22 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs and non-volatile computer executable programs, such as the MMU acceleration method described above. Processor 21 executes the MMU acceleration method by running the non-volatile software programs and instructions stored in memory 22.

[0129] The memory 22 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state memory device. In some embodiments, the memory 22 may optionally include a memory remotely located relative to the processor 21, and such remote memory may be connected to the processor 21 via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0130] The program instructions / modules are stored in the memory 22 and, when executed by the one or more processors 21 , perform the above-mentioned MMU acceleration method.

[0131] This embodiment also provides a device for MMU acceleration, such as Figure 4 As shown, it includes an instruction execution unit, an acceleration unit, an MMU and a memory; the acceleration unit is a device accelerated by the above-mentioned MMU;

[0132] The memory is used to store each virtual page.

[0133] The instruction execution unit is used to send the complete address information required for the task to the acceleration unit when the task starts to be executed, and to send the current address information of the current task sub-operation to the acceleration unit when executing the current task sub-operation.

[0134] The acceleration unit is used to determine the number of remaining addresses in the current virtual page based on the complete address information of the task and the current address information of the current task sub-operation, and to judge whether the task has the required next virtual page; wherein the current virtual page is the virtual page required by the current task sub-operation.

[0135] If it is determined that the number of remaining addresses in the current virtual page is less than a first preset number, and the task has the required next virtual page, the next virtual page is loaded from the memory into the cache, so that when the address mapping table of the MMU misses the target, the next virtual page in the cache is loaded into the address mapping table of the MMU for use.

[0136] This embodiment also provides a SoC chip, including the above-mentioned MMU acceleration device.

[0137] It is worth noting that the information interaction, execution process, etc. between the modules and units within the above-mentioned devices and systems are based on the same concept as the processing method embodiment of the present invention. The specific content can be found in the description of the method embodiment of the present invention and will not be repeated here.

[0138] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), a disk or an optical disk, etc.

[0139] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for MMU acceleration, characterized in that: Pre-setting a cache, the method comprising: Determining the number of remaining addresses in the current virtual page based on the complete address information of the task and the current address information of the current task sub-operation, and judging whether the task has a next virtual page required; wherein the current virtual page is the virtual page required by the current task sub-operation; If it is determined that the number of remaining addresses in the current virtual page is less than a first preset number, and the task has the required next virtual page, the next virtual page is loaded from the memory into the cache, so that when the address mapping table of the MMU misses the target, the next virtual page in the cache is loaded into the address mapping table of the MMU for use.

2. The MMU acceleration method according to claim 1, characterized in that: The step of loading the next virtual page from the memory into the cache is manifested as loading the base address of the next virtual page and the base address of the corresponding physical page into the cache, including: Calculating a base address of a next virtual page according to the current address information and the complete address information; According to the base address of the next virtual page, searching the memory for the base address of the corresponding physical page; The base address of the next virtual page and the base address of the corresponding physical page are stored in the cache.

3. The MMU acceleration method according to claim 2, characterized in that: The step of searching the memory for the base address of the corresponding physical page according to the base address of the next virtual page includes: Determining offsets at various levels according to the base address of the next virtual page; According to the base address and n-level offset of the n-level page table in the memory, the corresponding n-level storage position is determined, and the base address of the n-1-level page table is read from the n-level storage position until the base of the 1-level page table is read, and then the base address of the physical page corresponding to the next virtual page is read from the 1-level storage position in the 1-level page table.

4. The MMU acceleration method according to claim 1, characterized in that: Before loading the next virtual page from the memory into the cache, the method further includes: The MMU is searched for the existence of the next virtual page. If the MMU finds that the next virtual page exists, the next virtual page is not loaded from the memory into the cache.

5. The MMU acceleration method according to claim 1, characterized in that: When the address mapping table of the MMU misses the target, loading the next virtual page in the cache into the address mapping table of the MMU for use includes: Intercepting a page table query instruction from the MMU and searching the cache for the next virtual page; If the next virtual page is found, the next virtual page is returned to the MMU so that the MMU loads the next virtual page into the address mapping table of the MMU for use.

6. The MMU acceleration method according to claim 1, characterized in that: Also includes: Determining the number of remaining addresses required for the task based on the complete address information and the current address information; If the number of remaining addresses required for the task is less than a second preset number, sending a pre-read command to the instruction execution unit, so that the instruction execution unit issues task pre-read information according to the pre-read command; receiving task pre-read information from the instruction execution unit, reading complete address information of a next task from the task pre-read information, and determining a virtual page required by the next task according to the complete address information of the next task; The virtual pages required for the next task are loaded from the memory into the cache, so that when the next task is executed, the virtual pages required for the next task in the cache are loaded into the address mapping table of the MMU for use.

7. The MMU acceleration method according to any one of claims 1 to 6, characterized in that: The complete address information of the task is issued by the instruction execution unit when starting to execute the task, and the current address information is issued by the instruction execution unit when executing the current task sub-operation.

8. An MMU acceleration device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor to execute the MMU acceleration method according to any one of claims 1 to 7.

9. An MMU acceleration device, characterized in that: It includes an instruction execution unit, an acceleration unit, an MMU and a memory; the acceleration unit is the MMU acceleration device according to claim 8; The memory is used to store each virtual page; The instruction execution unit is used to send the complete address information required for the task to the acceleration unit when the task starts to be executed, and send the current address information of the current task sub-operation to the acceleration unit when executing the current task sub-operation; The acceleration unit is used to determine the number of remaining addresses in the current virtual page based on the complete address information of the task and the current address information of the current task sub-operation, and to judge whether the task has a next virtual page required; wherein the current virtual page is the virtual page required by the current task sub-operation; If it is determined that the number of remaining addresses in the current virtual page is less than a first preset number, and the task has the required next virtual page, the next virtual page is loaded from the memory into the cache, so that when the address mapping table of the MMU misses the target, the next virtual page in the cache is loaded into the address mapping table of the MMU for use.

10. A SoC chip, characterized in that: A device comprising the MMU acceleration device as claimed in claim 9.

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