Data processing device and method, electronic equipment and storage medium

Abstract

The invention provides a data processing device, and relates to the technical field of artificial intelligence, in particular to the technical field of chips. The apparatus comprises: a data handling unit configured to successively provide a plurality of target sub-data of target data to a target cache unit in response to determining that the target data is located in a first address space of a first storage unit and determining that a plurality of second address spaces to be written of the target data have intervals, the first address space is a continuous address space in the first storage unit, and the second address space is located in the second storage unit; the target cache unit is configured to execute the following operations to sequentially process each piece of target sub-data in the multiple pieces of target sub-data: determining at least one piece of to-be-written data according to the target sub-data; and writing the at least one piece of to-be-written data into the at least one second address space. The invention further provides a data processing method, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to the field of chip technology. More specifically, the present disclosure provides a data processing device, method, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence technology, the direct memory access (DMA) unit in artificial intelligence chips can improve data transmission efficiency. Summary of the Invention

[0003] The present disclosure provides a data processing apparatus, method, device, and storage medium.

[0004] According to one aspect of the present disclosure, a data processing device is provided, which includes: a data handling unit, configured to: in response to determining that target data is located in a first address space of a first storage unit and determining that there are gaps between multiple second address spaces to which the target data is to be written, successively provide multiple target sub-data of the target data to a target cache unit, wherein the first address space is a continuous address space in the first storage unit, the second address space is located in the second storage unit, the data volume of the target sub-data is less than or equal to the bandwidth of a target transmission channel, and the target transmission channel is a data transmission channel between the first storage unit and the second storage unit; a target cache unit, configured to perform the following operations to sequentially process each target sub-data in the multiple target sub-data: determine at least one data to be written based on the target sub-data; and write the at least one data to be written into at least one second address space.

[0005] According to another aspect of the present disclosure, an electronic device is provided, including the data processing device provided by the present disclosure.

[0006] According to another aspect of the present disclosure, a data processing method is provided, the method comprising: in response to determining that target data is located in a first address space of a first storage unit and determining that there are gaps between multiple second address spaces to which the target data is to be written, providing multiple target sub-data of the target data to a target cache unit in sequence, wherein the first address space is a continuous address space in the first storage unit, the second address space is located in the second storage unit, the data volume of the target sub-data is less than or equal to the bandwidth of a target transmission channel, and the target transmission channel is a data transmission channel between the first storage unit and the second storage unit; utilizing the target cache unit to perform the following operations to process each of the multiple target sub-data in sequence: determining at least one data to be written based on the target sub-data; and writing at least one data to be written into at least one second address space.

[0007] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method provided according to the present disclosure.

[0008] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0009] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, which implements the method provided according to the present disclosure when executed by a processor.

[0010] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0012] Figure 1 is a schematic block diagram of a data processing device according to an embodiment of the present disclosure;

[0013] Figure 2 is a schematic diagram of data transmission between a first storage unit and a second storage unit according to an embodiment of the present disclosure;

[0014] Figure 3A is a schematic diagram of properties of target data processed by a target cache unit according to one embodiment of the present disclosure;

[0015] Figure 3B is a schematic diagram of properties of target data processed by a target cache unit according to another embodiment of the present disclosure;

[0016] Figure 4 is a schematic diagram of an electronic device according to one embodiment of the present disclosure;

[0017] Figure 5 is a schematic flow chart of a data processing method according to an embodiment of the present disclosure; and

[0018] Figure 6 is a block diagram of an electronic device to which a data processing method according to an embodiment of the present disclosure can be applied. DETAILED DESCRIPTION

[0019] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0020] In order to improve the efficiency of data transmission, the direct memory access unit of the image processing unit (GPU) or the artificial intelligence chip can use a two-dimensional (2D) or three-dimensional (3D) method to carry out data transfer. That is, data can be carried multiple times in a cycle based on one instruction, without the need to carry it based on multiple instructions issued multiple times. In this way, the efficiency of data transmission can be improved. For example, by carrying data in a two-dimensional manner, N rows of data out of M rows of data can be carried. N is an integer less than or equal to M. M is an integer greater than 1, and N is an integer greater than or equal to 1. For another example, surface data may include M rows of data. By carrying data in a three-dimensional manner, at least one surface data can be carried, or multiple rows of data of different surface data can be carried.

[0021] However, when moving data from the first storage unit to the second storage unit, if the data is located in the continuous address space of the first storage unit and is to be written into multiple non-continuous address spaces of the second storage unit, part of the above data can be moved from the first storage unit to the second storage unit multiple times based on the number of transfers configured by the instruction.

[0022] Taking the three-dimensional transport method as an example, the number of two-dimensional data transports (loop2d) and the number of three-dimensional data transports (loop3d) can be configured. If the data is located in the continuous address space of the first storage unit and is to be written to multiple non-continuous address spaces of the second storage unit, the first storage unit can be read multiple times. The number of reads can be: the product of the number of two-dimensional data transports and the number of three-dimensional data transports (loop2d*loop3d). That is, the data is transported in a one-dimensional (1D) manner. The first storage unit can be an external storage unit, such as a global memory unit (GM). The second storage unit can be a local memory unit (LM). Therefore, if the first storage unit is read multiple times, the data transmission efficiency will be reduced, thereby reducing the performance of the chip.

[0023] Based on this, the present disclosure provides a data processing device to improve data transmission efficiency, which will be described below.

[0024] Figure 1 is a schematic block diagram of a data processing device according to an embodiment of the present disclosure.

[0025] like Figure 1 As shown, the apparatus 100 may include a data transport unit 110 and a target cache unit 120 .

[0026] The data transport unit 110 can be configured to: in response to determining that the target data is located in the first address space of the first storage unit and determining that there are gaps between multiple second address spaces where the target data is to be written, successively provide multiple target sub-data of the target data to the target cache unit.

[0027] In the disclosed embodiment, the first address space may be a continuous address space in the first storage unit. For example, the target data may be multiple continuous rows of data in the first storage unit. For another example, the target data may be multiple. The multiple target data may be from multiple surface data. In this case, the target data may be multiple continuous rows of surface data. The multiple surface data may be discontinuous or continuous.

[0028] In the disclosed embodiment, the second address space is located in the second storage unit. The amount of target sub-data is less than or equal to the bandwidth of the target transmission channel. The target transmission channel is the data transmission channel between the first storage unit and the second storage unit. For example, the bandwidth of the target transmission channel can be fully utilized to provide the target sub-data to the target cache unit as efficiently as possible.

[0029] In the embodiment of the present disclosure, the data handling unit may be a direct memory access unit.

[0030] The target cache unit 120 may be configured to process each target sub-data in sequence. The target cache unit 120 may receive the target sub-data provided by the data transport unit 110 and process the target sub-data.

[0031] The target cache unit 120 may be configured to perform the following operations to process each target sub-data: determining at least one data to be written based on the target sub-data; writing the at least one data to be written into at least one second address space; for example, the target sub-data may be split into multiple data to be written, and each of the data to be written may be written into the second address space.

[0032] Through the embodiments of the present disclosure, when the target data is located in the continuous address space of the first storage unit, the data can be directly read without waiting for the sub-instructions split from the original instruction to be issued, which can fully utilize the bandwidth of the data transmission channel, reduce the number of times data is read from the first storage unit, improve data reading efficiency, and help improve the performance of the device.

[0033] It can be understood that the above describes the data processing device of the present disclosure, and the data handling unit of the data processing device will be further described below.

[0034] In some embodiments, a data transfer unit can transfer data from a first storage unit to a second storage unit using a two-dimensional data transfer method and a three-dimensional data transfer method. The following description uses the three-dimensional data transfer method as an example. It is understood that the first storage unit and the second storage unit can be any different storage units. The following description uses the example of the first storage unit being a global storage unit and the second storage unit being a local storage unit.

[0035] In the disclosed embodiment, the data transport unit may transport multiple pieces of surface data multiple times. When transporting each piece of surface data, the data transport unit may transport multiple rows of data on the surface data multiple times. For example, the number of times surface data is transported may be loop3d. loop3d may be an integer greater than 1. When transporting each piece of surface data, the number of times row data is transported may be loop2d. loop2d may be an integer greater than 1.

[0036] When the plane data is transferred for the i-th time, the address gm_addr of the row data in the global storage unit of the plane data transferred for the j-th time can be determined by the following formula:

[0037] gm_addr = src_addr + i * src_ld1 + j * src_ld0 (Formula 1)

[0038] src_addr can be the starting address of multiple face data in the global storage unit. src_ld0 can be the data interval length of the global storage unit when using two-dimensional data transfer. src_ld1 can be the data interval length of the global storage unit when using three-dimensional data transfer. i can be an integer greater than or equal to 0 and less than or equal to loop3d. j can be an integer greater than or equal to 0 and less than or equal to loop2d.

[0039] In addition, when the plane data is transferred for the i-th time, the address lm_addr of the row data in the plane data transferred for the j-th time in the local storage unit can be determined by the following formula:

[0040] lm_addr=dst_addr+i*dst_ld1+j*dst_ld0 (Formula 2)

[0041] dst_addr may be the starting address in the local storage unit. dst_ld0 may be the data interval length of the local storage unit when two-dimensional data is transferred. dst_ld1 may be the data interval length of the local storage unit when three-dimensional data is transferred. It will be appreciated that, taking multiple lines of data as an example, the data interval length may be, for example, the length of the interval between the starting position of the first line of data and the starting position of the second line of data.

[0042] It is understandable that the above-mentioned target data can be one or more. The following will be explained with the example of one target data. It is also understandable that, in the case where the target data is one and is located in the continuous address space of the first storage unit, the target data can be multiple surface data, and the multiple surface data are located in the continuous address space of the first storage unit. That is, in the target data to be transported, the surface data is continuous and the row data is also continuous (src_len == src_ld0 and (src_len*loop_2d) == src_ldl). src_len can be the amount of data read each time.

[0043] In the embodiment of the present disclosure, at least one data to be written may be multiple. Figure 2 Provide explanation.

[0044] Figure 2 This is a schematic diagram of data transmission between a first storage unit and a second storage unit according to an embodiment of the present disclosure.

[0045] In the embodiment of the present disclosure, the data transport unit may provide the target sub-data to the target cache unit. Figure 2 As shown, the data transfer unit can provide the target sub-data data20 in the first storage unit 230 to the target cache unit 220. As a result, the target cache unit 220 can process the target sub-data data20. The data size of the target sub-data data20 can be equal to the bandwidth of the data transmission channel between the first storage unit 230 and the second storage unit 240.

[0046] In the disclosed embodiment, the target cache unit 220 may also be configured to determine at least one data to be written based on the target sub-data. For example, the configuration information of the target sub-data data20 may be determined based on the configuration information of the target data. The configuration information of the target sub-data data20 may also be used to determine the data to be written data200, the data to be written data201, and the data to be written data202. It will be appreciated that the configuration information may indicate multiple second address spaces.

[0047] In the embodiment of the present disclosure, the target cache unit 220 may also be configured to write at least one data to be written into at least one second address space. For example, according to the configuration information corresponding to the target data, the address information of each of the plurality of data to be written is determined. Figure 2As shown, according to the configuration information of the target data data20, the address information of the data to be written data200, the address information of the data to be written data201, and the address information of the data to be written data202 can be determined. The address information may include at least one of a starting address, a data amount, and an offset. The starting address may be the starting address of an initial address space in the second storage unit. The offset may be the offset between the starting address of the second address space and the starting address. Thus, the address information may indicate a second address space. It can be understood that based on the data amount, the offset, and the starting address of the initial address space, a second address space can be accurately determined. Through the embodiments of the present disclosure, the target cache unit can accurately write data into the corresponding second address space, which helps to improve the processing accuracy of the device.

[0048] In the embodiment of the present disclosure, the target cache unit 220 may also be configured to write at least one data to be written into at least one second address space. For example, according to the respective address information of the plurality of data to be written, the plurality of data to be written are written into the plurality of second address spaces respectively. For another example, in at least one processor cycle, the at least one data to be written is written into the at least one second address space. Figure 2 As shown, based on the address information of the data to be written data200, the address information of the data to be written data201 and the address information of the data to be written data202, in three different processor cycles, the data to be written data200, the data to be written data201 and the data to be written data202 can be written into the three second address spaces of the second storage unit 240 respectively.

[0049] Next, the target cache unit 220 can process the subsequent target sub-data of the target sub-data data200 until all the target sub-data of the target data are processed. It can be understood that, except for the last target sub-data, the data amounts of the other multiple target sub-data can be the same. It can also be understood that the target cache unit processes each target sub-data in the same or similar manner, and the present disclosure will not go into details here. Through the embodiment of the present disclosure, when the surface data of the target data to be transported is continuous and the corresponding row data is also continuous (src_len == src_ld0 and (src_len*loop_2d) == src_ld1), the data transport unit is equivalent to processing a one-dimensional direct memory access command, and the data volume src_len read by the command can be: the product of the data interval length of the global storage unit and the number of times the surface data is transported when three-dimensional data transport is adopted (src_ldl*loop3d). As a result, compared with the number of reads (loop2d*loop3d) required for the above-mentioned three-dimensional transport method, the number of data reads can be substantially reduced.

[0050] It is understood that the above description of the present disclosure uses the example of continuous surface data and continuous row data in the target data to be transported (src_len == src_ld0 and (src_len*loop_2d) == src_ld1) as an example. However, the present disclosure is not limited to this. In the case where multiple row data in each surface data of the target data to be transported are continuous, the multiple surface data may also be discontinuous, as will be explained below.

[0051] In the disclosed embodiment, there may be multiple target data. The multiple target data are located in multiple first address spaces of the first storage unit, and there are gaps between the multiple first address spaces. For example, among the multiple first address spaces, there may be a gap between at least two first address spaces. For another example, there may be gaps between the multiple first address spaces. When there are multiple gaps, the gaps may be different or the same.

[0052] It is understood that when there are multiple target data and they are located in different continuous address spaces of the first storage unit, the multiple target data can be multiple plane data. That is, in the target data to be transferred, the row data is continuous. The multiple target data are not continuous, that is, the multiple plane data are not continuous (src_len == src_ld0 and (src_len*loop_2d) != src_1d1).

[0053] In the embodiment of the present disclosure, the data transport unit may also be configured to perform the following operations to sequentially provide multiple target sub-data of the target data to the target cache unit: sequentially provide multiple target sub-data of each of the multiple target data to the target cache unit. For example, the data transport unit may provide the target sub-data of the target data to the target cache unit so that the target cache unit processes the target sub-data. Figure 2The difference between the illustrated embodiments is that, after processing the target data including the target sub-data, the target sub-data of the subsequent target data of the target data can be provided to the target cache unit. It can be understood that the way in which the target cache unit processes the target sub-data of different target data is the same or similar to the way in which the above-mentioned target sub-data data200 is processed, and the present disclosure will not go into details here. Through the embodiment of the present disclosure, when the surface data in the target data to be transported is discontinuous and the corresponding row data is continuous (src_len == src_ld0 and (src_len*loop_2d)!= src_ld1), the data transport unit is equivalent to processing multiple (for example, loop2d) one-dimensional direct memory access commands, and the amount of data read src_len of the command can be: the product of the data interval length of the global storage unit and the number of times the surface data is transported when three-dimensional data transport is adopted (src_ld0*loop2d). As a result, compared with the number of reads (loop2d*loop3d) required for the above-mentioned three-dimensional transport method, the number of data reads can be reduced.

[0054] It can be understood that the above description has been given of some examples in which the target data is located in the first address space of the first storage unit and the plurality of second address spaces to which the target data is to be written are spaced apart from each other. Figure 3A and Figure 3B The present disclosure is further described.

[0055] Figure 3A 4 is a schematic diagram of properties of target data processed by a target cache unit according to an embodiment of the present disclosure.

[0056] Figure 3A The first row is the header. Figure 3A The 2nd to 7th lines represent the attributes of different target data. Figure 3AIn the example, "0" can represent "no" and "1" can represent "yes". src_2d_size can represent the total amount of data for each two-dimensional data transfer during the three-dimensional data transfer from the global storage unit. For example, if the value of src_len==src_ld0 is 0, it can be indicated that the amount of data read each time is not equal to the data interval length of the global storage unit when two-dimensional data transfer is adopted. If the value of src_2d_size==src_ldl is 1, it can be indicated that the total amount of data for each two-dimensional data transfer during the three-dimensional data transfer is equal to the data interval length of the global storage unit when three-dimensional data transfer is adopted. If the value of loop_2d==1 is 1, it can be indicated that the number of two-dimensional data transfers during each three-dimensional data transfer is 1. If the value of loop_3d==0 is 0, it can be indicated that the number of three-dimensional data transfers is greater than 1 (for example, 5). In this case, the number of row data in each surface data is small, the row data is continuous and the surface data is also continuous, which is equivalent to performing a data read operation to obtain all the data. It can be understood that rows 3 to 7 are also target data with continuous row data and continuous surface data, and this disclosure will not go into details here.

[0057] Figure 3B is a schematic diagram of properties of target data processed by a target cache unit according to another embodiment of the present disclosure.

[0058] Figure 3B The first row is the header. Figure 3B The second line of represents the attributes of different target data. Figure 3BIn the example, "0" can represent "no" and "1" can represent "yes". dst_len can be the amount of data processed by the local storage unit each time. dst_2d_size can represent the total amount of two-dimensional data processed by the local storage unit each time during three-dimensional data handling. For example, if the value of src_len==src_ld0 is 1, it can be indicated that the amount of data read each time is equal to the data interval length of the global storage unit when two-dimensional data handling is adopted. If the value of src_2d_size==src_ld1 is 0, it can be indicated that the total amount of data of each two-dimensional data handling during three-dimensional data handling is not equal to the data interval length of the global storage unit when three-dimensional data handling is adopted. If the value of dst_len==dst_ld0 is 0, it can be indicated that the amount of data processed by the local storage unit each time is not equal to the data interval length of the local storage unit when two-dimensional data handling is adopted. If the value of dst_2d_size==dst_ld1 is 1, it can be indicated that the total amount of two-dimensional data handled by the local storage unit each time is equal to the data interval length of the local storage unit when three-dimensional data handling is adopted. If loop_2d == 1 is 0, it means that the number of 2D data transfers during each 3D data transfer is greater than 1 (for example, 6). If loop_3d == 0 is 0, it means that the number of 3D data transfers is greater than 1 (for example, 5). In this case, the row data is continuous and the surface data is discontinuous, which means that loop3d data read operations are required to obtain all the data.

[0059] I understand. Figure 3A and Figure 3B This is merely an example, and the present disclosure is not limited thereto. When target data is located in a continuous address space of a first storage unit, and multiple second address spaces to which the target data is to be written are spaced apart from each other, the data processing device of the present disclosure (e.g., device 100) can be used to perform data processing.

[0060] It can be understood that the above describes the device of the present disclosure, and the following will describe an electronic device including the device.

[0061] Figure 4 is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0062] like Figure 4 As shown, the electronic device 4000 may include a data processing device 400 .

[0063] In the embodiment of the present disclosure, the data processing device 400 may be the aforementioned device 100 .

[0064] It can be understood that the above description of the present disclosure includes a data processing device, and the following description will focus on the method of the present disclosure.

[0065] Figure 5 is a schematic flow chart of a data processing method according to an embodiment of the present disclosure.

[0066] like Figure 5 As shown, method 500 may include operations S510 to S520.

[0067] In operation S510 , in response to determining that target data is located in a first address space of a first storage unit and that multiple second address spaces to which the target data is to be written are spaced apart from each other, multiple target sub-data of the target data are sequentially provided to a target cache unit.

[0068] In an embodiment of the present disclosure, the first address space is a continuous address space in the first storage unit, the second address space is located in the second storage unit, the data volume of the target sub-data is less than or equal to the bandwidth of the target transmission channel, and the target transmission channel is a data transmission channel between the first storage unit and the second storage unit.

[0069] In operation S520 , each target sub-data in the plurality of target sub-data is processed in sequence using the target cache unit.

[0070] In the embodiment of the present disclosure, the target cache unit may perform the following operations: determining at least one data to be written according to the target sub-data, and writing the at least one data to be written into at least one second address space.

[0071] It is understood that operation S510 may be performed by the aforementioned data transport unit. The target cache unit may be the aforementioned target cache unit 120.

[0072] In some embodiments, the at least one data to be written is plural.

[0073] In some embodiments, writing at least one to-be-written data into at least one second address space includes: determining address information of each of a plurality of to-be-written data based on configuration information corresponding to the target data, the address information including at least one of the following: a starting address, a data size, and an offset, the address information being used to indicate the second address space; and writing the plurality of to-be-written data into the plurality of second address spaces based on the respective address information of the plurality of to-be-written data.

[0074] In some embodiments, writing the at least one to-be-written data into the at least one second address space includes: writing the at least one to-be-written data into the at least one second address space in at least one processor cycle.

[0075] In some embodiments, there are multiple target data, and the multiple target data are located in multiple first address spaces of the first storage unit, and there are gaps between the multiple first address spaces.

[0076] In some embodiments, providing the plurality of target sub-data of the target data to the target cache unit one by one includes: providing the plurality of target sub-data of each of the plurality of target data to the target cache unit one by one.

[0077] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0078] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0079] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0080] like Figure 6 As shown, the device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. Various programs and data required for the operation of the device 600 can also be stored in the RAM 603. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0081] Various components in device 600 are connected to I / O interface 605, including an input unit 606, such as a keyboard, mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a magnetic disk, optical disk, etc.; and a communication unit 609, such as a network card, modem, wireless communication transceiver, etc. The communication unit 609 allows device 600 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0082] The computing unit 601 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 601 performs the various methods and processes described above, such as the data processing method. For example, in some embodiments, the data processing method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the computing unit 601, one or more steps of the data processing method described above can be performed. Alternatively, in other embodiments, the computing unit 601 can be configured to perform the data processing method by any other appropriate means (e.g., by means of firmware).

[0083] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0084] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0085] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0086] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) display or an LCD (liquid crystal display)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0087] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0088] Computer systems may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The client and server relationship arises through computer programs running on the respective computers and having a client-server relationship to each other.

[0089] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0090] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A data processing device, comprising: a data transfer unit configured to: in response to determining that target data is located in a first address space of a first storage unit and that a plurality of second address spaces to which the target data is to be written are spaced apart from each other, sequentially provide a plurality of target sub-data of the target data to a target cache unit, wherein the first address space is a continuous address space in the first storage unit, the second address space is located in the second storage unit, and a data volume of the target sub-data is less than or equal to a bandwidth of a target transmission channel, the target transmission channel being a data transmission channel between the first storage unit and the second storage unit; The target cache unit is configured to perform the following operations to sequentially process each of the target sub-data: Determining at least one data to be written according to the target sub-data; Write at least one of the to-be-written data into at least one of the second address spaces.

2. The device according to claim 1, wherein At least one of the data to be written is multiple, The target cache unit is further configured to perform the following operations to write at least one of the to-be-written data into at least one second address space: determining, according to configuration information corresponding to the target data, address information of each of the plurality of data to be written, the address information including at least one of the following: a starting address, a data amount, and an offset, the address information being used to indicate the second address space; The plurality of data to be written are written into the plurality of second address spaces respectively according to respective address information of the plurality of data to be written.

3. The device according to claim 1, wherein The target cache unit is further configured to perform the following operations to write at least one of the to-be-written data into at least one second address space: In at least one processor cycle, at least one of the to-be-written data is written into at least one of the second address spaces.

4. The device according to any one of claims 1 to 3, wherein: There are multiple target data, and the multiple target data are located in multiple first address spaces of the first storage unit, and there are intervals between the multiple first address spaces.

5. The device according to claim 4, wherein The data transport unit is further configured to perform the following operations to sequentially provide the plurality of target sub-data of the target data to the target cache unit: The target sub-data of each of the target data are provided to the target cache unit in sequence.

6. An electronic device comprising the device according to any one of claims 1 to 5.

7. A data processing method, comprising: In response to determining that target data is located in a first address space of a first storage unit and that a plurality of second address spaces to which the target data is to be written are spaced apart from each other, sequentially providing a plurality of target sub-data of the target data to a target cache unit, wherein the first address space is a continuous address space in the first storage unit, the second address space is located in the second storage unit, and a data volume of the target sub-data is less than or equal to a bandwidth of a target transmission channel, the target transmission channel being a data transmission channel between the first storage unit and the second storage unit; The target cache unit is utilized to perform the following operations to sequentially process each of the plurality of target sub-data: Determining at least one data to be written according to the target sub-data; Write at least one of the to-be-written data into at least one of the second address spaces.

8. The method according to claim 7, wherein: At least one of the data to be written is multiple, Writing at least one of the to-be-written data into at least one of the second address spaces comprises: determining, according to configuration information corresponding to the target data, address information of each of the plurality of data to be written, the address information including at least one of the following: a starting address, a data amount, and an offset, the address information being used to indicate the second address space; The plurality of data to be written are written into the plurality of second address spaces respectively according to respective address information of the plurality of data to be written.

9. The method according to claim 7, wherein: Writing at least one of the to-be-written data into at least one of the second address spaces comprises: In at least one processor cycle, at least one of the to-be-written data is written into at least one of the second address spaces.

10. The method according to any one of claims 7 to 9, wherein: There are multiple target data, and the multiple target data are located in multiple first address spaces of the first storage unit, and there are intervals between the multiple first address spaces.

11. The method according to claim 10, wherein: The step of sequentially providing the plurality of target sub-data of the target data to the target cache unit comprises: The target sub-data of each of the target data are provided to the target cache unit in sequence.

12. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 7 to 11.

13. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 7 to 11.

14. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 7 to 11.

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